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arm: Remove swift-bmc machine
[qemu/rayw.git] / hw / arm / aspeed.c
blobfaf7a9fd6863a2af7655b05f9b290f189154b75f
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/i2c/i2c_mux_pca954x.h"
18 #include "hw/i2c/smbus_eeprom.h"
19 #include "hw/misc/pca9552.h"
20 #include "hw/sensor/tmp105.h"
21 #include "hw/misc/led.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/block-backend.h"
24 #include "hw/loader.h"
25 #include "qemu/error-report.h"
26 #include "qemu/units.h"
27
28 static struct arm_boot_info aspeed_board_binfo = {
29 .board_id = -1, /* device-tree-only board */
30 };
31
32 struct AspeedMachineState {
33 /* Private */
34 MachineState parent_obj;
35 /* Public */
36
37 AspeedSoCState soc;
38 MemoryRegion ram_container;
39 MemoryRegion max_ram;
40 bool mmio_exec;
41 char *fmc_model;
42 char *spi_model;
43 };
44
45 /* Palmetto hardware value: 0x120CE416 */
46 #define PALMETTO_BMC_HW_STRAP1 ( \
47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
49 SCU_AST2400_HW_STRAP_ACPI_DIS | \
50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
51 SCU_HW_STRAP_VGA_CLASS_CODE | \
52 SCU_HW_STRAP_LPC_RESET_PIN | \
53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
55 SCU_HW_STRAP_SPI_WIDTH | \
56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
58
59 /* TODO: Find the actual hardware value */
60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
63 SCU_AST2400_HW_STRAP_ACPI_DIS | \
64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
65 SCU_HW_STRAP_VGA_CLASS_CODE | \
66 SCU_HW_STRAP_LPC_RESET_PIN | \
67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69 SCU_HW_STRAP_SPI_WIDTH | \
70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72
73 /* AST2500 evb hardware value: 0xF100C2E6 */
74 #define AST2500_EVB_HW_STRAP1 (( \
75 AST2500_HW_STRAP1_DEFAULTS | \
76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
78 SCU_AST2500_HW_STRAP_UART_DEBUG | \
79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
80 SCU_HW_STRAP_MAC1_RGMII | \
81 SCU_HW_STRAP_MAC0_RGMII) & \
82 ~SCU_HW_STRAP_2ND_BOOT_WDT)
83
84 /* Romulus hardware value: 0xF10AD206 */
85 #define ROMULUS_BMC_HW_STRAP1 ( \
86 AST2500_HW_STRAP1_DEFAULTS | \
87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
89 SCU_AST2500_HW_STRAP_UART_DEBUG | \
90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
93
94 /* Sonorapass hardware value: 0xF100D216 */
95 #define SONORAPASS_BMC_HW_STRAP1 ( \
96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
98 SCU_AST2500_HW_STRAP_UART_DEBUG | \
99 SCU_AST2500_HW_STRAP_RESERVED28 | \
100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
101 SCU_HW_STRAP_VGA_CLASS_CODE | \
102 SCU_HW_STRAP_LPC_RESET_PIN | \
103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
105 SCU_HW_STRAP_VGA_BIOS_ROM | \
106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
107 SCU_AST2500_HW_STRAP_RESERVED1)
108
109 #define G220A_BMC_HW_STRAP1 ( \
110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
112 SCU_AST2500_HW_STRAP_UART_DEBUG | \
113 SCU_AST2500_HW_STRAP_RESERVED28 | \
114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
115 SCU_HW_STRAP_2ND_BOOT_WDT | \
116 SCU_HW_STRAP_VGA_CLASS_CODE | \
117 SCU_HW_STRAP_LPC_RESET_PIN | \
118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
119 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
120 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
121 SCU_AST2500_HW_STRAP_RESERVED1)
122
123 /* FP5280G2 hardware value: 0XF100D286 */
124 #define FP5280G2_BMC_HW_STRAP1 ( \
125 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
126 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
127 SCU_AST2500_HW_STRAP_UART_DEBUG | \
128 SCU_AST2500_HW_STRAP_RESERVED28 | \
129 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
130 SCU_HW_STRAP_VGA_CLASS_CODE | \
131 SCU_HW_STRAP_LPC_RESET_PIN | \
132 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
133 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
134 SCU_HW_STRAP_MAC1_RGMII | \
135 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
136 SCU_AST2500_HW_STRAP_RESERVED1)
137
138 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
139 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
140
141 /* Quanta-Q71l hardware value */
142 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
143 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
144 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
145 SCU_AST2400_HW_STRAP_ACPI_DIS | \
146 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
147 SCU_HW_STRAP_VGA_CLASS_CODE | \
148 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
149 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
150 SCU_HW_STRAP_SPI_WIDTH | \
151 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
152 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
153
154 /* AST2600 evb hardware value */
155 #define AST2600_EVB_HW_STRAP1 0x000000C0
156 #define AST2600_EVB_HW_STRAP2 0x00000003
157
158 /* Tacoma hardware value */
159 #define TACOMA_BMC_HW_STRAP1 0x00000000
160 #define TACOMA_BMC_HW_STRAP2 0x00000040
161
162 /* Rainier hardware value: (QEMU prototype) */
163 #define RAINIER_BMC_HW_STRAP1 0x00000000
164 #define RAINIER_BMC_HW_STRAP2 0x00000000
165
166 /* Fuji hardware value */
167 #define FUJI_BMC_HW_STRAP1 0x00000000
168 #define FUJI_BMC_HW_STRAP2 0x00000000
169
170 /*
171 * The max ram region is for firmwares that scan the address space
172 * with load/store to guess how much RAM the SoC has.
173 */
174 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
175 {
176 return 0;
177 }
178
179 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
180 unsigned size)
181 {
182 /* Discard writes */
183 }
184
185 static const MemoryRegionOps max_ram_ops = {
186 .read = max_ram_read,
187 .write = max_ram_write,
188 .endianness = DEVICE_NATIVE_ENDIAN,
189 };
190
191 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
192 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
193 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
194 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
195 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
196 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
197 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
198
199 static void aspeed_write_smpboot(ARMCPU *cpu,
200 const struct arm_boot_info *info)
201 {
202 static const uint32_t poll_mailbox_ready[] = {
203 /*
204 * r2 = per-cpu go sign value
205 * r1 = AST_SMP_MBOX_FIELD_ENTRY
206 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
207 */
208 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
209 0xe21000ff, /* ands r0, r0, #255 */
210 0xe59f201c, /* ldr r2, [pc, #28] */
211 0xe1822000, /* orr r2, r2, r0 */
212
213 0xe59f1018, /* ldr r1, [pc, #24] */
214 0xe59f0018, /* ldr r0, [pc, #24] */
215
216 0xe320f002, /* wfe */
217 0xe5904000, /* ldr r4, [r0] */
218 0xe1520004, /* cmp r2, r4 */
219 0x1afffffb, /* bne <wfe> */
220 0xe591f000, /* ldr pc, [r1] */
221 AST_SMP_MBOX_GOSIGN,
222 AST_SMP_MBOX_FIELD_ENTRY,
223 AST_SMP_MBOX_FIELD_GOSIGN,
224 };
225
226 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
227 sizeof(poll_mailbox_ready),
228 info->smp_loader_start);
229 }
230
231 static void aspeed_reset_secondary(ARMCPU *cpu,
232 const struct arm_boot_info *info)
233 {
234 AddressSpace *as = arm_boot_address_space(cpu, info);
235 CPUState *cs = CPU(cpu);
236
237 /* info->smp_bootreg_addr */
238 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
239 MEMTXATTRS_UNSPECIFIED, NULL);
240 cpu_set_pc(cs, info->smp_loader_start);
241 }
242
243 #define FIRMWARE_ADDR 0x0
244
245 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
246 Error **errp)
247 {
248 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
249 uint8_t *storage;
250 int64_t size;
251
252 /* The block backend size should have already been 'validated' by
253 * the creation of the m25p80 object.
254 */
255 size = blk_getlength(blk);
256 if (size <= 0) {
257 error_setg(errp, "failed to get flash size");
258 return;
259 }
260
261 if (rom_size > size) {
262 rom_size = size;
263 }
264
265 storage = g_new0(uint8_t, rom_size);
266 if (blk_pread(blk, 0, storage, rom_size) < 0) {
267 error_setg(errp, "failed to read the initial flash content");
268 return;
269 }
270
271 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
272 g_free(storage);
273 }
274
275 static void aspeed_board_init_flashes(AspeedSMCState *s,
276 const char *flashtype,
277 int unit0)
278 {
279 int i ;
280
281 for (i = 0; i < s->num_cs; ++i) {
282 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
283 qemu_irq cs_line;
284 DeviceState *dev;
285
286 dev = qdev_new(flashtype);
287 if (dinfo) {
288 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
289 }
290 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
291
292 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
293 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
294 }
295 }
296
297 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
298 {
299 DeviceState *card;
300
301 if (!dinfo) {
302 return;
303 }
304 card = qdev_new(TYPE_SD_CARD);
305 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
306 &error_fatal);
307 qdev_realize_and_unref(card,
308 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
309 &error_fatal);
310 }
311
312 static void aspeed_machine_init(MachineState *machine)
313 {
314 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
315 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
316 AspeedSoCClass *sc;
317 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
318 ram_addr_t max_ram_size;
319 int i;
320 NICInfo *nd = &nd_table[0];
321
322 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
323 4 * GiB);
324 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
325
326 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
327
328 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
329
330 /*
331 * This will error out if isize is not supported by memory controller.
332 */
333 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
334 &error_fatal);
335
336 for (i = 0; i < sc->macs_num; i++) {
337 if ((amc->macs_mask & (1 << i)) && nd->used) {
338 qemu_check_nic_model(nd, TYPE_FTGMAC100);
339 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
340 nd++;
341 }
342 }
343
344 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
345 &error_abort);
346 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
347 &error_abort);
348 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
349 &error_abort);
350 object_property_set_link(OBJECT(&bmc->soc), "dram",
351 OBJECT(machine->ram), &error_abort);
352 if (machine->kernel_filename) {
353 /*
354 * When booting with a -kernel command line there is no u-boot
355 * that runs to unlock the SCU. In this case set the default to
356 * be unlocked as the kernel expects
357 */
358 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
359 ASPEED_SCU_PROT_KEY, &error_abort);
360 }
361 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
362 amc->uart_default);
363 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
364
365 memory_region_add_subregion(get_system_memory(),
366 sc->memmap[ASPEED_DEV_SDRAM],
367 &bmc->ram_container);
368
369 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
370 &error_abort);
371 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
372 "max_ram", max_ram_size - machine->ram_size);
373 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
374
375 aspeed_board_init_flashes(&bmc->soc.fmc,
376 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
377 0);
378 aspeed_board_init_flashes(&bmc->soc.spi[0],
379 bmc->spi_model ? bmc->spi_model : amc->spi_model,
380 bmc->soc.fmc.num_cs);
381
382 /* Install first FMC flash content as a boot rom. */
383 if (drive0) {
384 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
385 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
386 uint64_t size = memory_region_size(&fl->mmio);
387
388 /*
389 * create a ROM region using the default mapping window size of
390 * the flash module. The window size is 64MB for the AST2400
391 * SoC and 128MB for the AST2500 SoC, which is twice as big as
392 * needed by the flash modules of the Aspeed machines.
393 */
394 if (ASPEED_MACHINE(machine)->mmio_exec) {
395 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
396 &fl->mmio, 0, size);
397 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
398 boot_rom);
399 } else {
400 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
401 size, &error_abort);
402 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
403 boot_rom);
404 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
405 }
406 }
407
408 if (machine->kernel_filename && sc->num_cpus > 1) {
409 /* With no u-boot we must set up a boot stub for the secondary CPU */
410 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
411 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
412 0x80, &error_abort);
413 memory_region_add_subregion(get_system_memory(),
414 AST_SMP_MAILBOX_BASE, smpboot);
415
416 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
417 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
418 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
419 }
420
421 aspeed_board_binfo.ram_size = machine->ram_size;
422 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
423
424 if (amc->i2c_init) {
425 amc->i2c_init(bmc);
426 }
427
428 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
429 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
430 drive_get(IF_SD, 0, i));
431 }
432
433 if (bmc->soc.emmc.num_slots) {
434 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
435 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
436 }
437
438 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
439 }
440
441 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
442 {
443 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
444 DeviceState *dev = DEVICE(i2c_dev);
445
446 qdev_prop_set_uint32(dev, "rom-size", rsize);
447 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
448 }
449
450 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
451 {
452 AspeedSoCState *soc = &bmc->soc;
453 DeviceState *dev;
454 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
455
456 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
457 * enough to provide basic RTC features. Alarms will be missing */
458 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
459
460 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
461 eeprom_buf);
462
463 /* add a TMP423 temperature sensor */
464 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
465 "tmp423", 0x4c));
466 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
467 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
468 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
469 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
470 }
471
472 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
473 {
474 AspeedSoCState *soc = &bmc->soc;
475
476 /*
477 * The quanta-q71l platform expects tmp75s which are compatible with
478 * tmp105s.
479 */
480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
483
484 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
485 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
486 /* TODO: Add Memory Riser i2c mux and eeproms. */
487
488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
490
491 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
492
493 /* i2c-7 */
494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
495 /* - i2c@0: pmbus@59 */
496 /* - i2c@1: pmbus@58 */
497 /* - i2c@2: pmbus@58 */
498 /* - i2c@3: pmbus@59 */
499
500 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
501 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
502 }
503
504 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
505 {
506 AspeedSoCState *soc = &bmc->soc;
507 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
508
509 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
510 eeprom_buf);
511
512 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
513 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
514 TYPE_TMP105, 0x4d);
515
516 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
517 * plugged on the I2C bus header */
518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
519 }
520
521 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
522 {
523 /* Start with some devices on our I2C busses */
524 ast2500_evb_i2c_init(bmc);
525 }
526
527 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
528 {
529 AspeedSoCState *soc = &bmc->soc;
530
531 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
532 * good enough */
533 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
534 }
535
536 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
537 {
538 AspeedSoCState *soc = &bmc->soc;
539
540 /* bus 2 : */
541 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
543 /* bus 2 : pca9546 @ 0x73 */
544
545 /* bus 3 : pca9548 @ 0x70 */
546
547 /* bus 4 : */
548 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
549 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
550 eeprom4_54);
551 /* PCA9539 @ 0x76, but PCA9552 is compatible */
552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
553 /* PCA9539 @ 0x77, but PCA9552 is compatible */
554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
555
556 /* bus 6 : */
557 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
559 /* bus 6 : pca9546 @ 0x73 */
560
561 /* bus 8 : */
562 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
563 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
564 eeprom8_56);
565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
567 /* bus 8 : adc128d818 @ 0x1d */
568 /* bus 8 : adc128d818 @ 0x1f */
569
570 /*
571 * bus 13 : pca9548 @ 0x71
572 * - channel 3:
573 * - tmm421 @ 0x4c
574 * - tmp421 @ 0x4e
575 * - tmp421 @ 0x4f
576 */
577
578 }
579
580 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
581 {
582 static const struct {
583 unsigned gpio_id;
584 LEDColor color;
585 const char *description;
586 bool gpio_polarity;
587 } pca1_leds[] = {
588 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
589 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
590 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
591 };
592 AspeedSoCState *soc = &bmc->soc;
593 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
594 DeviceState *dev;
595 LEDState *led;
596
597 /* Bus 3: TODO bmp280@77 */
598 /* Bus 3: TODO max31785@52 */
599 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
600 qdev_prop_set_string(dev, "description", "pca1");
601 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
602 aspeed_i2c_get_bus(&soc->i2c, 3),
603 &error_fatal);
604
605 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
606 led = led_create_simple(OBJECT(bmc),
607 pca1_leds[i].gpio_polarity,
608 pca1_leds[i].color,
609 pca1_leds[i].description);
610 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
611 qdev_get_gpio_in(DEVICE(led), 0));
612 }
613 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
615 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
616
617 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
619 0x4a);
620
621 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
622 * good enough */
623 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
624
625 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
626 eeprom_buf);
627 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
628 qdev_prop_set_string(dev, "description", "pca0");
629 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
630 aspeed_i2c_get_bus(&soc->i2c, 11),
631 &error_fatal);
632 /* Bus 11: TODO ucd90160@64 */
633 }
634
635 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
636 {
637 AspeedSoCState *soc = &bmc->soc;
638 DeviceState *dev;
639
640 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
641 "emc1413", 0x4c));
642 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
643 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
644 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
645
646 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
647 "emc1413", 0x4c));
648 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
649 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
650 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
651
652 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
653 "emc1413", 0x4c));
654 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
655 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
656 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
657
658 static uint8_t eeprom_buf[2 * 1024] = {
659 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
660 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
661 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
662 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
663 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
664 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
666 };
667 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
668 eeprom_buf);
669 }
670
671 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
672 {
673 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
674 DeviceState *dev = DEVICE(i2c_dev);
675
676 qdev_prop_set_uint32(dev, "rom-size", rsize);
677 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
678 }
679
680 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
681 {
682 AspeedSoCState *soc = &bmc->soc;
683 I2CSlave *i2c_mux;
684
685 /* The at24c256 */
686 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
687
688 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
690 0x48);
691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
692 0x49);
693
694 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
695 "pca9546", 0x70);
696 /* It expects a TMP112 but a TMP105 is compatible */
697 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
698 0x4a);
699
700 /* It expects a ds3232 but a ds1338 is good enough */
701 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
702
703 /* It expects a pca9555 but a pca9552 is compatible */
704 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552,
705 0x20);
706 }
707
708 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
709 {
710 AspeedSoCState *soc = &bmc->soc;
711 I2CSlave *i2c_mux;
712
713 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
714
715 /* The rainier expects a TMP275 but a TMP105 is compatible */
716 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
717 0x48);
718 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
719 0x49);
720 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
721 0x4a);
722 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
723 "pca9546", 0x70);
724 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
725 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
726 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
727
728 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
729 0x48);
730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
731 0x49);
732 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
733 "pca9546", 0x70);
734 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
735 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
736
737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
738 0x48);
739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
740 0x4a);
741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
742 0x4b);
743 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
744 "pca9546", 0x70);
745 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
746 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
747 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
748 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
749
750 /* Bus 7: TODO max31785@52 */
751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
752 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
753 /* Bus 7: TODO si7021-a20@20 */
754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
755 0x48);
756 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
757 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
758
759 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
760 0x48);
761 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
762 0x4a);
763 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
764 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
765 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
766 /* Bus 8: ucd90320@11 */
767 /* Bus 8: ucd90320@b */
768 /* Bus 8: ucd90320@c */
769
770 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
771 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
772 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
773
774 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
775 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
776 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
777
778 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
779 0x48);
780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
781 0x49);
782 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
783 "pca9546", 0x70);
784 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
785 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
786
787
788 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
789
790 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
791
792 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
793 }
794
795 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
796 I2CBus **channels)
797 {
798 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
799 for (int i = 0; i < 8; i++) {
800 channels[i] = pca954x_i2c_get_bus(mux, i);
801 }
802 }
803
804 #define TYPE_LM75 TYPE_TMP105
805 #define TYPE_TMP75 TYPE_TMP105
806 #define TYPE_TMP422 "tmp422"
807
808 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
809 {
810 AspeedSoCState *soc = &bmc->soc;
811 I2CBus *i2c[144] = {};
812
813 for (int i = 0; i < 16; i++) {
814 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
815 }
816 I2CBus *i2c180 = i2c[2];
817 I2CBus *i2c480 = i2c[8];
818 I2CBus *i2c600 = i2c[11];
819
820 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
821 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
822 /* NOTE: The device tree skips [32, 40) in the alias numbering */
823 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
824 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
825 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
826 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
827 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
828 for (int i = 0; i < 8; i++) {
829 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
830 }
831
832 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
833 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
834
835 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
836 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
837 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
838
839 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
840 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
841 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
842 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
843
844 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
845 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
846
847 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
848 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
849 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
850 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
851
852 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
853 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
854
855 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
856 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
857 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
858 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
859 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
860 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
861 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
862
863 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
864 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
865 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
866 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
867 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
868 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
869 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
870 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
871
872 for (int i = 0; i < 8; i++) {
873 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
874 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
875 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
876 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
877 }
878 }
879
880 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
881 {
882 return ASPEED_MACHINE(obj)->mmio_exec;
883 }
884
885 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
886 {
887 ASPEED_MACHINE(obj)->mmio_exec = value;
888 }
889
890 static void aspeed_machine_instance_init(Object *obj)
891 {
892 ASPEED_MACHINE(obj)->mmio_exec = false;
893 }
894
895 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
896 {
897 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
898 return g_strdup(bmc->fmc_model);
899 }
900
901 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
902 {
903 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
904
905 g_free(bmc->fmc_model);
906 bmc->fmc_model = g_strdup(value);
907 }
908
909 static char *aspeed_get_spi_model(Object *obj, Error **errp)
910 {
911 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
912 return g_strdup(bmc->spi_model);
913 }
914
915 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
916 {
917 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
918
919 g_free(bmc->spi_model);
920 bmc->spi_model = g_strdup(value);
921 }
922
923 static void aspeed_machine_class_props_init(ObjectClass *oc)
924 {
925 object_class_property_add_bool(oc, "execute-in-place",
926 aspeed_get_mmio_exec,
927 aspeed_set_mmio_exec);
928 object_class_property_set_description(oc, "execute-in-place",
929 "boot directly from CE0 flash device");
930
931 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
932 aspeed_set_fmc_model);
933 object_class_property_set_description(oc, "fmc-model",
934 "Change the FMC Flash model");
935 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
936 aspeed_set_spi_model);
937 object_class_property_set_description(oc, "spi-model",
938 "Change the SPI Flash model");
939 }
940
941 static int aspeed_soc_num_cpus(const char *soc_name)
942 {
943 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
944 return sc->num_cpus;
945 }
946
947 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
948 {
949 MachineClass *mc = MACHINE_CLASS(oc);
950 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
951
952 mc->init = aspeed_machine_init;
953 mc->no_floppy = 1;
954 mc->no_cdrom = 1;
955 mc->no_parallel = 1;
956 mc->default_ram_id = "ram";
957 amc->macs_mask = ASPEED_MAC0_ON;
958 amc->uart_default = ASPEED_DEV_UART5;
959
960 aspeed_machine_class_props_init(oc);
961 }
962
963 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
964 {
965 MachineClass *mc = MACHINE_CLASS(oc);
966 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
967
968 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
969 amc->soc_name = "ast2400-a1";
970 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
971 amc->fmc_model = "n25q256a";
972 amc->spi_model = "mx25l25635e";
973 amc->num_cs = 1;
974 amc->i2c_init = palmetto_bmc_i2c_init;
975 mc->default_ram_size = 256 * MiB;
976 mc->default_cpus = mc->min_cpus = mc->max_cpus =
977 aspeed_soc_num_cpus(amc->soc_name);
978 };
979
980 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
981 {
982 MachineClass *mc = MACHINE_CLASS(oc);
983 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
984
985 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
986 amc->soc_name = "ast2400-a1";
987 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
988 amc->fmc_model = "n25q256a";
989 amc->spi_model = "mx25l25635e";
990 amc->num_cs = 1;
991 amc->i2c_init = quanta_q71l_bmc_i2c_init;
992 mc->default_ram_size = 128 * MiB;
993 mc->default_cpus = mc->min_cpus = mc->max_cpus =
994 aspeed_soc_num_cpus(amc->soc_name);
995 }
996
997 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
998 void *data)
999 {
1000 MachineClass *mc = MACHINE_CLASS(oc);
1001 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1002
1003 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1004 amc->soc_name = "ast2400-a1";
1005 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1006 amc->fmc_model = "mx25l25635e";
1007 amc->spi_model = "mx25l25635e";
1008 amc->num_cs = 1;
1009 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1010 amc->i2c_init = palmetto_bmc_i2c_init;
1011 mc->default_ram_size = 256 * MiB;
1012 }
1013
1014 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1015 {
1016 MachineClass *mc = MACHINE_CLASS(oc);
1017 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1018
1019 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1020 amc->soc_name = "ast2500-a1";
1021 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1022 amc->fmc_model = "w25q256";
1023 amc->spi_model = "mx25l25635e";
1024 amc->num_cs = 1;
1025 amc->i2c_init = ast2500_evb_i2c_init;
1026 mc->default_ram_size = 512 * MiB;
1027 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1028 aspeed_soc_num_cpus(amc->soc_name);
1029 };
1030
1031 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1032 {
1033 MachineClass *mc = MACHINE_CLASS(oc);
1034 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1035
1036 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1037 amc->soc_name = "ast2500-a1";
1038 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1039 amc->fmc_model = "n25q256a";
1040 amc->spi_model = "mx66l1g45g";
1041 amc->num_cs = 2;
1042 amc->i2c_init = romulus_bmc_i2c_init;
1043 mc->default_ram_size = 512 * MiB;
1044 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1045 aspeed_soc_num_cpus(amc->soc_name);
1046 };
1047
1048 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1049 {
1050 MachineClass *mc = MACHINE_CLASS(oc);
1051 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1052
1053 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1054 amc->soc_name = "ast2500-a1";
1055 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1056 amc->fmc_model = "mx66l1g45g";
1057 amc->spi_model = "mx66l1g45g";
1058 amc->num_cs = 2;
1059 amc->i2c_init = sonorapass_bmc_i2c_init;
1060 mc->default_ram_size = 512 * MiB;
1061 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1062 aspeed_soc_num_cpus(amc->soc_name);
1063 };
1064
1065 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1066 {
1067 MachineClass *mc = MACHINE_CLASS(oc);
1068 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1069
1070 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1071 amc->soc_name = "ast2500-a1";
1072 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1073 amc->fmc_model = "mx25l25635e";
1074 amc->spi_model = "mx66l1g45g";
1075 amc->num_cs = 2;
1076 amc->i2c_init = witherspoon_bmc_i2c_init;
1077 mc->default_ram_size = 512 * MiB;
1078 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1079 aspeed_soc_num_cpus(amc->soc_name);
1080 };
1081
1082 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1083 {
1084 MachineClass *mc = MACHINE_CLASS(oc);
1085 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1086
1087 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1088 amc->soc_name = "ast2600-a3";
1089 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1090 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1091 amc->fmc_model = "w25q512jv";
1092 amc->spi_model = "mx66u51235f";
1093 amc->num_cs = 1;
1094 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1095 ASPEED_MAC3_ON;
1096 amc->i2c_init = ast2600_evb_i2c_init;
1097 mc->default_ram_size = 1 * GiB;
1098 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1099 aspeed_soc_num_cpus(amc->soc_name);
1100 };
1101
1102 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1103 {
1104 MachineClass *mc = MACHINE_CLASS(oc);
1105 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1106
1107 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1108 amc->soc_name = "ast2600-a3";
1109 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1110 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1111 amc->fmc_model = "mx66l1g45g";
1112 amc->spi_model = "mx66l1g45g";
1113 amc->num_cs = 2;
1114 amc->macs_mask = ASPEED_MAC2_ON;
1115 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1116 mc->default_ram_size = 1 * GiB;
1117 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1118 aspeed_soc_num_cpus(amc->soc_name);
1119 };
1120
1121 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1122 {
1123 MachineClass *mc = MACHINE_CLASS(oc);
1124 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1125
1126 mc->desc = "Bytedance G220A BMC (ARM1176)";
1127 amc->soc_name = "ast2500-a1";
1128 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1129 amc->fmc_model = "n25q512a";
1130 amc->spi_model = "mx25l25635e";
1131 amc->num_cs = 2;
1132 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1133 amc->i2c_init = g220a_bmc_i2c_init;
1134 mc->default_ram_size = 1024 * MiB;
1135 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1136 aspeed_soc_num_cpus(amc->soc_name);
1137 };
1138
1139 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1140 {
1141 MachineClass *mc = MACHINE_CLASS(oc);
1142 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1143
1144 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1145 amc->soc_name = "ast2500-a1";
1146 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1147 amc->fmc_model = "n25q512a";
1148 amc->spi_model = "mx25l25635e";
1149 amc->num_cs = 2;
1150 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1151 amc->i2c_init = fp5280g2_bmc_i2c_init;
1152 mc->default_ram_size = 512 * MiB;
1153 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1154 aspeed_soc_num_cpus(amc->soc_name);
1155 };
1156
1157 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1158 {
1159 MachineClass *mc = MACHINE_CLASS(oc);
1160 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1161
1162 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1163 amc->soc_name = "ast2600-a3";
1164 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1165 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1166 amc->fmc_model = "mx66l1g45g";
1167 amc->spi_model = "mx66l1g45g";
1168 amc->num_cs = 2;
1169 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1170 amc->i2c_init = rainier_bmc_i2c_init;
1171 mc->default_ram_size = 1 * GiB;
1172 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1173 aspeed_soc_num_cpus(amc->soc_name);
1174 };
1175
1176 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1177 #if HOST_LONG_BITS == 32
1178 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1179 #else
1180 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1181 #endif
1182
1183 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1184 {
1185 MachineClass *mc = MACHINE_CLASS(oc);
1186 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1187
1188 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1189 amc->soc_name = "ast2600-a3";
1190 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1191 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1192 amc->fmc_model = "mx66l1g45g";
1193 amc->spi_model = "mx66l1g45g";
1194 amc->num_cs = 2;
1195 amc->macs_mask = ASPEED_MAC3_ON;
1196 amc->i2c_init = fuji_bmc_i2c_init;
1197 amc->uart_default = ASPEED_DEV_UART1;
1198 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1199 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1200 aspeed_soc_num_cpus(amc->soc_name);
1201 };
1202
1203 static const TypeInfo aspeed_machine_types[] = {
1204 {
1205 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1206 .parent = TYPE_ASPEED_MACHINE,
1207 .class_init = aspeed_machine_palmetto_class_init,
1208 }, {
1209 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1210 .parent = TYPE_ASPEED_MACHINE,
1211 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1212 }, {
1213 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1214 .parent = TYPE_ASPEED_MACHINE,
1215 .class_init = aspeed_machine_ast2500_evb_class_init,
1216 }, {
1217 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1218 .parent = TYPE_ASPEED_MACHINE,
1219 .class_init = aspeed_machine_romulus_class_init,
1220 }, {
1221 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1222 .parent = TYPE_ASPEED_MACHINE,
1223 .class_init = aspeed_machine_sonorapass_class_init,
1224 }, {
1225 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1226 .parent = TYPE_ASPEED_MACHINE,
1227 .class_init = aspeed_machine_witherspoon_class_init,
1228 }, {
1229 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1230 .parent = TYPE_ASPEED_MACHINE,
1231 .class_init = aspeed_machine_ast2600_evb_class_init,
1232 }, {
1233 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1234 .parent = TYPE_ASPEED_MACHINE,
1235 .class_init = aspeed_machine_tacoma_class_init,
1236 }, {
1237 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1238 .parent = TYPE_ASPEED_MACHINE,
1239 .class_init = aspeed_machine_g220a_class_init,
1240 }, {
1241 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1242 .parent = TYPE_ASPEED_MACHINE,
1243 .class_init = aspeed_machine_fp5280g2_class_init,
1244 }, {
1245 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1246 .parent = TYPE_ASPEED_MACHINE,
1247 .class_init = aspeed_machine_quanta_q71l_class_init,
1248 }, {
1249 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1250 .parent = TYPE_ASPEED_MACHINE,
1251 .class_init = aspeed_machine_rainier_class_init,
1252 }, {
1253 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1254 .parent = TYPE_ASPEED_MACHINE,
1255 .class_init = aspeed_machine_fuji_class_init,
1256 }, {
1257 .name = TYPE_ASPEED_MACHINE,
1258 .parent = TYPE_MACHINE,
1259 .instance_size = sizeof(AspeedMachineState),
1260 .instance_init = aspeed_machine_instance_init,
1261 .class_size = sizeof(AspeedMachineClass),
1262 .class_init = aspeed_machine_class_init,
1263 .abstract = true,
1264 }
1265 };
1266
1267 DEFINE_TYPES(aspeed_machine_types)
Ray Wang's QEMU Repository