| blob | 49c722e8625c469fe17930a82e305f84bfe47175 |
1 /*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
10 static inline TCGv_ptr gen_avr_ptr(int reg)
11 {
12 TCGv_ptr r = tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
14 return r;
15 }
17 #define GEN_VR_LDX(name, opc2, opc3) \
18 static void glue(gen_, name)(DisasContext *ctx) \
19 { \
20 TCGv EA; \
21 TCGv_i64 avr; \
22 if (unlikely(!ctx->altivec_enabled)) { \
23 gen_exception(ctx, POWERPC_EXCP_VPU); \
24 return; \
25 } \
26 gen_set_access_type(ctx, ACCESS_INT); \
27 avr = tcg_temp_new_i64(); \
28 EA = tcg_temp_new(); \
29 gen_addr_reg_index(ctx, EA); \
30 tcg_gen_andi_tl(EA, EA, ~0xf); \
31 /* \
32 * We only need to swap high and low halves. gen_qemu_ld64_i64 \
33 * does necessary 64-bit byteswap already. \
34 */ \
35 if (ctx->le_mode) { \
36 gen_qemu_ld64_i64(ctx, avr, EA); \
37 set_avr64(rD(ctx->opcode), avr, false); \
38 tcg_gen_addi_tl(EA, EA, 8); \
39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, true); \
41 } else { \
42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
44 tcg_gen_addi_tl(EA, EA, 8); \
45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, false); \
47 } \
48 tcg_temp_free(EA); \
49 tcg_temp_free_i64(avr); \
50 }
52 #define GEN_VR_STX(name, opc2, opc3) \
53 static void gen_st##name(DisasContext *ctx) \
54 { \
55 TCGv EA; \
56 TCGv_i64 avr; \
57 if (unlikely(!ctx->altivec_enabled)) { \
58 gen_exception(ctx, POWERPC_EXCP_VPU); \
59 return; \
60 } \
61 gen_set_access_type(ctx, ACCESS_INT); \
62 avr = tcg_temp_new_i64(); \
63 EA = tcg_temp_new(); \
64 gen_addr_reg_index(ctx, EA); \
65 tcg_gen_andi_tl(EA, EA, ~0xf); \
66 /* \
67 * We only need to swap high and low halves. gen_qemu_st64_i64 \
68 * does necessary 64-bit byteswap already. \
69 */ \
70 if (ctx->le_mode) { \
71 get_avr64(avr, rD(ctx->opcode), false); \
72 gen_qemu_st64_i64(ctx, avr, EA); \
73 tcg_gen_addi_tl(EA, EA, 8); \
74 get_avr64(avr, rD(ctx->opcode), true); \
75 gen_qemu_st64_i64(ctx, avr, EA); \
76 } else { \
77 get_avr64(avr, rD(ctx->opcode), true); \
78 gen_qemu_st64_i64(ctx, avr, EA); \
79 tcg_gen_addi_tl(EA, EA, 8); \
80 get_avr64(avr, rD(ctx->opcode), false); \
81 gen_qemu_st64_i64(ctx, avr, EA); \
82 } \
83 tcg_temp_free(EA); \
84 tcg_temp_free_i64(avr); \
85 }
87 #define GEN_VR_LVE(name, opc2, opc3, size) \
88 static void gen_lve##name(DisasContext *ctx) \
89 { \
90 TCGv EA; \
91 TCGv_ptr rs; \
92 if (unlikely(!ctx->altivec_enabled)) { \
93 gen_exception(ctx, POWERPC_EXCP_VPU); \
94 return; \
95 } \
96 gen_set_access_type(ctx, ACCESS_INT); \
97 EA = tcg_temp_new(); \
98 gen_addr_reg_index(ctx, EA); \
99 if (size > 1) { \
100 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
101 } \
102 rs = gen_avr_ptr(rS(ctx->opcode)); \
103 gen_helper_lve##name(cpu_env, rs, EA); \
104 tcg_temp_free(EA); \
105 tcg_temp_free_ptr(rs); \
106 }
108 #define GEN_VR_STVE(name, opc2, opc3, size) \
109 static void gen_stve##name(DisasContext *ctx) \
110 { \
111 TCGv EA; \
112 TCGv_ptr rs; \
113 if (unlikely(!ctx->altivec_enabled)) { \
114 gen_exception(ctx, POWERPC_EXCP_VPU); \
115 return; \
116 } \
117 gen_set_access_type(ctx, ACCESS_INT); \
118 EA = tcg_temp_new(); \
119 gen_addr_reg_index(ctx, EA); \
120 if (size > 1) { \
121 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
122 } \
123 rs = gen_avr_ptr(rS(ctx->opcode)); \
124 gen_helper_stve##name(cpu_env, rs, EA); \
125 tcg_temp_free(EA); \
126 tcg_temp_free_ptr(rs); \
127 }
129 GEN_VR_LDX(lvx, 0x07, 0x03);
130 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
131 GEN_VR_LDX(lvxl, 0x07, 0x0B);
133 GEN_VR_LVE(bx, 0x07, 0x00, 1);
134 GEN_VR_LVE(hx, 0x07, 0x01, 2);
135 GEN_VR_LVE(wx, 0x07, 0x02, 4);
137 GEN_VR_STX(svx, 0x07, 0x07);
138 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
139 GEN_VR_STX(svxl, 0x07, 0x0F);
141 GEN_VR_STVE(bx, 0x07, 0x04, 1);
142 GEN_VR_STVE(hx, 0x07, 0x05, 2);
143 GEN_VR_STVE(wx, 0x07, 0x06, 4);
145 static void gen_mfvscr(DisasContext *ctx)
146 {
147 TCGv_i32 t;
148 TCGv_i64 avr;
149 if (unlikely(!ctx->altivec_enabled)) {
150 gen_exception(ctx, POWERPC_EXCP_VPU);
151 return;
152 }
153 avr = tcg_temp_new_i64();
154 tcg_gen_movi_i64(avr, 0);
155 set_avr64(rD(ctx->opcode), avr, true);
156 t = tcg_temp_new_i32();
157 gen_helper_mfvscr(t, cpu_env);
158 tcg_gen_extu_i32_i64(avr, t);
159 set_avr64(rD(ctx->opcode), avr, false);
160 tcg_temp_free_i32(t);
161 tcg_temp_free_i64(avr);
162 }
164 static void gen_mtvscr(DisasContext *ctx)
165 {
166 TCGv_i32 val;
167 int bofs;
169 if (unlikely(!ctx->altivec_enabled)) {
170 gen_exception(ctx, POWERPC_EXCP_VPU);
171 return;
172 }
174 val = tcg_temp_new_i32();
175 bofs = avr_full_offset(rB(ctx->opcode));
176 #ifdef HOST_WORDS_BIGENDIAN
177 bofs += 3 * 4;
178 #endif
180 tcg_gen_ld_i32(val, cpu_env, bofs);
181 gen_helper_mtvscr(cpu_env, val);
182 tcg_temp_free_i32(val);
183 }
185 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \
186 static void glue(gen_, name)(DisasContext *ctx) \
187 { \
188 TCGv_i64 t0; \
189 TCGv_i64 t1; \
190 TCGv_i64 t2; \
191 TCGv_i64 avr; \
192 TCGv_i64 ten, z; \
193 \
194 if (unlikely(!ctx->altivec_enabled)) { \
195 gen_exception(ctx, POWERPC_EXCP_VPU); \
196 return; \
197 } \
198 \
199 t0 = tcg_temp_new_i64(); \
200 t1 = tcg_temp_new_i64(); \
201 t2 = tcg_temp_new_i64(); \
202 avr = tcg_temp_new_i64(); \
203 ten = tcg_const_i64(10); \
204 z = tcg_const_i64(0); \
205 \
206 if (add_cin) { \
207 get_avr64(avr, rA(ctx->opcode), false); \
208 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
209 get_avr64(avr, rB(ctx->opcode), false); \
210 tcg_gen_andi_i64(t2, avr, 0xF); \
211 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
212 set_avr64(rD(ctx->opcode), avr, false); \
213 } else { \
214 get_avr64(avr, rA(ctx->opcode), false); \
215 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
216 set_avr64(rD(ctx->opcode), avr, false); \
217 } \
218 \
219 if (ret_carry) { \
220 get_avr64(avr, rA(ctx->opcode), true); \
221 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
222 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
223 set_avr64(rD(ctx->opcode), avr, false); \
224 set_avr64(rD(ctx->opcode), z, true); \
225 } else { \
226 get_avr64(avr, rA(ctx->opcode), true); \
227 tcg_gen_mul_i64(t0, avr, ten); \
228 tcg_gen_add_i64(avr, t0, t2); \
229 set_avr64(rD(ctx->opcode), avr, true); \
230 } \
231 \
232 tcg_temp_free_i64(t0); \
233 tcg_temp_free_i64(t1); \
234 tcg_temp_free_i64(t2); \
235 tcg_temp_free_i64(avr); \
236 tcg_temp_free_i64(ten); \
237 tcg_temp_free_i64(z); \
238 } \
240 GEN_VX_VMUL10(vmul10uq, 0, 0);
241 GEN_VX_VMUL10(vmul10euq, 1, 0);
242 GEN_VX_VMUL10(vmul10cuq, 0, 1);
243 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
245 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
246 static void glue(gen_, name)(DisasContext *ctx) \
247 { \
248 if (unlikely(!ctx->altivec_enabled)) { \
249 gen_exception(ctx, POWERPC_EXCP_VPU); \
250 return; \
251 } \
252 \
253 tcg_op(vece, \
254 avr_full_offset(rD(ctx->opcode)), \
255 avr_full_offset(rA(ctx->opcode)), \
256 avr_full_offset(rB(ctx->opcode)), \
257 16, 16); \
258 }
260 /* Logical operations */
261 GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
262 GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
263 GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
264 GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
265 GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
266 GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
267 GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
268 GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
270 #define GEN_VXFORM(name, opc2, opc3) \
271 static void glue(gen_, name)(DisasContext *ctx) \
272 { \
273 TCGv_ptr ra, rb, rd; \
274 if (unlikely(!ctx->altivec_enabled)) { \
275 gen_exception(ctx, POWERPC_EXCP_VPU); \
276 return; \
277 } \
278 ra = gen_avr_ptr(rA(ctx->opcode)); \
279 rb = gen_avr_ptr(rB(ctx->opcode)); \
280 rd = gen_avr_ptr(rD(ctx->opcode)); \
281 gen_helper_##name(rd, ra, rb); \
282 tcg_temp_free_ptr(ra); \
283 tcg_temp_free_ptr(rb); \
284 tcg_temp_free_ptr(rd); \
285 }
287 #define GEN_VXFORM_TRANS(name, opc2, opc3) \
288 static void glue(gen_, name)(DisasContext *ctx) \
289 { \
290 if (unlikely(!ctx->altivec_enabled)) { \
291 gen_exception(ctx, POWERPC_EXCP_VPU); \
292 return; \
293 } \
294 trans_##name(ctx); \
295 }
297 #define GEN_VXFORM_ENV(name, opc2, opc3) \
298 static void glue(gen_, name)(DisasContext *ctx) \
299 { \
300 TCGv_ptr ra, rb, rd; \
301 if (unlikely(!ctx->altivec_enabled)) { \
302 gen_exception(ctx, POWERPC_EXCP_VPU); \
303 return; \
304 } \
305 ra = gen_avr_ptr(rA(ctx->opcode)); \
306 rb = gen_avr_ptr(rB(ctx->opcode)); \
307 rd = gen_avr_ptr(rD(ctx->opcode)); \
308 gen_helper_##name(cpu_env, rd, ra, rb); \
309 tcg_temp_free_ptr(ra); \
310 tcg_temp_free_ptr(rb); \
311 tcg_temp_free_ptr(rd); \
312 }
314 #define GEN_VXFORM3(name, opc2, opc3) \
315 static void glue(gen_, name)(DisasContext *ctx) \
316 { \
317 TCGv_ptr ra, rb, rc, rd; \
318 if (unlikely(!ctx->altivec_enabled)) { \
319 gen_exception(ctx, POWERPC_EXCP_VPU); \
320 return; \
321 } \
322 ra = gen_avr_ptr(rA(ctx->opcode)); \
323 rb = gen_avr_ptr(rB(ctx->opcode)); \
324 rc = gen_avr_ptr(rC(ctx->opcode)); \
325 rd = gen_avr_ptr(rD(ctx->opcode)); \
326 gen_helper_##name(rd, ra, rb, rc); \
327 tcg_temp_free_ptr(ra); \
328 tcg_temp_free_ptr(rb); \
329 tcg_temp_free_ptr(rc); \
330 tcg_temp_free_ptr(rd); \
331 }
333 /*
334 * Support for Altivec instruction pairs that use bit 31 (Rc) as
335 * an opcode bit. In general, these pairs come from different
336 * versions of the ISA, so we must also support a pair of flags for
337 * each instruction.
338 */
339 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
340 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
341 { \
342 if ((Rc(ctx->opcode) == 0) && \
343 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
344 gen_##name0(ctx); \
345 } else if ((Rc(ctx->opcode) == 1) && \
346 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
347 gen_##name1(ctx); \
348 } else { \
349 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
350 } \
351 }
353 /*
354 * We use this macro if one instruction is realized with direct
355 * translation, and second one with helper.
356 */
357 #define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
358 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
359 { \
360 if ((Rc(ctx->opcode) == 0) && \
361 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
362 if (unlikely(!ctx->altivec_enabled)) { \
363 gen_exception(ctx, POWERPC_EXCP_VPU); \
364 return; \
365 } \
366 trans_##name0(ctx); \
367 } else if ((Rc(ctx->opcode) == 1) && \
368 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
369 gen_##name1(ctx); \
370 } else { \
371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
372 } \
373 }
375 /* Adds support to provide invalid mask */
376 #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
377 name1, flg1, flg2_1, inval1) \
378 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
379 { \
380 if ((Rc(ctx->opcode) == 0) && \
381 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
382 !(ctx->opcode & inval0)) { \
383 gen_##name0(ctx); \
384 } else if ((Rc(ctx->opcode) == 1) && \
385 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
386 !(ctx->opcode & inval1)) { \
387 gen_##name1(ctx); \
388 } else { \
389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
390 } \
391 }
393 #define GEN_VXFORM_HETRO(name, opc2, opc3) \
394 static void glue(gen_, name)(DisasContext *ctx) \
395 { \
396 TCGv_ptr rb; \
397 if (unlikely(!ctx->altivec_enabled)) { \
398 gen_exception(ctx, POWERPC_EXCP_VPU); \
399 return; \
400 } \
401 rb = gen_avr_ptr(rB(ctx->opcode)); \
402 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
403 tcg_temp_free_ptr(rb); \
404 }
406 GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
407 GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
408 vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
409 GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
410 GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
411 vmul10ecuq, PPC_NONE, PPC2_ISA300)
412 GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
413 GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
414 GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
415 GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
416 GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
417 GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
418 GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
419 GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
420 GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
421 GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
422 GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
423 GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
424 GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
425 GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
426 GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
427 GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
428 GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
429 GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
430 GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
431 GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
432 GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
433 GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
434 GEN_VXFORM(vavgub, 1, 16);
435 GEN_VXFORM(vabsdub, 1, 16);
436 GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
437 vabsdub, PPC_NONE, PPC2_ISA300)
438 GEN_VXFORM(vavguh, 1, 17);
439 GEN_VXFORM(vabsduh, 1, 17);
440 GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
441 vabsduh, PPC_NONE, PPC2_ISA300)
442 GEN_VXFORM(vavguw, 1, 18);
443 GEN_VXFORM(vabsduw, 1, 18);
444 GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
445 vabsduw, PPC_NONE, PPC2_ISA300)
446 GEN_VXFORM(vavgsb, 1, 20);
447 GEN_VXFORM(vavgsh, 1, 21);
448 GEN_VXFORM(vavgsw, 1, 22);
449 GEN_VXFORM(vmrghb, 6, 0);
450 GEN_VXFORM(vmrghh, 6, 1);
451 GEN_VXFORM(vmrghw, 6, 2);
452 GEN_VXFORM(vmrglb, 6, 4);
453 GEN_VXFORM(vmrglh, 6, 5);
454 GEN_VXFORM(vmrglw, 6, 6);
456 static void trans_vmrgew(DisasContext *ctx)
457 {
458 int VT = rD(ctx->opcode);
459 int VA = rA(ctx->opcode);
460 int VB = rB(ctx->opcode);
461 TCGv_i64 tmp = tcg_temp_new_i64();
462 TCGv_i64 avr = tcg_temp_new_i64();
464 get_avr64(avr, VB, true);
465 tcg_gen_shri_i64(tmp, avr, 32);
466 get_avr64(avr, VA, true);
467 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
468 set_avr64(VT, avr, true);
470 get_avr64(avr, VB, false);
471 tcg_gen_shri_i64(tmp, avr, 32);
472 get_avr64(avr, VA, false);
473 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
474 set_avr64(VT, avr, false);
476 tcg_temp_free_i64(tmp);
477 tcg_temp_free_i64(avr);
478 }
480 static void trans_vmrgow(DisasContext *ctx)
481 {
482 int VT = rD(ctx->opcode);
483 int VA = rA(ctx->opcode);
484 int VB = rB(ctx->opcode);
485 TCGv_i64 t0 = tcg_temp_new_i64();
486 TCGv_i64 t1 = tcg_temp_new_i64();
487 TCGv_i64 avr = tcg_temp_new_i64();
489 get_avr64(t0, VB, true);
490 get_avr64(t1, VA, true);
491 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
492 set_avr64(VT, avr, true);
494 get_avr64(t0, VB, false);
495 get_avr64(t1, VA, false);
496 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
497 set_avr64(VT, avr, false);
499 tcg_temp_free_i64(t0);
500 tcg_temp_free_i64(t1);
501 tcg_temp_free_i64(avr);
502 }
504 /*
505 * lvsl VRT,RA,RB - Load Vector for Shift Left
506 *
507 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
508 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
509 * Bytes sh:sh+15 of X are placed into vD.
510 */
511 static void trans_lvsl(DisasContext *ctx)
512 {
513 int VT = rD(ctx->opcode);
514 TCGv_i64 result = tcg_temp_new_i64();
515 TCGv_i64 sh = tcg_temp_new_i64();
516 TCGv EA = tcg_temp_new();
518 /* Get sh(from description) by anding EA with 0xf. */
519 gen_addr_reg_index(ctx, EA);
520 tcg_gen_extu_tl_i64(sh, EA);
521 tcg_gen_andi_i64(sh, sh, 0xfULL);
523 /*
524 * Create bytes sh:sh+7 of X(from description) and place them in
525 * higher doubleword of vD.
526 */
527 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
528 tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
529 set_avr64(VT, result, true);
530 /*
531 * Create bytes sh+8:sh+15 of X(from description) and place them in
532 * lower doubleword of vD.
533 */
534 tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
535 set_avr64(VT, result, false);
537 tcg_temp_free_i64(result);
538 tcg_temp_free_i64(sh);
539 tcg_temp_free(EA);
540 }
542 /*
543 * lvsr VRT,RA,RB - Load Vector for Shift Right
544 *
545 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
546 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
547 * Bytes (16-sh):(31-sh) of X are placed into vD.
548 */
549 static void trans_lvsr(DisasContext *ctx)
550 {
551 int VT = rD(ctx->opcode);
552 TCGv_i64 result = tcg_temp_new_i64();
553 TCGv_i64 sh = tcg_temp_new_i64();
554 TCGv EA = tcg_temp_new();
557 /* Get sh(from description) by anding EA with 0xf. */
558 gen_addr_reg_index(ctx, EA);
559 tcg_gen_extu_tl_i64(sh, EA);
560 tcg_gen_andi_i64(sh, sh, 0xfULL);
562 /*
563 * Create bytes (16-sh):(23-sh) of X(from description) and place them in
564 * higher doubleword of vD.
565 */
566 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
567 tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
568 set_avr64(VT, result, true);
569 /*
570 * Create bytes (24-sh):(32-sh) of X(from description) and place them in
571 * lower doubleword of vD.
572 */
573 tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
574 set_avr64(VT, result, false);
576 tcg_temp_free_i64(result);
577 tcg_temp_free_i64(sh);
578 tcg_temp_free(EA);
579 }
581 /*
582 * vsl VRT,VRA,VRB - Vector Shift Left
583 *
584 * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
585 * Lowest 3 bits in each byte element of register vB must be identical or
586 * result is undefined.
587 */
588 static void trans_vsl(DisasContext *ctx)
589 {
590 int VT = rD(ctx->opcode);
591 int VA = rA(ctx->opcode);
592 int VB = rB(ctx->opcode);
593 TCGv_i64 avr = tcg_temp_new_i64();
594 TCGv_i64 sh = tcg_temp_new_i64();
595 TCGv_i64 carry = tcg_temp_new_i64();
596 TCGv_i64 tmp = tcg_temp_new_i64();
598 /* Place bits 125-127 of vB in 'sh'. */
599 get_avr64(avr, VB, false);
600 tcg_gen_andi_i64(sh, avr, 0x07ULL);
602 /*
603 * Save highest 'sh' bits of lower doubleword element of vA in variable
604 * 'carry' and perform shift on lower doubleword.
605 */
606 get_avr64(avr, VA, false);
607 tcg_gen_subfi_i64(tmp, 32, sh);
608 tcg_gen_shri_i64(carry, avr, 32);
609 tcg_gen_shr_i64(carry, carry, tmp);
610 tcg_gen_shl_i64(avr, avr, sh);
611 set_avr64(VT, avr, false);
613 /*
614 * Perform shift on higher doubleword element of vA and replace lowest
615 * 'sh' bits with 'carry'.
616 */
617 get_avr64(avr, VA, true);
618 tcg_gen_shl_i64(avr, avr, sh);
619 tcg_gen_or_i64(avr, avr, carry);
620 set_avr64(VT, avr, true);
622 tcg_temp_free_i64(avr);
623 tcg_temp_free_i64(sh);
624 tcg_temp_free_i64(carry);
625 tcg_temp_free_i64(tmp);
626 }
628 /*
629 * vsr VRT,VRA,VRB - Vector Shift Right
630 *
631 * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
632 * Lowest 3 bits in each byte element of register vB must be identical or
633 * result is undefined.
634 */
635 static void trans_vsr(DisasContext *ctx)
636 {
637 int VT = rD(ctx->opcode);
638 int VA = rA(ctx->opcode);
639 int VB = rB(ctx->opcode);
640 TCGv_i64 avr = tcg_temp_new_i64();
641 TCGv_i64 sh = tcg_temp_new_i64();
642 TCGv_i64 carry = tcg_temp_new_i64();
643 TCGv_i64 tmp = tcg_temp_new_i64();
645 /* Place bits 125-127 of vB in 'sh'. */
646 get_avr64(avr, VB, false);
647 tcg_gen_andi_i64(sh, avr, 0x07ULL);
649 /*
650 * Save lowest 'sh' bits of higher doubleword element of vA in variable
651 * 'carry' and perform shift on higher doubleword.
652 */
653 get_avr64(avr, VA, true);
654 tcg_gen_subfi_i64(tmp, 32, sh);
655 tcg_gen_shli_i64(carry, avr, 32);
656 tcg_gen_shl_i64(carry, carry, tmp);
657 tcg_gen_shr_i64(avr, avr, sh);
658 set_avr64(VT, avr, true);
659 /*
660 * Perform shift on lower doubleword element of vA and replace highest
661 * 'sh' bits with 'carry'.
662 */
663 get_avr64(avr, VA, false);
664 tcg_gen_shr_i64(avr, avr, sh);
665 tcg_gen_or_i64(avr, avr, carry);
666 set_avr64(VT, avr, false);
668 tcg_temp_free_i64(avr);
669 tcg_temp_free_i64(sh);
670 tcg_temp_free_i64(carry);
671 tcg_temp_free_i64(tmp);
672 }
674 /*
675 * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
676 *
677 * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
678 * register are concatenated and placed into ith byte of appropriate doubleword
679 * element in destination register.
680 *
681 * Following solution is done for both doubleword elements of source register
682 * in parallel, in order to reduce the number of instructions needed(that's why
683 * arrays are used):
684 * First, both doubleword elements of source register vB are placed in
685 * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
686 * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
687 * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
688 * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
689 * have to be shifted right for 7 and 8 places, respectively, in order to get
690 * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
691 * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
692 * After first 8 iteration(first loop), all the first bits are in their final
693 * places, all second bits but second bit from eight byte are in their places...
694 * only 1 eight bit from eight byte is in it's place). In second loop we do all
695 * operations symmetrically, in order to get other half of bits in their final
696 * spots. Results for first and second doubleword elements are saved in
697 * result[0] and result[1] respectively. In the end those results are saved in
698 * appropriate doubleword element of destination register vD.
699 */
700 static void trans_vgbbd(DisasContext *ctx)
701 {
702 int VT = rD(ctx->opcode);
703 int VB = rB(ctx->opcode);
704 TCGv_i64 tmp = tcg_temp_new_i64();
705 uint64_t mask = 0x8040201008040201ULL;
706 int i, j;
708 TCGv_i64 result[2];
709 result[0] = tcg_temp_new_i64();
710 result[1] = tcg_temp_new_i64();
711 TCGv_i64 avr[2];
712 avr[0] = tcg_temp_new_i64();
713 avr[1] = tcg_temp_new_i64();
714 TCGv_i64 tcg_mask = tcg_temp_new_i64();
716 tcg_gen_movi_i64(tcg_mask, mask);
717 for (j = 0; j < 2; j++) {
718 get_avr64(avr[j], VB, j);
719 tcg_gen_and_i64(result[j], avr[j], tcg_mask);
720 }
721 for (i = 1; i < 8; i++) {
722 tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
723 for (j = 0; j < 2; j++) {
724 tcg_gen_shri_i64(tmp, avr[j], i * 7);
725 tcg_gen_and_i64(tmp, tmp, tcg_mask);
726 tcg_gen_or_i64(result[j], result[j], tmp);
727 }
728 }
729 for (i = 1; i < 8; i++) {
730 tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
731 for (j = 0; j < 2; j++) {
732 tcg_gen_shli_i64(tmp, avr[j], i * 7);
733 tcg_gen_and_i64(tmp, tmp, tcg_mask);
734 tcg_gen_or_i64(result[j], result[j], tmp);
735 }
736 }
737 for (j = 0; j < 2; j++) {
738 set_avr64(VT, result[j], j);
739 }
741 tcg_temp_free_i64(tmp);
742 tcg_temp_free_i64(tcg_mask);
743 tcg_temp_free_i64(result[0]);
744 tcg_temp_free_i64(result[1]);
745 tcg_temp_free_i64(avr[0]);
746 tcg_temp_free_i64(avr[1]);
747 }
749 /*
750 * vclzw VRT,VRB - Vector Count Leading Zeros Word
751 *
752 * Counting the number of leading zero bits of each word element in source
753 * register and placing result in appropriate word element of destination
754 * register.
755 */
756 static void trans_vclzw(DisasContext *ctx)
757 {
758 int VT = rD(ctx->opcode);
759 int VB = rB(ctx->opcode);
760 TCGv_i32 tmp = tcg_temp_new_i32();
761 int i;
763 /* Perform count for every word element using tcg_gen_clzi_i32. */
764 for (i = 0; i < 4; i++) {
765 tcg_gen_ld_i32(tmp, cpu_env,
766 offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
767 tcg_gen_clzi_i32(tmp, tmp, 32);
768 tcg_gen_st_i32(tmp, cpu_env,
769 offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
770 }
772 tcg_temp_free_i32(tmp);
773 }
775 /*
776 * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
777 *
778 * Counting the number of leading zero bits of each doubleword element in source
779 * register and placing result in appropriate doubleword element of destination
780 * register.
781 */
782 static void trans_vclzd(DisasContext *ctx)
783 {
784 int VT = rD(ctx->opcode);
785 int VB = rB(ctx->opcode);
786 TCGv_i64 avr = tcg_temp_new_i64();
788 /* high doubleword */
789 get_avr64(avr, VB, true);
790 tcg_gen_clzi_i64(avr, avr, 64);
791 set_avr64(VT, avr, true);
793 /* low doubleword */
794 get_avr64(avr, VB, false);
795 tcg_gen_clzi_i64(avr, avr, 64);
796 set_avr64(VT, avr, false);
798 tcg_temp_free_i64(avr);
799 }
801 GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
802 GEN_VXFORM(vrlwnm, 2, 6);
803 GEN_VXFORM(vsrv, 2, 28);
804 GEN_VXFORM(vslv, 2, 29);
805 GEN_VXFORM(vslo, 6, 16);
806 GEN_VXFORM(vsro, 6, 17);
807 GEN_VXFORM(vaddcuw, 0, 6);
808 GEN_VXFORM(vsubcuw, 0, 22);
810 static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
811 void (*gen_gvec)(unsigned, uint32_t, uint32_t,
812 uint32_t, uint32_t, uint32_t))
813 {
814 REQUIRE_VECTOR(ctx);
816 gen_gvec(vece, avr_full_offset(a->vrt), avr_full_offset(a->vra),
817 avr_full_offset(a->vrb), 16, 16);
819 return true;
820 }
822 TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv);
823 TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv);
824 TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv);
825 TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
827 TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv);
828 TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv);
829 TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv);
830 TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
832 TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv);
833 TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
834 TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
835 TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
837 static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
838 {
839 TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
841 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
842 REQUIRE_VECTOR(ctx);
844 n = tcg_temp_new_i64();
845 hi = tcg_temp_new_i64();
846 lo = tcg_temp_new_i64();
847 t0 = tcg_temp_new_i64();
849 get_avr64(lo, a->vra, false);
850 get_avr64(hi, a->vra, true);
852 get_avr64(n, a->vrb, true);
854 tcg_gen_andi_i64(t0, n, 64);
855 tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
856 tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
857 tcg_gen_andi_i64(n, n, 0x3F);
859 tcg_gen_shl_i64(t0, lo, n);
860 set_avr64(a->vrt, t0, false);
862 tcg_gen_shl_i64(hi, hi, n);
863 tcg_gen_xori_i64(n, n, 63);
864 tcg_gen_shr_i64(lo, lo, n);
865 tcg_gen_shri_i64(lo, lo, 1);
866 tcg_gen_or_i64(hi, hi, lo);
867 set_avr64(a->vrt, hi, true);
869 tcg_temp_free_i64(hi);
870 tcg_temp_free_i64(lo);
871 tcg_temp_free_i64(t0);
872 tcg_temp_free_i64(n);
874 return true;
875 }
877 #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
878 static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
879 TCGv_vec sat, TCGv_vec a, \
880 TCGv_vec b) \
881 { \
882 TCGv_vec x = tcg_temp_new_vec_matching(t); \
883 glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
884 glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
885 tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
886 tcg_gen_or_vec(VECE, sat, sat, x); \
887 tcg_temp_free_vec(x); \
888 } \
889 static void glue(gen_, NAME)(DisasContext *ctx) \
890 { \
891 static const TCGOpcode vecop_list[] = { \
892 glue(glue(INDEX_op_, NORM), _vec), \
893 glue(glue(INDEX_op_, SAT), _vec), \
894 INDEX_op_cmp_vec, 0 \
895 }; \
896 static const GVecGen4 g = { \
897 .fniv = glue(glue(gen_, NAME), _vec), \
898 .fno = glue(gen_helper_, NAME), \
899 .opt_opc = vecop_list, \
900 .write_aofs = true, \
901 .vece = VECE, \
902 }; \
903 if (unlikely(!ctx->altivec_enabled)) { \
904 gen_exception(ctx, POWERPC_EXCP_VPU); \
905 return; \
906 } \
907 tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
908 offsetof(CPUPPCState, vscr_sat), \
909 avr_full_offset(rA(ctx->opcode)), \
910 avr_full_offset(rB(ctx->opcode)), \
911 16, 16, &g); \
912 }
914 GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
915 GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
916 vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
917 GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
918 GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
919 vmul10euq, PPC_NONE, PPC2_ISA300)
920 GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
921 GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
922 GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
923 GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
924 GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
925 GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
926 GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
927 GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
928 GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
929 GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
930 GEN_VXFORM(vadduqm, 0, 4);
931 GEN_VXFORM(vaddcuq, 0, 5);
932 GEN_VXFORM3(vaddeuqm, 30, 0);
933 GEN_VXFORM3(vaddecuq, 30, 0);
934 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
935 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
936 GEN_VXFORM(vsubuqm, 0, 20);
937 GEN_VXFORM(vsubcuq, 0, 21);
938 GEN_VXFORM3(vsubeuqm, 31, 0);
939 GEN_VXFORM3(vsubecuq, 31, 0);
940 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
941 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
942 GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
943 GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
944 GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
945 GEN_VXFORM(vrlwmi, 2, 2);
946 GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
947 vrlwmi, PPC_NONE, PPC2_ISA300)
948 GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
949 GEN_VXFORM(vrldmi, 2, 3);
950 GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
951 vrldmi, PPC_NONE, PPC2_ISA300)
952 GEN_VXFORM_TRANS(vsl, 2, 7);
953 GEN_VXFORM(vrldnm, 2, 7);
954 GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
955 vrldnm, PPC_NONE, PPC2_ISA300)
956 GEN_VXFORM_TRANS(vsr, 2, 11);
957 GEN_VXFORM_ENV(vpkuhum, 7, 0);
958 GEN_VXFORM_ENV(vpkuwum, 7, 1);
959 GEN_VXFORM_ENV(vpkudum, 7, 17);
960 GEN_VXFORM_ENV(vpkuhus, 7, 2);
961 GEN_VXFORM_ENV(vpkuwus, 7, 3);
962 GEN_VXFORM_ENV(vpkudus, 7, 19);
963 GEN_VXFORM_ENV(vpkshus, 7, 4);
964 GEN_VXFORM_ENV(vpkswus, 7, 5);
965 GEN_VXFORM_ENV(vpksdus, 7, 21);
966 GEN_VXFORM_ENV(vpkshss, 7, 6);
967 GEN_VXFORM_ENV(vpkswss, 7, 7);
968 GEN_VXFORM_ENV(vpksdss, 7, 23);
969 GEN_VXFORM(vpkpx, 7, 12);
970 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
971 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
972 GEN_VXFORM_ENV(vsum4shs, 4, 25);
973 GEN_VXFORM_ENV(vsum2sws, 4, 26);
974 GEN_VXFORM_ENV(vsumsws, 4, 30);
975 GEN_VXFORM_ENV(vaddfp, 5, 0);
976 GEN_VXFORM_ENV(vsubfp, 5, 1);
977 GEN_VXFORM_ENV(vmaxfp, 5, 16);
978 GEN_VXFORM_ENV(vminfp, 5, 17);
979 GEN_VXFORM_HETRO(vextublx, 6, 24)
980 GEN_VXFORM_HETRO(vextuhlx, 6, 25)
981 GEN_VXFORM_HETRO(vextuwlx, 6, 26)
982 GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
983 vextuwlx, PPC_NONE, PPC2_ISA300)
984 GEN_VXFORM_HETRO(vextubrx, 6, 28)
985 GEN_VXFORM_HETRO(vextuhrx, 6, 29)
986 GEN_VXFORM_HETRO(vextuwrx, 6, 30)
987 GEN_VXFORM_TRANS(lvsl, 6, 31)
988 GEN_VXFORM_TRANS(lvsr, 6, 32)
989 GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
990 vextuwrx, PPC_NONE, PPC2_ISA300)
992 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
993 static void glue(gen_, name)(DisasContext *ctx) \
994 { \
995 TCGv_ptr ra, rb, rd; \
996 if (unlikely(!ctx->altivec_enabled)) { \
997 gen_exception(ctx, POWERPC_EXCP_VPU); \
998 return; \
999 } \
1000 ra = gen_avr_ptr(rA(ctx->opcode)); \
1001 rb = gen_avr_ptr(rB(ctx->opcode)); \
1002 rd = gen_avr_ptr(rD(ctx->opcode)); \
1003 gen_helper_##opname(cpu_env, rd, ra, rb); \
1004 tcg_temp_free_ptr(ra); \
1005 tcg_temp_free_ptr(rb); \
1006 tcg_temp_free_ptr(rd); \
1007 }
1009 #define GEN_VXRFORM(name, opc2, opc3) \
1010 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
1011 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
1013 /*
1014 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
1015 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
1016 * come from different versions of the ISA, so we must also support a
1017 * pair of flags for each instruction.
1018 */
1019 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
1020 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
1021 { \
1022 if ((Rc(ctx->opcode) == 0) && \
1023 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
1024 if (Rc21(ctx->opcode) == 0) { \
1025 gen_##name0(ctx); \
1026 } else { \
1027 gen_##name0##_(ctx); \
1028 } \
1029 } else if ((Rc(ctx->opcode) == 1) && \
1030 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
1031 if (Rc21(ctx->opcode) == 0) { \
1032 gen_##name1(ctx); \
1033 } else { \
1034 gen_##name1##_(ctx); \
1035 } \
1036 } else { \
1037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
1038 } \
1039 }
1041 static void do_vcmp_rc(int vrt)
1042 {
1043 TCGv_i64 tmp, set, clr;
1045 tmp = tcg_temp_new_i64();
1046 set = tcg_temp_new_i64();
1047 clr = tcg_temp_new_i64();
1049 get_avr64(tmp, vrt, true);
1050 tcg_gen_mov_i64(set, tmp);
1051 get_avr64(tmp, vrt, false);
1052 tcg_gen_or_i64(clr, set, tmp);
1053 tcg_gen_and_i64(set, set, tmp);
1055 tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1056 tcg_gen_shli_i64(clr, clr, 1);
1058 tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
1059 tcg_gen_shli_i64(set, set, 3);
1061 tcg_gen_or_i64(tmp, set, clr);
1062 tcg_gen_extrl_i64_i32(cpu_crf[6], tmp);
1064 tcg_temp_free_i64(tmp);
1065 tcg_temp_free_i64(set);
1066 tcg_temp_free_i64(clr);
1067 }
1069 static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
1070 {
1071 REQUIRE_VECTOR(ctx);
1073 tcg_gen_gvec_cmp(cond, vece, avr_full_offset(a->vrt),
1074 avr_full_offset(a->vra), avr_full_offset(a->vrb), 16, 16);
1076 if (a->rc) {
1077 do_vcmp_rc(a->vrt);
1078 }
1080 return true;
1081 }
1083 TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
1084 TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
1085 TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
1086 TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1088 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
1089 TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
1090 TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
1091 TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1092 TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
1093 TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
1094 TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
1095 TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
1097 TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
1098 TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
1099 TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
1101 static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1102 {
1103 TCGv_vec t0, t1, zero;
1105 t0 = tcg_temp_new_vec_matching(t);
1106 t1 = tcg_temp_new_vec_matching(t);
1107 zero = tcg_constant_vec_matching(t, vece, 0);
1109 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
1110 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
1111 tcg_gen_cmp_vec(TCG_COND_NE, vece, t, a, b);
1113 tcg_gen_or_vec(vece, t, t, t0);
1114 tcg_gen_or_vec(vece, t, t, t1);
1116 tcg_temp_free_vec(t0);
1117 tcg_temp_free_vec(t1);
1118 }
1120 static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece)
1121 {
1122 static const TCGOpcode vecop_list[] = {
1123 INDEX_op_cmp_vec, 0
1124 };
1125 static const GVecGen3 ops[3] = {
1126 {
1127 .fniv = gen_vcmpnez_vec,
1128 .fno = gen_helper_VCMPNEZB,
1129 .opt_opc = vecop_list,
1130 .vece = MO_8
1131 },
1132 {
1133 .fniv = gen_vcmpnez_vec,
1134 .fno = gen_helper_VCMPNEZH,
1135 .opt_opc = vecop_list,
1136 .vece = MO_16
1137 },
1138 {
1139 .fniv = gen_vcmpnez_vec,
1140 .fno = gen_helper_VCMPNEZW,
1141 .opt_opc = vecop_list,
1142 .vece = MO_32
1143 }
1144 };
1146 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1147 REQUIRE_VECTOR(ctx);
1149 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
1150 avr_full_offset(a->vrb), 16, 16, &ops[vece]);
1152 if (a->rc) {
1153 do_vcmp_rc(a->vrt);
1154 }
1156 return true;
1157 }
1159 TRANS(VCMPNEZB, do_vcmpnez, MO_8)
1160 TRANS(VCMPNEZH, do_vcmpnez, MO_16)
1161 TRANS(VCMPNEZW, do_vcmpnez, MO_32)
1163 static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
1164 {
1165 TCGv_i64 t0, t1, t2;
1167 t0 = tcg_temp_new_i64();
1168 t1 = tcg_temp_new_i64();
1169 t2 = tcg_temp_new_i64();
1171 get_avr64(t0, a->vra, true);
1172 get_avr64(t1, a->vrb, true);
1173 tcg_gen_xor_i64(t2, t0, t1);
1175 get_avr64(t0, a->vra, false);
1176 get_avr64(t1, a->vrb, false);
1177 tcg_gen_xor_i64(t1, t0, t1);
1179 tcg_gen_or_i64(t1, t1, t2);
1180 tcg_gen_setcondi_i64(TCG_COND_EQ, t1, t1, 0);
1181 tcg_gen_neg_i64(t1, t1);
1183 set_avr64(a->vrt, t1, true);
1184 set_avr64(a->vrt, t1, false);
1186 if (a->rc) {
1187 tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
1188 tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
1189 tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
1190 }
1192 tcg_temp_free_i64(t0);
1193 tcg_temp_free_i64(t1);
1194 tcg_temp_free_i64(t2);
1196 return true;
1197 }
1199 static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
1200 {
1201 TCGv_i64 t0, t1, t2;
1203 t0 = tcg_temp_new_i64();
1204 t1 = tcg_temp_new_i64();
1205 t2 = tcg_temp_new_i64();
1207 get_avr64(t0, a->vra, false);
1208 get_avr64(t1, a->vrb, false);
1209 tcg_gen_setcond_i64(TCG_COND_GTU, t2, t0, t1);
1211 get_avr64(t0, a->vra, true);
1212 get_avr64(t1, a->vrb, true);
1213 tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0));
1214 tcg_gen_setcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1);
1216 tcg_gen_or_i64(t1, t1, t2);
1217 tcg_gen_neg_i64(t1, t1);
1219 set_avr64(a->vrt, t1, true);
1220 set_avr64(a->vrt, t1, false);
1222 if (a->rc) {
1223 tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
1224 tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
1225 tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
1226 }
1228 tcg_temp_free_i64(t0);
1229 tcg_temp_free_i64(t1);
1230 tcg_temp_free_i64(t2);
1232 return true;
1233 }
1235 TRANS(VCMPGTSQ, do_vcmpgtq, true)
1236 TRANS(VCMPGTUQ, do_vcmpgtq, false)
1238 static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
1239 {
1240 TCGv_i64 vra, vrb;
1241 TCGLabel *gt, *lt, *done;
1243 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1244 REQUIRE_VECTOR(ctx);
1246 vra = tcg_temp_local_new_i64();
1247 vrb = tcg_temp_local_new_i64();
1248 gt = gen_new_label();
1249 lt = gen_new_label();
1250 done = gen_new_label();
1252 get_avr64(vra, a->vra, true);
1253 get_avr64(vrb, a->vrb, true);
1254 tcg_gen_brcond_i64((sign ? TCG_COND_GT : TCG_COND_GTU), vra, vrb, gt);
1255 tcg_gen_brcond_i64((sign ? TCG_COND_LT : TCG_COND_LTU), vra, vrb, lt);
1257 get_avr64(vra, a->vra, false);
1258 get_avr64(vrb, a->vrb, false);
1259 tcg_gen_brcond_i64(TCG_COND_GTU, vra, vrb, gt);
1260 tcg_gen_brcond_i64(TCG_COND_LTU, vra, vrb, lt);
1262 tcg_gen_movi_i32(cpu_crf[a->bf], CRF_EQ);
1263 tcg_gen_br(done);
1265 gen_set_label(gt);
1266 tcg_gen_movi_i32(cpu_crf[a->bf], CRF_GT);
1267 tcg_gen_br(done);
1269 gen_set_label(lt);
1270 tcg_gen_movi_i32(cpu_crf[a->bf], CRF_LT);
1271 tcg_gen_br(done);
1273 gen_set_label(done);
1274 tcg_temp_free_i64(vra);
1275 tcg_temp_free_i64(vrb);
1277 return true;
1278 }
1280 TRANS(VCMPSQ, do_vcmpq, true)
1281 TRANS(VCMPUQ, do_vcmpq, false)
1283 GEN_VXRFORM(vcmpeqfp, 3, 3)
1284 GEN_VXRFORM(vcmpgefp, 3, 7)
1285 GEN_VXRFORM(vcmpgtfp, 3, 11)
1286 GEN_VXRFORM(vcmpbfp, 3, 15)
1288 static void gen_vsplti(DisasContext *ctx, int vece)
1289 {
1290 int simm;
1292 if (unlikely(!ctx->altivec_enabled)) {
1293 gen_exception(ctx, POWERPC_EXCP_VPU);
1294 return;
1295 }
1297 simm = SIMM5(ctx->opcode);
1298 tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
1299 }
1301 #define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
1302 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
1304 GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
1305 GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
1306 GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
1308 #define GEN_VXFORM_NOA(name, opc2, opc3) \
1309 static void glue(gen_, name)(DisasContext *ctx) \
1310 { \
1311 TCGv_ptr rb, rd; \
1312 if (unlikely(!ctx->altivec_enabled)) { \
1313 gen_exception(ctx, POWERPC_EXCP_VPU); \
1314 return; \
1315 } \
1316 rb = gen_avr_ptr(rB(ctx->opcode)); \
1317 rd = gen_avr_ptr(rD(ctx->opcode)); \
1318 gen_helper_##name(rd, rb); \
1319 tcg_temp_free_ptr(rb); \
1320 tcg_temp_free_ptr(rd); \
1321 }
1323 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
1324 static void glue(gen_, name)(DisasContext *ctx) \
1325 { \
1326 TCGv_ptr rb, rd; \
1327 \
1328 if (unlikely(!ctx->altivec_enabled)) { \
1329 gen_exception(ctx, POWERPC_EXCP_VPU); \
1330 return; \
1331 } \
1332 rb = gen_avr_ptr(rB(ctx->opcode)); \
1333 rd = gen_avr_ptr(rD(ctx->opcode)); \
1334 gen_helper_##name(cpu_env, rd, rb); \
1335 tcg_temp_free_ptr(rb); \
1336 tcg_temp_free_ptr(rd); \
1337 }
1339 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
1340 static void glue(gen_, name)(DisasContext *ctx) \
1341 { \
1342 TCGv_ptr rb, rd; \
1343 if (unlikely(!ctx->altivec_enabled)) { \
1344 gen_exception(ctx, POWERPC_EXCP_VPU); \
1345 return; \
1346 } \
1347 rb = gen_avr_ptr(rB(ctx->opcode)); \
1348 rd = gen_avr_ptr(rD(ctx->opcode)); \
1349 gen_helper_##name(rd, rb); \
1350 tcg_temp_free_ptr(rb); \
1351 tcg_temp_free_ptr(rd); \
1352 }
1354 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
1355 static void glue(gen_, name)(DisasContext *ctx) \
1356 { \
1357 TCGv_ptr rb; \
1358 if (unlikely(!ctx->altivec_enabled)) { \
1359 gen_exception(ctx, POWERPC_EXCP_VPU); \
1360 return; \
1361 } \
1362 rb = gen_avr_ptr(rB(ctx->opcode)); \
1363 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
1364 tcg_temp_free_ptr(rb); \
1365 }
1366 GEN_VXFORM_NOA(vupkhsb, 7, 8);
1367 GEN_VXFORM_NOA(vupkhsh, 7, 9);
1368 GEN_VXFORM_NOA(vupkhsw, 7, 25);
1369 GEN_VXFORM_NOA(vupklsb, 7, 10);
1370 GEN_VXFORM_NOA(vupklsh, 7, 11);
1371 GEN_VXFORM_NOA(vupklsw, 7, 27);
1372 GEN_VXFORM_NOA(vupkhpx, 7, 13);
1373 GEN_VXFORM_NOA(vupklpx, 7, 15);
1374 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
1375 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
1376 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
1377 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
1378 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
1379 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
1380 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
1381 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
1382 GEN_VXFORM_NOA(vprtybw, 1, 24);
1383 GEN_VXFORM_NOA(vprtybd, 1, 24);
1384 GEN_VXFORM_NOA(vprtybq, 1, 24);
1386 static void gen_vsplt(DisasContext *ctx, int vece)
1387 {
1388 int uimm, dofs, bofs;
1390 if (unlikely(!ctx->altivec_enabled)) {
1391 gen_exception(ctx, POWERPC_EXCP_VPU);
1392 return;
1393 }
1395 uimm = UIMM5(ctx->opcode);
1396 bofs = avr_full_offset(rB(ctx->opcode));
1397 dofs = avr_full_offset(rD(ctx->opcode));
1399 /* Experimental testing shows that hardware masks the immediate. */
1400 bofs += (uimm << vece) & 15;
1401 #ifndef HOST_WORDS_BIGENDIAN
1402 bofs ^= 15;
1403 bofs &= ~((1 << vece) - 1);
1404 #endif
1406 tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
1407 }
1409 #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
1410 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
1412 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
1413 static void glue(gen_, name)(DisasContext *ctx) \
1414 { \
1415 TCGv_ptr rb, rd; \
1416 TCGv_i32 uimm; \
1417 \
1418 if (unlikely(!ctx->altivec_enabled)) { \
1419 gen_exception(ctx, POWERPC_EXCP_VPU); \
1420 return; \
1421 } \
1422 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
1423 rb = gen_avr_ptr(rB(ctx->opcode)); \
1424 rd = gen_avr_ptr(rD(ctx->opcode)); \
1425 gen_helper_##name(cpu_env, rd, rb, uimm); \
1426 tcg_temp_free_i32(uimm); \
1427 tcg_temp_free_ptr(rb); \
1428 tcg_temp_free_ptr(rd); \
1429 }
1431 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
1432 static void glue(gen_, name)(DisasContext *ctx) \
1433 { \
1434 TCGv_ptr rb, rd; \
1435 uint8_t uimm = UIMM4(ctx->opcode); \
1436 TCGv_i32 t0; \
1437 if (unlikely(!ctx->altivec_enabled)) { \
1438 gen_exception(ctx, POWERPC_EXCP_VPU); \
1439 return; \
1440 } \
1441 if (uimm > splat_max) { \
1442 uimm = 0; \
1443 } \
1444 t0 = tcg_temp_new_i32(); \
1445 tcg_gen_movi_i32(t0, uimm); \
1446 rb = gen_avr_ptr(rB(ctx->opcode)); \
1447 rd = gen_avr_ptr(rD(ctx->opcode)); \
1448 gen_helper_##name(rd, rb, t0); \
1449 tcg_temp_free_i32(t0); \
1450 tcg_temp_free_ptr(rb); \
1451 tcg_temp_free_ptr(rd); \
1452 }
1454 GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
1455 GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
1456 GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
1457 GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
1458 GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
1459 GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
1460 GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
1461 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
1462 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
1463 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
1464 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
1465 GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
1466 vextractub, PPC_NONE, PPC2_ISA300);
1467 GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
1468 vextractuh, PPC_NONE, PPC2_ISA300);
1469 GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
1470 vextractuw, PPC_NONE, PPC2_ISA300);
1472 static bool trans_VGNB(DisasContext *ctx, arg_VX_n *a)
1473 {
1474 /*
1475 * Similar to do_vextractm, we'll use a sequence of mask-shift-or operations
1476 * to gather the bits. The masks can be created with
1477 *
1478 * uint64_t mask(uint64_t n, uint64_t step)
1479 * {
1480 * uint64_t p = ((1UL << (1UL << step)) - 1UL) << ((n - 1UL) << step),
1481 * plen = n << step, m = 0;
1482 * for(int i = 0; i < 64/plen; i++) {
1483 * m |= p;
1484 * m = ror64(m, plen);
1485 * }
1486 * p >>= plen * DIV_ROUND_UP(64, plen) - 64;
1487 * return m | p;
1488 * }
1489 *
1490 * But since there are few values of N, we'll use a lookup table to avoid
1491 * these calculations at runtime.
1492 */
1493 static const uint64_t mask[6][5] = {
1494 {
1495 0xAAAAAAAAAAAAAAAAULL, 0xccccccccccccccccULL, 0xf0f0f0f0f0f0f0f0ULL,
1496 0xff00ff00ff00ff00ULL, 0xffff0000ffff0000ULL
1497 },
1498 {
1499 0x9249249249249249ULL, 0xC30C30C30C30C30CULL, 0xF00F00F00F00F00FULL,
1500 0xFF0000FF0000FF00ULL, 0xFFFF00000000FFFFULL
1501 },
1502 {
1503 /* For N >= 4, some mask operations can be elided */
1504 0x8888888888888888ULL, 0, 0xf000f000f000f000ULL, 0,
1505 0xFFFF000000000000ULL
1506 },
1507 {
1508 0x8421084210842108ULL, 0, 0xF0000F0000F0000FULL, 0, 0
1509 },
1510 {
1511 0x8208208208208208ULL, 0, 0xF00000F00000F000ULL, 0, 0
1512 },
1513 {
1514 0x8102040810204081ULL, 0, 0xF000000F000000F0ULL, 0, 0
1515 }
1516 };
1517 uint64_t m;
1518 int i, sh, nbits = DIV_ROUND_UP(64, a->n);
1519 TCGv_i64 hi, lo, t0, t1;
1521 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1522 REQUIRE_VECTOR(ctx);
1524 if (a->n < 2) {
1525 /*
1526 * "N can be any value between 2 and 7, inclusive." Otherwise, the
1527 * result is undefined, so we don't need to change RT. Also, N > 7 is
1528 * impossible since the immediate field is 3 bits only.
1529 */
1530 return true;
1531 }
1533 hi = tcg_temp_new_i64();
1534 lo = tcg_temp_new_i64();
1535 t0 = tcg_temp_new_i64();
1536 t1 = tcg_temp_new_i64();
1538 get_avr64(hi, a->vrb, true);
1539 get_avr64(lo, a->vrb, false);
1541 /* Align the lower doubleword so we can use the same mask */
1542 tcg_gen_shli_i64(lo, lo, a->n * nbits - 64);
1544 /*
1545 * Starting from the most significant bit, gather every Nth bit with a
1546 * sequence of mask-shift-or operation. E.g.: for N=3
1547 * AxxBxxCxxDxxExxFxxGxxHxxIxxJxxKxxLxxMxxNxxOxxPxxQxxRxxSxxTxxUxxV
1548 * & rep(0b100)
1549 * A..B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V
1550 * << 2
1551 * .B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V..
1552 * |
1553 * AB.BC.CD.DE.EF.FG.GH.HI.IJ.JK.KL.LM.MN.NO.OP.PQ.QR.RS.ST.TU.UV.V
1554 * & rep(0b110000)
1555 * AB....CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV..
1556 * << 4
1557 * ..CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV......
1558 * |
1559 * ABCD..CDEF..EFGH..GHIJ..IJKL..KLMN..MNOP..OPQR..QRST..STUV..UV..
1560 * & rep(0b111100000000)
1561 * ABCD........EFGH........IJKL........MNOP........QRST........UV..
1562 * << 8
1563 * ....EFGH........IJKL........MNOP........QRST........UV..........
1564 * |
1565 * ABCDEFGH....EFGHIJKL....IJKLMNOP....MNOPQRST....QRSTUV......UV..
1566 * & rep(0b111111110000000000000000)
1567 * ABCDEFGH................IJKLMNOP................QRSTUV..........
1568 * << 16
1569 * ........IJKLMNOP................QRSTUV..........................
1570 * |
1571 * ABCDEFGHIJKLMNOP........IJKLMNOPQRSTUV..........QRSTUV..........
1572 * & rep(0b111111111111111100000000000000000000000000000000)
1573 * ABCDEFGHIJKLMNOP................................QRSTUV..........
1574 * << 32
1575 * ................QRSTUV..........................................
1576 * |
1577 * ABCDEFGHIJKLMNOPQRSTUV..........................QRSTUV..........
1578 */
1579 for (i = 0, sh = a->n - 1; i < 5; i++, sh <<= 1) {
1580 m = mask[a->n - 2][i];
1581 if (m) {
1582 tcg_gen_andi_i64(hi, hi, m);
1583 tcg_gen_andi_i64(lo, lo, m);
1584 }
1585 if (sh < 64) {
1586 tcg_gen_shli_i64(t0, hi, sh);
1587 tcg_gen_shli_i64(t1, lo, sh);
1588 tcg_gen_or_i64(hi, t0, hi);
1589 tcg_gen_or_i64(lo, t1, lo);
1590 }
1591 }
1593 tcg_gen_andi_i64(hi, hi, ~(~0ULL >> nbits));
1594 tcg_gen_andi_i64(lo, lo, ~(~0ULL >> nbits));
1595 tcg_gen_shri_i64(lo, lo, nbits);
1596 tcg_gen_or_i64(hi, hi, lo);
1597 tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], hi);
1599 tcg_temp_free_i64(hi);
1600 tcg_temp_free_i64(lo);
1601 tcg_temp_free_i64(t0);
1602 tcg_temp_free_i64(t1);
1604 return true;
1605 }
1607 static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
1608 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
1609 {
1610 TCGv_ptr vrt, vra, vrb;
1611 TCGv rc;
1613 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1614 REQUIRE_VECTOR(ctx);
1616 vrt = gen_avr_ptr(a->vrt);
1617 vra = gen_avr_ptr(a->vra);
1618 vrb = gen_avr_ptr(a->vrb);
1619 rc = tcg_temp_new();
1621 tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
1622 if (right) {
1623 tcg_gen_subfi_tl(rc, 32 - size, rc);
1624 }
1625 gen_helper(cpu_env, vrt, vra, vrb, rc);
1627 tcg_temp_free_ptr(vrt);
1628 tcg_temp_free_ptr(vra);
1629 tcg_temp_free_ptr(vrb);
1630 tcg_temp_free(rc);
1631 return true;
1632 }
1634 TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
1635 TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
1636 TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
1637 TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
1639 TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
1640 TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
1641 TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
1642 TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
1644 static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1645 TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1646 {
1647 TCGv_ptr t;
1648 TCGv idx;
1650 t = gen_avr_ptr(vrt);
1651 idx = tcg_temp_new();
1653 tcg_gen_andi_tl(idx, ra, 0xF);
1654 if (right) {
1655 tcg_gen_subfi_tl(idx, 16 - size, idx);
1656 }
1658 gen_helper(cpu_env, t, rb, idx);
1660 tcg_temp_free_ptr(t);
1661 tcg_temp_free(idx);
1663 return true;
1664 }
1666 static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1667 int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1668 {
1669 bool ok;
1670 TCGv_i64 val;
1672 val = tcg_temp_new_i64();
1673 get_avr64(val, vrb, true);
1674 ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
1676 tcg_temp_free_i64(val);
1677 return ok;
1678 }
1680 static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1681 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1682 {
1683 bool ok;
1684 TCGv_i64 val;
1686 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1687 REQUIRE_VECTOR(ctx);
1689 val = tcg_temp_new_i64();
1690 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1692 ok = do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_helper);
1694 tcg_temp_free_i64(val);
1695 return ok;
1696 }
1698 static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1699 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1700 {
1701 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1702 REQUIRE_VECTOR(ctx);
1704 return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
1705 gen_helper);
1706 }
1708 static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1709 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1710 {
1711 bool ok;
1712 TCGv_i64 val;
1714 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1715 REQUIRE_VECTOR(ctx);
1717 if (a->uim > (16 - size)) {
1718 /*
1719 * PowerISA v3.1 says that the resulting value is undefined in this
1720 * case, so just log a guest error and leave VRT unchanged. The
1721 * real hardware would do a partial insert, e.g. if VRT is zeroed and
1722 * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
1723 * VRT = 0x0000...00001234, but we don't bother to reproduce this
1724 * behavior as software shouldn't rely on it.
1725 */
1726 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
1727 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1728 16 - size);
1729 return true;
1730 }
1732 val = tcg_temp_new_i64();
1733 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1735 ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
1736 gen_helper);
1738 tcg_temp_free_i64(val);
1739 return ok;
1740 }
1742 static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1743 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1744 {
1745 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1746 REQUIRE_VECTOR(ctx);
1748 if (a->uim > (16 - size)) {
1749 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
1750 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1751 16 - size);
1752 return true;
1753 }
1755 return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
1756 gen_helper);
1757 }
1759 TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
1760 TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
1761 TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
1762 TRANS(VINSDLX, do_vinsx_VX, 8, false, gen_helper_VINSDLX)
1764 TRANS(VINSBRX, do_vinsx_VX, 1, true, gen_helper_VINSBLX)
1765 TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
1766 TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
1767 TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
1769 TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
1770 TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
1772 TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
1773 TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
1774 TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
1776 TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
1777 TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
1778 TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
1780 TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
1781 TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
1782 TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
1783 TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
1785 static void gen_vsldoi(DisasContext *ctx)
1786 {
1787 TCGv_ptr ra, rb, rd;
1788 TCGv_i32 sh;
1789 if (unlikely(!ctx->altivec_enabled)) {
1790 gen_exception(ctx, POWERPC_EXCP_VPU);
1791 return;
1792 }
1793 ra = gen_avr_ptr(rA(ctx->opcode));
1794 rb = gen_avr_ptr(rB(ctx->opcode));
1795 rd = gen_avr_ptr(rD(ctx->opcode));
1796 sh = tcg_const_i32(VSH(ctx->opcode));
1797 gen_helper_vsldoi(rd, ra, rb, sh);
1798 tcg_temp_free_ptr(ra);
1799 tcg_temp_free_ptr(rb);
1800 tcg_temp_free_ptr(rd);
1801 tcg_temp_free_i32(sh);
1802 }
1804 static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
1805 {
1806 TCGv_i64 t0, t1, t2;
1808 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1809 REQUIRE_VECTOR(ctx);
1811 t0 = tcg_temp_new_i64();
1812 t1 = tcg_temp_new_i64();
1814 get_avr64(t0, a->vra, true);
1815 get_avr64(t1, a->vra, false);
1817 if (a->sh != 0) {
1818 t2 = tcg_temp_new_i64();
1820 get_avr64(t2, a->vrb, true);
1822 tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
1823 tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
1825 tcg_temp_free_i64(t2);
1826 }
1828 set_avr64(a->vrt, t0, true);
1829 set_avr64(a->vrt, t1, false);
1831 tcg_temp_free_i64(t0);
1832 tcg_temp_free_i64(t1);
1834 return true;
1835 }
1837 static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
1838 {
1839 TCGv_i64 t2, t1, t0;
1841 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1842 REQUIRE_VECTOR(ctx);
1844 t0 = tcg_temp_new_i64();
1845 t1 = tcg_temp_new_i64();
1847 get_avr64(t0, a->vrb, false);
1848 get_avr64(t1, a->vrb, true);
1850 if (a->sh != 0) {
1851 t2 = tcg_temp_new_i64();
1853 get_avr64(t2, a->vra, false);
1855 tcg_gen_extract2_i64(t0, t0, t1, a->sh);
1856 tcg_gen_extract2_i64(t1, t1, t2, a->sh);
1858 tcg_temp_free_i64(t2);
1859 }
1861 set_avr64(a->vrt, t0, false);
1862 set_avr64(a->vrt, t1, true);
1864 tcg_temp_free_i64(t0);
1865 tcg_temp_free_i64(t1);
1867 return true;
1868 }
1870 static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1871 {
1872 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1873 REQUIRE_VECTOR(ctx);
1875 tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
1876 (8 << vece) - 1, 16, 16);
1878 return true;
1879 }
1881 TRANS(VEXPANDBM, do_vexpand, MO_8)
1882 TRANS(VEXPANDHM, do_vexpand, MO_16)
1883 TRANS(VEXPANDWM, do_vexpand, MO_32)
1884 TRANS(VEXPANDDM, do_vexpand, MO_64)
1886 static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
1887 {
1888 TCGv_i64 tmp;
1890 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1891 REQUIRE_VECTOR(ctx);
1893 tmp = tcg_temp_new_i64();
1895 get_avr64(tmp, a->vrb, true);
1896 tcg_gen_sari_i64(tmp, tmp, 63);
1897 set_avr64(a->vrt, tmp, false);
1898 set_avr64(a->vrt, tmp, true);
1900 tcg_temp_free_i64(tmp);
1901 return true;
1902 }
1904 static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1905 {
1906 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
1907 mask = dup_const(vece, 1 << (elem_width - 1));
1908 uint64_t i, j;
1909 TCGv_i64 lo, hi, t0, t1;
1911 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1912 REQUIRE_VECTOR(ctx);
1914 hi = tcg_temp_new_i64();
1915 lo = tcg_temp_new_i64();
1916 t0 = tcg_temp_new_i64();
1917 t1 = tcg_temp_new_i64();
1919 get_avr64(lo, a->vrb, false);
1920 get_avr64(hi, a->vrb, true);
1922 tcg_gen_andi_i64(lo, lo, mask);
1923 tcg_gen_andi_i64(hi, hi, mask);
1925 /*
1926 * Gather the most significant bit of each element in the highest element
1927 * element. E.g. for bytes:
1928 * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
1929 * & dup(1 << (elem_width - 1))
1930 * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
1931 * << 32 - 4
1932 * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
1933 * |
1934 * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
1935 * << 16 - 2
1936 * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
1937 * |
1938 * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
1939 * << 8 - 1
1940 * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
1941 * |
1942 * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
1943 */
1944 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
1945 tcg_gen_shli_i64(t0, hi, j - i);
1946 tcg_gen_shli_i64(t1, lo, j - i);
1947 tcg_gen_or_i64(hi, hi, t0);
1948 tcg_gen_or_i64(lo, lo, t1);
1949 }
1951 tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
1952 tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
1953 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
1955 tcg_temp_free_i64(hi);
1956 tcg_temp_free_i64(lo);
1957 tcg_temp_free_i64(t0);
1958 tcg_temp_free_i64(t1);
1960 return true;
1961 }
1963 TRANS(VEXTRACTBM, do_vextractm, MO_8)
1964 TRANS(VEXTRACTHM, do_vextractm, MO_16)
1965 TRANS(VEXTRACTWM, do_vextractm, MO_32)
1966 TRANS(VEXTRACTDM, do_vextractm, MO_64)
1968 static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
1969 {
1970 TCGv_i64 tmp;
1972 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1973 REQUIRE_VECTOR(ctx);
1975 tmp = tcg_temp_new_i64();
1977 get_avr64(tmp, a->vrb, true);
1978 tcg_gen_shri_i64(tmp, tmp, 63);
1979 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
1981 tcg_temp_free_i64(tmp);
1983 return true;
1984 }
1986 static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1987 {
1988 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece;
1989 uint64_t c;
1990 int i, j;
1991 TCGv_i64 hi, lo, t0, t1;
1993 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1994 REQUIRE_VECTOR(ctx);
1996 hi = tcg_temp_new_i64();
1997 lo = tcg_temp_new_i64();
1998 t0 = tcg_temp_new_i64();
1999 t1 = tcg_temp_new_i64();
2001 tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]);
2002 tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half);
2003 tcg_gen_extract_i64(lo, t0, 0, elem_count_half);
2005 /*
2006 * Spread the bits into their respective elements.
2007 * E.g. for bytes:
2008 * 00000000000000000000000000000000000000000000000000000000abcdefgh
2009 * << 32 - 4
2010 * 0000000000000000000000000000abcdefgh0000000000000000000000000000
2011 * |
2012 * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh
2013 * << 16 - 2
2014 * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000
2015 * |
2016 * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh
2017 * << 8 - 1
2018 * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000
2019 * |
2020 * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh
2021 * & dup(1)
2022 * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
2023 * * 0xff
2024 * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
2025 */
2026 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
2027 tcg_gen_shli_i64(t0, hi, j - i);
2028 tcg_gen_shli_i64(t1, lo, j - i);
2029 tcg_gen_or_i64(hi, hi, t0);
2030 tcg_gen_or_i64(lo, lo, t1);
2031 }
2033 c = dup_const(vece, 1);
2034 tcg_gen_andi_i64(hi, hi, c);
2035 tcg_gen_andi_i64(lo, lo, c);
2037 c = MAKE_64BIT_MASK(0, elem_width);
2038 tcg_gen_muli_i64(hi, hi, c);
2039 tcg_gen_muli_i64(lo, lo, c);
2041 set_avr64(a->vrt, lo, false);
2042 set_avr64(a->vrt, hi, true);
2044 tcg_temp_free_i64(hi);
2045 tcg_temp_free_i64(lo);
2046 tcg_temp_free_i64(t0);
2047 tcg_temp_free_i64(t1);
2049 return true;
2050 }
2052 TRANS(MTVSRBM, do_mtvsrm, MO_8)
2053 TRANS(MTVSRHM, do_mtvsrm, MO_16)
2054 TRANS(MTVSRWM, do_mtvsrm, MO_32)
2055 TRANS(MTVSRDM, do_mtvsrm, MO_64)
2057 static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a)
2058 {
2059 TCGv_i64 tmp;
2061 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2062 REQUIRE_VECTOR(ctx);
2064 tmp = tcg_temp_new_i64();
2066 tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]);
2067 tcg_gen_sextract_i64(tmp, tmp, 0, 1);
2068 set_avr64(a->vrt, tmp, false);
2069 set_avr64(a->vrt, tmp, true);
2071 tcg_temp_free_i64(tmp);
2073 return true;
2074 }
2076 static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
2077 {
2078 const uint64_t mask = dup_const(MO_8, 1);
2079 uint64_t hi, lo;
2081 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2082 REQUIRE_VECTOR(ctx);
2084 hi = extract16(a->b, 8, 8);
2085 lo = extract16(a->b, 0, 8);
2087 for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) {
2088 hi |= hi << (j - i);
2089 lo |= lo << (j - i);
2090 }
2092 hi = (hi & mask) * 0xFF;
2093 lo = (lo & mask) * 0xFF;
2095 set_avr64(a->vrt, tcg_constant_i64(hi), true);
2096 set_avr64(a->vrt, tcg_constant_i64(lo), false);
2098 return true;
2099 }
2101 static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
2102 {
2103 TCGv_i64 rt, vrb, mask;
2104 rt = tcg_const_i64(0);
2105 vrb = tcg_temp_new_i64();
2106 mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
2108 for (int i = 0; i < 2; i++) {
2109 get_avr64(vrb, a->vrb, i);
2110 if (a->mp) {
2111 tcg_gen_and_i64(vrb, mask, vrb);
2112 } else {
2113 tcg_gen_andc_i64(vrb, mask, vrb);
2114 }
2115 tcg_gen_ctpop_i64(vrb, vrb);
2116 tcg_gen_add_i64(rt, rt, vrb);
2117 }
2119 tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
2120 tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
2122 tcg_temp_free_i64(vrb);
2123 tcg_temp_free_i64(rt);
2125 return true;
2126 }
2128 TRANS(VCNTMBB, do_vcntmb, MO_8)
2129 TRANS(VCNTMBH, do_vcntmb, MO_16)
2130 TRANS(VCNTMBW, do_vcntmb, MO_32)
2131 TRANS(VCNTMBD, do_vcntmb, MO_64)
2133 static bool do_vstri(DisasContext *ctx, arg_VX_tb_rc *a,
2134 void (*gen_helper)(TCGv_i32, TCGv_ptr, TCGv_ptr))
2135 {
2136 TCGv_ptr vrt, vrb;
2138 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2139 REQUIRE_VECTOR(ctx);
2141 vrt = gen_avr_ptr(a->vrt);
2142 vrb = gen_avr_ptr(a->vrb);
2144 if (a->rc) {
2145 gen_helper(cpu_crf[6], vrt, vrb);
2146 } else {
2147 TCGv_i32 discard = tcg_temp_new_i32();
2148 gen_helper(discard, vrt, vrb);
2149 tcg_temp_free_i32(discard);
2150 }
2152 tcg_temp_free_ptr(vrt);
2153 tcg_temp_free_ptr(vrb);
2155 return true;
2156 }
2158 TRANS(VSTRIBL, do_vstri, gen_helper_VSTRIBL)
2159 TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
2160 TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
2161 TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
2163 static bool do_vclrb(DisasContext *ctx, arg_VX *a, bool right)
2164 {
2165 TCGv_i64 rb, mh, ml, tmp,
2166 ones = tcg_constant_i64(-1),
2167 zero = tcg_constant_i64(0);
2169 rb = tcg_temp_new_i64();
2170 mh = tcg_temp_new_i64();
2171 ml = tcg_temp_new_i64();
2172 tmp = tcg_temp_new_i64();
2174 tcg_gen_extu_tl_i64(rb, cpu_gpr[a->vrb]);
2175 tcg_gen_andi_i64(tmp, rb, 7);
2176 tcg_gen_shli_i64(tmp, tmp, 3);
2177 if (right) {
2178 tcg_gen_shr_i64(tmp, ones, tmp);
2179 } else {
2180 tcg_gen_shl_i64(tmp, ones, tmp);
2181 }
2182 tcg_gen_not_i64(tmp, tmp);
2184 if (right) {
2185 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
2186 tmp, ones);
2187 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
2188 zero, tmp);
2189 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(16),
2190 ml, ones);
2191 } else {
2192 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
2193 tmp, ones);
2194 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
2195 zero, tmp);
2196 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
2197 mh, ones);
2198 }
2200 get_avr64(tmp, a->vra, true);
2201 tcg_gen_and_i64(tmp, tmp, mh);
2202 set_avr64(a->vrt, tmp, true);
2204 get_avr64(tmp, a->vra, false);
2205 tcg_gen_and_i64(tmp, tmp, ml);
2206 set_avr64(a->vrt, tmp, false);
2208 tcg_temp_free_i64(rb);
2209 tcg_temp_free_i64(mh);
2210 tcg_temp_free_i64(ml);
2211 tcg_temp_free_i64(tmp);
2213 return true;
2214 }
2216 TRANS(VCLRLB, do_vclrb, false)
2217 TRANS(VCLRRB, do_vclrb, true)
2219 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
2220 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
2221 { \
2222 TCGv_ptr ra, rb, rc, rd; \
2223 if (unlikely(!ctx->altivec_enabled)) { \
2224 gen_exception(ctx, POWERPC_EXCP_VPU); \
2225 return; \
2226 } \
2227 ra = gen_avr_ptr(rA(ctx->opcode)); \
2228 rb = gen_avr_ptr(rB(ctx->opcode)); \
2229 rc = gen_avr_ptr(rC(ctx->opcode)); \
2230 rd = gen_avr_ptr(rD(ctx->opcode)); \
2231 if (Rc(ctx->opcode)) { \
2232 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
2233 } else { \
2234 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
2235 } \
2236 tcg_temp_free_ptr(ra); \
2237 tcg_temp_free_ptr(rb); \
2238 tcg_temp_free_ptr(rc); \
2239 tcg_temp_free_ptr(rd); \
2240 }
2242 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
2244 static void gen_vmladduhm(DisasContext *ctx)
2245 {
2246 TCGv_ptr ra, rb, rc, rd;
2247 if (unlikely(!ctx->altivec_enabled)) {
2248 gen_exception(ctx, POWERPC_EXCP_VPU);
2249 return;
2250 }
2251 ra = gen_avr_ptr(rA(ctx->opcode));
2252 rb = gen_avr_ptr(rB(ctx->opcode));
2253 rc = gen_avr_ptr(rC(ctx->opcode));
2254 rd = gen_avr_ptr(rD(ctx->opcode));
2255 gen_helper_vmladduhm(rd, ra, rb, rc);
2256 tcg_temp_free_ptr(ra);
2257 tcg_temp_free_ptr(rb);
2258 tcg_temp_free_ptr(rc);
2259 tcg_temp_free_ptr(rd);
2260 }
2262 static void gen_vpermr(DisasContext *ctx)
2263 {
2264 TCGv_ptr ra, rb, rc, rd;
2265 if (unlikely(!ctx->altivec_enabled)) {
2266 gen_exception(ctx, POWERPC_EXCP_VPU);
2267 return;
2268 }
2269 ra = gen_avr_ptr(rA(ctx->opcode));
2270 rb = gen_avr_ptr(rB(ctx->opcode));
2271 rc = gen_avr_ptr(rC(ctx->opcode));
2272 rd = gen_avr_ptr(rD(ctx->opcode));
2273 gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
2274 tcg_temp_free_ptr(ra);
2275 tcg_temp_free_ptr(rb);
2276 tcg_temp_free_ptr(rc);
2277 tcg_temp_free_ptr(rd);
2278 }
2280 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
2281 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
2282 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
2283 GEN_VAFORM_PAIRED(vsel, vperm, 21)
2284 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
2286 GEN_VXFORM_NOA(vclzb, 1, 28)
2287 GEN_VXFORM_NOA(vclzh, 1, 29)
2288 GEN_VXFORM_TRANS(vclzw, 1, 30)
2289 GEN_VXFORM_TRANS(vclzd, 1, 31)
2290 GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
2291 GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
2293 static void gen_vexts_i64(TCGv_i64 t, TCGv_i64 b, int64_t s)
2294 {
2295 tcg_gen_sextract_i64(t, b, 0, 64 - s);
2296 }
2298 static void gen_vexts_i32(TCGv_i32 t, TCGv_i32 b, int32_t s)
2299 {
2300 tcg_gen_sextract_i32(t, b, 0, 32 - s);
2301 }
2303 static void gen_vexts_vec(unsigned vece, TCGv_vec t, TCGv_vec b, int64_t s)
2304 {
2305 tcg_gen_shli_vec(vece, t, b, s);
2306 tcg_gen_sari_vec(vece, t, t, s);
2307 }
2309 static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, unsigned vece, int64_t s)
2310 {
2311 static const TCGOpcode vecop_list[] = {
2312 INDEX_op_shli_vec, INDEX_op_sari_vec, 0
2313 };
2315 static const GVecGen2i op[2] = {
2316 {
2317 .fni4 = gen_vexts_i32,
2318 .fniv = gen_vexts_vec,
2319 .opt_opc = vecop_list,
2320 .vece = MO_32
2321 },
2322 {
2323 .fni8 = gen_vexts_i64,
2324 .fniv = gen_vexts_vec,
2325 .opt_opc = vecop_list,
2326 .vece = MO_64
2327 },
2328 };
2330 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2331 REQUIRE_VECTOR(ctx);
2333 tcg_gen_gvec_2i(avr_full_offset(a->vrt), avr_full_offset(a->vrb),
2334 16, 16, s, &op[vece - MO_32]);
2336 return true;
2337 }
2339 TRANS(VEXTSB2W, do_vexts, MO_32, 24);
2340 TRANS(VEXTSH2W, do_vexts, MO_32, 16);
2341 TRANS(VEXTSB2D, do_vexts, MO_64, 56);
2342 TRANS(VEXTSH2D, do_vexts, MO_64, 48);
2343 TRANS(VEXTSW2D, do_vexts, MO_64, 32);
2345 static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
2346 {
2347 TCGv_i64 tmp;
2349 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2350 REQUIRE_VECTOR(ctx);
2352 tmp = tcg_temp_new_i64();
2354 get_avr64(tmp, a->vrb, false);
2355 set_avr64(a->vrt, tmp, false);
2356 tcg_gen_sari_i64(tmp, tmp, 63);
2357 set_avr64(a->vrt, tmp, true);
2359 tcg_temp_free_i64(tmp);
2360 return true;
2361 }
2363 GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
2364 GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
2365 GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
2366 GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
2367 GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
2368 GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
2369 GEN_VXFORM_NOA(vpopcntb, 1, 28)
2370 GEN_VXFORM_NOA(vpopcnth, 1, 29)
2371 GEN_VXFORM_NOA(vpopcntw, 1, 30)
2372 GEN_VXFORM_NOA(vpopcntd, 1, 31)
2373 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
2374 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
2375 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
2376 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
2377 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
2378 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
2379 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
2380 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
2381 GEN_VXFORM(vbpermd, 6, 23);
2382 GEN_VXFORM(vbpermq, 6, 21);
2383 GEN_VXFORM_TRANS(vgbbd, 6, 20);
2384 GEN_VXFORM(vpmsumb, 4, 16)
2385 GEN_VXFORM(vpmsumh, 4, 17)
2386 GEN_VXFORM(vpmsumw, 4, 18)
2387 GEN_VXFORM(vpmsumd, 4, 19)
2389 #define GEN_BCD(op) \
2390 static void gen_##op(DisasContext *ctx) \
2391 { \
2392 TCGv_ptr ra, rb, rd; \
2393 TCGv_i32 ps; \
2394 \
2395 if (unlikely(!ctx->altivec_enabled)) { \
2396 gen_exception(ctx, POWERPC_EXCP_VPU); \
2397 return; \
2398 } \
2399 \
2400 ra = gen_avr_ptr(rA(ctx->opcode)); \
2401 rb = gen_avr_ptr(rB(ctx->opcode)); \
2402 rd = gen_avr_ptr(rD(ctx->opcode)); \
2403 \
2404 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2405 \
2406 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
2407 \
2408 tcg_temp_free_ptr(ra); \
2409 tcg_temp_free_ptr(rb); \
2410 tcg_temp_free_ptr(rd); \
2411 tcg_temp_free_i32(ps); \
2412 }
2414 #define GEN_BCD2(op) \
2415 static void gen_##op(DisasContext *ctx) \
2416 { \
2417 TCGv_ptr rd, rb; \
2418 TCGv_i32 ps; \
2419 \
2420 if (unlikely(!ctx->altivec_enabled)) { \
2421 gen_exception(ctx, POWERPC_EXCP_VPU); \
2422 return; \
2423 } \
2424 \
2425 rb = gen_avr_ptr(rB(ctx->opcode)); \
2426 rd = gen_avr_ptr(rD(ctx->opcode)); \
2427 \
2428 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2429 \
2430 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
2431 \
2432 tcg_temp_free_ptr(rb); \
2433 tcg_temp_free_ptr(rd); \
2434 tcg_temp_free_i32(ps); \
2435 }
2437 GEN_BCD(bcdadd)
2438 GEN_BCD(bcdsub)
2439 GEN_BCD2(bcdcfn)
2440 GEN_BCD2(bcdctn)
2441 GEN_BCD2(bcdcfz)
2442 GEN_BCD2(bcdctz)
2443 GEN_BCD2(bcdcfsq)
2444 GEN_BCD2(bcdctsq)
2445 GEN_BCD2(bcdsetsgn)
2446 GEN_BCD(bcdcpsgn);
2447 GEN_BCD(bcds);
2448 GEN_BCD(bcdus);
2449 GEN_BCD(bcdsr);
2450 GEN_BCD(bcdtrunc);
2451 GEN_BCD(bcdutrunc);
2453 static void gen_xpnd04_1(DisasContext *ctx)
2454 {
2455 switch (opc4(ctx->opcode)) {
2456 case 0:
2457 gen_bcdctsq(ctx);
2458 break;
2459 case 2:
2460 gen_bcdcfsq(ctx);
2461 break;
2462 case 4:
2463 gen_bcdctz(ctx);
2464 break;
2465 case 5:
2466 gen_bcdctn(ctx);
2467 break;
2468 case 6:
2469 gen_bcdcfz(ctx);
2470 break;
2471 case 7:
2472 gen_bcdcfn(ctx);
2473 break;
2474 case 31:
2475 gen_bcdsetsgn(ctx);
2476 break;
2477 default:
2478 gen_invalid(ctx);
2479 break;
2480 }
2481 }
2483 static void gen_xpnd04_2(DisasContext *ctx)
2484 {
2485 switch (opc4(ctx->opcode)) {
2486 case 0:
2487 gen_bcdctsq(ctx);
2488 break;
2489 case 2:
2490 gen_bcdcfsq(ctx);
2491 break;
2492 case 4:
2493 gen_bcdctz(ctx);
2494 break;
2495 case 6:
2496 gen_bcdcfz(ctx);
2497 break;
2498 case 7:
2499 gen_bcdcfn(ctx);
2500 break;
2501 case 31:
2502 gen_bcdsetsgn(ctx);
2503 break;
2504 default:
2505 gen_invalid(ctx);
2506 break;
2507 }
2508 }
2511 GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
2512 xpnd04_1, PPC_NONE, PPC2_ISA300)
2513 GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
2514 xpnd04_2, PPC_NONE, PPC2_ISA300)
2516 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
2517 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2518 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
2519 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2520 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
2521 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2522 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
2523 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2524 GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
2525 bcdcpsgn, PPC_NONE, PPC2_ISA300)
2526 GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
2527 bcds, PPC_NONE, PPC2_ISA300)
2528 GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
2529 bcdus, PPC_NONE, PPC2_ISA300)
2530 GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
2531 bcdtrunc, PPC_NONE, PPC2_ISA300)
2532 GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
2533 bcdtrunc, PPC_NONE, PPC2_ISA300)
2534 GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
2535 bcdutrunc, PPC_NONE, PPC2_ISA300)
2538 static void gen_vsbox(DisasContext *ctx)
2539 {
2540 TCGv_ptr ra, rd;
2541 if (unlikely(!ctx->altivec_enabled)) {
2542 gen_exception(ctx, POWERPC_EXCP_VPU);
2543 return;
2544 }
2545 ra = gen_avr_ptr(rA(ctx->opcode));
2546 rd = gen_avr_ptr(rD(ctx->opcode));
2547 gen_helper_vsbox(rd, ra);
2548 tcg_temp_free_ptr(ra);
2549 tcg_temp_free_ptr(rd);
2550 }
2552 GEN_VXFORM(vcipher, 4, 20)
2553 GEN_VXFORM(vcipherlast, 4, 20)
2554 GEN_VXFORM(vncipher, 4, 21)
2555 GEN_VXFORM(vncipherlast, 4, 21)
2557 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
2558 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2559 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
2560 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2562 #define VSHASIGMA(op) \
2563 static void gen_##op(DisasContext *ctx) \
2564 { \
2565 TCGv_ptr ra, rd; \
2566 TCGv_i32 st_six; \
2567 if (unlikely(!ctx->altivec_enabled)) { \
2568 gen_exception(ctx, POWERPC_EXCP_VPU); \
2569 return; \
2570 } \
2571 ra = gen_avr_ptr(rA(ctx->opcode)); \
2572 rd = gen_avr_ptr(rD(ctx->opcode)); \
2573 st_six = tcg_const_i32(rB(ctx->opcode)); \
2574 gen_helper_##op(rd, ra, st_six); \
2575 tcg_temp_free_ptr(ra); \
2576 tcg_temp_free_ptr(rd); \
2577 tcg_temp_free_i32(st_six); \
2578 }
2580 VSHASIGMA(vshasigmaw)
2581 VSHASIGMA(vshasigmad)
2583 GEN_VXFORM3(vpermxor, 22, 0xFF)
2584 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
2585 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
2587 static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
2588 {
2589 static const GVecGen3 g = {
2590 .fni8 = gen_helper_CFUGED,
2591 .vece = MO_64,
2592 };
2594 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2595 REQUIRE_VECTOR(ctx);
2597 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2598 avr_full_offset(a->vrb), 16, 16, &g);
2600 return true;
2601 }
2603 static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
2604 {
2605 static const GVecGen3i g = {
2606 .fni8 = do_cntzdm,
2607 .vece = MO_64,
2608 };
2610 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2611 REQUIRE_VECTOR(ctx);
2613 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2614 avr_full_offset(a->vrb), 16, 16, false, &g);
2616 return true;
2617 }
2619 static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
2620 {
2621 static const GVecGen3i g = {
2622 .fni8 = do_cntzdm,
2623 .vece = MO_64,
2624 };
2626 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2627 REQUIRE_VECTOR(ctx);
2629 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2630 avr_full_offset(a->vrb), 16, 16, true, &g);
2632 return true;
2633 }
2635 static bool trans_VPDEPD(DisasContext *ctx, arg_VX *a)
2636 {
2637 static const GVecGen3 g = {
2638 .fni8 = gen_helper_PDEPD,
2639 .vece = MO_64,
2640 };
2642 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2643 REQUIRE_VECTOR(ctx);
2645 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2646 avr_full_offset(a->vrb), 16, 16, &g);
2648 return true;
2649 }
2651 static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
2652 {
2653 static const GVecGen3 g = {
2654 .fni8 = gen_helper_PEXTD,
2655 .vece = MO_64,
2656 };
2658 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2659 REQUIRE_VECTOR(ctx);
2661 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2662 avr_full_offset(a->vrb), 16, 16, &g);
2664 return true;
2665 }
2667 static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA *a)
2668 {
2669 TCGv_i64 rl, rh, src1, src2;
2670 int dw;
2672 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2673 REQUIRE_VECTOR(ctx);
2675 rh = tcg_temp_new_i64();
2676 rl = tcg_temp_new_i64();
2677 src1 = tcg_temp_new_i64();
2678 src2 = tcg_temp_new_i64();
2680 get_avr64(rl, a->rc, false);
2681 get_avr64(rh, a->rc, true);
2683 for (dw = 0; dw < 2; dw++) {
2684 get_avr64(src1, a->vra, dw);
2685 get_avr64(src2, a->vrb, dw);
2686 tcg_gen_mulu2_i64(src1, src2, src1, src2);
2687 tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
2688 }
2690 set_avr64(a->vrt, rl, false);
2691 set_avr64(a->vrt, rh, true);
2693 tcg_temp_free_i64(rl);
2694 tcg_temp_free_i64(rh);
2695 tcg_temp_free_i64(src1);
2696 tcg_temp_free_i64(src2);
2698 return true;
2699 }
2701 static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
2702 {
2703 TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
2705 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2706 REQUIRE_VECTOR(ctx);
2708 tmp0 = tcg_temp_new_i64();
2709 tmp1 = tcg_temp_new_i64();
2710 prod1h = tcg_temp_new_i64();
2711 prod1l = tcg_temp_new_i64();
2712 prod0h = tcg_temp_new_i64();
2713 prod0l = tcg_temp_new_i64();
2714 zero = tcg_constant_i64(0);
2716 /* prod1 = vsr[vra+32].dw[1] * vsr[vrb+32].dw[1] */
2717 get_avr64(tmp0, a->vra, false);
2718 get_avr64(tmp1, a->vrb, false);
2719 tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
2721 /* prod0 = vsr[vra+32].dw[0] * vsr[vrb+32].dw[0] */
2722 get_avr64(tmp0, a->vra, true);
2723 get_avr64(tmp1, a->vrb, true);
2724 tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
2726 /* Sum lower 64-bits elements */
2727 get_avr64(tmp1, a->rc, false);
2728 tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
2729 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
2731 /*
2732 * Discard lower 64-bits, leaving the carry into bit 64.
2733 * Then sum the higher 64-bit elements.
2734 */
2735 get_avr64(tmp1, a->rc, true);
2736 tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero);
2737 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero);
2738 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0h, zero);
2740 /* Discard 64 more bits to complete the CHOP128(temp >> 128) */
2741 set_avr64(a->vrt, tmp0, false);
2742 set_avr64(a->vrt, zero, true);
2744 tcg_temp_free_i64(tmp0);
2745 tcg_temp_free_i64(tmp1);
2746 tcg_temp_free_i64(prod1h);
2747 tcg_temp_free_i64(prod1l);
2748 tcg_temp_free_i64(prod0h);
2749 tcg_temp_free_i64(prod0l);
2751 return true;
2752 }
2754 static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
2755 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
2756 {
2757 TCGv_ptr ra, rb, rd;
2758 REQUIRE_VECTOR(ctx);
2760 ra = gen_avr_ptr(a->vra);
2761 rb = gen_avr_ptr(a->vrb);
2762 rd = gen_avr_ptr(a->vrt);
2763 gen_helper(rd, ra, rb);
2764 tcg_temp_free_ptr(ra);
2765 tcg_temp_free_ptr(rb);
2766 tcg_temp_free_ptr(rd);
2768 return true;
2769 }
2771 static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
2772 void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
2773 {
2774 TCGv_i64 vra, vrb, vrt0, vrt1;
2775 REQUIRE_VECTOR(ctx);
2777 vra = tcg_temp_new_i64();
2778 vrb = tcg_temp_new_i64();
2779 vrt0 = tcg_temp_new_i64();
2780 vrt1 = tcg_temp_new_i64();
2782 get_avr64(vra, a->vra, even);
2783 get_avr64(vrb, a->vrb, even);
2784 gen_mul(vrt0, vrt1, vra, vrb);
2785 set_avr64(a->vrt, vrt0, false);
2786 set_avr64(a->vrt, vrt1, true);
2788 tcg_temp_free_i64(vra);
2789 tcg_temp_free_i64(vrb);
2790 tcg_temp_free_i64(vrt0);
2791 tcg_temp_free_i64(vrt1);
2793 return true;
2794 }
2796 static bool trans_VMULLD(DisasContext *ctx, arg_VX *a)
2797 {
2798 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2799 REQUIRE_VECTOR(ctx);
2801 tcg_gen_gvec_mul(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->vra),
2802 avr_full_offset(a->vrb), 16, 16);
2804 return true;
2805 }
2807 TRANS_FLAGS2(ALTIVEC_207, VMULESB, do_vx_helper, gen_helper_VMULESB)
2808 TRANS_FLAGS2(ALTIVEC_207, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
2809 TRANS_FLAGS2(ALTIVEC_207, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
2810 TRANS_FLAGS2(ALTIVEC_207, VMULOUB, do_vx_helper, gen_helper_VMULOUB)
2811 TRANS_FLAGS2(ALTIVEC_207, VMULESH, do_vx_helper, gen_helper_VMULESH)
2812 TRANS_FLAGS2(ALTIVEC_207, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
2813 TRANS_FLAGS2(ALTIVEC_207, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
2814 TRANS_FLAGS2(ALTIVEC_207, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
2815 TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
2816 TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
2817 TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
2818 TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
2819 TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
2820 TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
2821 TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
2822 TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
2824 static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2825 {
2826 TCGv_i64 hh, lh, temp;
2828 uint64_t c;
2829 hh = tcg_temp_new_i64();
2830 lh = tcg_temp_new_i64();
2831 temp = tcg_temp_new_i64();
2833 c = 0xFFFFFFFF;
2835 if (sign) {
2836 tcg_gen_ext32s_i64(lh, a);
2837 tcg_gen_ext32s_i64(temp, b);
2838 } else {
2839 tcg_gen_andi_i64(lh, a, c);
2840 tcg_gen_andi_i64(temp, b, c);
2841 }
2842 tcg_gen_mul_i64(lh, lh, temp);
2844 if (sign) {
2845 tcg_gen_sari_i64(hh, a, 32);
2846 tcg_gen_sari_i64(temp, b, 32);
2847 } else {
2848 tcg_gen_shri_i64(hh, a, 32);
2849 tcg_gen_shri_i64(temp, b, 32);
2850 }
2851 tcg_gen_mul_i64(hh, hh, temp);
2853 tcg_gen_shri_i64(lh, lh, 32);
2854 tcg_gen_andi_i64(hh, hh, c << 32);
2855 tcg_gen_or_i64(t, hh, lh);
2857 tcg_temp_free_i64(hh);
2858 tcg_temp_free_i64(lh);
2859 tcg_temp_free_i64(temp);
2860 }
2862 static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2863 {
2864 TCGv_i64 tlow;
2866 tlow = tcg_temp_new_i64();
2867 if (sign) {
2868 tcg_gen_muls2_i64(tlow, t, a, b);
2869 } else {
2870 tcg_gen_mulu2_i64(tlow, t, a, b);
2871 }
2873 tcg_temp_free_i64(tlow);
2874 }
2876 static bool do_vx_mulh(DisasContext *ctx, arg_VX *a, bool sign,
2877 void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, bool))
2878 {
2879 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2880 REQUIRE_VECTOR(ctx);
2882 TCGv_i64 vra, vrb, vrt;
2883 int i;
2885 vra = tcg_temp_new_i64();
2886 vrb = tcg_temp_new_i64();
2887 vrt = tcg_temp_new_i64();
2889 for (i = 0; i < 2; i++) {
2890 get_avr64(vra, a->vra, i);
2891 get_avr64(vrb, a->vrb, i);
2892 get_avr64(vrt, a->vrt, i);
2894 func(vrt, vra, vrb, sign);
2896 set_avr64(a->vrt, vrt, i);
2897 }
2899 tcg_temp_free_i64(vra);
2900 tcg_temp_free_i64(vrb);
2901 tcg_temp_free_i64(vrt);
2903 return true;
2905 }
2907 TRANS(VMULHSW, do_vx_mulh, true , do_vx_vmulhw_i64)
2908 TRANS(VMULHSD, do_vx_mulh, true , do_vx_vmulhd_i64)
2909 TRANS(VMULHUW, do_vx_mulh, false, do_vx_vmulhw_i64)
2910 TRANS(VMULHUD, do_vx_mulh, false, do_vx_vmulhd_i64)
2912 #undef GEN_VR_LDX
2913 #undef GEN_VR_STX
2914 #undef GEN_VR_LVE
2915 #undef GEN_VR_STVE
2917 #undef GEN_VX_LOGICAL
2918 #undef GEN_VX_LOGICAL_207
2919 #undef GEN_VXFORM
2920 #undef GEN_VXFORM_207
2921 #undef GEN_VXFORM_DUAL
2922 #undef GEN_VXRFORM_DUAL
2923 #undef GEN_VXRFORM1
2924 #undef GEN_VXRFORM
2925 #undef GEN_VXFORM_VSPLTI
2926 #undef GEN_VXFORM_NOA
2927 #undef GEN_VXFORM_UIMM
2928 #undef GEN_VAFORM_PAIRED
2930 #undef GEN_BCD2