target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "hw/registerfields.h"
  25 #include "exec/cpu-defs.h"
  26 #include "fpu/softfloat-types.h"
  27 #include "qom/object.h"
  28 #include "qemu/int128.h"
  29 #include "cpu_bits.h"
  30
  31 #define TCG_GUEST_DEFAULT_MO 0
  32
  33 #define TYPE_RISCV_CPU "riscv-cpu"
  34
  35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  38
  39 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  40 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  41 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  42 #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
  43 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
  44 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
  45 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  46 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
  47 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  48 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  49 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  50 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
  51
  52 #if defined(TARGET_RISCV32)
  53 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
  54 #elif defined(TARGET_RISCV64)
  55 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  56 #endif
  57
  58 #define RV(x) ((target_ulong)1 << (x - 'A'))
  59
  60 #define RVI RV('I')
  61 #define RVE RV('E') /* E and I are mutually exclusive */
  62 #define RVM RV('M')
  63 #define RVA RV('A')
  64 #define RVF RV('F')
  65 #define RVD RV('D')
  66 #define RVV RV('V')
  67 #define RVC RV('C')
  68 #define RVS RV('S')
  69 #define RVU RV('U')
  70 #define RVH RV('H')
  71 #define RVJ RV('J')
  72
  73 /* S extension denotes that Supervisor mode exists, however it is possible
  74    to have a core that support S mode but does not have an MMU and there
  75    is currently no bit in misa to indicate whether an MMU exists or not
  76    so a cpu features bitfield is required, likewise for optional PMP support */
  77 enum {
  78     RISCV_FEATURE_MMU,
  79     RISCV_FEATURE_PMP,
  80     RISCV_FEATURE_EPMP,
  81     RISCV_FEATURE_MISA,
  82     RISCV_FEATURE_AIA
  83 };
  84
  85 #define PRIV_VERSION_1_10_0 0x00011000
  86 #define PRIV_VERSION_1_11_0 0x00011100
  87
  88 #define VEXT_VERSION_1_00_0 0x00010000
  89
  90 enum {
  91     TRANSLATE_SUCCESS,
  92     TRANSLATE_FAIL,
  93     TRANSLATE_PMP_FAIL,
  94     TRANSLATE_G_STAGE_FAIL
  95 };
  96
  97 #define MMU_USER_IDX 3
  98
  99 #define MAX_RISCV_PMPS (16)
 100
 101 typedef struct CPURISCVState CPURISCVState;
 102
 103 #if !defined(CONFIG_USER_ONLY)
 104 #include "pmp.h"
 105 #endif
 106
 107 #define RV_VLEN_MAX 1024
 108
 109 FIELD(VTYPE, VLMUL, 0, 3)
 110 FIELD(VTYPE, VSEW, 3, 3)
 111 FIELD(VTYPE, VTA, 6, 1)
 112 FIELD(VTYPE, VMA, 7, 1)
 113 FIELD(VTYPE, VEDIV, 8, 2)
 114 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
 115
 116 struct CPURISCVState {
 117     target_ulong gpr[32];
 118     target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
 119     uint64_t fpr[32]; /* assume both F and D extensions */
 120
 121     /* vector coprocessor state. */
 122     uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
 123     target_ulong vxrm;
 124     target_ulong vxsat;
 125     target_ulong vl;
 126     target_ulong vstart;
 127     target_ulong vtype;
 128     bool vill;
 129
 130     target_ulong pc;
 131     target_ulong load_res;
 132     target_ulong load_val;
 133
 134     target_ulong frm;
 135
 136     target_ulong badaddr;
 137     uint32_t bins;
 138
 139     target_ulong guest_phys_fault_addr;
 140
 141     target_ulong priv_ver;
 142     target_ulong bext_ver;
 143     target_ulong vext_ver;
 144
 145     /* RISCVMXL, but uint32_t for vmstate migration */
 146     uint32_t misa_mxl;      /* current mxl */
 147     uint32_t misa_mxl_max;  /* max mxl for this cpu */
 148     uint32_t misa_ext;      /* current extensions */
 149     uint32_t misa_ext_mask; /* max ext for this cpu */
 150     uint32_t xl;            /* current xlen */
 151
 152     /* 128-bit helpers upper part return value */
 153     target_ulong retxh;
 154
 155     uint32_t features;
 156
 157 #ifdef CONFIG_USER_ONLY
 158     uint32_t elf_flags;
 159 #endif
 160
 161 #ifndef CONFIG_USER_ONLY
 162     target_ulong priv;
 163     /* This contains QEMU specific information about the virt state. */
 164     target_ulong virt;
 165     target_ulong geilen;
 166     target_ulong resetvec;
 167
 168     target_ulong mhartid;
 169     /*
 170      * For RV32 this is 32-bit mstatus and 32-bit mstatush.
 171      * For RV64 this is a 64-bit mstatus.
 172      */
 173     uint64_t mstatus;
 174
 175     uint64_t mip;
 176
 177     uint64_t miclaim;
 178
 179     uint64_t mie;
 180     uint64_t mideleg;
 181
 182     target_ulong satp;   /* since: priv-1.10.0 */
 183     target_ulong stval;
 184     target_ulong medeleg;
 185
 186     target_ulong stvec;
 187     target_ulong sepc;
 188     target_ulong scause;
 189
 190     target_ulong mtvec;
 191     target_ulong mepc;
 192     target_ulong mcause;
 193     target_ulong mtval;  /* since: priv-1.10.0 */
 194
 195     /* Machine and Supervisor interrupt priorities */
 196     uint8_t miprio[64];
 197     uint8_t siprio[64];
 198
 199     /* AIA CSRs */
 200     target_ulong miselect;
 201     target_ulong siselect;
 202
 203     /* Hypervisor CSRs */
 204     target_ulong hstatus;
 205     target_ulong hedeleg;
 206     uint64_t hideleg;
 207     target_ulong hcounteren;
 208     target_ulong htval;
 209     target_ulong htinst;
 210     target_ulong hgatp;
 211     target_ulong hgeie;
 212     target_ulong hgeip;
 213     uint64_t htimedelta;
 214
 215     /* Hypervisor controlled virtual interrupt priorities */
 216     target_ulong hvictl;
 217     uint8_t hviprio[64];
 218
 219     /* Upper 64-bits of 128-bit CSRs */
 220     uint64_t mscratchh;
 221     uint64_t sscratchh;
 222
 223     /* Virtual CSRs */
 224     /*
 225      * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
 226      * For RV64 this is a 64-bit vsstatus.
 227      */
 228     uint64_t vsstatus;
 229     target_ulong vstvec;
 230     target_ulong vsscratch;
 231     target_ulong vsepc;
 232     target_ulong vscause;
 233     target_ulong vstval;
 234     target_ulong vsatp;
 235
 236     /* AIA VS-mode CSRs */
 237     target_ulong vsiselect;
 238
 239     target_ulong mtval2;
 240     target_ulong mtinst;
 241
 242     /* HS Backup CSRs */
 243     target_ulong stvec_hs;
 244     target_ulong sscratch_hs;
 245     target_ulong sepc_hs;
 246     target_ulong scause_hs;
 247     target_ulong stval_hs;
 248     target_ulong satp_hs;
 249     uint64_t mstatus_hs;
 250
 251     /* Signals whether the current exception occurred with two-stage address
 252        translation active. */
 253     bool two_stage_lookup;
 254
 255     target_ulong scounteren;
 256     target_ulong mcounteren;
 257
 258     target_ulong sscratch;
 259     target_ulong mscratch;
 260
 261     /* temporary htif regs */
 262     uint64_t mfromhost;
 263     uint64_t mtohost;
 264     uint64_t timecmp;
 265
 266     /* physical memory protection */
 267     pmp_table_t pmp_state;
 268     target_ulong mseccfg;
 269
 270     /* machine specific rdtime callback */
 271     uint64_t (*rdtime_fn)(uint32_t);
 272     uint32_t rdtime_fn_arg;
 273
 274     /* machine specific AIA ireg read-modify-write callback */
 275 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
 276     ((((__xlen) & 0xff) << 24) | \
 277      (((__vgein) & 0x3f) << 20) | \
 278      (((__virt) & 0x1) << 18) | \
 279      (((__priv) & 0x3) << 16) | \
 280      (__isel & 0xffff))
 281 #define AIA_IREG_ISEL(__ireg)                  ((__ireg) & 0xffff)
 282 #define AIA_IREG_PRIV(__ireg)                  (((__ireg) >> 16) & 0x3)
 283 #define AIA_IREG_VIRT(__ireg)                  (((__ireg) >> 18) & 0x1)
 284 #define AIA_IREG_VGEIN(__ireg)                 (((__ireg) >> 20) & 0x3f)
 285 #define AIA_IREG_XLEN(__ireg)                  (((__ireg) >> 24) & 0xff)
 286     int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
 287         target_ulong *val, target_ulong new_val, target_ulong write_mask);
 288     void *aia_ireg_rmw_fn_arg[4];
 289
 290     /* True if in debugger mode.  */
 291     bool debugger;
 292
 293     /*
 294      * CSRs for PointerMasking extension
 295      */
 296     target_ulong mmte;
 297     target_ulong mpmmask;
 298     target_ulong mpmbase;
 299     target_ulong spmmask;
 300     target_ulong spmbase;
 301     target_ulong upmmask;
 302     target_ulong upmbase;
 303 #endif
 304     target_ulong cur_pmmask;
 305     target_ulong cur_pmbase;
 306
 307     float_status fp_status;
 308
 309     /* Fields from here on are preserved across CPU reset. */
 310     QEMUTimer *timer; /* Internal timer */
 311
 312     hwaddr kernel_addr;
 313     hwaddr fdt_addr;
 314
 315     /* kvm timer */
 316     bool kvm_timer_dirty;
 317     uint64_t kvm_timer_time;
 318     uint64_t kvm_timer_compare;
 319     uint64_t kvm_timer_state;
 320     uint64_t kvm_timer_frequency;
 321 };
 322
 323 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
 324                     RISCV_CPU)
 325
 326 /**
 327  * RISCVCPUClass:
 328  * @parent_realize: The parent class' realize handler.
 329  * @parent_reset: The parent class' reset handler.
 330  *
 331  * A RISCV CPU model.
 332  */
 333 struct RISCVCPUClass {
 334     /*< private >*/
 335     CPUClass parent_class;
 336     /*< public >*/
 337     DeviceRealize parent_realize;
 338     DeviceReset parent_reset;
 339 };
 340
 341 struct RISCVCPUConfig {
 342     bool ext_i;
 343     bool ext_e;
 344     bool ext_g;
 345     bool ext_m;
 346     bool ext_a;
 347     bool ext_f;
 348     bool ext_d;
 349     bool ext_c;
 350     bool ext_s;
 351     bool ext_u;
 352     bool ext_h;
 353     bool ext_j;
 354     bool ext_v;
 355     bool ext_zba;
 356     bool ext_zbb;
 357     bool ext_zbc;
 358     bool ext_zbs;
 359     bool ext_counters;
 360     bool ext_ifencei;
 361     bool ext_icsr;
 362     bool ext_svinval;
 363     bool ext_svnapot;
 364     bool ext_svpbmt;
 365     bool ext_zfh;
 366     bool ext_zfhmin;
 367     bool ext_zve32f;
 368     bool ext_zve64f;
 369
 370     /* Vendor-specific custom extensions */
 371     bool ext_XVentanaCondOps;
 372
 373     char *priv_spec;
 374     char *user_spec;
 375     char *bext_spec;
 376     char *vext_spec;
 377     uint16_t vlen;
 378     uint16_t elen;
 379     bool mmu;
 380     bool pmp;
 381     bool epmp;
 382     bool aia;
 383     uint64_t resetvec;
 384 };
 385
 386 typedef struct RISCVCPUConfig RISCVCPUConfig;
 387
 388 /**
 389  * RISCVCPU:
 390  * @env: #CPURISCVState
 391  *
 392  * A RISCV CPU.
 393  */
 394 struct RISCVCPU {
 395     /*< private >*/
 396     CPUState parent_obj;
 397     /*< public >*/
 398     CPUNegativeOffsetState neg;
 399     CPURISCVState env;
 400
 401     char *dyn_csr_xml;
 402     char *dyn_vreg_xml;
 403
 404     /* Configuration Settings */
 405     RISCVCPUConfig cfg;
 406 };
 407
 408 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 409 {
 410     return (env->misa_ext & ext) != 0;
 411 }
 412
 413 static inline bool riscv_feature(CPURISCVState *env, int feature)
 414 {
 415     return env->features & (1ULL << feature);
 416 }
 417
 418 static inline void riscv_set_feature(CPURISCVState *env, int feature)
 419 {
 420     env->features |= (1ULL << feature);
 421 }
 422
 423 #include "cpu_user.h"
 424
 425 extern const char * const riscv_int_regnames[];
 426 extern const char * const riscv_int_regnamesh[];
 427 extern const char * const riscv_fpr_regnames[];
 428
 429 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 430 void riscv_cpu_do_interrupt(CPUState *cpu);
 431 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 432                                int cpuid, void *opaque);
 433 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
 434                                int cpuid, void *opaque);
 435 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 436 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 437 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 438 uint8_t riscv_cpu_default_priority(int irq);
 439 int riscv_cpu_mirq_pending(CPURISCVState *env);
 440 int riscv_cpu_sirq_pending(CPURISCVState *env);
 441 int riscv_cpu_vsirq_pending(CPURISCVState *env);
 442 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 443 target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
 444 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
 445 bool riscv_cpu_vector_enabled(CPURISCVState *env);
 446 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 447 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 448 bool riscv_cpu_two_stage_lookup(int mmu_idx);
 449 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 450 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 451 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 452                                     MMUAccessType access_type, int mmu_idx,
 453                                     uintptr_t retaddr) QEMU_NORETURN;
 454 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 455                         MMUAccessType access_type, int mmu_idx,
 456                         bool probe, uintptr_t retaddr);
 457 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 458                                      vaddr addr, unsigned size,
 459                                      MMUAccessType access_type,
 460                                      int mmu_idx, MemTxAttrs attrs,
 461                                      MemTxResult response, uintptr_t retaddr);
 462 char *riscv_isa_string(RISCVCPU *cpu);
 463 void riscv_cpu_list(void);
 464
 465 #define cpu_list riscv_cpu_list
 466 #define cpu_mmu_index riscv_cpu_mmu_index
 467
 468 #ifndef CONFIG_USER_ONLY
 469 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 470 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 471 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
 472 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
 473 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 474 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
 475                              uint32_t arg);
 476 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
 477                                    int (*rmw_fn)(void *arg,
 478                                                  target_ulong reg,
 479                                                  target_ulong *val,
 480                                                  target_ulong new_val,
 481                                                  target_ulong write_mask),
 482                                    void *rmw_fn_arg);
 483 #endif
 484 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 485
 486 void riscv_translate_init(void);
 487 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 488                                          uint32_t exception, uintptr_t pc);
 489
 490 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 491 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 492
 493 #define TB_FLAGS_PRIV_MMU_MASK                3
 494 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 495 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 496 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
 497
 498 typedef CPURISCVState CPUArchState;
 499 typedef RISCVCPU ArchCPU;
 500 #include "exec/cpu-all.h"
 501
 502 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 503 FIELD(TB_FLAGS, LMUL, 3, 3)
 504 FIELD(TB_FLAGS, SEW, 6, 3)
 505 /* Skip MSTATUS_VS (0x600) bits */
 506 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
 507 FIELD(TB_FLAGS, VILL, 12, 1)
 508 /* Skip MSTATUS_FS (0x6000) bits */
 509 /* Is a Hypervisor instruction load/store allowed? */
 510 FIELD(TB_FLAGS, HLSX, 15, 1)
 511 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
 512 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
 513 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 514 FIELD(TB_FLAGS, XL, 20, 2)
 515 /* If PointerMasking should be applied */
 516 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
 517 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
 518
 519 #ifdef TARGET_RISCV32
 520 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 521 #else
 522 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 523 {
 524     return env->misa_mxl;
 525 }
 526 #endif
 527 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 528
 529 #if defined(TARGET_RISCV32)
 530 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 531 #else
 532 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 533 {
 534     RISCVMXL xl = env->misa_mxl;
 535 #if !defined(CONFIG_USER_ONLY)
 536     /*
 537      * When emulating a 32-bit-only cpu, use RV32.
 538      * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 539      * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 540      * back to RV64 for lower privs.
 541      */
 542     if (xl != MXL_RV32) {
 543         switch (env->priv) {
 544         case PRV_M:
 545             break;
 546         case PRV_U:
 547             xl = get_field(env->mstatus, MSTATUS64_UXL);
 548             break;
 549         default: /* PRV_S | PRV_H */
 550             xl = get_field(env->mstatus, MSTATUS64_SXL);
 551             break;
 552         }
 553     }
 554 #endif
 555     return xl;
 556 }
 557 #endif
 558
 559 static inline int riscv_cpu_xlen(CPURISCVState *env)
 560 {
 561     return 16 << env->xl;
 562 }
 563
 564 #ifdef TARGET_RISCV32
 565 #define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
 566 #else
 567 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 568 {
 569 #ifdef CONFIG_USER_ONLY
 570     return env->misa_mxl;
 571 #else
 572     return get_field(env->mstatus, MSTATUS64_SXL);
 573 #endif
 574 }
 575 #endif
 576
 577 /*
 578  * Encode LMUL to lmul as follows:
 579  *     LMUL    vlmul    lmul
 580  *      1       000       0
 581  *      2       001       1
 582  *      4       010       2
 583  *      8       011       3
 584  *      -       100       -
 585  *     1/8      101      -3
 586  *     1/4      110      -2
 587  *     1/2      111      -1
 588  *
 589  * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
 590  * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
 591  *      => VLMAX = vlen >> (1 + 3 - (-3))
 592  *               = 256 >> 7
 593  *               = 2
 594  */
 595 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 596 {
 597     uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
 598     int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
 599     return cpu->cfg.vlen >> (sew + 3 - lmul);
 600 }
 601
 602 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 603                           target_ulong *cs_base, uint32_t *pflags);
 604
 605 void riscv_cpu_update_mask(CPURISCVState *env);
 606
 607 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
 608                            target_ulong *ret_value,
 609                            target_ulong new_value, target_ulong write_mask);
 610 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
 611                                  target_ulong *ret_value,
 612                                  target_ulong new_value,
 613                                  target_ulong write_mask);
 614
 615 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 616                                    target_ulong val)
 617 {
 618     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 619 }
 620
 621 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 622 {
 623     target_ulong val = 0;
 624     riscv_csrrw(env, csrno, &val, 0, 0);
 625     return val;
 626 }
 627
 628 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
 629                                                  int csrno);
 630 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 631                                             target_ulong *ret_value);
 632 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 633                                              target_ulong new_value);
 634 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 635                                           target_ulong *ret_value,
 636                                           target_ulong new_value,
 637                                           target_ulong write_mask);
 638
 639 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
 640                                 Int128 *ret_value,
 641                                 Int128 new_value, Int128 write_mask);
 642
 643 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
 644                                                Int128 *ret_value);
 645 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
 646                                              Int128 new_value);
 647
 648 typedef struct {
 649     const char *name;
 650     riscv_csr_predicate_fn predicate;
 651     riscv_csr_read_fn read;
 652     riscv_csr_write_fn write;
 653     riscv_csr_op_fn op;
 654     riscv_csr_read128_fn read128;
 655     riscv_csr_write128_fn write128;
 656 } riscv_csr_operations;
 657
 658 /* CSR function table constants */
 659 enum {
 660     CSR_TABLE_SIZE = 0x1000
 661 };
 662
 663 /* CSR function table */
 664 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 665
 666 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 667 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 668
 669 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 670
 671 #endif /* RISCV_CPU_H */