2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include "hw/ppc/spapr.h"
15 #include "hw/ppc/spapr_cpu_core.h"
16 #include "hw/ppc/spapr_xive.h"
17 #include "hw/ppc/xics.h"
18 #include "hw/ppc/xics_spapr.h"
19 #include "sysemu/kvm.h"
23 void spapr_irq_msi_init(sPAPRMachineState
*spapr
, uint32_t nr_msis
)
25 spapr
->irq_map_nr
= nr_msis
;
26 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
29 int spapr_irq_msi_alloc(sPAPRMachineState
*spapr
, uint32_t num
, bool align
,
35 * The 'align_mask' parameter of bitmap_find_next_zero_area()
36 * should be one less than a power of 2; 0 means no
37 * alignment. Adapt the 'align' value of the former allocator
38 * to fit the requirements of bitmap_find_next_zero_area()
42 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
44 if (irq
== spapr
->irq_map_nr
) {
45 error_setg(errp
, "can't find a free %d-IRQ block", num
);
49 bitmap_set(spapr
->irq_map
, irq
, num
);
51 return irq
+ SPAPR_IRQ_MSI
;
54 void spapr_irq_msi_free(sPAPRMachineState
*spapr
, int irq
, uint32_t num
)
56 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
59 void spapr_irq_msi_reset(sPAPRMachineState
*spapr
)
61 bitmap_clear(spapr
->irq_map
, 0, spapr
->irq_map_nr
);
69 static ICSState
*spapr_ics_create(sPAPRMachineState
*spapr
,
70 int nr_irqs
, Error
**errp
)
72 Error
*local_err
= NULL
;
75 obj
= object_new(TYPE_ICS_SIMPLE
);
76 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
77 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
79 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &local_err
);
83 object_property_set_bool(obj
, true, "realized", &local_err
);
91 error_propagate(errp
, local_err
);
95 static void spapr_irq_init_xics(sPAPRMachineState
*spapr
, int nr_irqs
,
98 MachineState
*machine
= MACHINE(spapr
);
99 Error
*local_err
= NULL
;
100 bool xics_kvm
= false;
103 if (machine_kernel_irqchip_allowed(machine
) &&
104 !xics_kvm_init(spapr
, &local_err
)) {
107 if (machine_kernel_irqchip_required(machine
) && !xics_kvm
) {
108 error_prepend(&local_err
,
109 "kernel_irqchip requested but unavailable: ");
112 error_free(local_err
);
117 xics_spapr_init(spapr
);
120 spapr
->ics
= spapr_ics_create(spapr
, nr_irqs
, &local_err
);
123 error_propagate(errp
, local_err
);
126 #define ICS_IRQ_FREE(ics, srcno) \
127 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
129 static int spapr_irq_claim_xics(sPAPRMachineState
*spapr
, int irq
, bool lsi
,
132 ICSState
*ics
= spapr
->ics
;
136 if (!ics_valid_irq(ics
, irq
)) {
137 error_setg(errp
, "IRQ %d is invalid", irq
);
141 if (!ICS_IRQ_FREE(ics
, irq
- ics
->offset
)) {
142 error_setg(errp
, "IRQ %d is not free", irq
);
146 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
150 static void spapr_irq_free_xics(sPAPRMachineState
*spapr
, int irq
, int num
)
152 ICSState
*ics
= spapr
->ics
;
153 uint32_t srcno
= irq
- ics
->offset
;
156 if (ics_valid_irq(ics
, irq
)) {
157 trace_spapr_irq_free(0, irq
, num
);
158 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
159 if (ICS_IRQ_FREE(ics
, i
)) {
160 trace_spapr_irq_free_warn(0, i
);
162 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
167 static qemu_irq
spapr_qirq_xics(sPAPRMachineState
*spapr
, int irq
)
169 ICSState
*ics
= spapr
->ics
;
170 uint32_t srcno
= irq
- ics
->offset
;
172 if (ics_valid_irq(ics
, irq
)) {
173 return spapr
->qirqs
[srcno
];
179 static void spapr_irq_print_info_xics(sPAPRMachineState
*spapr
, Monitor
*mon
)
184 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
186 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
189 ics_pic_print_info(spapr
->ics
, mon
);
192 static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState
*spapr
,
193 PowerPCCPU
*cpu
, Error
**errp
)
195 Error
*local_err
= NULL
;
197 sPAPRCPUState
*spapr_cpu
= spapr_cpu_state(cpu
);
199 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
202 error_propagate(errp
, local_err
);
206 spapr_cpu
->icp
= ICP(obj
);
209 static int spapr_irq_post_load_xics(sPAPRMachineState
*spapr
, int version_id
)
211 if (!kvm_irqchip_in_kernel()) {
214 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
215 icp_resend(spapr_cpu_state(cpu
)->icp
);
221 static void spapr_irq_set_irq_xics(void *opaque
, int srcno
, int val
)
223 sPAPRMachineState
*spapr
= opaque
;
225 ics_simple_set_irq(spapr
->ics
, srcno
, val
);
228 static void spapr_irq_reset_xics(sPAPRMachineState
*spapr
, Error
**errp
)
230 /* TODO: create the KVM XICS device */
233 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
234 #define SPAPR_IRQ_XICS_NR_MSIS \
235 (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
237 sPAPRIrq spapr_irq_xics
= {
238 .nr_irqs
= SPAPR_IRQ_XICS_NR_IRQS
,
239 .nr_msis
= SPAPR_IRQ_XICS_NR_MSIS
,
240 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
242 .init
= spapr_irq_init_xics
,
243 .claim
= spapr_irq_claim_xics
,
244 .free
= spapr_irq_free_xics
,
245 .qirq
= spapr_qirq_xics
,
246 .print_info
= spapr_irq_print_info_xics
,
247 .dt_populate
= spapr_dt_xics
,
248 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
249 .post_load
= spapr_irq_post_load_xics
,
250 .reset
= spapr_irq_reset_xics
,
251 .set_irq
= spapr_irq_set_irq_xics
,
257 static void spapr_irq_init_xive(sPAPRMachineState
*spapr
, int nr_irqs
,
260 MachineState
*machine
= MACHINE(spapr
);
261 uint32_t nr_servers
= spapr_max_server_number(spapr
);
265 /* KVM XIVE device not yet available */
267 if (machine_kernel_irqchip_required(machine
)) {
268 error_setg(errp
, "kernel_irqchip requested. no KVM XIVE support");
273 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
274 qdev_prop_set_uint32(dev
, "nr-irqs", nr_irqs
);
276 * 8 XIVE END structures per CPU. One for each available priority
278 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
279 qdev_init_nofail(dev
);
281 spapr
->xive
= SPAPR_XIVE(dev
);
283 /* Enable the CPU IPIs */
284 for (i
= 0; i
< nr_servers
; ++i
) {
285 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
288 spapr_xive_hcall_init(spapr
);
291 static int spapr_irq_claim_xive(sPAPRMachineState
*spapr
, int irq
, bool lsi
,
294 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
295 error_setg(errp
, "IRQ %d is invalid", irq
);
301 static void spapr_irq_free_xive(sPAPRMachineState
*spapr
, int irq
, int num
)
305 for (i
= irq
; i
< irq
+ num
; ++i
) {
306 spapr_xive_irq_free(spapr
->xive
, i
);
310 static qemu_irq
spapr_qirq_xive(sPAPRMachineState
*spapr
, int irq
)
312 sPAPRXive
*xive
= spapr
->xive
;
314 if (irq
>= xive
->nr_irqs
) {
318 /* The sPAPR machine/device should have claimed the IRQ before */
319 assert(xive_eas_is_valid(&xive
->eat
[irq
]));
321 return spapr
->qirqs
[irq
];
324 static void spapr_irq_print_info_xive(sPAPRMachineState
*spapr
,
330 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
332 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
335 spapr_xive_pic_print_info(spapr
->xive
, mon
);
338 static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState
*spapr
,
339 PowerPCCPU
*cpu
, Error
**errp
)
341 Error
*local_err
= NULL
;
343 sPAPRCPUState
*spapr_cpu
= spapr_cpu_state(cpu
);
345 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
347 error_propagate(errp
, local_err
);
351 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
354 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
355 * don't beneficiate from the reset of the XIVE IRQ backend
357 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
360 static int spapr_irq_post_load_xive(sPAPRMachineState
*spapr
, int version_id
)
365 static void spapr_irq_reset_xive(sPAPRMachineState
*spapr
, Error
**errp
)
370 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
372 /* (TCG) Set the OS CAM line of the thread interrupt context. */
373 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
376 /* Activate the XIVE MMIOs */
377 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
380 static void spapr_irq_set_irq_xive(void *opaque
, int srcno
, int val
)
382 sPAPRMachineState
*spapr
= opaque
;
384 xive_source_set_irq(&spapr
->xive
->source
, srcno
, val
);
388 * XIVE uses the full IRQ number space. Set it to 8K to be compatible
392 #define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
393 #define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
395 sPAPRIrq spapr_irq_xive
= {
396 .nr_irqs
= SPAPR_IRQ_XIVE_NR_IRQS
,
397 .nr_msis
= SPAPR_IRQ_XIVE_NR_MSIS
,
398 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
400 .init
= spapr_irq_init_xive
,
401 .claim
= spapr_irq_claim_xive
,
402 .free
= spapr_irq_free_xive
,
403 .qirq
= spapr_qirq_xive
,
404 .print_info
= spapr_irq_print_info_xive
,
405 .dt_populate
= spapr_dt_xive
,
406 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
407 .post_load
= spapr_irq_post_load_xive
,
408 .reset
= spapr_irq_reset_xive
,
409 .set_irq
= spapr_irq_set_irq_xive
,
413 * Dual XIVE and XICS IRQ backend.
415 * Both interrupt mode, XIVE and XICS, objects are created but the
416 * machine starts in legacy interrupt mode (XICS). It can be changed
417 * by the CAS negotiation process and, in that case, the new mode is
418 * activated after an extra machine reset.
422 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
425 static sPAPRIrq
*spapr_irq_current(sPAPRMachineState
*spapr
)
427 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
428 &spapr_irq_xive
: &spapr_irq_xics
;
431 static void spapr_irq_init_dual(sPAPRMachineState
*spapr
, int nr_irqs
,
434 MachineState
*machine
= MACHINE(spapr
);
435 Error
*local_err
= NULL
;
437 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
438 error_setg(errp
, "No KVM support for the 'dual' machine");
442 spapr_irq_xics
.init(spapr
, spapr_irq_xics
.nr_irqs
, &local_err
);
444 error_propagate(errp
, local_err
);
448 spapr_irq_xive
.init(spapr
, spapr_irq_xive
.nr_irqs
, &local_err
);
450 error_propagate(errp
, local_err
);
455 static int spapr_irq_claim_dual(sPAPRMachineState
*spapr
, int irq
, bool lsi
,
458 Error
*local_err
= NULL
;
461 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
463 error_propagate(errp
, local_err
);
467 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
469 error_propagate(errp
, local_err
);
476 static void spapr_irq_free_dual(sPAPRMachineState
*spapr
, int irq
, int num
)
478 spapr_irq_xics
.free(spapr
, irq
, num
);
479 spapr_irq_xive
.free(spapr
, irq
, num
);
482 static qemu_irq
spapr_qirq_dual(sPAPRMachineState
*spapr
, int irq
)
484 return spapr_irq_current(spapr
)->qirq(spapr
, irq
);
487 static void spapr_irq_print_info_dual(sPAPRMachineState
*spapr
, Monitor
*mon
)
489 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
492 static void spapr_irq_dt_populate_dual(sPAPRMachineState
*spapr
,
493 uint32_t nr_servers
, void *fdt
,
496 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
499 static void spapr_irq_cpu_intc_create_dual(sPAPRMachineState
*spapr
,
500 PowerPCCPU
*cpu
, Error
**errp
)
502 Error
*local_err
= NULL
;
504 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
506 error_propagate(errp
, local_err
);
510 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
513 static int spapr_irq_post_load_dual(sPAPRMachineState
*spapr
, int version_id
)
516 * Force a reset of the XIVE backend after migration. The machine
517 * defaults to XICS at startup.
519 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
520 spapr_irq_xive
.reset(spapr
, &error_fatal
);
523 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
526 static void spapr_irq_reset_dual(sPAPRMachineState
*spapr
, Error
**errp
)
529 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
532 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
534 spapr_irq_current(spapr
)->reset(spapr
, errp
);
537 static void spapr_irq_set_irq_dual(void *opaque
, int srcno
, int val
)
539 sPAPRMachineState
*spapr
= opaque
;
541 spapr_irq_current(spapr
)->set_irq(spapr
, srcno
, val
);
545 * Define values in sync with the XIVE and XICS backend
547 #define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
548 #define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
550 sPAPRIrq spapr_irq_dual
= {
551 .nr_irqs
= SPAPR_IRQ_DUAL_NR_IRQS
,
552 .nr_msis
= SPAPR_IRQ_DUAL_NR_MSIS
,
553 .ov5
= SPAPR_OV5_XIVE_BOTH
,
555 .init
= spapr_irq_init_dual
,
556 .claim
= spapr_irq_claim_dual
,
557 .free
= spapr_irq_free_dual
,
558 .qirq
= spapr_qirq_dual
,
559 .print_info
= spapr_irq_print_info_dual
,
560 .dt_populate
= spapr_irq_dt_populate_dual
,
561 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
562 .post_load
= spapr_irq_post_load_dual
,
563 .reset
= spapr_irq_reset_dual
,
564 .set_irq
= spapr_irq_set_irq_dual
568 * sPAPR IRQ frontend routines for devices
570 void spapr_irq_init(sPAPRMachineState
*spapr
, Error
**errp
)
572 MachineState
*machine
= MACHINE(spapr
);
574 if (machine_kernel_irqchip_split(machine
)) {
575 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
579 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
581 "kernel_irqchip requested but only available with KVM");
585 /* Initialize the MSI IRQ allocator. */
586 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
587 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
590 spapr
->irq
->init(spapr
, spapr
->irq
->nr_irqs
, errp
);
592 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
593 spapr
->irq
->nr_irqs
);
596 int spapr_irq_claim(sPAPRMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
598 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
601 void spapr_irq_free(sPAPRMachineState
*spapr
, int irq
, int num
)
603 spapr
->irq
->free(spapr
, irq
, num
);
606 qemu_irq
spapr_qirq(sPAPRMachineState
*spapr
, int irq
)
608 return spapr
->irq
->qirq(spapr
, irq
);
611 int spapr_irq_post_load(sPAPRMachineState
*spapr
, int version_id
)
613 return spapr
->irq
->post_load(spapr
, version_id
);
616 void spapr_irq_reset(sPAPRMachineState
*spapr
, Error
**errp
)
618 if (spapr
->irq
->reset
) {
619 spapr
->irq
->reset(spapr
, errp
);
624 * XICS legacy routines - to deprecate one day
627 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
631 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
632 if (num
> (ics
->nr_irqs
- first
)) {
635 for (i
= first
; i
< first
+ num
; ++i
) {
636 if (!ICS_IRQ_FREE(ics
, i
)) {
640 if (i
== (first
+ num
)) {
648 int spapr_irq_find(sPAPRMachineState
*spapr
, int num
, bool align
, Error
**errp
)
650 ICSState
*ics
= spapr
->ics
;
656 * MSIMesage::data is used for storing VIRQ so
657 * it has to be aligned to num to support multiple
658 * MSI vectors. MSI-X is not affected by this.
659 * The hint is used for the first IRQ, the rest should
660 * be allocated continuously.
663 assert((num
== 1) || (num
== 2) || (num
== 4) ||
664 (num
== 8) || (num
== 16) || (num
== 32));
665 first
= ics_find_free_block(ics
, num
, num
);
667 first
= ics_find_free_block(ics
, num
, 1);
671 error_setg(errp
, "can't find a free %d-IRQ block", num
);
675 return first
+ ics
->offset
;
678 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
680 sPAPRIrq spapr_irq_xics_legacy
= {
681 .nr_irqs
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
682 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_IRQS
,
683 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
685 .init
= spapr_irq_init_xics
,
686 .claim
= spapr_irq_claim_xics
,
687 .free
= spapr_irq_free_xics
,
688 .qirq
= spapr_qirq_xics
,
689 .print_info
= spapr_irq_print_info_xics
,
690 .dt_populate
= spapr_dt_xics
,
691 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
692 .post_load
= spapr_irq_post_load_xics
,
693 .set_irq
= spapr_irq_set_irq_xics
,