target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, int is_user,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     if (cpreg_field_is_64bit(ri)) {
 123         return CPREG_FIELD64(env, ri);
 124     } else {
 125         return CPREG_FIELD32(env, ri);
 126     }
 127 }
 128
 129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 130                       uint64_t value)
 131 {
 132     if (cpreg_field_is_64bit(ri)) {
 133         CPREG_FIELD64(env, ri) = value;
 134     } else {
 135         CPREG_FIELD32(env, ri) = value;
 136     }
 137 }
 138
 139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 140 {
 141     /* Raw read of a coprocessor register (as needed for migration, etc). */
 142     if (ri->type & ARM_CP_CONST) {
 143         return ri->resetvalue;
 144     } else if (ri->raw_readfn) {
 145         return ri->raw_readfn(env, ri);
 146     } else if (ri->readfn) {
 147         return ri->readfn(env, ri);
 148     } else {
 149         return raw_read(env, ri);
 150     }
 151 }
 152
 153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 154                              uint64_t v)
 155 {
 156     /* Raw write of a coprocessor register (as needed for migration, etc).
 157      * Note that constant registers are treated as write-ignored; the
 158      * caller should check for success by whether a readback gives the
 159      * value written.
 160      */
 161     if (ri->type & ARM_CP_CONST) {
 162         return;
 163     } else if (ri->raw_writefn) {
 164         ri->raw_writefn(env, ri, v);
 165     } else if (ri->writefn) {
 166         ri->writefn(env, ri, v);
 167     } else {
 168         raw_write(env, ri, v);
 169     }
 170 }
 171
 172 bool write_cpustate_to_list(ARMCPU *cpu)
 173 {
 174     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 175     int i;
 176     bool ok = true;
 177
 178     for (i = 0; i < cpu->cpreg_array_len; i++) {
 179         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 180         const ARMCPRegInfo *ri;
 181
 182         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 183         if (!ri) {
 184             ok = false;
 185             continue;
 186         }
 187         if (ri->type & ARM_CP_NO_MIGRATE) {
 188             continue;
 189         }
 190         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 191     }
 192     return ok;
 193 }
 194
 195 bool write_list_to_cpustate(ARMCPU *cpu)
 196 {
 197     int i;
 198     bool ok = true;
 199
 200     for (i = 0; i < cpu->cpreg_array_len; i++) {
 201         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 202         uint64_t v = cpu->cpreg_values[i];
 203         const ARMCPRegInfo *ri;
 204
 205         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 206         if (!ri) {
 207             ok = false;
 208             continue;
 209         }
 210         if (ri->type & ARM_CP_NO_MIGRATE) {
 211             continue;
 212         }
 213         /* Write value and confirm it reads back as written
 214          * (to catch read-only registers and partially read-only
 215          * registers where the incoming migration value doesn't match)
 216          */
 217         write_raw_cp_reg(&cpu->env, ri, v);
 218         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 219             ok = false;
 220         }
 221     }
 222     return ok;
 223 }
 224
 225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 226 {
 227     ARMCPU *cpu = opaque;
 228     uint64_t regidx;
 229     const ARMCPRegInfo *ri;
 230
 231     regidx = *(uint32_t *)key;
 232     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 233
 234     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 235         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 236         /* The value array need not be initialized at this point */
 237         cpu->cpreg_array_len++;
 238     }
 239 }
 240
 241 static void count_cpreg(gpointer key, gpointer opaque)
 242 {
 243     ARMCPU *cpu = opaque;
 244     uint64_t regidx;
 245     const ARMCPRegInfo *ri;
 246
 247     regidx = *(uint32_t *)key;
 248     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 249
 250     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 251         cpu->cpreg_array_len++;
 252     }
 253 }
 254
 255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 256 {
 257     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 258     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 259
 260     if (aidx > bidx) {
 261         return 1;
 262     }
 263     if (aidx < bidx) {
 264         return -1;
 265     }
 266     return 0;
 267 }
 268
 269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 270 {
 271     GList **plist = udata;
 272
 273     *plist = g_list_prepend(*plist, key);
 274 }
 275
 276 void init_cpreg_list(ARMCPU *cpu)
 277 {
 278     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 279      * Note that we require cpreg_tuples[] to be sorted by key ID.
 280      */
 281     GList *keys = NULL;
 282     int arraylen;
 283
 284     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 285
 286     keys = g_list_sort(keys, cpreg_key_compare);
 287
 288     cpu->cpreg_array_len = 0;
 289
 290     g_list_foreach(keys, count_cpreg, cpu);
 291
 292     arraylen = cpu->cpreg_array_len;
 293     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 294     cpu->cpreg_values = g_new(uint64_t, arraylen);
 295     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 296     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 297     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 298     cpu->cpreg_array_len = 0;
 299
 300     g_list_foreach(keys, add_cpreg_to_list, cpu);
 301
 302     assert(cpu->cpreg_array_len == arraylen);
 303
 304     g_list_free(keys);
 305 }
 306
 307 /* Return true if extended addresses are enabled.
 308  * This is always the case if our translation regime is 64 bit,
 309  * but depends on TTBCR.EAE for 32 bit.
 310  */
 311 static inline bool extended_addresses_enabled(CPUARMState *env)
 312 {
 313     return arm_el_is_aa64(env, 1)
 314         || ((arm_feature(env, ARM_FEATURE_LPAE)
 315              && (env->cp15.c2_control & TTBCR_EAE)));
 316 }
 317
 318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 319 {
 320     ARMCPU *cpu = arm_env_get_cpu(env);
 321
 322     raw_write(env, ri, value);
 323     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 324 }
 325
 326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 327 {
 328     ARMCPU *cpu = arm_env_get_cpu(env);
 329
 330     if (raw_read(env, ri) != value) {
 331         /* Unlike real hardware the qemu TLB uses virtual addresses,
 332          * not modified virtual addresses, so this causes a TLB flush.
 333          */
 334         tlb_flush(CPU(cpu), 1);
 335         raw_write(env, ri, value);
 336     }
 337 }
 338
 339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 340                              uint64_t value)
 341 {
 342     ARMCPU *cpu = arm_env_get_cpu(env);
 343
 344     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 345         && !extended_addresses_enabled(env)) {
 346         /* For VMSA (when not using the LPAE long descriptor page table
 347          * format) this register includes the ASID, so do a TLB flush.
 348          * For PMSA it is purely a process ID and no action is needed.
 349          */
 350         tlb_flush(CPU(cpu), 1);
 351     }
 352     raw_write(env, ri, value);
 353 }
 354
 355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 356                           uint64_t value)
 357 {
 358     /* Invalidate all (TLBIALL) */
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     tlb_flush(CPU(cpu), 1);
 362 }
 363
 364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 365                           uint64_t value)
 366 {
 367     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 368     ARMCPU *cpu = arm_env_get_cpu(env);
 369
 370     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 371 }
 372
 373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 374                            uint64_t value)
 375 {
 376     /* Invalidate by ASID (TLBIASID) */
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     tlb_flush(CPU(cpu), value == 0);
 380 }
 381
 382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 383                            uint64_t value)
 384 {
 385     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 386     ARMCPU *cpu = arm_env_get_cpu(env);
 387
 388     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 389 }
 390
 391 static const ARMCPRegInfo cp_reginfo[] = {
 392     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 393       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 394       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 395     { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
 396       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 397       .access = PL1_RW,
 398       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
 399       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 400     REGINFO_SENTINEL
 401 };
 402
 403 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 404     /* NB: Some of these registers exist in v8 but with more precise
 405      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 406      */
 407     /* MMU Domain access control / MPU write buffer control */
 408     { .name = "DACR", .cp = 15,
 409       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 410       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 411       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 412     /* ??? This covers not just the impdef TLB lockdown registers but also
 413      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 414      */
 415     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 416       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 417     /* MMU TLB control. Note that the wildcarding means we cover not just
 418      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 419      */
 420     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 421       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 422       .type = ARM_CP_NO_MIGRATE },
 423     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 424       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 425       .type = ARM_CP_NO_MIGRATE },
 426     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 427       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 428       .type = ARM_CP_NO_MIGRATE },
 429     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 430       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 431       .type = ARM_CP_NO_MIGRATE },
 432     /* Cache maintenance ops; some of this space may be overridden later. */
 433     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 434       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 435       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 436     REGINFO_SENTINEL
 437 };
 438
 439 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 440     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 441      * over-broad.
 442      */
 443     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 444       .access = PL1_W, .type = ARM_CP_WFI },
 445     REGINFO_SENTINEL
 446 };
 447
 448 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 449     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 450      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 451      */
 452     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 453       .access = PL1_W, .type = ARM_CP_WFI },
 454     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 455      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 456      * OMAPCP will override this space.
 457      */
 458     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 459       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 460       .resetvalue = 0 },
 461     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 462       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 463       .resetvalue = 0 },
 464     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 465     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 466       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 467       .resetvalue = 0 },
 468     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 469      * implementing it as RAZ means the "debug architecture version" bits
 470      * will read as a reserved value, which should cause Linux to not try
 471      * to use the debug hardware.
 472      */
 473     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 474       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 475     REGINFO_SENTINEL
 476 };
 477
 478 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 479                         uint64_t value)
 480 {
 481     uint32_t mask = 0;
 482
 483     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 484     if (!arm_feature(env, ARM_FEATURE_V8)) {
 485         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 486          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 487          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 488          */
 489         if (arm_feature(env, ARM_FEATURE_VFP)) {
 490             /* VFP coprocessor: cp10 & cp11 [23:20] */
 491             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 492
 493             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 494                 /* ASEDIS [31] bit is RAO/WI */
 495                 value |= (1 << 31);
 496             }
 497
 498             /* VFPv3 and upwards with NEON implement 32 double precision
 499              * registers (D0-D31).
 500              */
 501             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 502                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 503                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 504                 value |= (1 << 30);
 505             }
 506         }
 507         value &= mask;
 508     }
 509     env->cp15.c1_coproc = value;
 510 }
 511
 512 static const ARMCPRegInfo v6_cp_reginfo[] = {
 513     /* prefetch by MVA in v6, NOP in v7 */
 514     { .name = "MVA_prefetch",
 515       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 516       .access = PL1_W, .type = ARM_CP_NOP },
 517     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 518       .access = PL0_W, .type = ARM_CP_NOP },
 519     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 520       .access = PL0_W, .type = ARM_CP_NOP },
 521     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 522       .access = PL0_W, .type = ARM_CP_NOP },
 523     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 524       .access = PL1_RW,
 525       .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 526       .resetvalue = 0, },
 527     /* Watchpoint Fault Address Register : should actually only be present
 528      * for 1136, 1176, 11MPCore.
 529      */
 530     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 531       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 532     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 533       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 534       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 535       .resetvalue = 0, .writefn = cpacr_write },
 536     REGINFO_SENTINEL
 537 };
 538
 539 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 540 {
 541     /* Performance monitor registers user accessibility is controlled
 542      * by PMUSERENR.
 543      */
 544     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 545         return CP_ACCESS_TRAP;
 546     }
 547     return CP_ACCESS_OK;
 548 }
 549
 550 #ifndef CONFIG_USER_ONLY
 551
 552 static inline bool arm_ccnt_enabled(CPUARMState *env)
 553 {
 554     /* This does not support checking PMCCFILTR_EL0 register */
 555
 556     if (!(env->cp15.c9_pmcr & PMCRE)) {
 557         return false;
 558     }
 559
 560     return true;
 561 }
 562
 563 void pmccntr_sync(CPUARMState *env)
 564 {
 565     uint64_t temp_ticks;
 566
 567     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 568                           get_ticks_per_sec(), 1000000);
 569
 570     if (env->cp15.c9_pmcr & PMCRD) {
 571         /* Increment once every 64 processor clock cycles */
 572         temp_ticks /= 64;
 573     }
 574
 575     if (arm_ccnt_enabled(env)) {
 576         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 577     }
 578 }
 579
 580 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 581                        uint64_t value)
 582 {
 583     pmccntr_sync(env);
 584
 585     if (value & PMCRC) {
 586         /* The counter has been reset */
 587         env->cp15.c15_ccnt = 0;
 588     }
 589
 590     /* only the DP, X, D and E bits are writable */
 591     env->cp15.c9_pmcr &= ~0x39;
 592     env->cp15.c9_pmcr |= (value & 0x39);
 593
 594     pmccntr_sync(env);
 595 }
 596
 597 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 598 {
 599     uint64_t total_ticks;
 600
 601     if (!arm_ccnt_enabled(env)) {
 602         /* Counter is disabled, do not change value */
 603         return env->cp15.c15_ccnt;
 604     }
 605
 606     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 607                            get_ticks_per_sec(), 1000000);
 608
 609     if (env->cp15.c9_pmcr & PMCRD) {
 610         /* Increment once every 64 processor clock cycles */
 611         total_ticks /= 64;
 612     }
 613     return total_ticks - env->cp15.c15_ccnt;
 614 }
 615
 616 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 617                         uint64_t value)
 618 {
 619     uint64_t total_ticks;
 620
 621     if (!arm_ccnt_enabled(env)) {
 622         /* Counter is disabled, set the absolute value */
 623         env->cp15.c15_ccnt = value;
 624         return;
 625     }
 626
 627     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 628                            get_ticks_per_sec(), 1000000);
 629
 630     if (env->cp15.c9_pmcr & PMCRD) {
 631         /* Increment once every 64 processor clock cycles */
 632         total_ticks /= 64;
 633     }
 634     env->cp15.c15_ccnt = total_ticks - value;
 635 }
 636
 637 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 638                             uint64_t value)
 639 {
 640     uint64_t cur_val = pmccntr_read(env, NULL);
 641
 642     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 643 }
 644
 645 #else /* CONFIG_USER_ONLY */
 646
 647 void pmccntr_sync(CPUARMState *env)
 648 {
 649 }
 650
 651 #endif
 652
 653 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 654                             uint64_t value)
 655 {
 656     pmccntr_sync(env);
 657     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 658     pmccntr_sync(env);
 659 }
 660
 661 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 662                             uint64_t value)
 663 {
 664     value &= (1 << 31);
 665     env->cp15.c9_pmcnten |= value;
 666 }
 667
 668 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 669                              uint64_t value)
 670 {
 671     value &= (1 << 31);
 672     env->cp15.c9_pmcnten &= ~value;
 673 }
 674
 675 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 676                          uint64_t value)
 677 {
 678     env->cp15.c9_pmovsr &= ~value;
 679 }
 680
 681 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 682                              uint64_t value)
 683 {
 684     env->cp15.c9_pmxevtyper = value & 0xff;
 685 }
 686
 687 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 688                             uint64_t value)
 689 {
 690     env->cp15.c9_pmuserenr = value & 1;
 691 }
 692
 693 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 694                              uint64_t value)
 695 {
 696     /* We have no event counters so only the C bit can be changed */
 697     value &= (1 << 31);
 698     env->cp15.c9_pminten |= value;
 699 }
 700
 701 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 702                              uint64_t value)
 703 {
 704     value &= (1 << 31);
 705     env->cp15.c9_pminten &= ~value;
 706 }
 707
 708 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 709                        uint64_t value)
 710 {
 711     /* Note that even though the AArch64 view of this register has bits
 712      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 713      * architectural requirements for bits which are RES0 only in some
 714      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 715      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 716      */
 717     raw_write(env, ri, value & ~0x1FULL);
 718 }
 719
 720 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 721 {
 722     ARMCPU *cpu = arm_env_get_cpu(env);
 723     return cpu->ccsidr[env->cp15.c0_cssel];
 724 }
 725
 726 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 727                          uint64_t value)
 728 {
 729     raw_write(env, ri, value & 0xf);
 730 }
 731
 732 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 733 {
 734     CPUState *cs = ENV_GET_CPU(env);
 735     uint64_t ret = 0;
 736
 737     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 738         ret |= CPSR_I;
 739     }
 740     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 741         ret |= CPSR_F;
 742     }
 743     /* External aborts are not possible in QEMU so A bit is always clear */
 744     return ret;
 745 }
 746
 747 static const ARMCPRegInfo v7_cp_reginfo[] = {
 748     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 749     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 750       .access = PL1_W, .type = ARM_CP_NOP },
 751     /* Performance monitors are implementation defined in v7,
 752      * but with an ARM recommended set of registers, which we
 753      * follow (although we don't actually implement any counters)
 754      *
 755      * Performance registers fall into three categories:
 756      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 757      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 758      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 759      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 760      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 761      */
 762     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 763       .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
 764       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 765       .writefn = pmcntenset_write,
 766       .accessfn = pmreg_access,
 767       .raw_writefn = raw_write },
 768     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 769       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 770       .access = PL0_RW, .accessfn = pmreg_access,
 771       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 772       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 773     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 774       .access = PL0_RW,
 775       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 776       .accessfn = pmreg_access,
 777       .writefn = pmcntenclr_write,
 778       .type = ARM_CP_NO_MIGRATE },
 779     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 780       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 781       .access = PL0_RW, .accessfn = pmreg_access,
 782       .type = ARM_CP_NO_MIGRATE,
 783       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 784       .writefn = pmcntenclr_write },
 785     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 786       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 787       .accessfn = pmreg_access,
 788       .writefn = pmovsr_write,
 789       .raw_writefn = raw_write },
 790     /* Unimplemented so WI. */
 791     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 792       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 793     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 794      * We choose to RAZ/WI.
 795      */
 796     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 797       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 798       .accessfn = pmreg_access },
 799 #ifndef CONFIG_USER_ONLY
 800     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 801       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 802       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 803       .accessfn = pmreg_access },
 804     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 805       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 806       .access = PL0_RW, .accessfn = pmreg_access,
 807       .type = ARM_CP_IO,
 808       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 809 #endif
 810     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 811       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 812       .writefn = pmccfiltr_write,
 813       .access = PL0_RW, .accessfn = pmreg_access,
 814       .type = ARM_CP_IO,
 815       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 816       .resetvalue = 0, },
 817     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 818       .access = PL0_RW,
 819       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 820       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 821       .raw_writefn = raw_write },
 822     /* Unimplemented, RAZ/WI. */
 823     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 824       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 825       .accessfn = pmreg_access },
 826     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 827       .access = PL0_R | PL1_RW,
 828       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 829       .resetvalue = 0,
 830       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 831     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 832       .access = PL1_RW,
 833       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 834       .resetvalue = 0,
 835       .writefn = pmintenset_write, .raw_writefn = raw_write },
 836     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 837       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 838       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 839       .resetvalue = 0, .writefn = pmintenclr_write, },
 840     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 841       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 842       .access = PL1_RW, .writefn = vbar_write,
 843       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
 844       .resetvalue = 0 },
 845     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 846       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 847       .resetvalue = 0, },
 848     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 849       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 850       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 851     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 852       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 853       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 854       .writefn = csselr_write, .resetvalue = 0 },
 855     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 856      * just RAZ for all cores:
 857      */
 858     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 859       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 860       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 861     /* Auxiliary fault status registers: these also are IMPDEF, and we
 862      * choose to RAZ/WI for all cores.
 863      */
 864     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 865       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 866       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 867     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 868       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 869       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 870     /* MAIR can just read-as-written because we don't implement caches
 871      * and so don't need to care about memory attributes.
 872      */
 873     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 874       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 875       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 876       .resetvalue = 0 },
 877     /* For non-long-descriptor page tables these are PRRR and NMRR;
 878      * regardless they still act as reads-as-written for QEMU.
 879      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 880      * definition.
 881      */
 882     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 883       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 884       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 885       .resetfn = arm_cp_reset_ignore },
 886     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 887       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 888       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 889       .resetfn = arm_cp_reset_ignore },
 890     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
 891       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
 892       .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
 893     REGINFO_SENTINEL
 894 };
 895
 896 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 897                         uint64_t value)
 898 {
 899     value &= 1;
 900     env->teecr = value;
 901 }
 902
 903 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 904 {
 905     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 906         return CP_ACCESS_TRAP;
 907     }
 908     return CP_ACCESS_OK;
 909 }
 910
 911 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 912     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 913       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 914       .resetvalue = 0,
 915       .writefn = teecr_write },
 916     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 917       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 918       .accessfn = teehbr_access, .resetvalue = 0 },
 919     REGINFO_SENTINEL
 920 };
 921
 922 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 923     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
 924       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
 925       .access = PL0_RW,
 926       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
 927     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 928       .access = PL0_RW,
 929       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
 930       .resetfn = arm_cp_reset_ignore },
 931     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
 932       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
 933       .access = PL0_R|PL1_W,
 934       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
 935     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 936       .access = PL0_R|PL1_W,
 937       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
 938       .resetfn = arm_cp_reset_ignore },
 939     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
 940       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
 941       .access = PL1_RW,
 942       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
 943     REGINFO_SENTINEL
 944 };
 945
 946 #ifndef CONFIG_USER_ONLY
 947
 948 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
 949 {
 950     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
 951     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
 952         return CP_ACCESS_TRAP;
 953     }
 954     return CP_ACCESS_OK;
 955 }
 956
 957 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
 958 {
 959     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
 960     if (arm_current_pl(env) == 0 &&
 961         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
 962         return CP_ACCESS_TRAP;
 963     }
 964     return CP_ACCESS_OK;
 965 }
 966
 967 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
 968 {
 969     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
 970      * EL0[PV]TEN is zero.
 971      */
 972     if (arm_current_pl(env) == 0 &&
 973         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
 974         return CP_ACCESS_TRAP;
 975     }
 976     return CP_ACCESS_OK;
 977 }
 978
 979 static CPAccessResult gt_pct_access(CPUARMState *env,
 980                                          const ARMCPRegInfo *ri)
 981 {
 982     return gt_counter_access(env, GTIMER_PHYS);
 983 }
 984
 985 static CPAccessResult gt_vct_access(CPUARMState *env,
 986                                          const ARMCPRegInfo *ri)
 987 {
 988     return gt_counter_access(env, GTIMER_VIRT);
 989 }
 990
 991 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 992 {
 993     return gt_timer_access(env, GTIMER_PHYS);
 994 }
 995
 996 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 997 {
 998     return gt_timer_access(env, GTIMER_VIRT);
 999 }
1000
1001 static uint64_t gt_get_countervalue(CPUARMState *env)
1002 {
1003     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1004 }
1005
1006 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1007 {
1008     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1009
1010     if (gt->ctl & 1) {
1011         /* Timer enabled: calculate and set current ISTATUS, irq, and
1012          * reset timer to when ISTATUS next has to change
1013          */
1014         uint64_t count = gt_get_countervalue(&cpu->env);
1015         /* Note that this must be unsigned 64 bit arithmetic: */
1016         int istatus = count >= gt->cval;
1017         uint64_t nexttick;
1018
1019         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1020         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1021                      (istatus && !(gt->ctl & 2)));
1022         if (istatus) {
1023             /* Next transition is when count rolls back over to zero */
1024             nexttick = UINT64_MAX;
1025         } else {
1026             /* Next transition is when we hit cval */
1027             nexttick = gt->cval;
1028         }
1029         /* Note that the desired next expiry time might be beyond the
1030          * signed-64-bit range of a QEMUTimer -- in this case we just
1031          * set the timer for as far in the future as possible. When the
1032          * timer expires we will reset the timer for any remaining period.
1033          */
1034         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1035             nexttick = INT64_MAX / GTIMER_SCALE;
1036         }
1037         timer_mod(cpu->gt_timer[timeridx], nexttick);
1038     } else {
1039         /* Timer disabled: ISTATUS and timer output always clear */
1040         gt->ctl &= ~4;
1041         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1042         timer_del(cpu->gt_timer[timeridx]);
1043     }
1044 }
1045
1046 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1047 {
1048     ARMCPU *cpu = arm_env_get_cpu(env);
1049     int timeridx = ri->opc1 & 1;
1050
1051     timer_del(cpu->gt_timer[timeridx]);
1052 }
1053
1054 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1055 {
1056     return gt_get_countervalue(env);
1057 }
1058
1059 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1060                           uint64_t value)
1061 {
1062     int timeridx = ri->opc1 & 1;
1063
1064     env->cp15.c14_timer[timeridx].cval = value;
1065     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1066 }
1067
1068 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1069 {
1070     int timeridx = ri->crm & 1;
1071
1072     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1073                       gt_get_countervalue(env));
1074 }
1075
1076 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1077                           uint64_t value)
1078 {
1079     int timeridx = ri->crm & 1;
1080
1081     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1082         + sextract64(value, 0, 32);
1083     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1084 }
1085
1086 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1087                          uint64_t value)
1088 {
1089     ARMCPU *cpu = arm_env_get_cpu(env);
1090     int timeridx = ri->crm & 1;
1091     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1092
1093     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1094     if ((oldval ^ value) & 1) {
1095         /* Enable toggled */
1096         gt_recalc_timer(cpu, timeridx);
1097     } else if ((oldval ^ value) & 2) {
1098         /* IMASK toggled: don't need to recalculate,
1099          * just set the interrupt line based on ISTATUS
1100          */
1101         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1102                      (oldval & 4) && !(value & 2));
1103     }
1104 }
1105
1106 void arm_gt_ptimer_cb(void *opaque)
1107 {
1108     ARMCPU *cpu = opaque;
1109
1110     gt_recalc_timer(cpu, GTIMER_PHYS);
1111 }
1112
1113 void arm_gt_vtimer_cb(void *opaque)
1114 {
1115     ARMCPU *cpu = opaque;
1116
1117     gt_recalc_timer(cpu, GTIMER_VIRT);
1118 }
1119
1120 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1121     /* Note that CNTFRQ is purely reads-as-written for the benefit
1122      * of software; writing it doesn't actually change the timer frequency.
1123      * Our reset value matches the fixed frequency we implement the timer at.
1124      */
1125     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1126       .type = ARM_CP_NO_MIGRATE,
1127       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1128       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1129       .resetfn = arm_cp_reset_ignore,
1130     },
1131     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1132       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1133       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1134       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1135       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1136     },
1137     /* overall control: mostly access permissions */
1138     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1139       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1140       .access = PL1_RW,
1141       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1142       .resetvalue = 0,
1143     },
1144     /* per-timer control */
1145     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1146       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1147       .accessfn = gt_ptimer_access,
1148       .fieldoffset = offsetoflow32(CPUARMState,
1149                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1150       .resetfn = arm_cp_reset_ignore,
1151       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1152     },
1153     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1154       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1155       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1156       .accessfn = gt_ptimer_access,
1157       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1158       .resetvalue = 0,
1159       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1160     },
1161     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1162       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1163       .accessfn = gt_vtimer_access,
1164       .fieldoffset = offsetoflow32(CPUARMState,
1165                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1166       .resetfn = arm_cp_reset_ignore,
1167       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1168     },
1169     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1170       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1171       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1172       .accessfn = gt_vtimer_access,
1173       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1174       .resetvalue = 0,
1175       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1176     },
1177     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1178     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1179       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1180       .accessfn = gt_ptimer_access,
1181       .readfn = gt_tval_read, .writefn = gt_tval_write,
1182     },
1183     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1184       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1185       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1186       .readfn = gt_tval_read, .writefn = gt_tval_write,
1187     },
1188     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1189       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1190       .accessfn = gt_vtimer_access,
1191       .readfn = gt_tval_read, .writefn = gt_tval_write,
1192     },
1193     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1194       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1195       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1196       .readfn = gt_tval_read, .writefn = gt_tval_write,
1197     },
1198     /* The counter itself */
1199     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1200       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1201       .accessfn = gt_pct_access,
1202       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1203     },
1204     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1205       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1206       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1207       .accessfn = gt_pct_access,
1208       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1209     },
1210     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1211       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1212       .accessfn = gt_vct_access,
1213       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1214     },
1215     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1216       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1217       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1218       .accessfn = gt_vct_access,
1219       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1220     },
1221     /* Comparison value, indicating when the timer goes off */
1222     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1223       .access = PL1_RW | PL0_R,
1224       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1225       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1226       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1227       .writefn = gt_cval_write, .raw_writefn = raw_write,
1228     },
1229     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1230       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1231       .access = PL1_RW | PL0_R,
1232       .type = ARM_CP_IO,
1233       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1234       .resetvalue = 0, .accessfn = gt_vtimer_access,
1235       .writefn = gt_cval_write, .raw_writefn = raw_write,
1236     },
1237     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1238       .access = PL1_RW | PL0_R,
1239       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1240       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1241       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1242       .writefn = gt_cval_write, .raw_writefn = raw_write,
1243     },
1244     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1245       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1246       .access = PL1_RW | PL0_R,
1247       .type = ARM_CP_IO,
1248       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1249       .resetvalue = 0, .accessfn = gt_vtimer_access,
1250       .writefn = gt_cval_write, .raw_writefn = raw_write,
1251     },
1252     REGINFO_SENTINEL
1253 };
1254
1255 #else
1256 /* In user-mode none of the generic timer registers are accessible,
1257  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1258  * so instead just don't register any of them.
1259  */
1260 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1261     REGINFO_SENTINEL
1262 };
1263
1264 #endif
1265
1266 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1267 {
1268     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1269         raw_write(env, ri, value);
1270     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1271         raw_write(env, ri, value & 0xfffff6ff);
1272     } else {
1273         raw_write(env, ri, value & 0xfffff1ff);
1274     }
1275 }
1276
1277 #ifndef CONFIG_USER_ONLY
1278 /* get_phys_addr() isn't present for user-mode-only targets */
1279
1280 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1281 {
1282     if (ri->opc2 & 4) {
1283         /* Other states are only available with TrustZone; in
1284          * a non-TZ implementation these registers don't exist
1285          * at all, which is an Uncategorized trap. This underdecoding
1286          * is safe because the reginfo is NO_MIGRATE.
1287          */
1288         return CP_ACCESS_TRAP_UNCATEGORIZED;
1289     }
1290     return CP_ACCESS_OK;
1291 }
1292
1293 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1294 {
1295     hwaddr phys_addr;
1296     target_ulong page_size;
1297     int prot;
1298     int ret, is_user = ri->opc2 & 2;
1299     int access_type = ri->opc2 & 1;
1300
1301     ret = get_phys_addr(env, value, access_type, is_user,
1302                         &phys_addr, &prot, &page_size);
1303     if (extended_addresses_enabled(env)) {
1304         /* ret is a DFSR/IFSR value for the long descriptor
1305          * translation table format, but with WnR always clear.
1306          * Convert it to a 64-bit PAR.
1307          */
1308         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1309         if (ret == 0) {
1310             par64 |= phys_addr & ~0xfffULL;
1311             /* We don't set the ATTR or SH fields in the PAR. */
1312         } else {
1313             par64 |= 1; /* F */
1314             par64 |= (ret & 0x3f) << 1; /* FS */
1315             /* Note that S2WLK and FSTAGE are always zero, because we don't
1316              * implement virtualization and therefore there can't be a stage 2
1317              * fault.
1318              */
1319         }
1320         env->cp15.par_el1 = par64;
1321     } else {
1322         /* ret is a DFSR/IFSR value for the short descriptor
1323          * translation table format (with WnR always clear).
1324          * Convert it to a 32-bit PAR.
1325          */
1326         if (ret == 0) {
1327             /* We do not set any attribute bits in the PAR */
1328             if (page_size == (1 << 24)
1329                 && arm_feature(env, ARM_FEATURE_V7)) {
1330                 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1331             } else {
1332                 env->cp15.par_el1 = phys_addr & 0xfffff000;
1333             }
1334         } else {
1335             env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1336                 ((ret & (1 << 12)) >> 6) |
1337                 ((ret & 0xf) << 1) | 1;
1338         }
1339     }
1340 }
1341 #endif
1342
1343 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1344     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1345       .access = PL1_RW, .resetvalue = 0,
1346       .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1347       .writefn = par_write },
1348 #ifndef CONFIG_USER_ONLY
1349     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1350       .access = PL1_W, .accessfn = ats_access,
1351       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1352 #endif
1353     REGINFO_SENTINEL
1354 };
1355
1356 /* Return basic MPU access permission bits.  */
1357 static uint32_t simple_mpu_ap_bits(uint32_t val)
1358 {
1359     uint32_t ret;
1360     uint32_t mask;
1361     int i;
1362     ret = 0;
1363     mask = 3;
1364     for (i = 0; i < 16; i += 2) {
1365         ret |= (val >> i) & mask;
1366         mask <<= 2;
1367     }
1368     return ret;
1369 }
1370
1371 /* Pad basic MPU access permission bits to extended format.  */
1372 static uint32_t extended_mpu_ap_bits(uint32_t val)
1373 {
1374     uint32_t ret;
1375     uint32_t mask;
1376     int i;
1377     ret = 0;
1378     mask = 3;
1379     for (i = 0; i < 16; i += 2) {
1380         ret |= (val & mask) << i;
1381         mask <<= 2;
1382     }
1383     return ret;
1384 }
1385
1386 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1387                                  uint64_t value)
1388 {
1389     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1390 }
1391
1392 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1393 {
1394     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1395 }
1396
1397 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1398                                  uint64_t value)
1399 {
1400     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1401 }
1402
1403 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1404 {
1405     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1406 }
1407
1408 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1409     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1410       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1411       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1412       .resetvalue = 0,
1413       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1414     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1415       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1416       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1417       .resetvalue = 0,
1418       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1419     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1420       .access = PL1_RW,
1421       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1422       .resetvalue = 0, },
1423     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1424       .access = PL1_RW,
1425       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1426       .resetvalue = 0, },
1427     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1428       .access = PL1_RW,
1429       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1430     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1431       .access = PL1_RW,
1432       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1433     /* Protection region base and size registers */
1434     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1435       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1436       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1437     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1438       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1439       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1440     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1441       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1442       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1443     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1444       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1445       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1446     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1447       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1448       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1449     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1450       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1451       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1452     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1453       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1454       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1455     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1456       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1457       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1458     REGINFO_SENTINEL
1459 };
1460
1461 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1462                                  uint64_t value)
1463 {
1464     int maskshift = extract32(value, 0, 3);
1465
1466     if (!arm_feature(env, ARM_FEATURE_V8)) {
1467         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1468             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1469              * using Long-desciptor translation table format */
1470             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1471         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1472             /* In an implementation that includes the Security Extensions
1473              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1474              * Short-descriptor translation table format.
1475              */
1476             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1477         } else {
1478             value &= TTBCR_N;
1479         }
1480     }
1481
1482     /* Note that we always calculate c2_mask and c2_base_mask, but
1483      * they are only used for short-descriptor tables (ie if EAE is 0);
1484      * for long-descriptor tables the TTBCR fields are used differently
1485      * and the c2_mask and c2_base_mask values are meaningless.
1486      */
1487     raw_write(env, ri, value);
1488     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1489     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1490 }
1491
1492 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1493                              uint64_t value)
1494 {
1495     ARMCPU *cpu = arm_env_get_cpu(env);
1496
1497     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1498         /* With LPAE the TTBCR could result in a change of ASID
1499          * via the TTBCR.A1 bit, so do a TLB flush.
1500          */
1501         tlb_flush(CPU(cpu), 1);
1502     }
1503     vmsa_ttbcr_raw_write(env, ri, value);
1504 }
1505
1506 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1507 {
1508     env->cp15.c2_base_mask = 0xffffc000u;
1509     raw_write(env, ri, 0);
1510     env->cp15.c2_mask = 0;
1511 }
1512
1513 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1514                                uint64_t value)
1515 {
1516     ARMCPU *cpu = arm_env_get_cpu(env);
1517
1518     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1519     tlb_flush(CPU(cpu), 1);
1520     raw_write(env, ri, value);
1521 }
1522
1523 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1524                             uint64_t value)
1525 {
1526     /* 64 bit accesses to the TTBRs can change the ASID and so we
1527      * must flush the TLB.
1528      */
1529     if (cpreg_field_is_64bit(ri)) {
1530         ARMCPU *cpu = arm_env_get_cpu(env);
1531
1532         tlb_flush(CPU(cpu), 1);
1533     }
1534     raw_write(env, ri, value);
1535 }
1536
1537 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1538     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1539       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1540       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1541       .resetfn = arm_cp_reset_ignore, },
1542     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1543       .access = PL1_RW,
1544       .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1545     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1546       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1547       .access = PL1_RW,
1548       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1549     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1550       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1551       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1552       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1553     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1554       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1555       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1556       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1557     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1558       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1559       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1560       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1561       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1562     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1563       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1564       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1565       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1566     /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1567     { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1568       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1569       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1570       .resetvalue = 0, },
1571     REGINFO_SENTINEL
1572 };
1573
1574 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1575                                 uint64_t value)
1576 {
1577     env->cp15.c15_ticonfig = value & 0xe7;
1578     /* The OS_TYPE bit in this register changes the reported CPUID! */
1579     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1580         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1581 }
1582
1583 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1584                                 uint64_t value)
1585 {
1586     env->cp15.c15_threadid = value & 0xffff;
1587 }
1588
1589 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1590                            uint64_t value)
1591 {
1592     /* Wait-for-interrupt (deprecated) */
1593     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1594 }
1595
1596 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1597                                   uint64_t value)
1598 {
1599     /* On OMAP there are registers indicating the max/min index of dcache lines
1600      * containing a dirty line; cache flush operations have to reset these.
1601      */
1602     env->cp15.c15_i_max = 0x000;
1603     env->cp15.c15_i_min = 0xff0;
1604 }
1605
1606 static const ARMCPRegInfo omap_cp_reginfo[] = {
1607     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1608       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1609       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1610       .resetvalue = 0, },
1611     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1612       .access = PL1_RW, .type = ARM_CP_NOP },
1613     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1614       .access = PL1_RW,
1615       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1616       .writefn = omap_ticonfig_write },
1617     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1618       .access = PL1_RW,
1619       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1620     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1621       .access = PL1_RW, .resetvalue = 0xff0,
1622       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1623     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1624       .access = PL1_RW,
1625       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1626       .writefn = omap_threadid_write },
1627     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1628       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1629       .type = ARM_CP_NO_MIGRATE,
1630       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1631     /* TODO: Peripheral port remap register:
1632      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1633      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1634      * when MMU is off.
1635      */
1636     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1637       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1638       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1639       .writefn = omap_cachemaint_write },
1640     { .name = "C9", .cp = 15, .crn = 9,
1641       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1642       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1643     REGINFO_SENTINEL
1644 };
1645
1646 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1647                               uint64_t value)
1648 {
1649     value &= 0x3fff;
1650     if (env->cp15.c15_cpar != value) {
1651         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1652         tb_flush(env);
1653         env->cp15.c15_cpar = value;
1654     }
1655 }
1656
1657 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1658     { .name = "XSCALE_CPAR",
1659       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1660       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1661       .writefn = xscale_cpar_write, },
1662     { .name = "XSCALE_AUXCR",
1663       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1664       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1665       .resetvalue = 0, },
1666     /* XScale specific cache-lockdown: since we have no cache we NOP these
1667      * and hope the guest does not really rely on cache behaviour.
1668      */
1669     { .name = "XSCALE_LOCK_ICACHE_LINE",
1670       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1671       .access = PL1_W, .type = ARM_CP_NOP },
1672     { .name = "XSCALE_UNLOCK_ICACHE",
1673       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1674       .access = PL1_W, .type = ARM_CP_NOP },
1675     { .name = "XSCALE_DCACHE_LOCK",
1676       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1677       .access = PL1_RW, .type = ARM_CP_NOP },
1678     { .name = "XSCALE_UNLOCK_DCACHE",
1679       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1680       .access = PL1_W, .type = ARM_CP_NOP },
1681     REGINFO_SENTINEL
1682 };
1683
1684 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1685     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1686      * implementation of this implementation-defined space.
1687      * Ideally this should eventually disappear in favour of actually
1688      * implementing the correct behaviour for all cores.
1689      */
1690     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1691       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1692       .access = PL1_RW,
1693       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1694       .resetvalue = 0 },
1695     REGINFO_SENTINEL
1696 };
1697
1698 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1699     /* Cache status: RAZ because we have no cache so it's always clean */
1700     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1701       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1702       .resetvalue = 0 },
1703     REGINFO_SENTINEL
1704 };
1705
1706 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1707     /* We never have a a block transfer operation in progress */
1708     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1709       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1710       .resetvalue = 0 },
1711     /* The cache ops themselves: these all NOP for QEMU */
1712     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1713       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1714     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1715       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1716     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1717       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1718     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1719       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1720     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1721       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1722     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1723       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1724     REGINFO_SENTINEL
1725 };
1726
1727 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1728     /* The cache test-and-clean instructions always return (1 << 30)
1729      * to indicate that there are no dirty cache lines.
1730      */
1731     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1732       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1733       .resetvalue = (1 << 30) },
1734     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1735       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1736       .resetvalue = (1 << 30) },
1737     REGINFO_SENTINEL
1738 };
1739
1740 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1741     /* Ignore ReadBuffer accesses */
1742     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1743       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1744       .access = PL1_RW, .resetvalue = 0,
1745       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1746     REGINFO_SENTINEL
1747 };
1748
1749 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1750 {
1751     CPUState *cs = CPU(arm_env_get_cpu(env));
1752     uint32_t mpidr = cs->cpu_index;
1753     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1754      * in later ARM ARM versions), or any of the higher affinity level fields,
1755      * so these bits always RAZ.
1756      */
1757     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1758         mpidr |= (1U << 31);
1759         /* Cores which are uniprocessor (non-coherent)
1760          * but still implement the MP extensions set
1761          * bit 30. (For instance, A9UP.) However we do
1762          * not currently model any of those cores.
1763          */
1764     }
1765     return mpidr;
1766 }
1767
1768 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1769     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1770       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1771       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1772     REGINFO_SENTINEL
1773 };
1774
1775 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1776     /* NOP AMAIR0/1: the override is because these clash with the rather
1777      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1778      */
1779     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1780       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1781       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1782       .resetvalue = 0 },
1783     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1784     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1785       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1786       .resetvalue = 0 },
1787     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1788       .access = PL1_RW, .type = ARM_CP_64BIT,
1789       .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1790     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1791       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1792       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1793       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1794     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1795       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1796       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1797       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1798     REGINFO_SENTINEL
1799 };
1800
1801 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1802 {
1803     return vfp_get_fpcr(env);
1804 }
1805
1806 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1807                             uint64_t value)
1808 {
1809     vfp_set_fpcr(env, value);
1810 }
1811
1812 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1813 {
1814     return vfp_get_fpsr(env);
1815 }
1816
1817 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1818                             uint64_t value)
1819 {
1820     vfp_set_fpsr(env, value);
1821 }
1822
1823 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1824 {
1825     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1826         return CP_ACCESS_TRAP;
1827     }
1828     return CP_ACCESS_OK;
1829 }
1830
1831 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1832                             uint64_t value)
1833 {
1834     env->daif = value & PSTATE_DAIF;
1835 }
1836
1837 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1838                                           const ARMCPRegInfo *ri)
1839 {
1840     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1841      * SCTLR_EL1.UCI is set.
1842      */
1843     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1844         return CP_ACCESS_TRAP;
1845     }
1846     return CP_ACCESS_OK;
1847 }
1848
1849 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
1850  * Page D4-1736 (DDI0487A.b)
1851  */
1852
1853 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1854                                uint64_t value)
1855 {
1856     /* Invalidate by VA (AArch64 version) */
1857     ARMCPU *cpu = arm_env_get_cpu(env);
1858     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1859
1860     tlb_flush_page(CPU(cpu), pageaddr);
1861 }
1862
1863 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1864                                 uint64_t value)
1865 {
1866     /* Invalidate by VA, all ASIDs (AArch64 version) */
1867     ARMCPU *cpu = arm_env_get_cpu(env);
1868     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1869
1870     tlb_flush_page(CPU(cpu), pageaddr);
1871 }
1872
1873 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1874                                  uint64_t value)
1875 {
1876     /* Invalidate by ASID (AArch64 version) */
1877     ARMCPU *cpu = arm_env_get_cpu(env);
1878     int asid = extract64(value, 48, 16);
1879     tlb_flush(CPU(cpu), asid == 0);
1880 }
1881
1882 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1883 {
1884     /* We don't implement EL2, so the only control on DC ZVA is the
1885      * bit in the SCTLR which can prohibit access for EL0.
1886      */
1887     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1888         return CP_ACCESS_TRAP;
1889     }
1890     return CP_ACCESS_OK;
1891 }
1892
1893 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1894 {
1895     ARMCPU *cpu = arm_env_get_cpu(env);
1896     int dzp_bit = 1 << 4;
1897
1898     /* DZP indicates whether DC ZVA access is allowed */
1899     if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1900         dzp_bit = 0;
1901     }
1902     return cpu->dcz_blocksize | dzp_bit;
1903 }
1904
1905 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1906 {
1907     if (!(env->pstate & PSTATE_SP)) {
1908         /* Access to SP_EL0 is undefined if it's being used as
1909          * the stack pointer.
1910          */
1911         return CP_ACCESS_TRAP_UNCATEGORIZED;
1912     }
1913     return CP_ACCESS_OK;
1914 }
1915
1916 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1917 {
1918     return env->pstate & PSTATE_SP;
1919 }
1920
1921 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1922 {
1923     update_spsel(env, val);
1924 }
1925
1926 static const ARMCPRegInfo v8_cp_reginfo[] = {
1927     /* Minimal set of EL0-visible registers. This will need to be expanded
1928      * significantly for system emulation of AArch64 CPUs.
1929      */
1930     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1931       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1932       .access = PL0_RW, .type = ARM_CP_NZCV },
1933     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1934       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1935       .type = ARM_CP_NO_MIGRATE,
1936       .access = PL0_RW, .accessfn = aa64_daif_access,
1937       .fieldoffset = offsetof(CPUARMState, daif),
1938       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1939     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1940       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1941       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1942     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1943       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1944       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1945     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1946       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1947       .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1948       .readfn = aa64_dczid_read },
1949     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1950       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1951       .access = PL0_W, .type = ARM_CP_DC_ZVA,
1952 #ifndef CONFIG_USER_ONLY
1953       /* Avoid overhead of an access check that always passes in user-mode */
1954       .accessfn = aa64_zva_access,
1955 #endif
1956     },
1957     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1958       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1959       .access = PL1_R, .type = ARM_CP_CURRENTEL },
1960     /* Cache ops: all NOPs since we don't emulate caches */
1961     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1962       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1963       .access = PL1_W, .type = ARM_CP_NOP },
1964     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1965       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1966       .access = PL1_W, .type = ARM_CP_NOP },
1967     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1968       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1969       .access = PL0_W, .type = ARM_CP_NOP,
1970       .accessfn = aa64_cacheop_access },
1971     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1972       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1973       .access = PL1_W, .type = ARM_CP_NOP },
1974     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1975       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1976       .access = PL1_W, .type = ARM_CP_NOP },
1977     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1978       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1979       .access = PL0_W, .type = ARM_CP_NOP,
1980       .accessfn = aa64_cacheop_access },
1981     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1982       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1983       .access = PL1_W, .type = ARM_CP_NOP },
1984     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1985       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1986       .access = PL0_W, .type = ARM_CP_NOP,
1987       .accessfn = aa64_cacheop_access },
1988     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1989       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1990       .access = PL0_W, .type = ARM_CP_NOP,
1991       .accessfn = aa64_cacheop_access },
1992     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1993       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1994       .access = PL1_W, .type = ARM_CP_NOP },
1995     /* TLBI operations */
1996     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1997       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1998       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1999       .writefn = tlbiall_write },
2000     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2001       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2002       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2003       .writefn = tlbi_aa64_va_write },
2004     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2005       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2006       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2007       .writefn = tlbi_aa64_asid_write },
2008     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2009       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2010       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2011       .writefn = tlbi_aa64_vaa_write },
2012     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2013       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2014       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2015       .writefn = tlbi_aa64_va_write },
2016     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2017       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2018       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2019       .writefn = tlbi_aa64_vaa_write },
2020     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2021       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2022       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2023       .writefn = tlbiall_write },
2024     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2025       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2026       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2027       .writefn = tlbi_aa64_va_write },
2028     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2029       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2030       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2031       .writefn = tlbi_aa64_asid_write },
2032     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2033       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2034       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2035       .writefn = tlbi_aa64_vaa_write },
2036     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2037       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2038       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2039       .writefn = tlbi_aa64_va_write },
2040     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2041       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2042       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2043       .writefn = tlbi_aa64_vaa_write },
2044 #ifndef CONFIG_USER_ONLY
2045     /* 64 bit address translation operations */
2046     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2047       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2048       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2049     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2050       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2051       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2052     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2053       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2054       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2055     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2056       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2057       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2058 #endif
2059     /* 32 bit TLB invalidates, Inner Shareable */
2060     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2061       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2062     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2063       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2064     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2065       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2066     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2067       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2068     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2069       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2070     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2071       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2072     /* 32 bit ITLB invalidates */
2073     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2074       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2075     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2076       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2077     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2078       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2079     /* 32 bit DTLB invalidates */
2080     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2081       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2082     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2083       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2084     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2085       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2086     /* 32 bit TLB invalidates */
2087     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2088       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2089     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2090       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2091     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2092       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2093     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2094       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2095     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2096       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2097     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2098       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2099     /* 32 bit cache operations */
2100     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2101       .type = ARM_CP_NOP, .access = PL1_W },
2102     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2103       .type = ARM_CP_NOP, .access = PL1_W },
2104     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2105       .type = ARM_CP_NOP, .access = PL1_W },
2106     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2107       .type = ARM_CP_NOP, .access = PL1_W },
2108     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2109       .type = ARM_CP_NOP, .access = PL1_W },
2110     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2111       .type = ARM_CP_NOP, .access = PL1_W },
2112     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2113       .type = ARM_CP_NOP, .access = PL1_W },
2114     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2115       .type = ARM_CP_NOP, .access = PL1_W },
2116     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2117       .type = ARM_CP_NOP, .access = PL1_W },
2118     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2119       .type = ARM_CP_NOP, .access = PL1_W },
2120     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2121       .type = ARM_CP_NOP, .access = PL1_W },
2122     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2123       .type = ARM_CP_NOP, .access = PL1_W },
2124     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2125       .type = ARM_CP_NOP, .access = PL1_W },
2126     /* MMU Domain access control / MPU write buffer control */
2127     { .name = "DACR", .cp = 15,
2128       .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2129       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2130       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2131     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2132       .type = ARM_CP_NO_MIGRATE,
2133       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2134       .access = PL1_RW,
2135       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2136     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2137       .type = ARM_CP_NO_MIGRATE,
2138       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2139       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2140     /* We rely on the access checks not allowing the guest to write to the
2141      * state field when SPSel indicates that it's being used as the stack
2142      * pointer.
2143      */
2144     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2145       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2146       .access = PL1_RW, .accessfn = sp_el0_access,
2147       .type = ARM_CP_NO_MIGRATE,
2148       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2149     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2150       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2151       .type = ARM_CP_NO_MIGRATE,
2152       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2153     REGINFO_SENTINEL
2154 };
2155
2156 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2157 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2158     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2159       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2160       .access = PL2_RW,
2161       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2162     REGINFO_SENTINEL
2163 };
2164
2165 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2166     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2167       .type = ARM_CP_NO_MIGRATE,
2168       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2169       .access = PL2_RW,
2170       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2171     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2172       .type = ARM_CP_NO_MIGRATE,
2173       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2174       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2175     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2176       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2177       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2178     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2179       .type = ARM_CP_NO_MIGRATE,
2180       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2181       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2182     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2183       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2184       .access = PL2_RW, .writefn = vbar_write,
2185       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2186       .resetvalue = 0 },
2187     REGINFO_SENTINEL
2188 };
2189
2190 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2191     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2192       .type = ARM_CP_NO_MIGRATE,
2193       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2194       .access = PL3_RW,
2195       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2196     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2197       .type = ARM_CP_NO_MIGRATE,
2198       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2199       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2200     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2201       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2202       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2203     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2204       .type = ARM_CP_NO_MIGRATE,
2205       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2206       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2207     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2208       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2209       .access = PL3_RW, .writefn = vbar_write,
2210       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2211       .resetvalue = 0 },
2212     REGINFO_SENTINEL
2213 };
2214
2215 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2216                         uint64_t value)
2217 {
2218     ARMCPU *cpu = arm_env_get_cpu(env);
2219
2220     if (raw_read(env, ri) == value) {
2221         /* Skip the TLB flush if nothing actually changed; Linux likes
2222          * to do a lot of pointless SCTLR writes.
2223          */
2224         return;
2225     }
2226
2227     raw_write(env, ri, value);
2228     /* ??? Lots of these bits are not implemented.  */
2229     /* This may enable/disable the MMU, so do a TLB flush.  */
2230     tlb_flush(CPU(cpu), 1);
2231 }
2232
2233 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2234 {
2235     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2236      * but the AArch32 CTR has its own reginfo struct)
2237      */
2238     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2239         return CP_ACCESS_TRAP;
2240     }
2241     return CP_ACCESS_OK;
2242 }
2243
2244 static const ARMCPRegInfo debug_cp_reginfo[] = {
2245     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2246      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2247      * unlike DBGDRAR it is never accessible from EL0.
2248      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2249      * accessor.
2250      */
2251     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2252       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2253     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2254       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2255       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2256     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2257       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2258     /* Dummy implementation of monitor debug system control register:
2259      * we don't support debug. (The 32-bit alias is DBGDSCRext.)
2260      */
2261     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2262       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2263       .access = PL1_RW,
2264       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2265       .resetvalue = 0 },
2266     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2267     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2268       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2269       .access = PL1_W, .type = ARM_CP_NOP },
2270     REGINFO_SENTINEL
2271 };
2272
2273 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2274     /* 64 bit access versions of the (dummy) debug registers */
2275     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2276       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2277     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2278       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2279     REGINFO_SENTINEL
2280 };
2281
2282 static void define_debug_regs(ARMCPU *cpu)
2283 {
2284     /* Define v7 and v8 architectural debug registers.
2285      * These are just dummy implementations for now.
2286      */
2287     int i;
2288     int wrps, brps;
2289     ARMCPRegInfo dbgdidr = {
2290         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2291         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2292     };
2293
2294     brps = extract32(cpu->dbgdidr, 24, 4);
2295     wrps = extract32(cpu->dbgdidr, 28, 4);
2296
2297     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2298      * of the debug registers such as number of breakpoints;
2299      * check that if they both exist then they agree.
2300      */
2301     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2302         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2303         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2304     }
2305
2306     define_one_arm_cp_reg(cpu, &dbgdidr);
2307     define_arm_cp_regs(cpu, debug_cp_reginfo);
2308
2309     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2310         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2311     }
2312
2313     for (i = 0; i < brps + 1; i++) {
2314         ARMCPRegInfo dbgregs[] = {
2315             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2316               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2317               .access = PL1_RW,
2318               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2319             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2320               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2321               .access = PL1_RW,
2322               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2323             REGINFO_SENTINEL
2324         };
2325         define_arm_cp_regs(cpu, dbgregs);
2326     }
2327
2328     for (i = 0; i < wrps + 1; i++) {
2329         ARMCPRegInfo dbgregs[] = {
2330             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2331               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2332               .access = PL1_RW,
2333               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2334             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2335               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2336               .access = PL1_RW,
2337               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2338                REGINFO_SENTINEL
2339         };
2340         define_arm_cp_regs(cpu, dbgregs);
2341     }
2342 }
2343
2344 void register_cp_regs_for_features(ARMCPU *cpu)
2345 {
2346     /* Register all the coprocessor registers based on feature bits */
2347     CPUARMState *env = &cpu->env;
2348     if (arm_feature(env, ARM_FEATURE_M)) {
2349         /* M profile has no coprocessor registers */
2350         return;
2351     }
2352
2353     define_arm_cp_regs(cpu, cp_reginfo);
2354     if (!arm_feature(env, ARM_FEATURE_V8)) {
2355         /* Must go early as it is full of wildcards that may be
2356          * overridden by later definitions.
2357          */
2358         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2359     }
2360
2361     if (arm_feature(env, ARM_FEATURE_V6)) {
2362         /* The ID registers all have impdef reset values */
2363         ARMCPRegInfo v6_idregs[] = {
2364             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2365               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2366               .access = PL1_R, .type = ARM_CP_CONST,
2367               .resetvalue = cpu->id_pfr0 },
2368             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2369               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2370               .access = PL1_R, .type = ARM_CP_CONST,
2371               .resetvalue = cpu->id_pfr1 },
2372             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2373               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2374               .access = PL1_R, .type = ARM_CP_CONST,
2375               .resetvalue = cpu->id_dfr0 },
2376             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2377               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2378               .access = PL1_R, .type = ARM_CP_CONST,
2379               .resetvalue = cpu->id_afr0 },
2380             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2381               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2382               .access = PL1_R, .type = ARM_CP_CONST,
2383               .resetvalue = cpu->id_mmfr0 },
2384             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2385               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2386               .access = PL1_R, .type = ARM_CP_CONST,
2387               .resetvalue = cpu->id_mmfr1 },
2388             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2389               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2390               .access = PL1_R, .type = ARM_CP_CONST,
2391               .resetvalue = cpu->id_mmfr2 },
2392             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2393               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2394               .access = PL1_R, .type = ARM_CP_CONST,
2395               .resetvalue = cpu->id_mmfr3 },
2396             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2397               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2398               .access = PL1_R, .type = ARM_CP_CONST,
2399               .resetvalue = cpu->id_isar0 },
2400             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2401               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2402               .access = PL1_R, .type = ARM_CP_CONST,
2403               .resetvalue = cpu->id_isar1 },
2404             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2405               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2406               .access = PL1_R, .type = ARM_CP_CONST,
2407               .resetvalue = cpu->id_isar2 },
2408             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2409               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2410               .access = PL1_R, .type = ARM_CP_CONST,
2411               .resetvalue = cpu->id_isar3 },
2412             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2413               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2414               .access = PL1_R, .type = ARM_CP_CONST,
2415               .resetvalue = cpu->id_isar4 },
2416             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2417               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2418               .access = PL1_R, .type = ARM_CP_CONST,
2419               .resetvalue = cpu->id_isar5 },
2420             /* 6..7 are as yet unallocated and must RAZ */
2421             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2422               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2423               .resetvalue = 0 },
2424             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2425               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2426               .resetvalue = 0 },
2427             REGINFO_SENTINEL
2428         };
2429         define_arm_cp_regs(cpu, v6_idregs);
2430         define_arm_cp_regs(cpu, v6_cp_reginfo);
2431     } else {
2432         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2433     }
2434     if (arm_feature(env, ARM_FEATURE_V6K)) {
2435         define_arm_cp_regs(cpu, v6k_cp_reginfo);
2436     }
2437     if (arm_feature(env, ARM_FEATURE_V7)) {
2438         /* v7 performance monitor control register: same implementor
2439          * field as main ID register, and we implement only the cycle
2440          * count register.
2441          */
2442 #ifndef CONFIG_USER_ONLY
2443         ARMCPRegInfo pmcr = {
2444             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2445             .access = PL0_RW,
2446             .type = ARM_CP_IO | ARM_CP_NO_MIGRATE,
2447             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
2448             .accessfn = pmreg_access, .writefn = pmcr_write,
2449             .raw_writefn = raw_write,
2450         };
2451         ARMCPRegInfo pmcr64 = {
2452             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
2453             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
2454             .access = PL0_RW, .accessfn = pmreg_access,
2455             .type = ARM_CP_IO,
2456             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2457             .resetvalue = cpu->midr & 0xff000000,
2458             .writefn = pmcr_write, .raw_writefn = raw_write,
2459         };
2460         define_one_arm_cp_reg(cpu, &pmcr);
2461         define_one_arm_cp_reg(cpu, &pmcr64);
2462 #endif
2463         ARMCPRegInfo clidr = {
2464             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2465             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2466             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2467         };
2468         define_one_arm_cp_reg(cpu, &clidr);
2469         define_arm_cp_regs(cpu, v7_cp_reginfo);
2470         define_debug_regs(cpu);
2471     } else {
2472         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2473     }
2474     if (arm_feature(env, ARM_FEATURE_V8)) {
2475         /* AArch64 ID registers, which all have impdef reset values */
2476         ARMCPRegInfo v8_idregs[] = {
2477             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2478               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2479               .access = PL1_R, .type = ARM_CP_CONST,
2480               .resetvalue = cpu->id_aa64pfr0 },
2481             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2482               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2483               .access = PL1_R, .type = ARM_CP_CONST,
2484               .resetvalue = cpu->id_aa64pfr1},
2485             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2486               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2487               .access = PL1_R, .type = ARM_CP_CONST,
2488               /* We mask out the PMUVer field, because we don't currently
2489                * implement the PMU. Not advertising it prevents the guest
2490                * from trying to use it and getting UNDEFs on registers we
2491                * don't implement.
2492                */
2493               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2494             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2495               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2496               .access = PL1_R, .type = ARM_CP_CONST,
2497               .resetvalue = cpu->id_aa64dfr1 },
2498             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2499               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2500               .access = PL1_R, .type = ARM_CP_CONST,
2501               .resetvalue = cpu->id_aa64afr0 },
2502             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2503               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2504               .access = PL1_R, .type = ARM_CP_CONST,
2505               .resetvalue = cpu->id_aa64afr1 },
2506             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2507               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2508               .access = PL1_R, .type = ARM_CP_CONST,
2509               .resetvalue = cpu->id_aa64isar0 },
2510             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2511               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2512               .access = PL1_R, .type = ARM_CP_CONST,
2513               .resetvalue = cpu->id_aa64isar1 },
2514             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2515               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2516               .access = PL1_R, .type = ARM_CP_CONST,
2517               .resetvalue = cpu->id_aa64mmfr0 },
2518             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2519               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2520               .access = PL1_R, .type = ARM_CP_CONST,
2521               .resetvalue = cpu->id_aa64mmfr1 },
2522             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2523               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2524               .access = PL1_R, .type = ARM_CP_CONST,
2525               .resetvalue = cpu->mvfr0 },
2526             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2527               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2528               .access = PL1_R, .type = ARM_CP_CONST,
2529               .resetvalue = cpu->mvfr1 },
2530             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2531               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2532               .access = PL1_R, .type = ARM_CP_CONST,
2533               .resetvalue = cpu->mvfr2 },
2534             REGINFO_SENTINEL
2535         };
2536         ARMCPRegInfo rvbar = {
2537             .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2538             .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2539             .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2540         };
2541         define_one_arm_cp_reg(cpu, &rvbar);
2542         define_arm_cp_regs(cpu, v8_idregs);
2543         define_arm_cp_regs(cpu, v8_cp_reginfo);
2544     }
2545     if (arm_feature(env, ARM_FEATURE_EL2)) {
2546         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
2547     } else {
2548         /* If EL2 is missing but higher ELs are enabled, we need to
2549          * register the no_el2 reginfos.
2550          */
2551         if (arm_feature(env, ARM_FEATURE_EL3)) {
2552             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
2553         }
2554     }
2555     if (arm_feature(env, ARM_FEATURE_EL3)) {
2556         define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
2557     }
2558     if (arm_feature(env, ARM_FEATURE_MPU)) {
2559         /* These are the MPU registers prior to PMSAv6. Any new
2560          * PMSA core later than the ARM946 will require that we
2561          * implement the PMSAv6 or PMSAv7 registers, which are
2562          * completely different.
2563          */
2564         assert(!arm_feature(env, ARM_FEATURE_V6));
2565         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2566     } else {
2567         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2568     }
2569     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2570         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2571     }
2572     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2573         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2574     }
2575     if (arm_feature(env, ARM_FEATURE_VAPA)) {
2576         define_arm_cp_regs(cpu, vapa_cp_reginfo);
2577     }
2578     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2579         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2580     }
2581     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2582         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2583     }
2584     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2585         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2586     }
2587     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2588         define_arm_cp_regs(cpu, omap_cp_reginfo);
2589     }
2590     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2591         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2592     }
2593     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2594         define_arm_cp_regs(cpu, xscale_cp_reginfo);
2595     }
2596     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2597         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2598     }
2599     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2600         define_arm_cp_regs(cpu, lpae_cp_reginfo);
2601     }
2602     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2603      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2604      * be read-only (ie write causes UNDEF exception).
2605      */
2606     {
2607         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
2608             /* Pre-v8 MIDR space.
2609              * Note that the MIDR isn't a simple constant register because
2610              * of the TI925 behaviour where writes to another register can
2611              * cause the MIDR value to change.
2612              *
2613              * Unimplemented registers in the c15 0 0 0 space default to
2614              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2615              * and friends override accordingly.
2616              */
2617             { .name = "MIDR",
2618               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2619               .access = PL1_R, .resetvalue = cpu->midr,
2620               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2621               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2622               .type = ARM_CP_OVERRIDE },
2623             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2624             { .name = "DUMMY",
2625               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2626               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2627             { .name = "DUMMY",
2628               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2629               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2630             { .name = "DUMMY",
2631               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2632               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2633             { .name = "DUMMY",
2634               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2635               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2636             { .name = "DUMMY",
2637               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2638               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2639             REGINFO_SENTINEL
2640         };
2641         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
2642             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2643              * variable-MIDR TI925 behaviour. Instead we have a single
2644              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2645              */
2646             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
2647               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
2648               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2649             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
2650               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
2651               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2652             REGINFO_SENTINEL
2653         };
2654         ARMCPRegInfo id_cp_reginfo[] = {
2655             /* These are common to v8 and pre-v8 */
2656             { .name = "CTR",
2657               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2658               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2659             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2660               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2661               .access = PL0_R, .accessfn = ctr_el0_access,
2662               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2663             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2664             { .name = "TCMTR",
2665               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2666               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2667             { .name = "TLBTR",
2668               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2669               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2670             REGINFO_SENTINEL
2671         };
2672         ARMCPRegInfo crn0_wi_reginfo = {
2673             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2674             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2675             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2676         };
2677         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2678             arm_feature(env, ARM_FEATURE_STRONGARM)) {
2679             ARMCPRegInfo *r;
2680             /* Register the blanket "writes ignored" value first to cover the
2681              * whole space. Then update the specific ID registers to allow write
2682              * access, so that they ignore writes rather than causing them to
2683              * UNDEF.
2684              */
2685             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2686             for (r = id_pre_v8_midr_cp_reginfo;
2687                  r->type != ARM_CP_SENTINEL; r++) {
2688                 r->access = PL1_RW;
2689             }
2690             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2691                 r->access = PL1_RW;
2692             }
2693         }
2694         if (arm_feature(env, ARM_FEATURE_V8)) {
2695             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
2696         } else {
2697             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
2698         }
2699         define_arm_cp_regs(cpu, id_cp_reginfo);
2700     }
2701
2702     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2703         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2704     }
2705
2706     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2707         ARMCPRegInfo auxcr = {
2708             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2709             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2710             .access = PL1_RW, .type = ARM_CP_CONST,
2711             .resetvalue = cpu->reset_auxcr
2712         };
2713         define_one_arm_cp_reg(cpu, &auxcr);
2714     }
2715
2716     if (arm_feature(env, ARM_FEATURE_CBAR)) {
2717         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2718             /* 32 bit view is [31:18] 0...0 [43:32]. */
2719             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
2720                 | extract64(cpu->reset_cbar, 32, 12);
2721             ARMCPRegInfo cbar_reginfo[] = {
2722                 { .name = "CBAR",
2723                   .type = ARM_CP_CONST,
2724                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2725                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
2726                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
2727                   .type = ARM_CP_CONST,
2728                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
2729                   .access = PL1_R, .resetvalue = cbar32 },
2730                 REGINFO_SENTINEL
2731             };
2732             /* We don't implement a r/w 64 bit CBAR currently */
2733             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
2734             define_arm_cp_regs(cpu, cbar_reginfo);
2735         } else {
2736             ARMCPRegInfo cbar = {
2737                 .name = "CBAR",
2738                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2739                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2740                 .fieldoffset = offsetof(CPUARMState,
2741                                         cp15.c15_config_base_address)
2742             };
2743             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
2744                 cbar.access = PL1_R;
2745                 cbar.fieldoffset = 0;
2746                 cbar.type = ARM_CP_CONST;
2747             }
2748             define_one_arm_cp_reg(cpu, &cbar);
2749         }
2750     }
2751
2752     /* Generic registers whose values depend on the implementation */
2753     {
2754         ARMCPRegInfo sctlr = {
2755             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2756             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2757             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2758             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2759             .raw_writefn = raw_write,
2760         };
2761         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2762             /* Normally we would always end the TB on an SCTLR write, but Linux
2763              * arch/arm/mach-pxa/sleep.S expects two instructions following
2764              * an MMU enable to execute from cache.  Imitate this behaviour.
2765              */
2766             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2767         }
2768         define_one_arm_cp_reg(cpu, &sctlr);
2769     }
2770 }
2771
2772 ARMCPU *cpu_arm_init(const char *cpu_model)
2773 {
2774     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2775 }
2776
2777 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2778 {
2779     CPUState *cs = CPU(cpu);
2780     CPUARMState *env = &cpu->env;
2781
2782     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2783         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2784                                  aarch64_fpu_gdb_set_reg,
2785                                  34, "aarch64-fpu.xml", 0);
2786     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2787         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2788                                  51, "arm-neon.xml", 0);
2789     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2790         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2791                                  35, "arm-vfp3.xml", 0);
2792     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2793         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2794                                  19, "arm-vfp.xml", 0);
2795     }
2796 }
2797
2798 /* Sort alphabetically by type name, except for "any". */
2799 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2800 {
2801     ObjectClass *class_a = (ObjectClass *)a;
2802     ObjectClass *class_b = (ObjectClass *)b;
2803     const char *name_a, *name_b;
2804
2805     name_a = object_class_get_name(class_a);
2806     name_b = object_class_get_name(class_b);
2807     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2808         return 1;
2809     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2810         return -1;
2811     } else {
2812         return strcmp(name_a, name_b);
2813     }
2814 }
2815
2816 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2817 {
2818     ObjectClass *oc = data;
2819     CPUListState *s = user_data;
2820     const char *typename;
2821     char *name;
2822
2823     typename = object_class_get_name(oc);
2824     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2825     (*s->cpu_fprintf)(s->file, "  %s\n",
2826                       name);
2827     g_free(name);
2828 }
2829
2830 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2831 {
2832     CPUListState s = {
2833         .file = f,
2834         .cpu_fprintf = cpu_fprintf,
2835     };
2836     GSList *list;
2837
2838     list = object_class_get_list(TYPE_ARM_CPU, false);
2839     list = g_slist_sort(list, arm_cpu_list_compare);
2840     (*cpu_fprintf)(f, "Available CPUs:\n");
2841     g_slist_foreach(list, arm_cpu_list_entry, &s);
2842     g_slist_free(list);
2843 #ifdef CONFIG_KVM
2844     /* The 'host' CPU type is dynamically registered only if KVM is
2845      * enabled, so we have to special-case it here:
2846      */
2847     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
2848 #endif
2849 }
2850
2851 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2852 {
2853     ObjectClass *oc = data;
2854     CpuDefinitionInfoList **cpu_list = user_data;
2855     CpuDefinitionInfoList *entry;
2856     CpuDefinitionInfo *info;
2857     const char *typename;
2858
2859     typename = object_class_get_name(oc);
2860     info = g_malloc0(sizeof(*info));
2861     info->name = g_strndup(typename,
2862                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
2863
2864     entry = g_malloc0(sizeof(*entry));
2865     entry->value = info;
2866     entry->next = *cpu_list;
2867     *cpu_list = entry;
2868 }
2869
2870 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2871 {
2872     CpuDefinitionInfoList *cpu_list = NULL;
2873     GSList *list;
2874
2875     list = object_class_get_list(TYPE_ARM_CPU, false);
2876     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2877     g_slist_free(list);
2878
2879     return cpu_list;
2880 }
2881
2882 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2883                                    void *opaque, int state,
2884                                    int crm, int opc1, int opc2)
2885 {
2886     /* Private utility function for define_one_arm_cp_reg_with_opaque():
2887      * add a single reginfo struct to the hash table.
2888      */
2889     uint32_t *key = g_new(uint32_t, 1);
2890     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2891     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2892     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2893         /* The AArch32 view of a shared register sees the lower 32 bits
2894          * of a 64 bit backing field. It is not migratable as the AArch64
2895          * view handles that. AArch64 also handles reset.
2896          * We assume it is a cp15 register if the .cp field is left unset.
2897          */
2898         if (r2->cp == 0) {
2899             r2->cp = 15;
2900         }
2901         r2->type |= ARM_CP_NO_MIGRATE;
2902         r2->resetfn = arm_cp_reset_ignore;
2903 #ifdef HOST_WORDS_BIGENDIAN
2904         if (r2->fieldoffset) {
2905             r2->fieldoffset += sizeof(uint32_t);
2906         }
2907 #endif
2908     }
2909     if (state == ARM_CP_STATE_AA64) {
2910         /* To allow abbreviation of ARMCPRegInfo
2911          * definitions, we treat cp == 0 as equivalent to
2912          * the value for "standard guest-visible sysreg".
2913          * STATE_BOTH definitions are also always "standard
2914          * sysreg" in their AArch64 view (the .cp value may
2915          * be non-zero for the benefit of the AArch32 view).
2916          */
2917         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
2918             r2->cp = CP_REG_ARM64_SYSREG_CP;
2919         }
2920         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2921                                   r2->opc0, opc1, opc2);
2922     } else {
2923         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2924     }
2925     if (opaque) {
2926         r2->opaque = opaque;
2927     }
2928     /* reginfo passed to helpers is correct for the actual access,
2929      * and is never ARM_CP_STATE_BOTH:
2930      */
2931     r2->state = state;
2932     /* Make sure reginfo passed to helpers for wildcarded regs
2933      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2934      */
2935     r2->crm = crm;
2936     r2->opc1 = opc1;
2937     r2->opc2 = opc2;
2938     /* By convention, for wildcarded registers only the first
2939      * entry is used for migration; the others are marked as
2940      * NO_MIGRATE so we don't try to transfer the register
2941      * multiple times. Special registers (ie NOP/WFI) are
2942      * never migratable.
2943      */
2944     if ((r->type & ARM_CP_SPECIAL) ||
2945         ((r->crm == CP_ANY) && crm != 0) ||
2946         ((r->opc1 == CP_ANY) && opc1 != 0) ||
2947         ((r->opc2 == CP_ANY) && opc2 != 0)) {
2948         r2->type |= ARM_CP_NO_MIGRATE;
2949     }
2950
2951     /* Overriding of an existing definition must be explicitly
2952      * requested.
2953      */
2954     if (!(r->type & ARM_CP_OVERRIDE)) {
2955         ARMCPRegInfo *oldreg;
2956         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2957         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2958             fprintf(stderr, "Register redefined: cp=%d %d bit "
2959                     "crn=%d crm=%d opc1=%d opc2=%d, "
2960                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2961                     r2->crn, r2->crm, r2->opc1, r2->opc2,
2962                     oldreg->name, r2->name);
2963             g_assert_not_reached();
2964         }
2965     }
2966     g_hash_table_insert(cpu->cp_regs, key, r2);
2967 }
2968
2969
2970 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2971                                        const ARMCPRegInfo *r, void *opaque)
2972 {
2973     /* Define implementations of coprocessor registers.
2974      * We store these in a hashtable because typically
2975      * there are less than 150 registers in a space which
2976      * is 16*16*16*8*8 = 262144 in size.
2977      * Wildcarding is supported for the crm, opc1 and opc2 fields.
2978      * If a register is defined twice then the second definition is
2979      * used, so this can be used to define some generic registers and
2980      * then override them with implementation specific variations.
2981      * At least one of the original and the second definition should
2982      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2983      * against accidental use.
2984      *
2985      * The state field defines whether the register is to be
2986      * visible in the AArch32 or AArch64 execution state. If the
2987      * state is set to ARM_CP_STATE_BOTH then we synthesise a
2988      * reginfo structure for the AArch32 view, which sees the lower
2989      * 32 bits of the 64 bit register.
2990      *
2991      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2992      * be wildcarded. AArch64 registers are always considered to be 64
2993      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2994      * the register, if any.
2995      */
2996     int crm, opc1, opc2, state;
2997     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2998     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2999     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
3000     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
3001     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
3002     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
3003     /* 64 bit registers have only CRm and Opc1 fields */
3004     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
3005     /* op0 only exists in the AArch64 encodings */
3006     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
3007     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3008     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
3009     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3010      * encodes a minimum access level for the register. We roll this
3011      * runtime check into our general permission check code, so check
3012      * here that the reginfo's specified permissions are strict enough
3013      * to encompass the generic architectural permission check.
3014      */
3015     if (r->state != ARM_CP_STATE_AA32) {
3016         int mask = 0;
3017         switch (r->opc1) {
3018         case 0: case 1: case 2:
3019             /* min_EL EL1 */
3020             mask = PL1_RW;
3021             break;
3022         case 3:
3023             /* min_EL EL0 */
3024             mask = PL0_RW;
3025             break;
3026         case 4:
3027             /* min_EL EL2 */
3028             mask = PL2_RW;
3029             break;
3030         case 5:
3031             /* unallocated encoding, so not possible */
3032             assert(false);
3033             break;
3034         case 6:
3035             /* min_EL EL3 */
3036             mask = PL3_RW;
3037             break;
3038         case 7:
3039             /* min_EL EL1, secure mode only (we don't check the latter) */
3040             mask = PL1_RW;
3041             break;
3042         default:
3043             /* broken reginfo with out-of-range opc1 */
3044             assert(false);
3045             break;
3046         }
3047         /* assert our permissions are not too lax (stricter is fine) */
3048         assert((r->access & ~mask) == 0);
3049     }
3050
3051     /* Check that the register definition has enough info to handle
3052      * reads and writes if they are permitted.
3053      */
3054     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3055         if (r->access & PL3_R) {
3056             assert(r->fieldoffset || r->readfn);
3057         }
3058         if (r->access & PL3_W) {
3059             assert(r->fieldoffset || r->writefn);
3060         }
3061     }
3062     /* Bad type field probably means missing sentinel at end of reg list */
3063     assert(cptype_valid(r->type));
3064     for (crm = crmmin; crm <= crmmax; crm++) {
3065         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3066             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3067                 for (state = ARM_CP_STATE_AA32;
3068                      state <= ARM_CP_STATE_AA64; state++) {
3069                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3070                         continue;
3071                     }
3072                     add_cpreg_to_hashtable(cpu, r, opaque, state,
3073                                            crm, opc1, opc2);
3074                 }
3075             }
3076         }
3077     }
3078 }
3079
3080 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3081                                     const ARMCPRegInfo *regs, void *opaque)
3082 {
3083     /* Define a whole list of registers */
3084     const ARMCPRegInfo *r;
3085     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3086         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3087     }
3088 }
3089
3090 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3091 {
3092     return g_hash_table_lookup(cpregs, &encoded_cp);
3093 }
3094
3095 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3096                          uint64_t value)
3097 {
3098     /* Helper coprocessor write function for write-ignore registers */
3099 }
3100
3101 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3102 {
3103     /* Helper coprocessor write function for read-as-zero registers */
3104     return 0;
3105 }
3106
3107 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3108 {
3109     /* Helper coprocessor reset function for do-nothing-on-reset registers */
3110 }
3111
3112 static int bad_mode_switch(CPUARMState *env, int mode)
3113 {
3114     /* Return true if it is not valid for us to switch to
3115      * this CPU mode (ie all the UNPREDICTABLE cases in
3116      * the ARM ARM CPSRWriteByInstr pseudocode).
3117      */
3118     switch (mode) {
3119     case ARM_CPU_MODE_USR:
3120     case ARM_CPU_MODE_SYS:
3121     case ARM_CPU_MODE_SVC:
3122     case ARM_CPU_MODE_ABT:
3123     case ARM_CPU_MODE_UND:
3124     case ARM_CPU_MODE_IRQ:
3125     case ARM_CPU_MODE_FIQ:
3126         return 0;
3127     default:
3128         return 1;
3129     }
3130 }
3131
3132 uint32_t cpsr_read(CPUARMState *env)
3133 {
3134     int ZF;
3135     ZF = (env->ZF == 0);
3136     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3137         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3138         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3139         | ((env->condexec_bits & 0xfc) << 8)
3140         | (env->GE << 16) | (env->daif & CPSR_AIF);
3141 }
3142
3143 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3144 {
3145     if (mask & CPSR_NZCV) {
3146         env->ZF = (~val) & CPSR_Z;
3147         env->NF = val;
3148         env->CF = (val >> 29) & 1;
3149         env->VF = (val << 3) & 0x80000000;
3150     }
3151     if (mask & CPSR_Q)
3152         env->QF = ((val & CPSR_Q) != 0);
3153     if (mask & CPSR_T)
3154         env->thumb = ((val & CPSR_T) != 0);
3155     if (mask & CPSR_IT_0_1) {
3156         env->condexec_bits &= ~3;
3157         env->condexec_bits |= (val >> 25) & 3;
3158     }
3159     if (mask & CPSR_IT_2_7) {
3160         env->condexec_bits &= 3;
3161         env->condexec_bits |= (val >> 8) & 0xfc;
3162     }
3163     if (mask & CPSR_GE) {
3164         env->GE = (val >> 16) & 0xf;
3165     }
3166
3167     env->daif &= ~(CPSR_AIF & mask);
3168     env->daif |= val & CPSR_AIF & mask;
3169
3170     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3171         if (bad_mode_switch(env, val & CPSR_M)) {
3172             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3173              * We choose to ignore the attempt and leave the CPSR M field
3174              * untouched.
3175              */
3176             mask &= ~CPSR_M;
3177         } else {
3178             switch_mode(env, val & CPSR_M);
3179         }
3180     }
3181     mask &= ~CACHED_CPSR_BITS;
3182     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3183 }
3184
3185 /* Sign/zero extend */
3186 uint32_t HELPER(sxtb16)(uint32_t x)
3187 {
3188     uint32_t res;
3189     res = (uint16_t)(int8_t)x;
3190     res |= (uint32_t)(int8_t)(x >> 16) << 16;
3191     return res;
3192 }
3193
3194 uint32_t HELPER(uxtb16)(uint32_t x)
3195 {
3196     uint32_t res;
3197     res = (uint16_t)(uint8_t)x;
3198     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3199     return res;
3200 }
3201
3202 uint32_t HELPER(clz)(uint32_t x)
3203 {
3204     return clz32(x);
3205 }
3206
3207 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3208 {
3209     if (den == 0)
3210       return 0;
3211     if (num == INT_MIN && den == -1)
3212       return INT_MIN;
3213     return num / den;
3214 }
3215
3216 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3217 {
3218     if (den == 0)
3219       return 0;
3220     return num / den;
3221 }
3222
3223 uint32_t HELPER(rbit)(uint32_t x)
3224 {
3225     x =  ((x & 0xff000000) >> 24)
3226        | ((x & 0x00ff0000) >> 8)
3227        | ((x & 0x0000ff00) << 8)
3228        | ((x & 0x000000ff) << 24);
3229     x =  ((x & 0xf0f0f0f0) >> 4)
3230        | ((x & 0x0f0f0f0f) << 4);
3231     x =  ((x & 0x88888888) >> 3)
3232        | ((x & 0x44444444) >> 1)
3233        | ((x & 0x22222222) << 1)
3234        | ((x & 0x11111111) << 3);
3235     return x;
3236 }
3237
3238 #if defined(CONFIG_USER_ONLY)
3239
3240 void arm_cpu_do_interrupt(CPUState *cs)
3241 {
3242     cs->exception_index = -1;
3243 }
3244
3245 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3246                              int mmu_idx)
3247 {
3248     ARMCPU *cpu = ARM_CPU(cs);
3249     CPUARMState *env = &cpu->env;
3250
3251     env->exception.vaddress = address;
3252     if (rw == 2) {
3253         cs->exception_index = EXCP_PREFETCH_ABORT;
3254     } else {
3255         cs->exception_index = EXCP_DATA_ABORT;
3256     }
3257     return 1;
3258 }
3259
3260 /* These should probably raise undefined insn exceptions.  */
3261 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3262 {
3263     ARMCPU *cpu = arm_env_get_cpu(env);
3264
3265     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3266 }
3267
3268 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3269 {
3270     ARMCPU *cpu = arm_env_get_cpu(env);
3271
3272     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3273     return 0;
3274 }
3275
3276 void switch_mode(CPUARMState *env, int mode)
3277 {
3278     ARMCPU *cpu = arm_env_get_cpu(env);
3279
3280     if (mode != ARM_CPU_MODE_USR) {
3281         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3282     }
3283 }
3284
3285 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3286 {
3287     ARMCPU *cpu = arm_env_get_cpu(env);
3288
3289     cpu_abort(CPU(cpu), "banked r13 write\n");
3290 }
3291
3292 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3293 {
3294     ARMCPU *cpu = arm_env_get_cpu(env);
3295
3296     cpu_abort(CPU(cpu), "banked r13 read\n");
3297     return 0;
3298 }
3299
3300 #else
3301
3302 /* Map CPU modes onto saved register banks.  */
3303 int bank_number(int mode)
3304 {
3305     switch (mode) {
3306     case ARM_CPU_MODE_USR:
3307     case ARM_CPU_MODE_SYS:
3308         return 0;
3309     case ARM_CPU_MODE_SVC:
3310         return 1;
3311     case ARM_CPU_MODE_ABT:
3312         return 2;
3313     case ARM_CPU_MODE_UND:
3314         return 3;
3315     case ARM_CPU_MODE_IRQ:
3316         return 4;
3317     case ARM_CPU_MODE_FIQ:
3318         return 5;
3319     case ARM_CPU_MODE_HYP:
3320         return 6;
3321     case ARM_CPU_MODE_MON:
3322         return 7;
3323     }
3324     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3325 }
3326
3327 void switch_mode(CPUARMState *env, int mode)
3328 {
3329     int old_mode;
3330     int i;
3331
3332     old_mode = env->uncached_cpsr & CPSR_M;
3333     if (mode == old_mode)
3334         return;
3335
3336     if (old_mode == ARM_CPU_MODE_FIQ) {
3337         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3338         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3339     } else if (mode == ARM_CPU_MODE_FIQ) {
3340         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3341         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3342     }
3343
3344     i = bank_number(old_mode);
3345     env->banked_r13[i] = env->regs[13];
3346     env->banked_r14[i] = env->regs[14];
3347     env->banked_spsr[i] = env->spsr;
3348
3349     i = bank_number(mode);
3350     env->regs[13] = env->banked_r13[i];
3351     env->regs[14] = env->banked_r14[i];
3352     env->spsr = env->banked_spsr[i];
3353 }
3354
3355 static void v7m_push(CPUARMState *env, uint32_t val)
3356 {
3357     CPUState *cs = CPU(arm_env_get_cpu(env));
3358
3359     env->regs[13] -= 4;
3360     stl_phys(cs->as, env->regs[13], val);
3361 }
3362
3363 static uint32_t v7m_pop(CPUARMState *env)
3364 {
3365     CPUState *cs = CPU(arm_env_get_cpu(env));
3366     uint32_t val;
3367
3368     val = ldl_phys(cs->as, env->regs[13]);
3369     env->regs[13] += 4;
3370     return val;
3371 }
3372
3373 /* Switch to V7M main or process stack pointer.  */
3374 static void switch_v7m_sp(CPUARMState *env, int process)
3375 {
3376     uint32_t tmp;
3377     if (env->v7m.current_sp != process) {
3378         tmp = env->v7m.other_sp;
3379         env->v7m.other_sp = env->regs[13];
3380         env->regs[13] = tmp;
3381         env->v7m.current_sp = process;
3382     }
3383 }
3384
3385 static void do_v7m_exception_exit(CPUARMState *env)
3386 {
3387     uint32_t type;
3388     uint32_t xpsr;
3389
3390     type = env->regs[15];
3391     if (env->v7m.exception != 0)
3392         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3393
3394     /* Switch to the target stack.  */
3395     switch_v7m_sp(env, (type & 4) != 0);
3396     /* Pop registers.  */
3397     env->regs[0] = v7m_pop(env);
3398     env->regs[1] = v7m_pop(env);
3399     env->regs[2] = v7m_pop(env);
3400     env->regs[3] = v7m_pop(env);
3401     env->regs[12] = v7m_pop(env);
3402     env->regs[14] = v7m_pop(env);
3403     env->regs[15] = v7m_pop(env);
3404     xpsr = v7m_pop(env);
3405     xpsr_write(env, xpsr, 0xfffffdff);
3406     /* Undo stack alignment.  */
3407     if (xpsr & 0x200)
3408         env->regs[13] |= 4;
3409     /* ??? The exception return type specifies Thread/Handler mode.  However
3410        this is also implied by the xPSR value. Not sure what to do
3411        if there is a mismatch.  */
3412     /* ??? Likewise for mismatches between the CONTROL register and the stack
3413        pointer.  */
3414 }
3415
3416 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3417 {
3418     ARMCPU *cpu = ARM_CPU(cs);
3419     CPUARMState *env = &cpu->env;
3420     uint32_t xpsr = xpsr_read(env);
3421     uint32_t lr;
3422     uint32_t addr;
3423
3424     arm_log_exception(cs->exception_index);
3425
3426     lr = 0xfffffff1;
3427     if (env->v7m.current_sp)
3428         lr |= 4;
3429     if (env->v7m.exception == 0)
3430         lr |= 8;
3431
3432     /* For exceptions we just mark as pending on the NVIC, and let that
3433        handle it.  */
3434     /* TODO: Need to escalate if the current priority is higher than the
3435        one we're raising.  */
3436     switch (cs->exception_index) {
3437     case EXCP_UDEF:
3438         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3439         return;
3440     case EXCP_SWI:
3441         /* The PC already points to the next instruction.  */
3442         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3443         return;
3444     case EXCP_PREFETCH_ABORT:
3445     case EXCP_DATA_ABORT:
3446         /* TODO: if we implemented the MPU registers, this is where we
3447          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3448          */
3449         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3450         return;
3451     case EXCP_BKPT:
3452         if (semihosting_enabled) {
3453             int nr;
3454             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3455             if (nr == 0xab) {
3456                 env->regs[15] += 2;
3457                 env->regs[0] = do_arm_semihosting(env);
3458                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3459                 return;
3460             }
3461         }
3462         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3463         return;
3464     case EXCP_IRQ:
3465         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3466         break;
3467     case EXCP_EXCEPTION_EXIT:
3468         do_v7m_exception_exit(env);
3469         return;
3470     default:
3471         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3472         return; /* Never happens.  Keep compiler happy.  */
3473     }
3474
3475     /* Align stack pointer.  */
3476     /* ??? Should only do this if Configuration Control Register
3477        STACKALIGN bit is set.  */
3478     if (env->regs[13] & 4) {
3479         env->regs[13] -= 4;
3480         xpsr |= 0x200;
3481     }
3482     /* Switch to the handler mode.  */
3483     v7m_push(env, xpsr);
3484     v7m_push(env, env->regs[15]);
3485     v7m_push(env, env->regs[14]);
3486     v7m_push(env, env->regs[12]);
3487     v7m_push(env, env->regs[3]);
3488     v7m_push(env, env->regs[2]);
3489     v7m_push(env, env->regs[1]);
3490     v7m_push(env, env->regs[0]);
3491     switch_v7m_sp(env, 0);
3492     /* Clear IT bits */
3493     env->condexec_bits = 0;
3494     env->regs[14] = lr;
3495     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3496     env->regs[15] = addr & 0xfffffffe;
3497     env->thumb = addr & 1;
3498 }
3499
3500 /* Handle a CPU exception.  */
3501 void arm_cpu_do_interrupt(CPUState *cs)
3502 {
3503     ARMCPU *cpu = ARM_CPU(cs);
3504     CPUARMState *env = &cpu->env;
3505     uint32_t addr;
3506     uint32_t mask;
3507     int new_mode;
3508     uint32_t offset;
3509
3510     assert(!IS_M(env));
3511
3512     arm_log_exception(cs->exception_index);
3513
3514     /* TODO: Vectored interrupt controller.  */
3515     switch (cs->exception_index) {
3516     case EXCP_UDEF:
3517         new_mode = ARM_CPU_MODE_UND;
3518         addr = 0x04;
3519         mask = CPSR_I;
3520         if (env->thumb)
3521             offset = 2;
3522         else
3523             offset = 4;
3524         break;
3525     case EXCP_SWI:
3526         if (semihosting_enabled) {
3527             /* Check for semihosting interrupt.  */
3528             if (env->thumb) {
3529                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3530                     & 0xff;
3531             } else {
3532                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3533                     & 0xffffff;
3534             }
3535             /* Only intercept calls from privileged modes, to provide some
3536                semblance of security.  */
3537             if (((mask == 0x123456 && !env->thumb)
3538                     || (mask == 0xab && env->thumb))
3539                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3540                 env->regs[0] = do_arm_semihosting(env);
3541                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3542                 return;
3543             }
3544         }
3545         new_mode = ARM_CPU_MODE_SVC;
3546         addr = 0x08;
3547         mask = CPSR_I;
3548         /* The PC already points to the next instruction.  */
3549         offset = 0;
3550         break;
3551     case EXCP_BKPT:
3552         /* See if this is a semihosting syscall.  */
3553         if (env->thumb && semihosting_enabled) {
3554             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3555             if (mask == 0xab
3556                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3557                 env->regs[15] += 2;
3558                 env->regs[0] = do_arm_semihosting(env);
3559                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3560                 return;
3561             }
3562         }
3563         env->exception.fsr = 2;
3564         /* Fall through to prefetch abort.  */
3565     case EXCP_PREFETCH_ABORT:
3566         env->cp15.ifsr_el2 = env->exception.fsr;
3567         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
3568                                         env->exception.vaddress);
3569         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3570                       env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3571         new_mode = ARM_CPU_MODE_ABT;
3572         addr = 0x0c;
3573         mask = CPSR_A | CPSR_I;
3574         offset = 4;
3575         break;
3576     case EXCP_DATA_ABORT:
3577         env->cp15.esr_el[1] = env->exception.fsr;
3578         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
3579                                         env->exception.vaddress);
3580         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3581                       (uint32_t)env->cp15.esr_el[1],
3582                       (uint32_t)env->exception.vaddress);
3583         new_mode = ARM_CPU_MODE_ABT;
3584         addr = 0x10;
3585         mask = CPSR_A | CPSR_I;
3586         offset = 8;
3587         break;
3588     case EXCP_IRQ:
3589         new_mode = ARM_CPU_MODE_IRQ;
3590         addr = 0x18;
3591         /* Disable IRQ and imprecise data aborts.  */
3592         mask = CPSR_A | CPSR_I;
3593         offset = 4;
3594         break;
3595     case EXCP_FIQ:
3596         new_mode = ARM_CPU_MODE_FIQ;
3597         addr = 0x1c;
3598         /* Disable FIQ, IRQ and imprecise data aborts.  */
3599         mask = CPSR_A | CPSR_I | CPSR_F;
3600         offset = 4;
3601         break;
3602     default:
3603         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3604         return; /* Never happens.  Keep compiler happy.  */
3605     }
3606     /* High vectors.  */
3607     if (env->cp15.c1_sys & SCTLR_V) {
3608         /* when enabled, base address cannot be remapped.  */
3609         addr += 0xffff0000;
3610     } else {
3611         /* ARM v7 architectures provide a vector base address register to remap
3612          * the interrupt vector table.
3613          * This register is only followed in non-monitor mode, and has a secure
3614          * and un-secure copy. Since the cpu is always in a un-secure operation
3615          * and is never in monitor mode this feature is always active.
3616          * Note: only bits 31:5 are valid.
3617          */
3618         addr += env->cp15.vbar_el[1];
3619     }
3620     switch_mode (env, new_mode);
3621     /* For exceptions taken to AArch32 we must clear the SS bit in both
3622      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
3623      */
3624     env->uncached_cpsr &= ~PSTATE_SS;
3625     env->spsr = cpsr_read(env);
3626     /* Clear IT bits.  */
3627     env->condexec_bits = 0;
3628     /* Switch to the new mode, and to the correct instruction set.  */
3629     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3630     env->daif |= mask;
3631     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3632      * and we should just guard the thumb mode on V4 */
3633     if (arm_feature(env, ARM_FEATURE_V4T)) {
3634         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3635     }
3636     env->regs[14] = env->regs[15] + offset;
3637     env->regs[15] = addr;
3638     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3639 }
3640
3641 /* Check section/page access permissions.
3642    Returns the page protection flags, or zero if the access is not
3643    permitted.  */
3644 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3645                            int access_type, int is_user)
3646 {
3647   int prot_ro;
3648
3649   if (domain_prot == 3) {
3650     return PAGE_READ | PAGE_WRITE;
3651   }
3652
3653   if (access_type == 1)
3654       prot_ro = 0;
3655   else
3656       prot_ro = PAGE_READ;
3657
3658   switch (ap) {
3659   case 0:
3660       if (arm_feature(env, ARM_FEATURE_V7)) {
3661           return 0;
3662       }
3663       if (access_type == 1)
3664           return 0;
3665       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3666       case SCTLR_S:
3667           return is_user ? 0 : PAGE_READ;
3668       case SCTLR_R:
3669           return PAGE_READ;
3670       default:
3671           return 0;
3672       }
3673   case 1:
3674       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3675   case 2:
3676       if (is_user)
3677           return prot_ro;
3678       else
3679           return PAGE_READ | PAGE_WRITE;
3680   case 3:
3681       return PAGE_READ | PAGE_WRITE;
3682   case 4: /* Reserved.  */
3683       return 0;
3684   case 5:
3685       return is_user ? 0 : prot_ro;
3686   case 6:
3687       return prot_ro;
3688   case 7:
3689       if (!arm_feature (env, ARM_FEATURE_V6K))
3690           return 0;
3691       return prot_ro;
3692   default:
3693       abort();
3694   }
3695 }
3696
3697 static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
3698                                          uint32_t address)
3699 {
3700     if (address & env->cp15.c2_mask) {
3701         if ((env->cp15.c2_control & TTBCR_PD1)) {
3702             /* Translation table walk disabled for TTBR1 */
3703             return false;
3704         }
3705         *table = env->cp15.ttbr1_el1 & 0xffffc000;
3706     } else {
3707         if ((env->cp15.c2_control & TTBCR_PD0)) {
3708             /* Translation table walk disabled for TTBR0 */
3709             return false;
3710         }
3711         *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3712     }
3713     *table |= (address >> 18) & 0x3ffc;
3714     return true;
3715 }
3716
3717 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3718                             int is_user, hwaddr *phys_ptr,
3719                             int *prot, target_ulong *page_size)
3720 {
3721     CPUState *cs = CPU(arm_env_get_cpu(env));
3722     int code;
3723     uint32_t table;
3724     uint32_t desc;
3725     int type;
3726     int ap;
3727     int domain = 0;
3728     int domain_prot;
3729     hwaddr phys_addr;
3730
3731     /* Pagetable walk.  */
3732     /* Lookup l1 descriptor.  */
3733     if (!get_level1_table_address(env, &table, address)) {
3734         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3735         code = 5;
3736         goto do_fault;
3737     }
3738     desc = ldl_phys(cs->as, table);
3739     type = (desc & 3);
3740     domain = (desc >> 5) & 0x0f;
3741     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3742     if (type == 0) {
3743         /* Section translation fault.  */
3744         code = 5;
3745         goto do_fault;
3746     }
3747     if (domain_prot == 0 || domain_prot == 2) {
3748         if (type == 2)
3749             code = 9; /* Section domain fault.  */
3750         else
3751             code = 11; /* Page domain fault.  */
3752         goto do_fault;
3753     }
3754     if (type == 2) {
3755         /* 1Mb section.  */
3756         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3757         ap = (desc >> 10) & 3;
3758         code = 13;
3759         *page_size = 1024 * 1024;
3760     } else {
3761         /* Lookup l2 entry.  */
3762         if (type == 1) {
3763             /* Coarse pagetable.  */
3764             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3765         } else {
3766             /* Fine pagetable.  */
3767             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3768         }
3769         desc = ldl_phys(cs->as, table);
3770         switch (desc & 3) {
3771         case 0: /* Page translation fault.  */
3772             code = 7;
3773             goto do_fault;
3774         case 1: /* 64k page.  */
3775             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3776             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3777             *page_size = 0x10000;
3778             break;
3779         case 2: /* 4k page.  */
3780             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3781             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3782             *page_size = 0x1000;
3783             break;
3784         case 3: /* 1k page.  */
3785             if (type == 1) {
3786                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3787                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3788                 } else {
3789                     /* Page translation fault.  */
3790                     code = 7;
3791                     goto do_fault;
3792                 }
3793             } else {
3794                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3795             }
3796             ap = (desc >> 4) & 3;
3797             *page_size = 0x400;
3798             break;
3799         default:
3800             /* Never happens, but compiler isn't smart enough to tell.  */
3801             abort();
3802         }
3803         code = 15;
3804     }
3805     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3806     if (!*prot) {
3807         /* Access permission fault.  */
3808         goto do_fault;
3809     }
3810     *prot |= PAGE_EXEC;
3811     *phys_ptr = phys_addr;
3812     return 0;
3813 do_fault:
3814     return code | (domain << 4);
3815 }
3816
3817 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3818                             int is_user, hwaddr *phys_ptr,
3819                             int *prot, target_ulong *page_size)
3820 {
3821     CPUState *cs = CPU(arm_env_get_cpu(env));
3822     int code;
3823     uint32_t table;
3824     uint32_t desc;
3825     uint32_t xn;
3826     uint32_t pxn = 0;
3827     int type;
3828     int ap;
3829     int domain = 0;
3830     int domain_prot;
3831     hwaddr phys_addr;
3832
3833     /* Pagetable walk.  */
3834     /* Lookup l1 descriptor.  */
3835     if (!get_level1_table_address(env, &table, address)) {
3836         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3837         code = 5;
3838         goto do_fault;
3839     }
3840     desc = ldl_phys(cs->as, table);
3841     type = (desc & 3);
3842     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3843         /* Section translation fault, or attempt to use the encoding
3844          * which is Reserved on implementations without PXN.
3845          */
3846         code = 5;
3847         goto do_fault;
3848     }
3849     if ((type == 1) || !(desc & (1 << 18))) {
3850         /* Page or Section.  */
3851         domain = (desc >> 5) & 0x0f;
3852     }
3853     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3854     if (domain_prot == 0 || domain_prot == 2) {
3855         if (type != 1) {
3856             code = 9; /* Section domain fault.  */
3857         } else {
3858             code = 11; /* Page domain fault.  */
3859         }
3860         goto do_fault;
3861     }
3862     if (type != 1) {
3863         if (desc & (1 << 18)) {
3864             /* Supersection.  */
3865             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3866             *page_size = 0x1000000;
3867         } else {
3868             /* Section.  */
3869             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3870             *page_size = 0x100000;
3871         }
3872         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3873         xn = desc & (1 << 4);
3874         pxn = desc & 1;
3875         code = 13;
3876     } else {
3877         if (arm_feature(env, ARM_FEATURE_PXN)) {
3878             pxn = (desc >> 2) & 1;
3879         }
3880         /* Lookup l2 entry.  */
3881         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3882         desc = ldl_phys(cs->as, table);
3883         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3884         switch (desc & 3) {
3885         case 0: /* Page translation fault.  */
3886             code = 7;
3887             goto do_fault;
3888         case 1: /* 64k page.  */
3889             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3890             xn = desc & (1 << 15);
3891             *page_size = 0x10000;
3892             break;
3893         case 2: case 3: /* 4k page.  */
3894             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3895             xn = desc & 1;
3896             *page_size = 0x1000;
3897             break;
3898         default:
3899             /* Never happens, but compiler isn't smart enough to tell.  */
3900             abort();
3901         }
3902         code = 15;
3903     }
3904     if (domain_prot == 3) {
3905         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3906     } else {
3907         if (pxn && !is_user) {
3908             xn = 1;
3909         }
3910         if (xn && access_type == 2)
3911             goto do_fault;
3912
3913         /* The simplified model uses AP[0] as an access control bit.  */
3914         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3915             /* Access flag fault.  */
3916             code = (code == 15) ? 6 : 3;
3917             goto do_fault;
3918         }
3919         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3920         if (!*prot) {
3921             /* Access permission fault.  */
3922             goto do_fault;
3923         }
3924         if (!xn) {
3925             *prot |= PAGE_EXEC;
3926         }
3927     }
3928     *phys_ptr = phys_addr;
3929     return 0;
3930 do_fault:
3931     return code | (domain << 4);
3932 }
3933
3934 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3935  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3936  */
3937 typedef enum {
3938     translation_fault = 1,
3939     access_fault = 2,
3940     permission_fault = 3,
3941 } MMUFaultType;
3942
3943 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3944                               int access_type, int is_user,
3945                               hwaddr *phys_ptr, int *prot,
3946                               target_ulong *page_size_ptr)
3947 {
3948     CPUState *cs = CPU(arm_env_get_cpu(env));
3949     /* Read an LPAE long-descriptor translation table. */
3950     MMUFaultType fault_type = translation_fault;
3951     uint32_t level = 1;
3952     uint32_t epd;
3953     int32_t tsz;
3954     uint32_t tg;
3955     uint64_t ttbr;
3956     int ttbr_select;
3957     hwaddr descaddr, descmask;
3958     uint32_t tableattrs;
3959     target_ulong page_size;
3960     uint32_t attrs;
3961     int32_t granule_sz = 9;
3962     int32_t va_size = 32;
3963     int32_t tbi = 0;
3964
3965     if (arm_el_is_aa64(env, 1)) {
3966         va_size = 64;
3967         if (extract64(address, 55, 1))
3968             tbi = extract64(env->cp15.c2_control, 38, 1);
3969         else
3970             tbi = extract64(env->cp15.c2_control, 37, 1);
3971         tbi *= 8;
3972     }
3973
3974     /* Determine whether this address is in the region controlled by
3975      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3976      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3977      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3978      */
3979     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3980     if (arm_el_is_aa64(env, 1)) {
3981         t0sz = MIN(t0sz, 39);
3982         t0sz = MAX(t0sz, 16);
3983     }
3984     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3985     if (arm_el_is_aa64(env, 1)) {
3986         t1sz = MIN(t1sz, 39);
3987         t1sz = MAX(t1sz, 16);
3988     }
3989     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3990         /* there is a ttbr0 region and we are in it (high bits all zero) */
3991         ttbr_select = 0;
3992     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3993         /* there is a ttbr1 region and we are in it (high bits all one) */
3994         ttbr_select = 1;
3995     } else if (!t0sz) {
3996         /* ttbr0 region is "everything not in the ttbr1 region" */
3997         ttbr_select = 0;
3998     } else if (!t1sz) {
3999         /* ttbr1 region is "everything not in the ttbr0 region" */
4000         ttbr_select = 1;
4001     } else {
4002         /* in the gap between the two regions, this is a Translation fault */
4003         fault_type = translation_fault;
4004         goto do_fault;
4005     }
4006
4007     /* Note that QEMU ignores shareability and cacheability attributes,
4008      * so we don't need to do anything with the SH, ORGN, IRGN fields
4009      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
4010      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
4011      * implement any ASID-like capability so we can ignore it (instead
4012      * we will always flush the TLB any time the ASID is changed).
4013      */
4014     if (ttbr_select == 0) {
4015         ttbr = env->cp15.ttbr0_el1;
4016         epd = extract32(env->cp15.c2_control, 7, 1);
4017         tsz = t0sz;
4018
4019         tg = extract32(env->cp15.c2_control, 14, 2);
4020         if (tg == 1) { /* 64KB pages */
4021             granule_sz = 13;
4022         }
4023         if (tg == 2) { /* 16KB pages */
4024             granule_sz = 11;
4025         }
4026     } else {
4027         ttbr = env->cp15.ttbr1_el1;
4028         epd = extract32(env->cp15.c2_control, 23, 1);
4029         tsz = t1sz;
4030
4031         tg = extract32(env->cp15.c2_control, 30, 2);
4032         if (tg == 3)  { /* 64KB pages */
4033             granule_sz = 13;
4034         }
4035         if (tg == 1) { /* 16KB pages */
4036             granule_sz = 11;
4037         }
4038     }
4039
4040     if (epd) {
4041         /* Translation table walk disabled => Translation fault on TLB miss */
4042         goto do_fault;
4043     }
4044
4045     /* The starting level depends on the virtual address size which can be
4046      * up to 48-bits and the translation granule size.
4047      */
4048     if ((va_size - tsz) > (granule_sz * 4 + 3)) {
4049         level = 0;
4050     } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
4051         level = 1;
4052     } else {
4053         level = 2;
4054     }
4055
4056     /* Clear the vaddr bits which aren't part of the within-region address,
4057      * so that we don't have to special case things when calculating the
4058      * first descriptor address.
4059      */
4060     if (tsz) {
4061         address &= (1ULL << (va_size - tsz)) - 1;
4062     }
4063
4064     descmask = (1ULL << (granule_sz + 3)) - 1;
4065
4066     /* Now we can extract the actual base address from the TTBR */
4067     descaddr = extract64(ttbr, 0, 48);
4068     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
4069
4070     tableattrs = 0;
4071     for (;;) {
4072         uint64_t descriptor;
4073
4074         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
4075         descaddr &= ~7ULL;
4076         descriptor = ldq_phys(cs->as, descaddr);
4077         if (!(descriptor & 1) ||
4078             (!(descriptor & 2) && (level == 3))) {
4079             /* Invalid, or the Reserved level 3 encoding */
4080             goto do_fault;
4081         }
4082         descaddr = descriptor & 0xfffffff000ULL;
4083
4084         if ((descriptor & 2) && (level < 3)) {
4085             /* Table entry. The top five bits are attributes which  may
4086              * propagate down through lower levels of the table (and
4087              * which are all arranged so that 0 means "no effect", so
4088              * we can gather them up by ORing in the bits at each level).
4089              */
4090             tableattrs |= extract64(descriptor, 59, 5);
4091             level++;
4092             continue;
4093         }
4094         /* Block entry at level 1 or 2, or page entry at level 3.
4095          * These are basically the same thing, although the number
4096          * of bits we pull in from the vaddr varies.
4097          */
4098         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
4099         descaddr |= (address & (page_size - 1));
4100         /* Extract attributes from the descriptor and merge with table attrs */
4101         attrs = extract64(descriptor, 2, 10)
4102             | (extract64(descriptor, 52, 12) << 10);
4103         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
4104         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
4105         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
4106          * means "force PL1 access only", which means forcing AP[1] to 0.
4107          */
4108         if (extract32(tableattrs, 2, 1)) {
4109             attrs &= ~(1 << 4);
4110         }
4111         /* Since we're always in the Non-secure state, NSTable is ignored. */
4112         break;
4113     }
4114     /* Here descaddr is the final physical address, and attributes
4115      * are all in attrs.
4116      */
4117     fault_type = access_fault;
4118     if ((attrs & (1 << 8)) == 0) {
4119         /* Access flag */
4120         goto do_fault;
4121     }
4122     fault_type = permission_fault;
4123     if (is_user && !(attrs & (1 << 4))) {
4124         /* Unprivileged access not enabled */
4125         goto do_fault;
4126     }
4127     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4128     if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
4129         (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
4130         (!is_user && (attrs & (1 << 11)))) {
4131         /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4132          * treat XN/UXN as UXN for v8.
4133          */
4134         if (access_type == 2) {
4135             goto do_fault;
4136         }
4137         *prot &= ~PAGE_EXEC;
4138     }
4139     if (attrs & (1 << 5)) {
4140         /* Write access forbidden */
4141         if (access_type == 1) {
4142             goto do_fault;
4143         }
4144         *prot &= ~PAGE_WRITE;
4145     }
4146
4147     *phys_ptr = descaddr;
4148     *page_size_ptr = page_size;
4149     return 0;
4150
4151 do_fault:
4152     /* Long-descriptor format IFSR/DFSR value */
4153     return (1 << 9) | (fault_type << 2) | level;
4154 }
4155
4156 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
4157                              int access_type, int is_user,
4158                              hwaddr *phys_ptr, int *prot)
4159 {
4160     int n;
4161     uint32_t mask;
4162     uint32_t base;
4163
4164     *phys_ptr = address;
4165     for (n = 7; n >= 0; n--) {
4166         base = env->cp15.c6_region[n];
4167         if ((base & 1) == 0)
4168             continue;
4169         mask = 1 << ((base >> 1) & 0x1f);
4170         /* Keep this shift separate from the above to avoid an
4171            (undefined) << 32.  */
4172         mask = (mask << 1) - 1;
4173         if (((base ^ address) & ~mask) == 0)
4174             break;
4175     }
4176     if (n < 0)
4177         return 2;
4178
4179     if (access_type == 2) {
4180         mask = env->cp15.pmsav5_insn_ap;
4181     } else {
4182         mask = env->cp15.pmsav5_data_ap;
4183     }
4184     mask = (mask >> (n * 4)) & 0xf;
4185     switch (mask) {
4186     case 0:
4187         return 1;
4188     case 1:
4189         if (is_user)
4190           return 1;
4191         *prot = PAGE_READ | PAGE_WRITE;
4192         break;
4193     case 2:
4194         *prot = PAGE_READ;
4195         if (!is_user)
4196             *prot |= PAGE_WRITE;
4197         break;
4198     case 3:
4199         *prot = PAGE_READ | PAGE_WRITE;
4200         break;
4201     case 5:
4202         if (is_user)
4203             return 1;
4204         *prot = PAGE_READ;
4205         break;
4206     case 6:
4207         *prot = PAGE_READ;
4208         break;
4209     default:
4210         /* Bad permission.  */
4211         return 1;
4212     }
4213     *prot |= PAGE_EXEC;
4214     return 0;
4215 }
4216
4217 /* get_phys_addr - get the physical address for this virtual address
4218  *
4219  * Find the physical address corresponding to the given virtual address,
4220  * by doing a translation table walk on MMU based systems or using the
4221  * MPU state on MPU based systems.
4222  *
4223  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4224  * prot and page_size are not filled in, and the return value provides
4225  * information on why the translation aborted, in the format of a
4226  * DFSR/IFSR fault register, with the following caveats:
4227  *  * we honour the short vs long DFSR format differences.
4228  *  * the WnR bit is never set (the caller must do this).
4229  *  * for MPU based systems we don't bother to return a full FSR format
4230  *    value.
4231  *
4232  * @env: CPUARMState
4233  * @address: virtual address to get physical address for
4234  * @access_type: 0 for read, 1 for write, 2 for execute
4235  * @is_user: 0 for privileged access, 1 for user
4236  * @phys_ptr: set to the physical address corresponding to the virtual address
4237  * @prot: set to the permissions for the page containing phys_ptr
4238  * @page_size: set to the size of the page containing phys_ptr
4239  */
4240 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
4241                                 int access_type, int is_user,
4242                                 hwaddr *phys_ptr, int *prot,
4243                                 target_ulong *page_size)
4244 {
4245     /* Fast Context Switch Extension.  */
4246     if (address < 0x02000000)
4247         address += env->cp15.c13_fcse;
4248
4249     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
4250         /* MMU/MPU disabled.  */
4251         *phys_ptr = address;
4252         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4253         *page_size = TARGET_PAGE_SIZE;
4254         return 0;
4255     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4256         *page_size = TARGET_PAGE_SIZE;
4257         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4258                                  prot);
4259     } else if (extended_addresses_enabled(env)) {
4260         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4261                                   prot, page_size);
4262     } else if (env->cp15.c1_sys & SCTLR_XP) {
4263         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4264                                 prot, page_size);
4265     } else {
4266         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4267                                 prot, page_size);
4268     }
4269 }
4270
4271 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4272                              int access_type, int mmu_idx)
4273 {
4274     ARMCPU *cpu = ARM_CPU(cs);
4275     CPUARMState *env = &cpu->env;
4276     hwaddr phys_addr;
4277     target_ulong page_size;
4278     int prot;
4279     int ret, is_user;
4280     uint32_t syn;
4281     bool same_el = (arm_current_pl(env) != 0);
4282
4283     is_user = mmu_idx == MMU_USER_IDX;
4284     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4285                         &page_size);
4286     if (ret == 0) {
4287         /* Map a single [sub]page.  */
4288         phys_addr &= TARGET_PAGE_MASK;
4289         address &= TARGET_PAGE_MASK;
4290         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4291         return 0;
4292     }
4293
4294     /* AArch64 syndrome does not have an LPAE bit */
4295     syn = ret & ~(1 << 9);
4296
4297     /* For insn and data aborts we assume there is no instruction syndrome
4298      * information; this is always true for exceptions reported to EL1.
4299      */
4300     if (access_type == 2) {
4301         syn = syn_insn_abort(same_el, 0, 0, syn);
4302         cs->exception_index = EXCP_PREFETCH_ABORT;
4303     } else {
4304         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4305         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4306             ret |= (1 << 11);
4307         }
4308         cs->exception_index = EXCP_DATA_ABORT;
4309     }
4310
4311     env->exception.syndrome = syn;
4312     env->exception.vaddress = address;
4313     env->exception.fsr = ret;
4314     return 1;
4315 }
4316
4317 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4318 {
4319     ARMCPU *cpu = ARM_CPU(cs);
4320     hwaddr phys_addr;
4321     target_ulong page_size;
4322     int prot;
4323     int ret;
4324
4325     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4326
4327     if (ret != 0) {
4328         return -1;
4329     }
4330
4331     return phys_addr;
4332 }
4333
4334 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4335 {
4336     if ((env->uncached_cpsr & CPSR_M) == mode) {
4337         env->regs[13] = val;
4338     } else {
4339         env->banked_r13[bank_number(mode)] = val;
4340     }
4341 }
4342
4343 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4344 {
4345     if ((env->uncached_cpsr & CPSR_M) == mode) {
4346         return env->regs[13];
4347     } else {
4348         return env->banked_r13[bank_number(mode)];
4349     }
4350 }
4351
4352 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4353 {
4354     ARMCPU *cpu = arm_env_get_cpu(env);
4355
4356     switch (reg) {
4357     case 0: /* APSR */
4358         return xpsr_read(env) & 0xf8000000;
4359     case 1: /* IAPSR */
4360         return xpsr_read(env) & 0xf80001ff;
4361     case 2: /* EAPSR */
4362         return xpsr_read(env) & 0xff00fc00;
4363     case 3: /* xPSR */
4364         return xpsr_read(env) & 0xff00fdff;
4365     case 5: /* IPSR */
4366         return xpsr_read(env) & 0x000001ff;
4367     case 6: /* EPSR */
4368         return xpsr_read(env) & 0x0700fc00;
4369     case 7: /* IEPSR */
4370         return xpsr_read(env) & 0x0700edff;
4371     case 8: /* MSP */
4372         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4373     case 9: /* PSP */
4374         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4375     case 16: /* PRIMASK */
4376         return (env->daif & PSTATE_I) != 0;
4377     case 17: /* BASEPRI */
4378     case 18: /* BASEPRI_MAX */
4379         return env->v7m.basepri;
4380     case 19: /* FAULTMASK */
4381         return (env->daif & PSTATE_F) != 0;
4382     case 20: /* CONTROL */
4383         return env->v7m.control;
4384     default:
4385         /* ??? For debugging only.  */
4386         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4387         return 0;
4388     }
4389 }
4390
4391 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4392 {
4393     ARMCPU *cpu = arm_env_get_cpu(env);
4394
4395     switch (reg) {
4396     case 0: /* APSR */
4397         xpsr_write(env, val, 0xf8000000);
4398         break;
4399     case 1: /* IAPSR */
4400         xpsr_write(env, val, 0xf8000000);
4401         break;
4402     case 2: /* EAPSR */
4403         xpsr_write(env, val, 0xfe00fc00);
4404         break;
4405     case 3: /* xPSR */
4406         xpsr_write(env, val, 0xfe00fc00);
4407         break;
4408     case 5: /* IPSR */
4409         /* IPSR bits are readonly.  */
4410         break;
4411     case 6: /* EPSR */
4412         xpsr_write(env, val, 0x0600fc00);
4413         break;
4414     case 7: /* IEPSR */
4415         xpsr_write(env, val, 0x0600fc00);
4416         break;
4417     case 8: /* MSP */
4418         if (env->v7m.current_sp)
4419             env->v7m.other_sp = val;
4420         else
4421             env->regs[13] = val;
4422         break;
4423     case 9: /* PSP */
4424         if (env->v7m.current_sp)
4425             env->regs[13] = val;
4426         else
4427             env->v7m.other_sp = val;
4428         break;
4429     case 16: /* PRIMASK */
4430         if (val & 1) {
4431             env->daif |= PSTATE_I;
4432         } else {
4433             env->daif &= ~PSTATE_I;
4434         }
4435         break;
4436     case 17: /* BASEPRI */
4437         env->v7m.basepri = val & 0xff;
4438         break;
4439     case 18: /* BASEPRI_MAX */
4440         val &= 0xff;
4441         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4442             env->v7m.basepri = val;
4443         break;
4444     case 19: /* FAULTMASK */
4445         if (val & 1) {
4446             env->daif |= PSTATE_F;
4447         } else {
4448             env->daif &= ~PSTATE_F;
4449         }
4450         break;
4451     case 20: /* CONTROL */
4452         env->v7m.control = val & 3;
4453         switch_v7m_sp(env, (val & 2) != 0);
4454         break;
4455     default:
4456         /* ??? For debugging only.  */
4457         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4458         return;
4459     }
4460 }
4461
4462 #endif
4463
4464 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4465 {
4466     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4467      * Note that we do not implement the (architecturally mandated)
4468      * alignment fault for attempts to use this on Device memory
4469      * (which matches the usual QEMU behaviour of not implementing either
4470      * alignment faults or any memory attribute handling).
4471      */
4472
4473     ARMCPU *cpu = arm_env_get_cpu(env);
4474     uint64_t blocklen = 4 << cpu->dcz_blocksize;
4475     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4476
4477 #ifndef CONFIG_USER_ONLY
4478     {
4479         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4480          * the block size so we might have to do more than one TLB lookup.
4481          * We know that in fact for any v8 CPU the page size is at least 4K
4482          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4483          * 1K as an artefact of legacy v5 subpage support being present in the
4484          * same QEMU executable.
4485          */
4486         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4487         void *hostaddr[maxidx];
4488         int try, i;
4489
4490         for (try = 0; try < 2; try++) {
4491
4492             for (i = 0; i < maxidx; i++) {
4493                 hostaddr[i] = tlb_vaddr_to_host(env,
4494                                                 vaddr + TARGET_PAGE_SIZE * i,
4495                                                 1, cpu_mmu_index(env));
4496                 if (!hostaddr[i]) {
4497                     break;
4498                 }
4499             }
4500             if (i == maxidx) {
4501                 /* If it's all in the TLB it's fair game for just writing to;
4502                  * we know we don't need to update dirty status, etc.
4503                  */
4504                 for (i = 0; i < maxidx - 1; i++) {
4505                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4506                 }
4507                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4508                 return;
4509             }
4510             /* OK, try a store and see if we can populate the tlb. This
4511              * might cause an exception if the memory isn't writable,
4512              * in which case we will longjmp out of here. We must for
4513              * this purpose use the actual register value passed to us
4514              * so that we get the fault address right.
4515              */
4516             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4517             /* Now we can populate the other TLB entries, if any */
4518             for (i = 0; i < maxidx; i++) {
4519                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4520                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4521                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4522                 }
4523             }
4524         }
4525
4526         /* Slow path (probably attempt to do this to an I/O device or
4527          * similar, or clearing of a block of code we have translations
4528          * cached for). Just do a series of byte writes as the architecture
4529          * demands. It's not worth trying to use a cpu_physical_memory_map(),
4530          * memset(), unmap() sequence here because:
4531          *  + we'd need to account for the blocksize being larger than a page
4532          *  + the direct-RAM access case is almost always going to be dealt
4533          *    with in the fastpath code above, so there's no speed benefit
4534          *  + we would have to deal with the map returning NULL because the
4535          *    bounce buffer was in use
4536          */
4537         for (i = 0; i < blocklen; i++) {
4538             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4539         }
4540     }
4541 #else
4542     memset(g2h(vaddr), 0, blocklen);
4543 #endif
4544 }
4545
4546 /* Note that signed overflow is undefined in C.  The following routines are
4547    careful to use unsigned types where modulo arithmetic is required.
4548    Failure to do so _will_ break on newer gcc.  */
4549
4550 /* Signed saturating arithmetic.  */
4551
4552 /* Perform 16-bit signed saturating addition.  */
4553 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4554 {
4555     uint16_t res;
4556
4557     res = a + b;
4558     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4559         if (a & 0x8000)
4560             res = 0x8000;
4561         else
4562             res = 0x7fff;
4563     }
4564     return res;
4565 }
4566
4567 /* Perform 8-bit signed saturating addition.  */
4568 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4569 {
4570     uint8_t res;
4571
4572     res = a + b;
4573     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4574         if (a & 0x80)
4575             res = 0x80;
4576         else
4577             res = 0x7f;
4578     }
4579     return res;
4580 }
4581
4582 /* Perform 16-bit signed saturating subtraction.  */
4583 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4584 {
4585     uint16_t res;
4586
4587     res = a - b;
4588     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4589         if (a & 0x8000)
4590             res = 0x8000;
4591         else
4592             res = 0x7fff;
4593     }
4594     return res;
4595 }
4596
4597 /* Perform 8-bit signed saturating subtraction.  */
4598 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4599 {
4600     uint8_t res;
4601
4602     res = a - b;
4603     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4604         if (a & 0x80)
4605             res = 0x80;
4606         else
4607             res = 0x7f;
4608     }
4609     return res;
4610 }
4611
4612 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4613 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4614 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
4615 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
4616 #define PFX q
4617
4618 #include "op_addsub.h"
4619
4620 /* Unsigned saturating arithmetic.  */
4621 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4622 {
4623     uint16_t res;
4624     res = a + b;
4625     if (res < a)
4626         res = 0xffff;
4627     return res;
4628 }
4629
4630 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4631 {
4632     if (a > b)
4633         return a - b;
4634     else
4635         return 0;
4636 }
4637
4638 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4639 {
4640     uint8_t res;
4641     res = a + b;
4642     if (res < a)
4643         res = 0xff;
4644     return res;
4645 }
4646
4647 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4648 {
4649     if (a > b)
4650         return a - b;
4651     else
4652         return 0;
4653 }
4654
4655 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4656 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4657 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
4658 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
4659 #define PFX uq
4660
4661 #include "op_addsub.h"
4662
4663 /* Signed modulo arithmetic.  */
4664 #define SARITH16(a, b, n, op) do { \
4665     int32_t sum; \
4666     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4667     RESULT(sum, n, 16); \
4668     if (sum >= 0) \
4669         ge |= 3 << (n * 2); \
4670     } while(0)
4671
4672 #define SARITH8(a, b, n, op) do { \
4673     int32_t sum; \
4674     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4675     RESULT(sum, n, 8); \
4676     if (sum >= 0) \
4677         ge |= 1 << n; \
4678     } while(0)
4679
4680
4681 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4682 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4683 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
4684 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
4685 #define PFX s
4686 #define ARITH_GE
4687
4688 #include "op_addsub.h"
4689
4690 /* Unsigned modulo arithmetic.  */
4691 #define ADD16(a, b, n) do { \
4692     uint32_t sum; \
4693     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4694     RESULT(sum, n, 16); \
4695     if ((sum >> 16) == 1) \
4696         ge |= 3 << (n * 2); \
4697     } while(0)
4698
4699 #define ADD8(a, b, n) do { \
4700     uint32_t sum; \
4701     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4702     RESULT(sum, n, 8); \
4703     if ((sum >> 8) == 1) \
4704         ge |= 1 << n; \
4705     } while(0)
4706
4707 #define SUB16(a, b, n) do { \
4708     uint32_t sum; \
4709     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4710     RESULT(sum, n, 16); \
4711     if ((sum >> 16) == 0) \
4712         ge |= 3 << (n * 2); \
4713     } while(0)
4714
4715 #define SUB8(a, b, n) do { \
4716     uint32_t sum; \
4717     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4718     RESULT(sum, n, 8); \
4719     if ((sum >> 8) == 0) \
4720         ge |= 1 << n; \
4721     } while(0)
4722
4723 #define PFX u
4724 #define ARITH_GE
4725
4726 #include "op_addsub.h"
4727
4728 /* Halved signed arithmetic.  */
4729 #define ADD16(a, b, n) \
4730   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4731 #define SUB16(a, b, n) \
4732   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4733 #define ADD8(a, b, n) \
4734   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4735 #define SUB8(a, b, n) \
4736   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4737 #define PFX sh
4738
4739 #include "op_addsub.h"
4740
4741 /* Halved unsigned arithmetic.  */
4742 #define ADD16(a, b, n) \
4743   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4744 #define SUB16(a, b, n) \
4745   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4746 #define ADD8(a, b, n) \
4747   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4748 #define SUB8(a, b, n) \
4749   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4750 #define PFX uh
4751
4752 #include "op_addsub.h"
4753
4754 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4755 {
4756     if (a > b)
4757         return a - b;
4758     else
4759         return b - a;
4760 }
4761
4762 /* Unsigned sum of absolute byte differences.  */
4763 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4764 {
4765     uint32_t sum;
4766     sum = do_usad(a, b);
4767     sum += do_usad(a >> 8, b >> 8);
4768     sum += do_usad(a >> 16, b >>16);
4769     sum += do_usad(a >> 24, b >> 24);
4770     return sum;
4771 }
4772
4773 /* For ARMv6 SEL instruction.  */
4774 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4775 {
4776     uint32_t mask;
4777
4778     mask = 0;
4779     if (flags & 1)
4780         mask |= 0xff;
4781     if (flags & 2)
4782         mask |= 0xff00;
4783     if (flags & 4)
4784         mask |= 0xff0000;
4785     if (flags & 8)
4786         mask |= 0xff000000;
4787     return (a & mask) | (b & ~mask);
4788 }
4789
4790 /* VFP support.  We follow the convention used for VFP instructions:
4791    Single precision routines have a "s" suffix, double precision a
4792    "d" suffix.  */
4793
4794 /* Convert host exception flags to vfp form.  */
4795 static inline int vfp_exceptbits_from_host(int host_bits)
4796 {
4797     int target_bits = 0;
4798
4799     if (host_bits & float_flag_invalid)
4800         target_bits |= 1;
4801     if (host_bits & float_flag_divbyzero)
4802         target_bits |= 2;
4803     if (host_bits & float_flag_overflow)
4804         target_bits |= 4;
4805     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4806         target_bits |= 8;
4807     if (host_bits & float_flag_inexact)
4808         target_bits |= 0x10;
4809     if (host_bits & float_flag_input_denormal)
4810         target_bits |= 0x80;
4811     return target_bits;
4812 }
4813
4814 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4815 {
4816     int i;
4817     uint32_t fpscr;
4818
4819     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4820             | (env->vfp.vec_len << 16)
4821             | (env->vfp.vec_stride << 20);
4822     i = get_float_exception_flags(&env->vfp.fp_status);
4823     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4824     fpscr |= vfp_exceptbits_from_host(i);
4825     return fpscr;
4826 }
4827
4828 uint32_t vfp_get_fpscr(CPUARMState *env)
4829 {
4830     return HELPER(vfp_get_fpscr)(env);
4831 }
4832
4833 /* Convert vfp exception flags to target form.  */
4834 static inline int vfp_exceptbits_to_host(int target_bits)
4835 {
4836     int host_bits = 0;
4837
4838     if (target_bits & 1)
4839         host_bits |= float_flag_invalid;
4840     if (target_bits & 2)
4841         host_bits |= float_flag_divbyzero;
4842     if (target_bits & 4)
4843         host_bits |= float_flag_overflow;
4844     if (target_bits & 8)
4845         host_bits |= float_flag_underflow;
4846     if (target_bits & 0x10)
4847         host_bits |= float_flag_inexact;
4848     if (target_bits & 0x80)
4849         host_bits |= float_flag_input_denormal;
4850     return host_bits;
4851 }
4852
4853 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4854 {
4855     int i;
4856     uint32_t changed;
4857
4858     changed = env->vfp.xregs[ARM_VFP_FPSCR];
4859     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4860     env->vfp.vec_len = (val >> 16) & 7;
4861     env->vfp.vec_stride = (val >> 20) & 3;
4862
4863     changed ^= val;
4864     if (changed & (3 << 22)) {
4865         i = (val >> 22) & 3;
4866         switch (i) {
4867         case FPROUNDING_TIEEVEN:
4868             i = float_round_nearest_even;
4869             break;
4870         case FPROUNDING_POSINF:
4871             i = float_round_up;
4872             break;
4873         case FPROUNDING_NEGINF:
4874             i = float_round_down;
4875             break;
4876         case FPROUNDING_ZERO:
4877             i = float_round_to_zero;
4878             break;
4879         }
4880         set_float_rounding_mode(i, &env->vfp.fp_status);
4881     }
4882     if (changed & (1 << 24)) {
4883         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4884         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4885     }
4886     if (changed & (1 << 25))
4887         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4888
4889     i = vfp_exceptbits_to_host(val);
4890     set_float_exception_flags(i, &env->vfp.fp_status);
4891     set_float_exception_flags(0, &env->vfp.standard_fp_status);
4892 }
4893
4894 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4895 {
4896     HELPER(vfp_set_fpscr)(env, val);
4897 }
4898
4899 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4900
4901 #define VFP_BINOP(name) \
4902 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4903 { \
4904     float_status *fpst = fpstp; \
4905     return float32_ ## name(a, b, fpst); \
4906 } \
4907 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4908 { \
4909     float_status *fpst = fpstp; \
4910     return float64_ ## name(a, b, fpst); \
4911 }
4912 VFP_BINOP(add)
4913 VFP_BINOP(sub)
4914 VFP_BINOP(mul)
4915 VFP_BINOP(div)
4916 VFP_BINOP(min)
4917 VFP_BINOP(max)
4918 VFP_BINOP(minnum)
4919 VFP_BINOP(maxnum)
4920 #undef VFP_BINOP
4921
4922 float32 VFP_HELPER(neg, s)(float32 a)
4923 {
4924     return float32_chs(a);
4925 }
4926
4927 float64 VFP_HELPER(neg, d)(float64 a)
4928 {
4929     return float64_chs(a);
4930 }
4931
4932 float32 VFP_HELPER(abs, s)(float32 a)
4933 {
4934     return float32_abs(a);
4935 }
4936
4937 float64 VFP_HELPER(abs, d)(float64 a)
4938 {
4939     return float64_abs(a);
4940 }
4941
4942 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4943 {
4944     return float32_sqrt(a, &env->vfp.fp_status);
4945 }
4946
4947 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4948 {
4949     return float64_sqrt(a, &env->vfp.fp_status);
4950 }
4951
4952 /* XXX: check quiet/signaling case */
4953 #define DO_VFP_cmp(p, type) \
4954 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
4955 { \
4956     uint32_t flags; \
4957     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4958     case 0: flags = 0x6; break; \
4959     case -1: flags = 0x8; break; \
4960     case 1: flags = 0x2; break; \
4961     default: case 2: flags = 0x3; break; \
4962     } \
4963     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4964         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4965 } \
4966 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4967 { \
4968     uint32_t flags; \
4969     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4970     case 0: flags = 0x6; break; \
4971     case -1: flags = 0x8; break; \
4972     case 1: flags = 0x2; break; \
4973     default: case 2: flags = 0x3; break; \
4974     } \
4975     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4976         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4977 }
4978 DO_VFP_cmp(s, float32)
4979 DO_VFP_cmp(d, float64)
4980 #undef DO_VFP_cmp
4981
4982 /* Integer to float and float to integer conversions */
4983
4984 #define CONV_ITOF(name, fsz, sign) \
4985     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4986 { \
4987     float_status *fpst = fpstp; \
4988     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4989 }
4990
4991 #define CONV_FTOI(name, fsz, sign, round) \
4992 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4993 { \
4994     float_status *fpst = fpstp; \
4995     if (float##fsz##_is_any_nan(x)) { \
4996         float_raise(float_flag_invalid, fpst); \
4997         return 0; \
4998     } \
4999     return float##fsz##_to_##sign##int32##round(x, fpst); \
5000 }
5001
5002 #define FLOAT_CONVS(name, p, fsz, sign) \
5003 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
5004 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
5005 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
5006
5007 FLOAT_CONVS(si, s, 32, )
5008 FLOAT_CONVS(si, d, 64, )
5009 FLOAT_CONVS(ui, s, 32, u)
5010 FLOAT_CONVS(ui, d, 64, u)
5011
5012 #undef CONV_ITOF
5013 #undef CONV_FTOI
5014 #undef FLOAT_CONVS
5015
5016 /* floating point conversion */
5017 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
5018 {
5019     float64 r = float32_to_float64(x, &env->vfp.fp_status);
5020     /* ARM requires that S<->D conversion of any kind of NaN generates
5021      * a quiet NaN by forcing the most significant frac bit to 1.
5022      */
5023     return float64_maybe_silence_nan(r);
5024 }
5025
5026 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
5027 {
5028     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
5029     /* ARM requires that S<->D conversion of any kind of NaN generates
5030      * a quiet NaN by forcing the most significant frac bit to 1.
5031      */
5032     return float32_maybe_silence_nan(r);
5033 }
5034
5035 /* VFP3 fixed point conversion.  */
5036 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
5037 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
5038                                      void *fpstp) \
5039 { \
5040     float_status *fpst = fpstp; \
5041     float##fsz tmp; \
5042     tmp = itype##_to_##float##fsz(x, fpst); \
5043     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
5044 }
5045
5046 /* Notice that we want only input-denormal exception flags from the
5047  * scalbn operation: the other possible flags (overflow+inexact if
5048  * we overflow to infinity, output-denormal) aren't correct for the
5049  * complete scale-and-convert operation.
5050  */
5051 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
5052 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
5053                                              uint32_t shift, \
5054                                              void *fpstp) \
5055 { \
5056     float_status *fpst = fpstp; \
5057     int old_exc_flags = get_float_exception_flags(fpst); \
5058     float##fsz tmp; \
5059     if (float##fsz##_is_any_nan(x)) { \
5060         float_raise(float_flag_invalid, fpst); \
5061         return 0; \
5062     } \
5063     tmp = float##fsz##_scalbn(x, shift, fpst); \
5064     old_exc_flags |= get_float_exception_flags(fpst) \
5065         & float_flag_input_denormal; \
5066     set_float_exception_flags(old_exc_flags, fpst); \
5067     return float##fsz##_to_##itype##round(tmp, fpst); \
5068 }
5069
5070 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
5071 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5072 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
5073 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5074
5075 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
5076 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5077 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5078
5079 VFP_CONV_FIX(sh, d, 64, 64, int16)
5080 VFP_CONV_FIX(sl, d, 64, 64, int32)
5081 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
5082 VFP_CONV_FIX(uh, d, 64, 64, uint16)
5083 VFP_CONV_FIX(ul, d, 64, 64, uint32)
5084 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
5085 VFP_CONV_FIX(sh, s, 32, 32, int16)
5086 VFP_CONV_FIX(sl, s, 32, 32, int32)
5087 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
5088 VFP_CONV_FIX(uh, s, 32, 32, uint16)
5089 VFP_CONV_FIX(ul, s, 32, 32, uint32)
5090 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
5091 #undef VFP_CONV_FIX
5092 #undef VFP_CONV_FIX_FLOAT
5093 #undef VFP_CONV_FLOAT_FIX_ROUND
5094
5095 /* Set the current fp rounding mode and return the old one.
5096  * The argument is a softfloat float_round_ value.
5097  */
5098 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
5099 {
5100     float_status *fp_status = &env->vfp.fp_status;
5101
5102     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5103     set_float_rounding_mode(rmode, fp_status);
5104
5105     return prev_rmode;
5106 }
5107
5108 /* Set the current fp rounding mode in the standard fp status and return
5109  * the old one. This is for NEON instructions that need to change the
5110  * rounding mode but wish to use the standard FPSCR values for everything
5111  * else. Always set the rounding mode back to the correct value after
5112  * modifying it.
5113  * The argument is a softfloat float_round_ value.
5114  */
5115 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
5116 {
5117     float_status *fp_status = &env->vfp.standard_fp_status;
5118
5119     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5120     set_float_rounding_mode(rmode, fp_status);
5121
5122     return prev_rmode;
5123 }
5124
5125 /* Half precision conversions.  */
5126 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
5127 {
5128     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5129     float32 r = float16_to_float32(make_float16(a), ieee, s);
5130     if (ieee) {
5131         return float32_maybe_silence_nan(r);
5132     }
5133     return r;
5134 }
5135
5136 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
5137 {
5138     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5139     float16 r = float32_to_float16(a, ieee, s);
5140     if (ieee) {
5141         r = float16_maybe_silence_nan(r);
5142     }
5143     return float16_val(r);
5144 }
5145
5146 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5147 {
5148     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
5149 }
5150
5151 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5152 {
5153     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
5154 }
5155
5156 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5157 {
5158     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
5159 }
5160
5161 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5162 {
5163     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
5164 }
5165
5166 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
5167 {
5168     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5169     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
5170     if (ieee) {
5171         return float64_maybe_silence_nan(r);
5172     }
5173     return r;
5174 }
5175
5176 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
5177 {
5178     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5179     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
5180     if (ieee) {
5181         r = float16_maybe_silence_nan(r);
5182     }
5183     return float16_val(r);
5184 }
5185
5186 #define float32_two make_float32(0x40000000)
5187 #define float32_three make_float32(0x40400000)
5188 #define float32_one_point_five make_float32(0x3fc00000)
5189
5190 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
5191 {
5192     float_status *s = &env->vfp.standard_fp_status;
5193     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5194         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5195         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5196             float_raise(float_flag_input_denormal, s);
5197         }
5198         return float32_two;
5199     }
5200     return float32_sub(float32_two, float32_mul(a, b, s), s);
5201 }
5202
5203 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
5204 {
5205     float_status *s = &env->vfp.standard_fp_status;
5206     float32 product;
5207     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5208         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5209         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5210             float_raise(float_flag_input_denormal, s);
5211         }
5212         return float32_one_point_five;
5213     }
5214     product = float32_mul(a, b, s);
5215     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
5216 }
5217
5218 /* NEON helpers.  */
5219
5220 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5221  * int->float conversions at run-time.  */
5222 #define float64_256 make_float64(0x4070000000000000LL)
5223 #define float64_512 make_float64(0x4080000000000000LL)
5224 #define float32_maxnorm make_float32(0x7f7fffff)
5225 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5226
5227 /* Reciprocal functions
5228  *
5229  * The algorithm that must be used to calculate the estimate
5230  * is specified by the ARM ARM, see FPRecipEstimate()
5231  */
5232
5233 static float64 recip_estimate(float64 a, float_status *real_fp_status)
5234 {
5235     /* These calculations mustn't set any fp exception flags,
5236      * so we use a local copy of the fp_status.
5237      */
5238     float_status dummy_status = *real_fp_status;
5239     float_status *s = &dummy_status;
5240     /* q = (int)(a * 512.0) */
5241     float64 q = float64_mul(float64_512, a, s);
5242     int64_t q_int = float64_to_int64_round_to_zero(q, s);
5243
5244     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5245     q = int64_to_float64(q_int, s);
5246     q = float64_add(q, float64_half, s);
5247     q = float64_div(q, float64_512, s);
5248     q = float64_div(float64_one, q, s);
5249
5250     /* s = (int)(256.0 * r + 0.5) */
5251     q = float64_mul(q, float64_256, s);
5252     q = float64_add(q, float64_half, s);
5253     q_int = float64_to_int64_round_to_zero(q, s);
5254
5255     /* return (double)s / 256.0 */
5256     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5257 }
5258
5259 /* Common wrapper to call recip_estimate */
5260 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5261 {
5262     uint64_t val64 = float64_val(num);
5263     uint64_t frac = extract64(val64, 0, 52);
5264     int64_t exp = extract64(val64, 52, 11);
5265     uint64_t sbit;
5266     float64 scaled, estimate;
5267
5268     /* Generate the scaled number for the estimate function */
5269     if (exp == 0) {
5270         if (extract64(frac, 51, 1) == 0) {
5271             exp = -1;
5272             frac = extract64(frac, 0, 50) << 2;
5273         } else {
5274             frac = extract64(frac, 0, 51) << 1;
5275         }
5276     }
5277
5278     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5279     scaled = make_float64((0x3feULL << 52)
5280                           | extract64(frac, 44, 8) << 44);
5281
5282     estimate = recip_estimate(scaled, fpst);
5283
5284     /* Build new result */
5285     val64 = float64_val(estimate);
5286     sbit = 0x8000000000000000ULL & val64;
5287     exp = off - exp;
5288     frac = extract64(val64, 0, 52);
5289
5290     if (exp == 0) {
5291         frac = 1ULL << 51 | extract64(frac, 1, 51);
5292     } else if (exp == -1) {
5293         frac = 1ULL << 50 | extract64(frac, 2, 50);
5294         exp = 0;
5295     }
5296
5297     return make_float64(sbit | (exp << 52) | frac);
5298 }
5299
5300 static bool round_to_inf(float_status *fpst, bool sign_bit)
5301 {
5302     switch (fpst->float_rounding_mode) {
5303     case float_round_nearest_even: /* Round to Nearest */
5304         return true;
5305     case float_round_up: /* Round to +Inf */
5306         return !sign_bit;
5307     case float_round_down: /* Round to -Inf */
5308         return sign_bit;
5309     case float_round_to_zero: /* Round to Zero */
5310         return false;
5311     }
5312
5313     g_assert_not_reached();
5314 }
5315
5316 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5317 {
5318     float_status *fpst = fpstp;
5319     float32 f32 = float32_squash_input_denormal(input, fpst);
5320     uint32_t f32_val = float32_val(f32);
5321     uint32_t f32_sbit = 0x80000000ULL & f32_val;
5322     int32_t f32_exp = extract32(f32_val, 23, 8);
5323     uint32_t f32_frac = extract32(f32_val, 0, 23);
5324     float64 f64, r64;
5325     uint64_t r64_val;
5326     int64_t r64_exp;
5327     uint64_t r64_frac;
5328
5329     if (float32_is_any_nan(f32)) {
5330         float32 nan = f32;
5331         if (float32_is_signaling_nan(f32)) {
5332             float_raise(float_flag_invalid, fpst);
5333             nan = float32_maybe_silence_nan(f32);
5334         }
5335         if (fpst->default_nan_mode) {
5336             nan =  float32_default_nan;
5337         }
5338         return nan;
5339     } else if (float32_is_infinity(f32)) {
5340         return float32_set_sign(float32_zero, float32_is_neg(f32));
5341     } else if (float32_is_zero(f32)) {
5342         float_raise(float_flag_divbyzero, fpst);
5343         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5344     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5345         /* Abs(value) < 2.0^-128 */
5346         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5347         if (round_to_inf(fpst, f32_sbit)) {
5348             return float32_set_sign(float32_infinity, float32_is_neg(f32));
5349         } else {
5350             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5351         }
5352     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5353         float_raise(float_flag_underflow, fpst);
5354         return float32_set_sign(float32_zero, float32_is_neg(f32));
5355     }
5356
5357
5358     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5359     r64 = call_recip_estimate(f64, 253, fpst);
5360     r64_val = float64_val(r64);
5361     r64_exp = extract64(r64_val, 52, 11);
5362     r64_frac = extract64(r64_val, 0, 52);
5363
5364     /* result = sign : result_exp<7:0> : fraction<51:29>; */
5365     return make_float32(f32_sbit |
5366                         (r64_exp & 0xff) << 23 |
5367                         extract64(r64_frac, 29, 24));
5368 }
5369
5370 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5371 {
5372     float_status *fpst = fpstp;
5373     float64 f64 = float64_squash_input_denormal(input, fpst);
5374     uint64_t f64_val = float64_val(f64);
5375     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5376     int64_t f64_exp = extract64(f64_val, 52, 11);
5377     float64 r64;
5378     uint64_t r64_val;
5379     int64_t r64_exp;
5380     uint64_t r64_frac;
5381
5382     /* Deal with any special cases */
5383     if (float64_is_any_nan(f64)) {
5384         float64 nan = f64;
5385         if (float64_is_signaling_nan(f64)) {
5386             float_raise(float_flag_invalid, fpst);
5387             nan = float64_maybe_silence_nan(f64);
5388         }
5389         if (fpst->default_nan_mode) {
5390             nan =  float64_default_nan;
5391         }
5392         return nan;
5393     } else if (float64_is_infinity(f64)) {
5394         return float64_set_sign(float64_zero, float64_is_neg(f64));
5395     } else if (float64_is_zero(f64)) {
5396         float_raise(float_flag_divbyzero, fpst);
5397         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5398     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5399         /* Abs(value) < 2.0^-1024 */
5400         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5401         if (round_to_inf(fpst, f64_sbit)) {
5402             return float64_set_sign(float64_infinity, float64_is_neg(f64));
5403         } else {
5404             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5405         }
5406     } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5407         float_raise(float_flag_underflow, fpst);
5408         return float64_set_sign(float64_zero, float64_is_neg(f64));
5409     }
5410
5411     r64 = call_recip_estimate(f64, 2045, fpst);
5412     r64_val = float64_val(r64);
5413     r64_exp = extract64(r64_val, 52, 11);
5414     r64_frac = extract64(r64_val, 0, 52);
5415
5416     /* result = sign : result_exp<10:0> : fraction<51:0> */
5417     return make_float64(f64_sbit |
5418                         ((r64_exp & 0x7ff) << 52) |
5419                         r64_frac);
5420 }
5421
5422 /* The algorithm that must be used to calculate the estimate
5423  * is specified by the ARM ARM.
5424  */
5425 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5426 {
5427     /* These calculations mustn't set any fp exception flags,
5428      * so we use a local copy of the fp_status.
5429      */
5430     float_status dummy_status = *real_fp_status;
5431     float_status *s = &dummy_status;
5432     float64 q;
5433     int64_t q_int;
5434
5435     if (float64_lt(a, float64_half, s)) {
5436         /* range 0.25 <= a < 0.5 */
5437
5438         /* a in units of 1/512 rounded down */
5439         /* q0 = (int)(a * 512.0);  */
5440         q = float64_mul(float64_512, a, s);
5441         q_int = float64_to_int64_round_to_zero(q, s);
5442
5443         /* reciprocal root r */
5444         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
5445         q = int64_to_float64(q_int, s);
5446         q = float64_add(q, float64_half, s);
5447         q = float64_div(q, float64_512, s);
5448         q = float64_sqrt(q, s);
5449         q = float64_div(float64_one, q, s);
5450     } else {
5451         /* range 0.5 <= a < 1.0 */
5452
5453         /* a in units of 1/256 rounded down */
5454         /* q1 = (int)(a * 256.0); */
5455         q = float64_mul(float64_256, a, s);
5456         int64_t q_int = float64_to_int64_round_to_zero(q, s);
5457
5458         /* reciprocal root r */
5459         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5460         q = int64_to_float64(q_int, s);
5461         q = float64_add(q, float64_half, s);
5462         q = float64_div(q, float64_256, s);
5463         q = float64_sqrt(q, s);
5464         q = float64_div(float64_one, q, s);
5465     }
5466     /* r in units of 1/256 rounded to nearest */
5467     /* s = (int)(256.0 * r + 0.5); */
5468
5469     q = float64_mul(q, float64_256,s );
5470     q = float64_add(q, float64_half, s);
5471     q_int = float64_to_int64_round_to_zero(q, s);
5472
5473     /* return (double)s / 256.0;*/
5474     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5475 }
5476
5477 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5478 {
5479     float_status *s = fpstp;
5480     float32 f32 = float32_squash_input_denormal(input, s);
5481     uint32_t val = float32_val(f32);
5482     uint32_t f32_sbit = 0x80000000 & val;
5483     int32_t f32_exp = extract32(val, 23, 8);
5484     uint32_t f32_frac = extract32(val, 0, 23);
5485     uint64_t f64_frac;
5486     uint64_t val64;
5487     int result_exp;
5488     float64 f64;
5489
5490     if (float32_is_any_nan(f32)) {
5491         float32 nan = f32;
5492         if (float32_is_signaling_nan(f32)) {
5493             float_raise(float_flag_invalid, s);
5494             nan = float32_maybe_silence_nan(f32);
5495         }
5496         if (s->default_nan_mode) {
5497             nan =  float32_default_nan;
5498         }
5499         return nan;
5500     } else if (float32_is_zero(f32)) {
5501         float_raise(float_flag_divbyzero, s);
5502         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5503     } else if (float32_is_neg(f32)) {
5504         float_raise(float_flag_invalid, s);
5505         return float32_default_nan;
5506     } else if (float32_is_infinity(f32)) {
5507         return float32_zero;
5508     }
5509
5510     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5511      * preserving the parity of the exponent.  */
5512
5513     f64_frac = ((uint64_t) f32_frac) << 29;
5514     if (f32_exp == 0) {
5515         while (extract64(f64_frac, 51, 1) == 0) {
5516             f64_frac = f64_frac << 1;
5517             f32_exp = f32_exp-1;
5518         }
5519         f64_frac = extract64(f64_frac, 0, 51) << 1;
5520     }
5521
5522     if (extract64(f32_exp, 0, 1) == 0) {
5523         f64 = make_float64(((uint64_t) f32_sbit) << 32
5524                            | (0x3feULL << 52)
5525                            | f64_frac);
5526     } else {
5527         f64 = make_float64(((uint64_t) f32_sbit) << 32
5528                            | (0x3fdULL << 52)
5529                            | f64_frac);
5530     }
5531
5532     result_exp = (380 - f32_exp) / 2;
5533
5534     f64 = recip_sqrt_estimate(f64, s);
5535
5536     val64 = float64_val(f64);
5537
5538     val = ((result_exp & 0xff) << 23)
5539         | ((val64 >> 29)  & 0x7fffff);
5540     return make_float32(val);
5541 }
5542
5543 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5544 {
5545     float_status *s = fpstp;
5546     float64 f64 = float64_squash_input_denormal(input, s);
5547     uint64_t val = float64_val(f64);
5548     uint64_t f64_sbit = 0x8000000000000000ULL & val;
5549     int64_t f64_exp = extract64(val, 52, 11);
5550     uint64_t f64_frac = extract64(val, 0, 52);
5551     int64_t result_exp;
5552     uint64_t result_frac;
5553
5554     if (float64_is_any_nan(f64)) {
5555         float64 nan = f64;
5556         if (float64_is_signaling_nan(f64)) {
5557             float_raise(float_flag_invalid, s);
5558             nan = float64_maybe_silence_nan(f64);
5559         }
5560         if (s->default_nan_mode) {
5561             nan =  float64_default_nan;
5562         }
5563         return nan;
5564     } else if (float64_is_zero(f64)) {
5565         float_raise(float_flag_divbyzero, s);
5566         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5567     } else if (float64_is_neg(f64)) {
5568         float_raise(float_flag_invalid, s);
5569         return float64_default_nan;
5570     } else if (float64_is_infinity(f64)) {
5571         return float64_zero;
5572     }
5573
5574     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5575      * preserving the parity of the exponent.  */
5576
5577     if (f64_exp == 0) {
5578         while (extract64(f64_frac, 51, 1) == 0) {
5579             f64_frac = f64_frac << 1;
5580             f64_exp = f64_exp - 1;
5581         }
5582         f64_frac = extract64(f64_frac, 0, 51) << 1;
5583     }
5584
5585     if (extract64(f64_exp, 0, 1) == 0) {
5586         f64 = make_float64(f64_sbit
5587                            | (0x3feULL << 52)
5588                            | f64_frac);
5589     } else {
5590         f64 = make_float64(f64_sbit
5591                            | (0x3fdULL << 52)
5592                            | f64_frac);
5593     }
5594
5595     result_exp = (3068 - f64_exp) / 2;
5596
5597     f64 = recip_sqrt_estimate(f64, s);
5598
5599     result_frac = extract64(float64_val(f64), 0, 52);
5600
5601     return make_float64(f64_sbit |
5602                         ((result_exp & 0x7ff) << 52) |
5603                         result_frac);
5604 }
5605
5606 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5607 {
5608     float_status *s = fpstp;
5609     float64 f64;
5610
5611     if ((a & 0x80000000) == 0) {
5612         return 0xffffffff;
5613     }
5614
5615     f64 = make_float64((0x3feULL << 52)
5616                        | ((int64_t)(a & 0x7fffffff) << 21));
5617
5618     f64 = recip_estimate(f64, s);
5619
5620     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5621 }
5622
5623 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5624 {
5625     float_status *fpst = fpstp;
5626     float64 f64;
5627
5628     if ((a & 0xc0000000) == 0) {
5629         return 0xffffffff;
5630     }
5631
5632     if (a & 0x80000000) {
5633         f64 = make_float64((0x3feULL << 52)
5634                            | ((uint64_t)(a & 0x7fffffff) << 21));
5635     } else { /* bits 31-30 == '01' */
5636         f64 = make_float64((0x3fdULL << 52)
5637                            | ((uint64_t)(a & 0x3fffffff) << 22));
5638     }
5639
5640     f64 = recip_sqrt_estimate(f64, fpst);
5641
5642     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5643 }
5644
5645 /* VFPv4 fused multiply-accumulate */
5646 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5647 {
5648     float_status *fpst = fpstp;
5649     return float32_muladd(a, b, c, 0, fpst);
5650 }
5651
5652 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5653 {
5654     float_status *fpst = fpstp;
5655     return float64_muladd(a, b, c, 0, fpst);
5656 }
5657
5658 /* ARMv8 round to integral */
5659 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5660 {
5661     return float32_round_to_int(x, fp_status);
5662 }
5663
5664 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5665 {
5666     return float64_round_to_int(x, fp_status);
5667 }
5668
5669 float32 HELPER(rints)(float32 x, void *fp_status)
5670 {
5671     int old_flags = get_float_exception_flags(fp_status), new_flags;
5672     float32 ret;
5673
5674     ret = float32_round_to_int(x, fp_status);
5675
5676     /* Suppress any inexact exceptions the conversion produced */
5677     if (!(old_flags & float_flag_inexact)) {
5678         new_flags = get_float_exception_flags(fp_status);
5679         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5680     }
5681
5682     return ret;
5683 }
5684
5685 float64 HELPER(rintd)(float64 x, void *fp_status)
5686 {
5687     int old_flags = get_float_exception_flags(fp_status), new_flags;
5688     float64 ret;
5689
5690     ret = float64_round_to_int(x, fp_status);
5691
5692     new_flags = get_float_exception_flags(fp_status);
5693
5694     /* Suppress any inexact exceptions the conversion produced */
5695     if (!(old_flags & float_flag_inexact)) {
5696         new_flags = get_float_exception_flags(fp_status);
5697         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5698     }
5699
5700     return ret;
5701 }
5702
5703 /* Convert ARM rounding mode to softfloat */
5704 int arm_rmode_to_sf(int rmode)
5705 {
5706     switch (rmode) {
5707     case FPROUNDING_TIEAWAY:
5708         rmode = float_round_ties_away;
5709         break;
5710     case FPROUNDING_ODD:
5711         /* FIXME: add support for TIEAWAY and ODD */
5712         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5713                       rmode);
5714     case FPROUNDING_TIEEVEN:
5715     default:
5716         rmode = float_round_nearest_even;
5717         break;
5718     case FPROUNDING_POSINF:
5719         rmode = float_round_up;
5720         break;
5721     case FPROUNDING_NEGINF:
5722         rmode = float_round_down;
5723         break;
5724     case FPROUNDING_ZERO:
5725         rmode = float_round_to_zero;
5726         break;
5727     }
5728     return rmode;
5729 }
5730
5731 /* CRC helpers.
5732  * The upper bytes of val (above the number specified by 'bytes') must have
5733  * been zeroed out by the caller.
5734  */
5735 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5736 {
5737     uint8_t buf[4];
5738
5739     stl_le_p(buf, val);
5740
5741     /* zlib crc32 converts the accumulator and output to one's complement.  */
5742     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5743 }
5744
5745 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5746 {
5747     uint8_t buf[4];
5748
5749     stl_le_p(buf, val);
5750
5751     /* Linux crc32c converts the output to one's complement.  */
5752     return crc32c(acc, buf, bytes) ^ 0xffffffff;
5753 }