target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7
   8 #define CPUArchState struct CPUMIPSState
   9
  10 #include "qemu-common.h"
  11 #include "cpu-qom.h"
  12 #include "mips-defs.h"
  13 #include "exec/cpu-defs.h"
  14 #include "fpu/softfloat.h"
  15
  16 struct CPUMIPSState;
  17
  18 typedef struct r4k_tlb_t r4k_tlb_t;
  19 struct r4k_tlb_t {
  20     target_ulong VPN;
  21     uint32_t PageMask;
  22     uint8_t ASID;
  23     unsigned int G:1;
  24     unsigned int C0:3;
  25     unsigned int C1:3;
  26     unsigned int V0:1;
  27     unsigned int V1:1;
  28     unsigned int D0:1;
  29     unsigned int D1:1;
  30     unsigned int XI0:1;
  31     unsigned int XI1:1;
  32     unsigned int RI0:1;
  33     unsigned int RI1:1;
  34     unsigned int EHINV:1;
  35     uint64_t PFN[2];
  36 };
  37
  38 #if !defined(CONFIG_USER_ONLY)
  39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  40 struct CPUMIPSTLBContext {
  41     uint32_t nb_tlb;
  42     uint32_t tlb_in_use;
  43     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  44     void (*helper_tlbwi)(struct CPUMIPSState *env);
  45     void (*helper_tlbwr)(struct CPUMIPSState *env);
  46     void (*helper_tlbp)(struct CPUMIPSState *env);
  47     void (*helper_tlbr)(struct CPUMIPSState *env);
  48     void (*helper_tlbinv)(struct CPUMIPSState *env);
  49     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  50     union {
  51         struct {
  52             r4k_tlb_t tlb[MIPS_TLB_MAX];
  53         } r4k;
  54     } mmu;
  55 };
  56 #endif
  57
  58 /* MSA Context */
  59 #define MSA_WRLEN (128)
  60
  61 enum CPUMIPSMSADataFormat {
  62     DF_BYTE = 0,
  63     DF_HALF,
  64     DF_WORD,
  65     DF_DOUBLE
  66 };
  67
  68 typedef union wr_t wr_t;
  69 union wr_t {
  70     int8_t  b[MSA_WRLEN/8];
  71     int16_t h[MSA_WRLEN/16];
  72     int32_t w[MSA_WRLEN/32];
  73     int64_t d[MSA_WRLEN/64];
  74 };
  75
  76 typedef union fpr_t fpr_t;
  77 union fpr_t {
  78     float64  fd;   /* ieee double precision */
  79     float32  fs[2];/* ieee single precision */
  80     uint64_t d;    /* binary double fixed-point */
  81     uint32_t w[2]; /* binary single fixed-point */
  82 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  83     wr_t     wr;   /* vector data */
  84 };
  85 /* define FP_ENDIAN_IDX to access the same location
  86  * in the fpr_t union regardless of the host endianness
  87  */
  88 #if defined(HOST_WORDS_BIGENDIAN)
  89 #  define FP_ENDIAN_IDX 1
  90 #else
  91 #  define FP_ENDIAN_IDX 0
  92 #endif
  93
  94 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  95 struct CPUMIPSFPUContext {
  96     /* Floating point registers */
  97     fpr_t fpr[32];
  98     float_status fp_status;
  99     /* fpu implementation/revision register (fir) */
 100     uint32_t fcr0;
 101 #define FCR0_FREP 29
 102 #define FCR0_UFRP 28
 103 #define FCR0_HAS2008 23
 104 #define FCR0_F64 22
 105 #define FCR0_L 21
 106 #define FCR0_W 20
 107 #define FCR0_3D 19
 108 #define FCR0_PS 18
 109 #define FCR0_D 17
 110 #define FCR0_S 16
 111 #define FCR0_PRID 8
 112 #define FCR0_REV 0
 113     /* fcsr */
 114     uint32_t fcr31;
 115 #define FCR31_ABS2008 19
 116 #define FCR31_NAN2008 18
 117 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 118 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 119 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 120 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 121 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 122 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 123 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 124 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 125 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 126 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 127 #define FP_INEXACT        1
 128 #define FP_UNDERFLOW      2
 129 #define FP_OVERFLOW       4
 130 #define FP_DIV0           8
 131 #define FP_INVALID        16
 132 #define FP_UNIMPLEMENTED  32
 133 };
 134
 135 #define NB_MMU_MODES 3
 136 #define TARGET_INSN_START_EXTRA_WORDS 2
 137
 138 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 139 struct CPUMIPSMVPContext {
 140     int32_t CP0_MVPControl;
 141 #define CP0MVPCo_CPA    3
 142 #define CP0MVPCo_STLB   2
 143 #define CP0MVPCo_VPC    1
 144 #define CP0MVPCo_EVP    0
 145     int32_t CP0_MVPConf0;
 146 #define CP0MVPC0_M      31
 147 #define CP0MVPC0_TLBS   29
 148 #define CP0MVPC0_GS     28
 149 #define CP0MVPC0_PCP    27
 150 #define CP0MVPC0_PTLBE  16
 151 #define CP0MVPC0_TCA    15
 152 #define CP0MVPC0_PVPE   10
 153 #define CP0MVPC0_PTC    0
 154     int32_t CP0_MVPConf1;
 155 #define CP0MVPC1_CIM    31
 156 #define CP0MVPC1_CIF    30
 157 #define CP0MVPC1_PCX    20
 158 #define CP0MVPC1_PCP2   10
 159 #define CP0MVPC1_PCP1   0
 160 };
 161
 162 typedef struct mips_def_t mips_def_t;
 163
 164 #define MIPS_SHADOW_SET_MAX 16
 165 #define MIPS_TC_MAX 5
 166 #define MIPS_FPU_MAX 1
 167 #define MIPS_DSP_ACC 4
 168 #define MIPS_KSCRATCH_NUM 6
 169 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
 170
 171 typedef struct TCState TCState;
 172 struct TCState {
 173     target_ulong gpr[32];
 174     target_ulong PC;
 175     target_ulong HI[MIPS_DSP_ACC];
 176     target_ulong LO[MIPS_DSP_ACC];
 177     target_ulong ACX[MIPS_DSP_ACC];
 178     target_ulong DSPControl;
 179     int32_t CP0_TCStatus;
 180 #define CP0TCSt_TCU3    31
 181 #define CP0TCSt_TCU2    30
 182 #define CP0TCSt_TCU1    29
 183 #define CP0TCSt_TCU0    28
 184 #define CP0TCSt_TMX     27
 185 #define CP0TCSt_RNST    23
 186 #define CP0TCSt_TDS     21
 187 #define CP0TCSt_DT      20
 188 #define CP0TCSt_DA      15
 189 #define CP0TCSt_A       13
 190 #define CP0TCSt_TKSU    11
 191 #define CP0TCSt_IXMT    10
 192 #define CP0TCSt_TASID   0
 193     int32_t CP0_TCBind;
 194 #define CP0TCBd_CurTC   21
 195 #define CP0TCBd_TBE     17
 196 #define CP0TCBd_CurVPE  0
 197     target_ulong CP0_TCHalt;
 198     target_ulong CP0_TCContext;
 199     target_ulong CP0_TCSchedule;
 200     target_ulong CP0_TCScheFBack;
 201     int32_t CP0_Debug_tcstatus;
 202     target_ulong CP0_UserLocal;
 203
 204     int32_t msacsr;
 205
 206 #define MSACSR_FS       24
 207 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 208 #define MSACSR_NX       18
 209 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 210 #define MSACSR_CEF      2
 211 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 212 #define MSACSR_RM       0
 213 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 214 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 215         MSACSR_FS_MASK)
 216
 217     float_status msa_fp_status;
 218 };
 219
 220 typedef struct CPUMIPSState CPUMIPSState;
 221 struct CPUMIPSState {
 222     TCState active_tc;
 223     CPUMIPSFPUContext active_fpu;
 224
 225     uint32_t current_tc;
 226     uint32_t current_fpu;
 227
 228     uint32_t SEGBITS;
 229     uint32_t PABITS;
 230 #if defined(TARGET_MIPS64)
 231 # define PABITS_BASE 36
 232 #else
 233 # define PABITS_BASE 32
 234 #endif
 235     target_ulong SEGMask;
 236     uint64_t PAMask;
 237 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 238
 239     int32_t msair;
 240 #define MSAIR_ProcID    8
 241 #define MSAIR_Rev       0
 242
 243     int32_t CP0_Index;
 244     /* CP0_MVP* are per MVP registers. */
 245     int32_t CP0_VPControl;
 246 #define CP0VPCtl_DIS    0
 247     int32_t CP0_Random;
 248     int32_t CP0_VPEControl;
 249 #define CP0VPECo_YSI    21
 250 #define CP0VPECo_GSI    20
 251 #define CP0VPECo_EXCPT  16
 252 #define CP0VPECo_TE     15
 253 #define CP0VPECo_TargTC 0
 254     int32_t CP0_VPEConf0;
 255 #define CP0VPEC0_M      31
 256 #define CP0VPEC0_XTC    21
 257 #define CP0VPEC0_TCS    19
 258 #define CP0VPEC0_SCS    18
 259 #define CP0VPEC0_DSC    17
 260 #define CP0VPEC0_ICS    16
 261 #define CP0VPEC0_MVP    1
 262 #define CP0VPEC0_VPA    0
 263     int32_t CP0_VPEConf1;
 264 #define CP0VPEC1_NCX    20
 265 #define CP0VPEC1_NCP2   10
 266 #define CP0VPEC1_NCP1   0
 267     target_ulong CP0_YQMask;
 268     target_ulong CP0_VPESchedule;
 269     target_ulong CP0_VPEScheFBack;
 270     int32_t CP0_VPEOpt;
 271 #define CP0VPEOpt_IWX7  15
 272 #define CP0VPEOpt_IWX6  14
 273 #define CP0VPEOpt_IWX5  13
 274 #define CP0VPEOpt_IWX4  12
 275 #define CP0VPEOpt_IWX3  11
 276 #define CP0VPEOpt_IWX2  10
 277 #define CP0VPEOpt_IWX1  9
 278 #define CP0VPEOpt_IWX0  8
 279 #define CP0VPEOpt_DWX7  7
 280 #define CP0VPEOpt_DWX6  6
 281 #define CP0VPEOpt_DWX5  5
 282 #define CP0VPEOpt_DWX4  4
 283 #define CP0VPEOpt_DWX3  3
 284 #define CP0VPEOpt_DWX2  2
 285 #define CP0VPEOpt_DWX1  1
 286 #define CP0VPEOpt_DWX0  0
 287     uint64_t CP0_EntryLo0;
 288     uint64_t CP0_EntryLo1;
 289 #if defined(TARGET_MIPS64)
 290 # define CP0EnLo_RI 63
 291 # define CP0EnLo_XI 62
 292 #else
 293 # define CP0EnLo_RI 31
 294 # define CP0EnLo_XI 30
 295 #endif
 296     int32_t CP0_GlobalNumber;
 297 #define CP0GN_VPId 0
 298     target_ulong CP0_Context;
 299     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 300     int32_t CP0_PageMask;
 301     int32_t CP0_PageGrain_rw_bitmask;
 302     int32_t CP0_PageGrain;
 303 #define CP0PG_RIE 31
 304 #define CP0PG_XIE 30
 305 #define CP0PG_ELPA 29
 306 #define CP0PG_IEC 27
 307     int32_t CP0_Wired;
 308     int32_t CP0_SRSConf0_rw_bitmask;
 309     int32_t CP0_SRSConf0;
 310 #define CP0SRSC0_M      31
 311 #define CP0SRSC0_SRS3   20
 312 #define CP0SRSC0_SRS2   10
 313 #define CP0SRSC0_SRS1   0
 314     int32_t CP0_SRSConf1_rw_bitmask;
 315     int32_t CP0_SRSConf1;
 316 #define CP0SRSC1_M      31
 317 #define CP0SRSC1_SRS6   20
 318 #define CP0SRSC1_SRS5   10
 319 #define CP0SRSC1_SRS4   0
 320     int32_t CP0_SRSConf2_rw_bitmask;
 321     int32_t CP0_SRSConf2;
 322 #define CP0SRSC2_M      31
 323 #define CP0SRSC2_SRS9   20
 324 #define CP0SRSC2_SRS8   10
 325 #define CP0SRSC2_SRS7   0
 326     int32_t CP0_SRSConf3_rw_bitmask;
 327     int32_t CP0_SRSConf3;
 328 #define CP0SRSC3_M      31
 329 #define CP0SRSC3_SRS12  20
 330 #define CP0SRSC3_SRS11  10
 331 #define CP0SRSC3_SRS10  0
 332     int32_t CP0_SRSConf4_rw_bitmask;
 333     int32_t CP0_SRSConf4;
 334 #define CP0SRSC4_SRS15  20
 335 #define CP0SRSC4_SRS14  10
 336 #define CP0SRSC4_SRS13  0
 337     int32_t CP0_HWREna;
 338     target_ulong CP0_BadVAddr;
 339     uint32_t CP0_BadInstr;
 340     uint32_t CP0_BadInstrP;
 341     int32_t CP0_Count;
 342     target_ulong CP0_EntryHi;
 343 #define CP0EnHi_EHINV 10
 344     int32_t CP0_Compare;
 345     int32_t CP0_Status;
 346 #define CP0St_CU3   31
 347 #define CP0St_CU2   30
 348 #define CP0St_CU1   29
 349 #define CP0St_CU0   28
 350 #define CP0St_RP    27
 351 #define CP0St_FR    26
 352 #define CP0St_RE    25
 353 #define CP0St_MX    24
 354 #define CP0St_PX    23
 355 #define CP0St_BEV   22
 356 #define CP0St_TS    21
 357 #define CP0St_SR    20
 358 #define CP0St_NMI   19
 359 #define CP0St_IM    8
 360 #define CP0St_KX    7
 361 #define CP0St_SX    6
 362 #define CP0St_UX    5
 363 #define CP0St_KSU   3
 364 #define CP0St_ERL   2
 365 #define CP0St_EXL   1
 366 #define CP0St_IE    0
 367     int32_t CP0_IntCtl;
 368 #define CP0IntCtl_IPTI 29
 369 #define CP0IntCtl_IPPCI 26
 370 #define CP0IntCtl_VS 5
 371     int32_t CP0_SRSCtl;
 372 #define CP0SRSCtl_HSS 26
 373 #define CP0SRSCtl_EICSS 18
 374 #define CP0SRSCtl_ESS 12
 375 #define CP0SRSCtl_PSS 6
 376 #define CP0SRSCtl_CSS 0
 377     int32_t CP0_SRSMap;
 378 #define CP0SRSMap_SSV7 28
 379 #define CP0SRSMap_SSV6 24
 380 #define CP0SRSMap_SSV5 20
 381 #define CP0SRSMap_SSV4 16
 382 #define CP0SRSMap_SSV3 12
 383 #define CP0SRSMap_SSV2 8
 384 #define CP0SRSMap_SSV1 4
 385 #define CP0SRSMap_SSV0 0
 386     int32_t CP0_Cause;
 387 #define CP0Ca_BD   31
 388 #define CP0Ca_TI   30
 389 #define CP0Ca_CE   28
 390 #define CP0Ca_DC   27
 391 #define CP0Ca_PCI  26
 392 #define CP0Ca_IV   23
 393 #define CP0Ca_WP   22
 394 #define CP0Ca_IP    8
 395 #define CP0Ca_IP_mask 0x0000FF00
 396 #define CP0Ca_EC    2
 397     target_ulong CP0_EPC;
 398     int32_t CP0_PRid;
 399     int32_t CP0_EBase;
 400     target_ulong CP0_CMGCRBase;
 401     int32_t CP0_Config0;
 402 #define CP0C0_M    31
 403 #define CP0C0_K23  28
 404 #define CP0C0_KU   25
 405 #define CP0C0_MDU  20
 406 #define CP0C0_MM   18
 407 #define CP0C0_BM   16
 408 #define CP0C0_BE   15
 409 #define CP0C0_AT   13
 410 #define CP0C0_AR   10
 411 #define CP0C0_MT   7
 412 #define CP0C0_VI   3
 413 #define CP0C0_K0   0
 414     int32_t CP0_Config1;
 415 #define CP0C1_M    31
 416 #define CP0C1_MMU  25
 417 #define CP0C1_IS   22
 418 #define CP0C1_IL   19
 419 #define CP0C1_IA   16
 420 #define CP0C1_DS   13
 421 #define CP0C1_DL   10
 422 #define CP0C1_DA   7
 423 #define CP0C1_C2   6
 424 #define CP0C1_MD   5
 425 #define CP0C1_PC   4
 426 #define CP0C1_WR   3
 427 #define CP0C1_CA   2
 428 #define CP0C1_EP   1
 429 #define CP0C1_FP   0
 430     int32_t CP0_Config2;
 431 #define CP0C2_M    31
 432 #define CP0C2_TU   28
 433 #define CP0C2_TS   24
 434 #define CP0C2_TL   20
 435 #define CP0C2_TA   16
 436 #define CP0C2_SU   12
 437 #define CP0C2_SS   8
 438 #define CP0C2_SL   4
 439 #define CP0C2_SA   0
 440     int32_t CP0_Config3;
 441 #define CP0C3_M    31
 442 #define CP0C3_BPG  30
 443 #define CP0C3_CMGCR 29
 444 #define CP0C3_MSAP  28
 445 #define CP0C3_BP 27
 446 #define CP0C3_BI 26
 447 #define CP0C3_IPLW 21
 448 #define CP0C3_MMAR 18
 449 #define CP0C3_MCU  17
 450 #define CP0C3_ISA_ON_EXC 16
 451 #define CP0C3_ISA  14
 452 #define CP0C3_ULRI 13
 453 #define CP0C3_RXI  12
 454 #define CP0C3_DSP2P 11
 455 #define CP0C3_DSPP 10
 456 #define CP0C3_LPA  7
 457 #define CP0C3_VEIC 6
 458 #define CP0C3_VInt 5
 459 #define CP0C3_SP   4
 460 #define CP0C3_CDMM 3
 461 #define CP0C3_MT   2
 462 #define CP0C3_SM   1
 463 #define CP0C3_TL   0
 464     int32_t CP0_Config4;
 465     int32_t CP0_Config4_rw_bitmask;
 466 #define CP0C4_M    31
 467 #define CP0C4_IE   29
 468 #define CP0C4_KScrExist 16
 469 #define CP0C4_MMUExtDef 14
 470 #define CP0C4_FTLBPageSize 8
 471 #define CP0C4_FTLBWays 4
 472 #define CP0C4_FTLBSets 0
 473 #define CP0C4_MMUSizeExt 0
 474     int32_t CP0_Config5;
 475     int32_t CP0_Config5_rw_bitmask;
 476 #define CP0C5_M          31
 477 #define CP0C5_K          30
 478 #define CP0C5_CV         29
 479 #define CP0C5_EVA        28
 480 #define CP0C5_MSAEn      27
 481 #define CP0C5_XNP        13
 482 #define CP0C5_UFE        9
 483 #define CP0C5_FRE        8
 484 #define CP0C5_VP         7
 485 #define CP0C5_SBRI       6
 486 #define CP0C5_MVH        5
 487 #define CP0C5_LLB        4
 488 #define CP0C5_MRP        3
 489 #define CP0C5_UFR        2
 490 #define CP0C5_NFExists   0
 491     int32_t CP0_Config6;
 492     int32_t CP0_Config7;
 493     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 494     int32_t CP0_MAARI;
 495     /* XXX: Maybe make LLAddr per-TC? */
 496     uint64_t lladdr;
 497     target_ulong llval;
 498     target_ulong llnewval;
 499     target_ulong llreg;
 500     uint64_t CP0_LLAddr_rw_bitmask;
 501     int CP0_LLAddr_shift;
 502     target_ulong CP0_WatchLo[8];
 503     int32_t CP0_WatchHi[8];
 504     target_ulong CP0_XContext;
 505     int32_t CP0_Framemask;
 506     int32_t CP0_Debug;
 507 #define CP0DB_DBD  31
 508 #define CP0DB_DM   30
 509 #define CP0DB_LSNM 28
 510 #define CP0DB_Doze 27
 511 #define CP0DB_Halt 26
 512 #define CP0DB_CNT  25
 513 #define CP0DB_IBEP 24
 514 #define CP0DB_DBEP 21
 515 #define CP0DB_IEXI 20
 516 #define CP0DB_VER  15
 517 #define CP0DB_DEC  10
 518 #define CP0DB_SSt  8
 519 #define CP0DB_DINT 5
 520 #define CP0DB_DIB  4
 521 #define CP0DB_DDBS 3
 522 #define CP0DB_DDBL 2
 523 #define CP0DB_DBp  1
 524 #define CP0DB_DSS  0
 525     target_ulong CP0_DEPC;
 526     int32_t CP0_Performance0;
 527     int32_t CP0_ErrCtl;
 528 #define CP0EC_WST 29
 529 #define CP0EC_SPR 28
 530 #define CP0EC_ITC 26
 531     uint64_t CP0_TagLo;
 532     int32_t CP0_DataLo;
 533     int32_t CP0_TagHi;
 534     int32_t CP0_DataHi;
 535     target_ulong CP0_ErrorEPC;
 536     int32_t CP0_DESAVE;
 537     /* We waste some space so we can handle shadow registers like TCs. */
 538     TCState tcs[MIPS_SHADOW_SET_MAX];
 539     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 540     /* QEMU */
 541     int error_code;
 542 #define EXCP_TLB_NOMATCH   0x1
 543 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 544     uint32_t hflags;    /* CPU State */
 545     /* TMASK defines different execution modes */
 546 #define MIPS_HFLAG_TMASK  0xF5807FF
 547 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 548     /* The KSU flags must be the lowest bits in hflags. The flag order
 549        must be the same as defined for CP0 Status. This allows to use
 550        the bits as the value of mmu_idx. */
 551 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 552 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 553 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 554 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 555 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 556 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 557 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 558 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 559 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 560     /* True if the MIPS IV COP1X instructions can be used.  This also
 561        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 562        and RSQRT.D.  */
 563 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 564 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 565 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 566 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 567 #define MIPS_HFLAG_M16_SHIFT 10
 568     /* If translation is interrupted between the branch instruction and
 569      * the delay slot, record what type of branch it is so that we can
 570      * resume translation properly.  It might be possible to reduce
 571      * this from three bits to two.  */
 572 #define MIPS_HFLAG_BMASK_BASE  0x803800
 573 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 574 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 575 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 576 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 577     /* Extra flags about the current pending branch.  */
 578 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 579 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 580 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 581 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 582 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 583 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 584 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 585     /* MIPS DSP resources access. */
 586 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 587 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 588     /* Extra flag about HWREna register. */
 589 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 590 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 591 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 592 #define MIPS_HFLAG_MSA   0x1000000
 593 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 594 #define MIPS_HFLAG_ELPA  0x4000000
 595 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
 596     target_ulong btarget;        /* Jump / branch target               */
 597     target_ulong bcond;          /* Branch condition (if needed)       */
 598
 599     int SYNCI_Step; /* Address step size for SYNCI */
 600     int CCRes; /* Cycle count resolution/divisor */
 601     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 602     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 603     int insn_flags; /* Supported instruction set */
 604
 605     CPU_COMMON
 606
 607     /* Fields from here on are preserved across CPU reset. */
 608     CPUMIPSMVPContext *mvp;
 609 #if !defined(CONFIG_USER_ONLY)
 610     CPUMIPSTLBContext *tlb;
 611 #endif
 612
 613     const mips_def_t *cpu_model;
 614     void *irq[8];
 615     QEMUTimer *timer; /* Internal timer */
 616     MemoryRegion *itc_tag; /* ITC Configuration Tags */
 617 };
 618
 619 /**
 620  * MIPSCPU:
 621  * @env: #CPUMIPSState
 622  *
 623  * A MIPS CPU.
 624  */
 625 struct MIPSCPU {
 626     /*< private >*/
 627     CPUState parent_obj;
 628     /*< public >*/
 629
 630     CPUMIPSState env;
 631 };
 632
 633 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
 634 {
 635     return container_of(env, MIPSCPU, env);
 636 }
 637
 638 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
 639
 640 #define ENV_OFFSET offsetof(MIPSCPU, env)
 641
 642 #ifndef CONFIG_USER_ONLY
 643 extern const struct VMStateDescription vmstate_mips_cpu;
 644 #endif
 645
 646 void mips_cpu_do_interrupt(CPUState *cpu);
 647 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 648 void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 649                          int flags);
 650 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 651 int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 652 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 653 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 654                                   int is_write, int is_user, uintptr_t retaddr);
 655
 656 #if !defined(CONFIG_USER_ONLY)
 657 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 658                         target_ulong address, int rw, int access_type);
 659 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 660                            target_ulong address, int rw, int access_type);
 661 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 662                      target_ulong address, int rw, int access_type);
 663 void r4k_helper_tlbwi(CPUMIPSState *env);
 664 void r4k_helper_tlbwr(CPUMIPSState *env);
 665 void r4k_helper_tlbp(CPUMIPSState *env);
 666 void r4k_helper_tlbr(CPUMIPSState *env);
 667 void r4k_helper_tlbinv(CPUMIPSState *env);
 668 void r4k_helper_tlbinvf(CPUMIPSState *env);
 669
 670 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 671                                 bool is_write, bool is_exec, int unused,
 672                                 unsigned size);
 673 #endif
 674
 675 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 676
 677 #define cpu_exec cpu_mips_exec
 678 #define cpu_signal_handler cpu_mips_signal_handler
 679 #define cpu_list mips_cpu_list
 680
 681 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 682 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 683
 684 /* MMU modes definitions. We carefully match the indices with our
 685    hflags layout. */
 686 #define MMU_MODE0_SUFFIX _kernel
 687 #define MMU_MODE1_SUFFIX _super
 688 #define MMU_MODE2_SUFFIX _user
 689 #define MMU_USER_IDX 2
 690 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 691 {
 692     return env->hflags & MIPS_HFLAG_KSU;
 693 }
 694
 695 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 696 {
 697     return (env->CP0_Status & (1 << CP0St_IE)) &&
 698         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 699         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 700         !(env->hflags & MIPS_HFLAG_DM) &&
 701         /* Note that the TCStatus IXMT field is initialized to zero,
 702            and only MT capable cores can set it to one. So we don't
 703            need to check for MT capabilities here.  */
 704         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 705 }
 706
 707 /* Check if there is pending and not masked out interrupt */
 708 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 709 {
 710     int32_t pending;
 711     int32_t status;
 712     bool r;
 713
 714     pending = env->CP0_Cause & CP0Ca_IP_mask;
 715     status = env->CP0_Status & CP0Ca_IP_mask;
 716
 717     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 718         /* A MIPS configured with a vectorizing external interrupt controller
 719            will feed a vector into the Cause pending lines. The core treats
 720            the status lines as a vector level, not as indiviual masks.  */
 721         r = pending > status;
 722     } else {
 723         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 724            treats the pending lines as individual interrupt lines, the status
 725            lines are individual masks.  */
 726         r = (pending & status) != 0;
 727     }
 728     return r;
 729 }
 730
 731 #include "exec/cpu-all.h"
 732
 733 /* Memory access type :
 734  * may be needed for precise access rights control and precise exceptions.
 735  */
 736 enum {
 737     /* 1 bit to define user level / supervisor access */
 738     ACCESS_USER  = 0x00,
 739     ACCESS_SUPER = 0x01,
 740     /* 1 bit to indicate direction */
 741     ACCESS_STORE = 0x02,
 742     /* Type of instruction that generated the access */
 743     ACCESS_CODE  = 0x10, /* Code fetch access                */
 744     ACCESS_INT   = 0x20, /* Integer load/store access        */
 745     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 746 };
 747
 748 /* Exceptions */
 749 enum {
 750     EXCP_NONE          = -1,
 751     EXCP_RESET         = 0,
 752     EXCP_SRESET,
 753     EXCP_DSS,
 754     EXCP_DINT,
 755     EXCP_DDBL,
 756     EXCP_DDBS,
 757     EXCP_NMI,
 758     EXCP_MCHECK,
 759     EXCP_EXT_INTERRUPT, /* 8 */
 760     EXCP_DFWATCH,
 761     EXCP_DIB,
 762     EXCP_IWATCH,
 763     EXCP_AdEL,
 764     EXCP_AdES,
 765     EXCP_TLBF,
 766     EXCP_IBE,
 767     EXCP_DBp, /* 16 */
 768     EXCP_SYSCALL,
 769     EXCP_BREAK,
 770     EXCP_CpU,
 771     EXCP_RI,
 772     EXCP_OVERFLOW,
 773     EXCP_TRAP,
 774     EXCP_FPE,
 775     EXCP_DWATCH, /* 24 */
 776     EXCP_LTLBL,
 777     EXCP_TLBL,
 778     EXCP_TLBS,
 779     EXCP_DBE,
 780     EXCP_THREAD,
 781     EXCP_MDMX,
 782     EXCP_C2E,
 783     EXCP_CACHE, /* 32 */
 784     EXCP_DSPDIS,
 785     EXCP_MSADIS,
 786     EXCP_MSAFPE,
 787     EXCP_TLBXI,
 788     EXCP_TLBRI,
 789
 790     EXCP_LAST = EXCP_TLBRI,
 791 };
 792 /* Dummy exception for conditional stores.  */
 793 #define EXCP_SC 0x100
 794
 795 /*
 796  * This is an interrnally generated WAKE request line.
 797  * It is driven by the CPU itself. Raised when the MT
 798  * block wants to wake a VPE from an inactive state and
 799  * cleared when VPE goes from active to inactive.
 800  */
 801 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 802
 803 int cpu_mips_exec(CPUState *cpu);
 804 void mips_tcg_init(void);
 805 MIPSCPU *cpu_mips_init(const char *cpu_model);
 806 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 807
 808 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
 809 bool cpu_supports_cps_smp(const char *cpu_model);
 810
 811 /* TODO QOM'ify CPU reset and remove */
 812 void cpu_state_reset(CPUMIPSState *s);
 813
 814 /* mips_timer.c */
 815 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 816 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 817 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 818 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 819 void cpu_mips_start_count(CPUMIPSState *env);
 820 void cpu_mips_stop_count(CPUMIPSState *env);
 821
 822 /* mips_int.c */
 823 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 824
 825 /* helper.c */
 826 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 827                               int mmu_idx);
 828 #if !defined(CONFIG_USER_ONLY)
 829 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 830 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 831                                                int rw);
 832 #endif
 833 target_ulong exception_resume_pc (CPUMIPSState *env);
 834
 835 /* op_helper.c */
 836 extern unsigned int ieee_rm[];
 837 int ieee_ex_to_mips(int xcpt);
 838
 839 static inline void restore_rounding_mode(CPUMIPSState *env)
 840 {
 841     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 842                             &env->active_fpu.fp_status);
 843 }
 844
 845 static inline void restore_flush_mode(CPUMIPSState *env)
 846 {
 847     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
 848                       &env->active_fpu.fp_status);
 849 }
 850
 851 static inline void restore_fp_status(CPUMIPSState *env)
 852 {
 853     restore_rounding_mode(env);
 854     restore_flush_mode(env);
 855 }
 856
 857 static inline void restore_msa_fp_status(CPUMIPSState *env)
 858 {
 859     float_status *status = &env->active_tc.msa_fp_status;
 860     int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 861     bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 862
 863     set_float_rounding_mode(ieee_rm[rounding_mode], status);
 864     set_flush_to_zero(flush_to_zero, status);
 865     set_flush_inputs_to_zero(flush_to_zero, status);
 866 }
 867
 868 static inline void restore_pamask(CPUMIPSState *env)
 869 {
 870     if (env->hflags & MIPS_HFLAG_ELPA) {
 871         env->PAMask = (1ULL << env->PABITS) - 1;
 872     } else {
 873         env->PAMask = PAMASK_BASE;
 874     }
 875 }
 876
 877 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 878                                         target_ulong *cs_base, uint32_t *flags)
 879 {
 880     *pc = env->active_tc.PC;
 881     *cs_base = 0;
 882     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 883                             MIPS_HFLAG_HWRENA_ULR);
 884 }
 885
 886 static inline int mips_vpe_active(CPUMIPSState *env)
 887 {
 888     int active = 1;
 889
 890     /* Check that the VPE is enabled.  */
 891     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 892         active = 0;
 893     }
 894     /* Check that the VPE is activated.  */
 895     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 896         active = 0;
 897     }
 898
 899     /* Now verify that there are active thread contexts in the VPE.
 900
 901        This assumes the CPU model will internally reschedule threads
 902        if the active one goes to sleep. If there are no threads available
 903        the active one will be in a sleeping state, and we can turn off
 904        the entire VPE.  */
 905     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 906         /* TC is not activated.  */
 907         active = 0;
 908     }
 909     if (env->active_tc.CP0_TCHalt & 1) {
 910         /* TC is in halt state.  */
 911         active = 0;
 912     }
 913
 914     return active;
 915 }
 916
 917 static inline int mips_vp_active(CPUMIPSState *env)
 918 {
 919     CPUState *other_cs = first_cpu;
 920
 921     /* Check if the VP disabled other VPs (which means the VP is enabled) */
 922     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 923         return 1;
 924     }
 925
 926     /* Check if the virtual processor is disabled due to a DVP */
 927     CPU_FOREACH(other_cs) {
 928         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 929         if ((&other_cpu->env != env) &&
 930             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 931             return 0;
 932         }
 933     }
 934     return 1;
 935 }
 936
 937 static inline void compute_hflags(CPUMIPSState *env)
 938 {
 939     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 940                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 941                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 942                      MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
 943                      MIPS_HFLAG_ELPA);
 944     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 945         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 946         !(env->hflags & MIPS_HFLAG_DM)) {
 947         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 948     }
 949 #if defined(TARGET_MIPS64)
 950     if ((env->insn_flags & ISA_MIPS3) &&
 951         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 952          (env->CP0_Status & (1 << CP0St_PX)) ||
 953          (env->CP0_Status & (1 << CP0St_UX)))) {
 954         env->hflags |= MIPS_HFLAG_64;
 955     }
 956
 957     if (!(env->insn_flags & ISA_MIPS3)) {
 958         env->hflags |= MIPS_HFLAG_AWRAP;
 959     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 960                !(env->CP0_Status & (1 << CP0St_UX))) {
 961         env->hflags |= MIPS_HFLAG_AWRAP;
 962     } else if (env->insn_flags & ISA_MIPS64R6) {
 963         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 964         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 965              !(env->CP0_Status & (1 << CP0St_SX))) ||
 966             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 967              !(env->CP0_Status & (1 << CP0St_KX)))) {
 968             env->hflags |= MIPS_HFLAG_AWRAP;
 969         }
 970     }
 971 #endif
 972     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 973          !(env->insn_flags & ISA_MIPS32R6)) ||
 974         !(env->hflags & MIPS_HFLAG_KSU)) {
 975         env->hflags |= MIPS_HFLAG_CP0;
 976     }
 977     if (env->CP0_Status & (1 << CP0St_CU1)) {
 978         env->hflags |= MIPS_HFLAG_FPU;
 979     }
 980     if (env->CP0_Status & (1 << CP0St_FR)) {
 981         env->hflags |= MIPS_HFLAG_F64;
 982     }
 983     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 984         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 985         env->hflags |= MIPS_HFLAG_SBRI;
 986     }
 987     if (env->insn_flags & ASE_DSPR2) {
 988         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 989            so enable to access DSPR2 resources. */
 990         if (env->CP0_Status & (1 << CP0St_MX)) {
 991             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 992         }
 993
 994     } else if (env->insn_flags & ASE_DSP) {
 995         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 996            so enable to access DSP resources. */
 997         if (env->CP0_Status & (1 << CP0St_MX)) {
 998             env->hflags |= MIPS_HFLAG_DSP;
 999         }
1000
1001     }
1002     if (env->insn_flags & ISA_MIPS32R2) {
1003         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
1004             env->hflags |= MIPS_HFLAG_COP1X;
1005         }
1006     } else if (env->insn_flags & ISA_MIPS32) {
1007         if (env->hflags & MIPS_HFLAG_64) {
1008             env->hflags |= MIPS_HFLAG_COP1X;
1009         }
1010     } else if (env->insn_flags & ISA_MIPS4) {
1011         /* All supported MIPS IV CPUs use the XX (CU3) to enable
1012            and disable the MIPS IV extensions to the MIPS III ISA.
1013            Some other MIPS IV CPUs ignore the bit, so the check here
1014            would be too restrictive for them.  */
1015         if (env->CP0_Status & (1U << CP0St_CU3)) {
1016             env->hflags |= MIPS_HFLAG_COP1X;
1017         }
1018     }
1019     if (env->insn_flags & ASE_MSA) {
1020         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
1021             env->hflags |= MIPS_HFLAG_MSA;
1022         }
1023     }
1024     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
1025         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
1026             env->hflags |= MIPS_HFLAG_FRE;
1027         }
1028     }
1029     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
1030         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
1031             env->hflags |= MIPS_HFLAG_ELPA;
1032         }
1033     }
1034 }
1035
1036 void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global);
1037 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
1038 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
1039 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
1040
1041 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
1042                                           int error_code, uintptr_t pc);
1043
1044 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
1045                                                     uint32_t exception,
1046                                                     uintptr_t pc)
1047 {
1048     do_raise_exception_err(env, exception, 0, pc);
1049 }
1050
1051 #endif /* !defined (__MIPS_CPU_H__) */