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target/ppc: Split out gen_load_locked
[qemu/rayw.git] / target / ppc / translate.c
blobf48fcbeefbfb27193af71245a0a4d2f7cf6aab54
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/translator.h"
35 #include "exec/log.h"
36
37
38 #define CPU_SINGLE_STEP 0x1
39 #define CPU_BRANCH_STEP 0x2
40 #define GDBSTUB_SINGLE_STEP 0x4
41
42 /* Include definitions for instructions classes and implementations flags */
43 //#define PPC_DEBUG_DISAS
44 //#define DO_PPC_STATISTICS
45
46 #ifdef PPC_DEBUG_DISAS
47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 #else
49 # define LOG_DISAS(...) do { } while (0)
50 #endif
51 /*****************************************************************************/
52 /* Code translation helpers */
53
54 /* global register indexes */
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 snprintf(p, cpu_reg_names_size, "r%dH", i);
106 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gprh[i]), p);
108 p += (i < 10) ? 4 : 5;
109 cpu_reg_names_size -= (i < 10) ? 4 : 5;
110
111 snprintf(p, cpu_reg_names_size, "fp%d", i);
112 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
113 offsetof(CPUPPCState, fpr[i]), p);
114 p += (i < 10) ? 4 : 5;
115 cpu_reg_names_size -= (i < 10) ? 4 : 5;
116
117 snprintf(p, cpu_reg_names_size, "avr%dH", i);
118 #ifdef HOST_WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, avr[i].u64[0]), p);
121 #else
122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
123 offsetof(CPUPPCState, avr[i].u64[1]), p);
124 #endif
125 p += (i < 10) ? 6 : 7;
126 cpu_reg_names_size -= (i < 10) ? 6 : 7;
127
128 snprintf(p, cpu_reg_names_size, "avr%dL", i);
129 #ifdef HOST_WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
131 offsetof(CPUPPCState, avr[i].u64[1]), p);
132 #else
133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
134 offsetof(CPUPPCState, avr[i].u64[0]), p);
135 #endif
136 p += (i < 10) ? 6 : 7;
137 cpu_reg_names_size -= (i < 10) ? 6 : 7;
138 snprintf(p, cpu_reg_names_size, "vsr%d", i);
139 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
140 offsetof(CPUPPCState, vsr[i]), p);
141 p += (i < 10) ? 5 : 6;
142 cpu_reg_names_size -= (i < 10) ? 5 : 6;
143 }
144
145 cpu_nip = tcg_global_mem_new(cpu_env,
146 offsetof(CPUPPCState, nip), "nip");
147
148 cpu_msr = tcg_global_mem_new(cpu_env,
149 offsetof(CPUPPCState, msr), "msr");
150
151 cpu_ctr = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, ctr), "ctr");
153
154 cpu_lr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, lr), "lr");
156
157 #if defined(TARGET_PPC64)
158 cpu_cfar = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, cfar), "cfar");
160 #endif
161
162 cpu_xer = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, xer), "xer");
164 cpu_so = tcg_global_mem_new(cpu_env,
165 offsetof(CPUPPCState, so), "SO");
166 cpu_ov = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, ov), "OV");
168 cpu_ca = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, ca), "CA");
170 cpu_ov32 = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov32), "OV32");
172 cpu_ca32 = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca32), "CA32");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178 cpu_reserve_val = tcg_global_mem_new(cpu_env,
179 offsetof(CPUPPCState, reserve_val),
180 "reserve_val");
181
182 cpu_fpscr = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, fpscr), "fpscr");
184
185 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
186 offsetof(CPUPPCState, access_type), "access_type");
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 DisasContextBase base;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv, dr, le_mode;
196 bool lazy_tlb_flush;
197 bool need_access_type;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 bool gtse;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->base.pc_next - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->base.pc_next - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->base.pc_next);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->base.pc_next);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
380 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
381
382 typedef struct opcode_t {
383 unsigned char opc1, opc2, opc3, opc4;
384 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
385 unsigned char pad[4];
386 #endif
387 opc_handler_t handler;
388 const char *oname;
389 } opcode_t;
390
391 /* Helpers for priv. check */
392 #define GEN_PRIV \
393 do { \
394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
395 } while (0)
396
397 #if defined(CONFIG_USER_ONLY)
398 #define CHK_HV GEN_PRIV
399 #define CHK_SV GEN_PRIV
400 #define CHK_HVRM GEN_PRIV
401 #else
402 #define CHK_HV \
403 do { \
404 if (unlikely(ctx->pr || !ctx->hv)) { \
405 GEN_PRIV; \
406 } \
407 } while (0)
408 #define CHK_SV \
409 do { \
410 if (unlikely(ctx->pr)) { \
411 GEN_PRIV; \
412 } \
413 } while (0)
414 #define CHK_HVRM \
415 do { \
416 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
417 GEN_PRIV; \
418 } \
419 } while (0)
420 #endif
421
422 #define CHK_NONE
423
424 /*****************************************************************************/
425 /* PowerPC instructions table */
426
427 #if defined(DO_PPC_STATISTICS)
428 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
429 { \
430 .opc1 = op1, \
431 .opc2 = op2, \
432 .opc3 = op3, \
433 .opc4 = 0xff, \
434 .handler = { \
435 .inval1 = invl, \
436 .type = _typ, \
437 .type2 = _typ2, \
438 .handler = &gen_##name, \
439 .oname = stringify(name), \
440 }, \
441 .oname = stringify(name), \
442 }
443 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
444 { \
445 .opc1 = op1, \
446 .opc2 = op2, \
447 .opc3 = op3, \
448 .opc4 = 0xff, \
449 .handler = { \
450 .inval1 = invl1, \
451 .inval2 = invl2, \
452 .type = _typ, \
453 .type2 = _typ2, \
454 .handler = &gen_##name, \
455 .oname = stringify(name), \
456 }, \
457 .oname = stringify(name), \
458 }
459 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
460 { \
461 .opc1 = op1, \
462 .opc2 = op2, \
463 .opc3 = op3, \
464 .opc4 = 0xff, \
465 .handler = { \
466 .inval1 = invl, \
467 .type = _typ, \
468 .type2 = _typ2, \
469 .handler = &gen_##name, \
470 .oname = onam, \
471 }, \
472 .oname = onam, \
473 }
474 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
475 { \
476 .opc1 = op1, \
477 .opc2 = op2, \
478 .opc3 = op3, \
479 .opc4 = op4, \
480 .handler = { \
481 .inval1 = invl, \
482 .type = _typ, \
483 .type2 = _typ2, \
484 .handler = &gen_##name, \
485 .oname = stringify(name), \
486 }, \
487 .oname = stringify(name), \
488 }
489 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
490 { \
491 .opc1 = op1, \
492 .opc2 = op2, \
493 .opc3 = op3, \
494 .opc4 = op4, \
495 .handler = { \
496 .inval1 = invl, \
497 .type = _typ, \
498 .type2 = _typ2, \
499 .handler = &gen_##name, \
500 .oname = onam, \
501 }, \
502 .oname = onam, \
503 }
504 #else
505 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
506 { \
507 .opc1 = op1, \
508 .opc2 = op2, \
509 .opc3 = op3, \
510 .opc4 = 0xff, \
511 .handler = { \
512 .inval1 = invl, \
513 .type = _typ, \
514 .type2 = _typ2, \
515 .handler = &gen_##name, \
516 }, \
517 .oname = stringify(name), \
518 }
519 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .opc4 = 0xff, \
525 .handler = { \
526 .inval1 = invl1, \
527 .inval2 = invl2, \
528 .type = _typ, \
529 .type2 = _typ2, \
530 .handler = &gen_##name, \
531 }, \
532 .oname = stringify(name), \
533 }
534 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
535 { \
536 .opc1 = op1, \
537 .opc2 = op2, \
538 .opc3 = op3, \
539 .opc4 = 0xff, \
540 .handler = { \
541 .inval1 = invl, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = onam, \
547 }
548 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
549 { \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .opc4 = op4, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = stringify(name), \
561 }
562 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
563 { \
564 .opc1 = op1, \
565 .opc2 = op2, \
566 .opc3 = op3, \
567 .opc4 = op4, \
568 .handler = { \
569 .inval1 = invl, \
570 .type = _typ, \
571 .type2 = _typ2, \
572 .handler = &gen_##name, \
573 }, \
574 .oname = onam, \
575 }
576 #endif
577
578 /* SPR load/store helpers */
579 static inline void gen_load_spr(TCGv t, int reg)
580 {
581 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
582 }
583
584 static inline void gen_store_spr(int reg, TCGv t)
585 {
586 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
587 }
588
589 /* Invalid instruction */
590 static void gen_invalid(DisasContext *ctx)
591 {
592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
593 }
594
595 static opc_handler_t invalid_handler = {
596 .inval1 = 0xFFFFFFFF,
597 .inval2 = 0xFFFFFFFF,
598 .type = PPC_NONE,
599 .type2 = PPC_NONE,
600 .handler = gen_invalid,
601 };
602
603 /*** Integer comparison ***/
604
605 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
606 {
607 TCGv t0 = tcg_temp_new();
608 TCGv t1 = tcg_temp_new();
609 TCGv_i32 t = tcg_temp_new_i32();
610
611 tcg_gen_movi_tl(t0, CRF_EQ);
612 tcg_gen_movi_tl(t1, CRF_LT);
613 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0);
614 tcg_gen_movi_tl(t1, CRF_GT);
615 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0);
616
617 tcg_gen_trunc_tl_i32(t, t0);
618 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
619 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
620
621 tcg_temp_free(t0);
622 tcg_temp_free(t1);
623 tcg_temp_free_i32(t);
624 }
625
626 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
627 {
628 TCGv t0 = tcg_const_tl(arg1);
629 gen_op_cmp(arg0, t0, s, crf);
630 tcg_temp_free(t0);
631 }
632
633 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
634 {
635 TCGv t0, t1;
636 t0 = tcg_temp_new();
637 t1 = tcg_temp_new();
638 if (s) {
639 tcg_gen_ext32s_tl(t0, arg0);
640 tcg_gen_ext32s_tl(t1, arg1);
641 } else {
642 tcg_gen_ext32u_tl(t0, arg0);
643 tcg_gen_ext32u_tl(t1, arg1);
644 }
645 gen_op_cmp(t0, t1, s, crf);
646 tcg_temp_free(t1);
647 tcg_temp_free(t0);
648 }
649
650 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
651 {
652 TCGv t0 = tcg_const_tl(arg1);
653 gen_op_cmp32(arg0, t0, s, crf);
654 tcg_temp_free(t0);
655 }
656
657 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
658 {
659 if (NARROW_MODE(ctx)) {
660 gen_op_cmpi32(reg, 0, 1, 0);
661 } else {
662 gen_op_cmpi(reg, 0, 1, 0);
663 }
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
670 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
671 1, crfD(ctx->opcode));
672 } else {
673 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
674 1, crfD(ctx->opcode));
675 }
676 }
677
678 /* cmpi */
679 static void gen_cmpi(DisasContext *ctx)
680 {
681 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
682 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
683 1, crfD(ctx->opcode));
684 } else {
685 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
686 1, crfD(ctx->opcode));
687 }
688 }
689
690 /* cmpl */
691 static void gen_cmpl(DisasContext *ctx)
692 {
693 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
694 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
695 0, crfD(ctx->opcode));
696 } else {
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 }
700 }
701
702 /* cmpli */
703 static void gen_cmpli(DisasContext *ctx)
704 {
705 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
706 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 } else {
709 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
710 0, crfD(ctx->opcode));
711 }
712 }
713
714 /* cmprb - range comparison: isupper, isaplha, islower*/
715 static void gen_cmprb(DisasContext *ctx)
716 {
717 TCGv_i32 src1 = tcg_temp_new_i32();
718 TCGv_i32 src2 = tcg_temp_new_i32();
719 TCGv_i32 src2lo = tcg_temp_new_i32();
720 TCGv_i32 src2hi = tcg_temp_new_i32();
721 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
722
723 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
724 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
725
726 tcg_gen_andi_i32(src1, src1, 0xFF);
727 tcg_gen_ext8u_i32(src2lo, src2);
728 tcg_gen_shri_i32(src2, src2, 8);
729 tcg_gen_ext8u_i32(src2hi, src2);
730
731 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
732 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
733 tcg_gen_and_i32(crf, src2lo, src2hi);
734
735 if (ctx->opcode & 0x00200000) {
736 tcg_gen_shri_i32(src2, src2, 8);
737 tcg_gen_ext8u_i32(src2lo, src2);
738 tcg_gen_shri_i32(src2, src2, 8);
739 tcg_gen_ext8u_i32(src2hi, src2);
740 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
741 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
742 tcg_gen_and_i32(src2lo, src2lo, src2hi);
743 tcg_gen_or_i32(crf, crf, src2lo);
744 }
745 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
746 tcg_temp_free_i32(src1);
747 tcg_temp_free_i32(src2);
748 tcg_temp_free_i32(src2lo);
749 tcg_temp_free_i32(src2hi);
750 }
751
752 #if defined(TARGET_PPC64)
753 /* cmpeqb */
754 static void gen_cmpeqb(DisasContext *ctx)
755 {
756 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
757 cpu_gpr[rB(ctx->opcode)]);
758 }
759 #endif
760
761 /* isel (PowerPC 2.03 specification) */
762 static void gen_isel(DisasContext *ctx)
763 {
764 uint32_t bi = rC(ctx->opcode);
765 uint32_t mask = 0x08 >> (bi & 0x03);
766 TCGv t0 = tcg_temp_new();
767 TCGv zr;
768
769 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
770 tcg_gen_andi_tl(t0, t0, mask);
771
772 zr = tcg_const_tl(0);
773 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
774 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
775 cpu_gpr[rB(ctx->opcode)]);
776 tcg_temp_free(zr);
777 tcg_temp_free(t0);
778 }
779
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext *ctx)
782 {
783 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
784 cpu_gpr[rB(ctx->opcode)]);
785 }
786
787 /*** Integer arithmetic ***/
788
789 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
790 TCGv arg1, TCGv arg2, int sub)
791 {
792 TCGv t0 = tcg_temp_new();
793
794 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
795 tcg_gen_xor_tl(t0, arg1, arg2);
796 if (sub) {
797 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
798 } else {
799 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
800 }
801 tcg_temp_free(t0);
802 if (NARROW_MODE(ctx)) {
803 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
804 if (is_isa300(ctx)) {
805 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
806 }
807 } else {
808 if (is_isa300(ctx)) {
809 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
810 }
811 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
812 }
813 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
814 }
815
816 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
817 TCGv res, TCGv arg0, TCGv arg1,
818 int sub)
819 {
820 TCGv t0;
821
822 if (!is_isa300(ctx)) {
823 return;
824 }
825
826 t0 = tcg_temp_new();
827 if (sub) {
828 tcg_gen_eqv_tl(t0, arg0, arg1);
829 } else {
830 tcg_gen_xor_tl(t0, arg0, arg1);
831 }
832 tcg_gen_xor_tl(t0, t0, res);
833 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
834 tcg_temp_free(t0);
835 }
836
837 /* Common add function */
838 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
839 TCGv arg2, bool add_ca, bool compute_ca,
840 bool compute_ov, bool compute_rc0)
841 {
842 TCGv t0 = ret;
843
844 if (compute_ca || compute_ov) {
845 t0 = tcg_temp_new();
846 }
847
848 if (compute_ca) {
849 if (NARROW_MODE(ctx)) {
850 /* Caution: a non-obvious corner case of the spec is that we
851 must produce the *entire* 64-bit addition, but produce the
852 carry into bit 32. */
853 TCGv t1 = tcg_temp_new();
854 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
855 tcg_gen_add_tl(t0, arg1, arg2);
856 if (add_ca) {
857 tcg_gen_add_tl(t0, t0, cpu_ca);
858 }
859 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
860 tcg_temp_free(t1);
861 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
862 if (is_isa300(ctx)) {
863 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
864 }
865 } else {
866 TCGv zero = tcg_const_tl(0);
867 if (add_ca) {
868 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
869 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
870 } else {
871 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
872 }
873 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
874 tcg_temp_free(zero);
875 }
876 } else {
877 tcg_gen_add_tl(t0, arg1, arg2);
878 if (add_ca) {
879 tcg_gen_add_tl(t0, t0, cpu_ca);
880 }
881 }
882
883 if (compute_ov) {
884 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
885 }
886 if (unlikely(compute_rc0)) {
887 gen_set_Rc0(ctx, t0);
888 }
889
890 if (t0 != ret) {
891 tcg_gen_mov_tl(ret, t0);
892 tcg_temp_free(t0);
893 }
894 }
895 /* Add functions with two operands */
896 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
898 { \
899 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
900 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
901 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
902 }
903 /* Add functions with one operand and one immediate */
904 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
905 add_ca, compute_ca, compute_ov) \
906 static void glue(gen_, name)(DisasContext *ctx) \
907 { \
908 TCGv t0 = tcg_const_tl(const_val); \
909 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
910 cpu_gpr[rA(ctx->opcode)], t0, \
911 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
912 tcg_temp_free(t0); \
913 }
914
915 /* add add. addo addo. */
916 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
917 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
918 /* addc addc. addco addco. */
919 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
920 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
921 /* adde adde. addeo addeo. */
922 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
923 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
924 /* addme addme. addmeo addmeo. */
925 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
926 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
927 /* addze addze. addzeo addzeo.*/
928 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
929 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
930 /* addi */
931 static void gen_addi(DisasContext *ctx)
932 {
933 target_long simm = SIMM(ctx->opcode);
934
935 if (rA(ctx->opcode) == 0) {
936 /* li case */
937 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
938 } else {
939 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
940 cpu_gpr[rA(ctx->opcode)], simm);
941 }
942 }
943 /* addic addic.*/
944 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
945 {
946 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
947 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
948 c, 0, 1, 0, compute_rc0);
949 tcg_temp_free(c);
950 }
951
952 static void gen_addic(DisasContext *ctx)
953 {
954 gen_op_addic(ctx, 0);
955 }
956
957 static void gen_addic_(DisasContext *ctx)
958 {
959 gen_op_addic(ctx, 1);
960 }
961
962 /* addis */
963 static void gen_addis(DisasContext *ctx)
964 {
965 target_long simm = SIMM(ctx->opcode);
966
967 if (rA(ctx->opcode) == 0) {
968 /* lis case */
969 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
970 } else {
971 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
972 cpu_gpr[rA(ctx->opcode)], simm << 16);
973 }
974 }
975
976 /* addpcis */
977 static void gen_addpcis(DisasContext *ctx)
978 {
979 target_long d = DX(ctx->opcode);
980
981 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
982 }
983
984 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
985 TCGv arg2, int sign, int compute_ov)
986 {
987 TCGv_i32 t0 = tcg_temp_new_i32();
988 TCGv_i32 t1 = tcg_temp_new_i32();
989 TCGv_i32 t2 = tcg_temp_new_i32();
990 TCGv_i32 t3 = tcg_temp_new_i32();
991
992 tcg_gen_trunc_tl_i32(t0, arg1);
993 tcg_gen_trunc_tl_i32(t1, arg2);
994 if (sign) {
995 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
996 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
997 tcg_gen_and_i32(t2, t2, t3);
998 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
999 tcg_gen_or_i32(t2, t2, t3);
1000 tcg_gen_movi_i32(t3, 0);
1001 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1002 tcg_gen_div_i32(t3, t0, t1);
1003 tcg_gen_extu_i32_tl(ret, t3);
1004 } else {
1005 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1006 tcg_gen_movi_i32(t3, 0);
1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1008 tcg_gen_divu_i32(t3, t0, t1);
1009 tcg_gen_extu_i32_tl(ret, t3);
1010 }
1011 if (compute_ov) {
1012 tcg_gen_extu_i32_tl(cpu_ov, t2);
1013 if (is_isa300(ctx)) {
1014 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1015 }
1016 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1017 }
1018 tcg_temp_free_i32(t0);
1019 tcg_temp_free_i32(t1);
1020 tcg_temp_free_i32(t2);
1021 tcg_temp_free_i32(t3);
1022
1023 if (unlikely(Rc(ctx->opcode) != 0))
1024 gen_set_Rc0(ctx, ret);
1025 }
1026 /* Div functions */
1027 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1028 static void glue(gen_, name)(DisasContext *ctx) \
1029 { \
1030 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1031 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1032 sign, compute_ov); \
1033 }
1034 /* divwu divwu. divwuo divwuo. */
1035 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1036 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1037 /* divw divw. divwo divwo. */
1038 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1039 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1040
1041 /* div[wd]eu[o][.] */
1042 #define GEN_DIVE(name, hlpr, compute_ov) \
1043 static void gen_##name(DisasContext *ctx) \
1044 { \
1045 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1046 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1047 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1048 tcg_temp_free_i32(t0); \
1049 if (unlikely(Rc(ctx->opcode) != 0)) { \
1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1051 } \
1052 }
1053
1054 GEN_DIVE(divweu, divweu, 0);
1055 GEN_DIVE(divweuo, divweu, 1);
1056 GEN_DIVE(divwe, divwe, 0);
1057 GEN_DIVE(divweo, divwe, 1);
1058
1059 #if defined(TARGET_PPC64)
1060 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1061 TCGv arg2, int sign, int compute_ov)
1062 {
1063 TCGv_i64 t0 = tcg_temp_new_i64();
1064 TCGv_i64 t1 = tcg_temp_new_i64();
1065 TCGv_i64 t2 = tcg_temp_new_i64();
1066 TCGv_i64 t3 = tcg_temp_new_i64();
1067
1068 tcg_gen_mov_i64(t0, arg1);
1069 tcg_gen_mov_i64(t1, arg2);
1070 if (sign) {
1071 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1072 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1073 tcg_gen_and_i64(t2, t2, t3);
1074 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1075 tcg_gen_or_i64(t2, t2, t3);
1076 tcg_gen_movi_i64(t3, 0);
1077 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1078 tcg_gen_div_i64(ret, t0, t1);
1079 } else {
1080 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1081 tcg_gen_movi_i64(t3, 0);
1082 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1083 tcg_gen_divu_i64(ret, t0, t1);
1084 }
1085 if (compute_ov) {
1086 tcg_gen_mov_tl(cpu_ov, t2);
1087 if (is_isa300(ctx)) {
1088 tcg_gen_mov_tl(cpu_ov32, t2);
1089 }
1090 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1091 }
1092 tcg_temp_free_i64(t0);
1093 tcg_temp_free_i64(t1);
1094 tcg_temp_free_i64(t2);
1095 tcg_temp_free_i64(t3);
1096
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, ret);
1099 }
1100
1101 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1102 static void glue(gen_, name)(DisasContext *ctx) \
1103 { \
1104 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1105 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1106 sign, compute_ov); \
1107 }
1108 /* divdu divdu. divduo divduo. */
1109 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1110 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1111 /* divd divd. divdo divdo. */
1112 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1113 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1114
1115 GEN_DIVE(divdeu, divdeu, 0);
1116 GEN_DIVE(divdeuo, divdeu, 1);
1117 GEN_DIVE(divde, divde, 0);
1118 GEN_DIVE(divdeo, divde, 1);
1119 #endif
1120
1121 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1122 TCGv arg2, int sign)
1123 {
1124 TCGv_i32 t0 = tcg_temp_new_i32();
1125 TCGv_i32 t1 = tcg_temp_new_i32();
1126
1127 tcg_gen_trunc_tl_i32(t0, arg1);
1128 tcg_gen_trunc_tl_i32(t1, arg2);
1129 if (sign) {
1130 TCGv_i32 t2 = tcg_temp_new_i32();
1131 TCGv_i32 t3 = tcg_temp_new_i32();
1132 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1133 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1134 tcg_gen_and_i32(t2, t2, t3);
1135 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1136 tcg_gen_or_i32(t2, t2, t3);
1137 tcg_gen_movi_i32(t3, 0);
1138 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1139 tcg_gen_rem_i32(t3, t0, t1);
1140 tcg_gen_ext_i32_tl(ret, t3);
1141 tcg_temp_free_i32(t2);
1142 tcg_temp_free_i32(t3);
1143 } else {
1144 TCGv_i32 t2 = tcg_const_i32(1);
1145 TCGv_i32 t3 = tcg_const_i32(0);
1146 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1147 tcg_gen_remu_i32(t3, t0, t1);
1148 tcg_gen_extu_i32_tl(ret, t3);
1149 tcg_temp_free_i32(t2);
1150 tcg_temp_free_i32(t3);
1151 }
1152 tcg_temp_free_i32(t0);
1153 tcg_temp_free_i32(t1);
1154 }
1155
1156 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1157 static void glue(gen_, name)(DisasContext *ctx) \
1158 { \
1159 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign); \
1162 }
1163
1164 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1165 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1166
1167 #if defined(TARGET_PPC64)
1168 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1169 TCGv arg2, int sign)
1170 {
1171 TCGv_i64 t0 = tcg_temp_new_i64();
1172 TCGv_i64 t1 = tcg_temp_new_i64();
1173
1174 tcg_gen_mov_i64(t0, arg1);
1175 tcg_gen_mov_i64(t1, arg2);
1176 if (sign) {
1177 TCGv_i64 t2 = tcg_temp_new_i64();
1178 TCGv_i64 t3 = tcg_temp_new_i64();
1179 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1180 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1181 tcg_gen_and_i64(t2, t2, t3);
1182 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1183 tcg_gen_or_i64(t2, t2, t3);
1184 tcg_gen_movi_i64(t3, 0);
1185 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1186 tcg_gen_rem_i64(ret, t0, t1);
1187 tcg_temp_free_i64(t2);
1188 tcg_temp_free_i64(t3);
1189 } else {
1190 TCGv_i64 t2 = tcg_const_i64(1);
1191 TCGv_i64 t3 = tcg_const_i64(0);
1192 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1193 tcg_gen_remu_i64(ret, t0, t1);
1194 tcg_temp_free_i64(t2);
1195 tcg_temp_free_i64(t3);
1196 }
1197 tcg_temp_free_i64(t0);
1198 tcg_temp_free_i64(t1);
1199 }
1200
1201 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1202 static void glue(gen_, name)(DisasContext *ctx) \
1203 { \
1204 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1206 sign); \
1207 }
1208
1209 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1210 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1211 #endif
1212
1213 /* mulhw mulhw. */
1214 static void gen_mulhw(DisasContext *ctx)
1215 {
1216 TCGv_i32 t0 = tcg_temp_new_i32();
1217 TCGv_i32 t1 = tcg_temp_new_i32();
1218
1219 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1220 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1221 tcg_gen_muls2_i32(t0, t1, t0, t1);
1222 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1223 tcg_temp_free_i32(t0);
1224 tcg_temp_free_i32(t1);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1227 }
1228
1229 /* mulhwu mulhwu. */
1230 static void gen_mulhwu(DisasContext *ctx)
1231 {
1232 TCGv_i32 t0 = tcg_temp_new_i32();
1233 TCGv_i32 t1 = tcg_temp_new_i32();
1234
1235 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1237 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1238 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1239 tcg_temp_free_i32(t0);
1240 tcg_temp_free_i32(t1);
1241 if (unlikely(Rc(ctx->opcode) != 0))
1242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1243 }
1244
1245 /* mullw mullw. */
1246 static void gen_mullw(DisasContext *ctx)
1247 {
1248 #if defined(TARGET_PPC64)
1249 TCGv_i64 t0, t1;
1250 t0 = tcg_temp_new_i64();
1251 t1 = tcg_temp_new_i64();
1252 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1253 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1254 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1255 tcg_temp_free(t0);
1256 tcg_temp_free(t1);
1257 #else
1258 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1259 cpu_gpr[rB(ctx->opcode)]);
1260 #endif
1261 if (unlikely(Rc(ctx->opcode) != 0))
1262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1263 }
1264
1265 /* mullwo mullwo. */
1266 static void gen_mullwo(DisasContext *ctx)
1267 {
1268 TCGv_i32 t0 = tcg_temp_new_i32();
1269 TCGv_i32 t1 = tcg_temp_new_i32();
1270
1271 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1272 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1273 tcg_gen_muls2_i32(t0, t1, t0, t1);
1274 #if defined(TARGET_PPC64)
1275 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1276 #else
1277 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1278 #endif
1279
1280 tcg_gen_sari_i32(t0, t0, 31);
1281 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1282 tcg_gen_extu_i32_tl(cpu_ov, t0);
1283 if (is_isa300(ctx)) {
1284 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1285 }
1286 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1287
1288 tcg_temp_free_i32(t0);
1289 tcg_temp_free_i32(t1);
1290 if (unlikely(Rc(ctx->opcode) != 0))
1291 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1292 }
1293
1294 /* mulli */
1295 static void gen_mulli(DisasContext *ctx)
1296 {
1297 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1298 SIMM(ctx->opcode));
1299 }
1300
1301 #if defined(TARGET_PPC64)
1302 /* mulhd mulhd. */
1303 static void gen_mulhd(DisasContext *ctx)
1304 {
1305 TCGv lo = tcg_temp_new();
1306 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1307 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1308 tcg_temp_free(lo);
1309 if (unlikely(Rc(ctx->opcode) != 0)) {
1310 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1311 }
1312 }
1313
1314 /* mulhdu mulhdu. */
1315 static void gen_mulhdu(DisasContext *ctx)
1316 {
1317 TCGv lo = tcg_temp_new();
1318 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1320 tcg_temp_free(lo);
1321 if (unlikely(Rc(ctx->opcode) != 0)) {
1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1323 }
1324 }
1325
1326 /* mulld mulld. */
1327 static void gen_mulld(DisasContext *ctx)
1328 {
1329 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1330 cpu_gpr[rB(ctx->opcode)]);
1331 if (unlikely(Rc(ctx->opcode) != 0))
1332 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1333 }
1334
1335 /* mulldo mulldo. */
1336 static void gen_mulldo(DisasContext *ctx)
1337 {
1338 TCGv_i64 t0 = tcg_temp_new_i64();
1339 TCGv_i64 t1 = tcg_temp_new_i64();
1340
1341 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1342 cpu_gpr[rB(ctx->opcode)]);
1343 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1344
1345 tcg_gen_sari_i64(t0, t0, 63);
1346 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1347 if (is_isa300(ctx)) {
1348 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1349 }
1350 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1351
1352 tcg_temp_free_i64(t0);
1353 tcg_temp_free_i64(t1);
1354
1355 if (unlikely(Rc(ctx->opcode) != 0)) {
1356 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1357 }
1358 }
1359 #endif
1360
1361 /* Common subf function */
1362 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1363 TCGv arg2, bool add_ca, bool compute_ca,
1364 bool compute_ov, bool compute_rc0)
1365 {
1366 TCGv t0 = ret;
1367
1368 if (compute_ca || compute_ov) {
1369 t0 = tcg_temp_new();
1370 }
1371
1372 if (compute_ca) {
1373 /* dest = ~arg1 + arg2 [+ ca]. */
1374 if (NARROW_MODE(ctx)) {
1375 /* Caution: a non-obvious corner case of the spec is that we
1376 must produce the *entire* 64-bit addition, but produce the
1377 carry into bit 32. */
1378 TCGv inv1 = tcg_temp_new();
1379 TCGv t1 = tcg_temp_new();
1380 tcg_gen_not_tl(inv1, arg1);
1381 if (add_ca) {
1382 tcg_gen_add_tl(t0, arg2, cpu_ca);
1383 } else {
1384 tcg_gen_addi_tl(t0, arg2, 1);
1385 }
1386 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1387 tcg_gen_add_tl(t0, t0, inv1);
1388 tcg_temp_free(inv1);
1389 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1390 tcg_temp_free(t1);
1391 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1392 if (is_isa300(ctx)) {
1393 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1394 }
1395 } else if (add_ca) {
1396 TCGv zero, inv1 = tcg_temp_new();
1397 tcg_gen_not_tl(inv1, arg1);
1398 zero = tcg_const_tl(0);
1399 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1400 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1401 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1402 tcg_temp_free(zero);
1403 tcg_temp_free(inv1);
1404 } else {
1405 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1406 tcg_gen_sub_tl(t0, arg2, arg1);
1407 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1408 }
1409 } else if (add_ca) {
1410 /* Since we're ignoring carry-out, we can simplify the
1411 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1412 tcg_gen_sub_tl(t0, arg2, arg1);
1413 tcg_gen_add_tl(t0, t0, cpu_ca);
1414 tcg_gen_subi_tl(t0, t0, 1);
1415 } else {
1416 tcg_gen_sub_tl(t0, arg2, arg1);
1417 }
1418
1419 if (compute_ov) {
1420 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1421 }
1422 if (unlikely(compute_rc0)) {
1423 gen_set_Rc0(ctx, t0);
1424 }
1425
1426 if (t0 != ret) {
1427 tcg_gen_mov_tl(ret, t0);
1428 tcg_temp_free(t0);
1429 }
1430 }
1431 /* Sub functions with Two operands functions */
1432 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1433 static void glue(gen_, name)(DisasContext *ctx) \
1434 { \
1435 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1436 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1437 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1438 }
1439 /* Sub functions with one operand and one immediate */
1440 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1441 add_ca, compute_ca, compute_ov) \
1442 static void glue(gen_, name)(DisasContext *ctx) \
1443 { \
1444 TCGv t0 = tcg_const_tl(const_val); \
1445 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1446 cpu_gpr[rA(ctx->opcode)], t0, \
1447 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1448 tcg_temp_free(t0); \
1449 }
1450 /* subf subf. subfo subfo. */
1451 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1452 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1453 /* subfc subfc. subfco subfco. */
1454 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1455 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1456 /* subfe subfe. subfeo subfo. */
1457 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1458 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1459 /* subfme subfme. subfmeo subfmeo. */
1460 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1461 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1462 /* subfze subfze. subfzeo subfzeo.*/
1463 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1464 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1465
1466 /* subfic */
1467 static void gen_subfic(DisasContext *ctx)
1468 {
1469 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1470 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1471 c, 0, 1, 0, 0);
1472 tcg_temp_free(c);
1473 }
1474
1475 /* neg neg. nego nego. */
1476 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1477 {
1478 TCGv zero = tcg_const_tl(0);
1479 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1480 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1481 tcg_temp_free(zero);
1482 }
1483
1484 static void gen_neg(DisasContext *ctx)
1485 {
1486 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1487 if (unlikely(Rc(ctx->opcode))) {
1488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1489 }
1490 }
1491
1492 static void gen_nego(DisasContext *ctx)
1493 {
1494 gen_op_arith_neg(ctx, 1);
1495 }
1496
1497 /*** Integer logical ***/
1498 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1499 static void glue(gen_, name)(DisasContext *ctx) \
1500 { \
1501 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1502 cpu_gpr[rB(ctx->opcode)]); \
1503 if (unlikely(Rc(ctx->opcode) != 0)) \
1504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1505 }
1506
1507 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1508 static void glue(gen_, name)(DisasContext *ctx) \
1509 { \
1510 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1511 if (unlikely(Rc(ctx->opcode) != 0)) \
1512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1513 }
1514
1515 /* and & and. */
1516 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1517 /* andc & andc. */
1518 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1519
1520 /* andi. */
1521 static void gen_andi_(DisasContext *ctx)
1522 {
1523 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1524 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1525 }
1526
1527 /* andis. */
1528 static void gen_andis_(DisasContext *ctx)
1529 {
1530 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1532 }
1533
1534 /* cntlzw */
1535 static void gen_cntlzw(DisasContext *ctx)
1536 {
1537 TCGv_i32 t = tcg_temp_new_i32();
1538
1539 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1540 tcg_gen_clzi_i32(t, t, 32);
1541 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1542 tcg_temp_free_i32(t);
1543
1544 if (unlikely(Rc(ctx->opcode) != 0))
1545 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1546 }
1547
1548 /* cnttzw */
1549 static void gen_cnttzw(DisasContext *ctx)
1550 {
1551 TCGv_i32 t = tcg_temp_new_i32();
1552
1553 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1554 tcg_gen_ctzi_i32(t, t, 32);
1555 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1556 tcg_temp_free_i32(t);
1557
1558 if (unlikely(Rc(ctx->opcode) != 0)) {
1559 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1560 }
1561 }
1562
1563 /* eqv & eqv. */
1564 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1565 /* extsb & extsb. */
1566 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1567 /* extsh & extsh. */
1568 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1569 /* nand & nand. */
1570 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1571 /* nor & nor. */
1572 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1573
1574 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1575 static void gen_pause(DisasContext *ctx)
1576 {
1577 TCGv_i32 t0 = tcg_const_i32(0);
1578 tcg_gen_st_i32(t0, cpu_env,
1579 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1580 tcg_temp_free_i32(t0);
1581
1582 /* Stop translation, this gives other CPUs a chance to run */
1583 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
1584 }
1585 #endif /* defined(TARGET_PPC64) */
1586
1587 /* or & or. */
1588 static void gen_or(DisasContext *ctx)
1589 {
1590 int rs, ra, rb;
1591
1592 rs = rS(ctx->opcode);
1593 ra = rA(ctx->opcode);
1594 rb = rB(ctx->opcode);
1595 /* Optimisation for mr. ri case */
1596 if (rs != ra || rs != rb) {
1597 if (rs != rb)
1598 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1599 else
1600 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1601 if (unlikely(Rc(ctx->opcode) != 0))
1602 gen_set_Rc0(ctx, cpu_gpr[ra]);
1603 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1604 gen_set_Rc0(ctx, cpu_gpr[rs]);
1605 #if defined(TARGET_PPC64)
1606 } else if (rs != 0) { /* 0 is nop */
1607 int prio = 0;
1608
1609 switch (rs) {
1610 case 1:
1611 /* Set process priority to low */
1612 prio = 2;
1613 break;
1614 case 6:
1615 /* Set process priority to medium-low */
1616 prio = 3;
1617 break;
1618 case 2:
1619 /* Set process priority to normal */
1620 prio = 4;
1621 break;
1622 #if !defined(CONFIG_USER_ONLY)
1623 case 31:
1624 if (!ctx->pr) {
1625 /* Set process priority to very low */
1626 prio = 1;
1627 }
1628 break;
1629 case 5:
1630 if (!ctx->pr) {
1631 /* Set process priority to medium-hight */
1632 prio = 5;
1633 }
1634 break;
1635 case 3:
1636 if (!ctx->pr) {
1637 /* Set process priority to high */
1638 prio = 6;
1639 }
1640 break;
1641 case 7:
1642 if (ctx->hv && !ctx->pr) {
1643 /* Set process priority to very high */
1644 prio = 7;
1645 }
1646 break;
1647 #endif
1648 default:
1649 break;
1650 }
1651 if (prio) {
1652 TCGv t0 = tcg_temp_new();
1653 gen_load_spr(t0, SPR_PPR);
1654 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1655 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1656 gen_store_spr(SPR_PPR, t0);
1657 tcg_temp_free(t0);
1658 }
1659 #if !defined(CONFIG_USER_ONLY)
1660 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1661 * CPU and the kernel hangs. This applies to all encodings other
1662 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1663 * and all currently undefined.
1664 */
1665 gen_pause(ctx);
1666 #endif
1667 #endif
1668 }
1669 }
1670 /* orc & orc. */
1671 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1672
1673 /* xor & xor. */
1674 static void gen_xor(DisasContext *ctx)
1675 {
1676 /* Optimisation for "set to zero" case */
1677 if (rS(ctx->opcode) != rB(ctx->opcode))
1678 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1679 else
1680 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1681 if (unlikely(Rc(ctx->opcode) != 0))
1682 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1683 }
1684
1685 /* ori */
1686 static void gen_ori(DisasContext *ctx)
1687 {
1688 target_ulong uimm = UIMM(ctx->opcode);
1689
1690 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1691 return;
1692 }
1693 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1694 }
1695
1696 /* oris */
1697 static void gen_oris(DisasContext *ctx)
1698 {
1699 target_ulong uimm = UIMM(ctx->opcode);
1700
1701 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1702 /* NOP */
1703 return;
1704 }
1705 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1706 }
1707
1708 /* xori */
1709 static void gen_xori(DisasContext *ctx)
1710 {
1711 target_ulong uimm = UIMM(ctx->opcode);
1712
1713 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1714 /* NOP */
1715 return;
1716 }
1717 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1718 }
1719
1720 /* xoris */
1721 static void gen_xoris(DisasContext *ctx)
1722 {
1723 target_ulong uimm = UIMM(ctx->opcode);
1724
1725 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1726 /* NOP */
1727 return;
1728 }
1729 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1730 }
1731
1732 /* popcntb : PowerPC 2.03 specification */
1733 static void gen_popcntb(DisasContext *ctx)
1734 {
1735 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1736 }
1737
1738 static void gen_popcntw(DisasContext *ctx)
1739 {
1740 #if defined(TARGET_PPC64)
1741 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1742 #else
1743 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1744 #endif
1745 }
1746
1747 #if defined(TARGET_PPC64)
1748 /* popcntd: PowerPC 2.06 specification */
1749 static void gen_popcntd(DisasContext *ctx)
1750 {
1751 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1752 }
1753 #endif
1754
1755 /* prtyw: PowerPC 2.05 specification */
1756 static void gen_prtyw(DisasContext *ctx)
1757 {
1758 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1759 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1760 TCGv t0 = tcg_temp_new();
1761 tcg_gen_shri_tl(t0, rs, 16);
1762 tcg_gen_xor_tl(ra, rs, t0);
1763 tcg_gen_shri_tl(t0, ra, 8);
1764 tcg_gen_xor_tl(ra, ra, t0);
1765 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1766 tcg_temp_free(t0);
1767 }
1768
1769 #if defined(TARGET_PPC64)
1770 /* prtyd: PowerPC 2.05 specification */
1771 static void gen_prtyd(DisasContext *ctx)
1772 {
1773 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1774 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1775 TCGv t0 = tcg_temp_new();
1776 tcg_gen_shri_tl(t0, rs, 32);
1777 tcg_gen_xor_tl(ra, rs, t0);
1778 tcg_gen_shri_tl(t0, ra, 16);
1779 tcg_gen_xor_tl(ra, ra, t0);
1780 tcg_gen_shri_tl(t0, ra, 8);
1781 tcg_gen_xor_tl(ra, ra, t0);
1782 tcg_gen_andi_tl(ra, ra, 1);
1783 tcg_temp_free(t0);
1784 }
1785 #endif
1786
1787 #if defined(TARGET_PPC64)
1788 /* bpermd */
1789 static void gen_bpermd(DisasContext *ctx)
1790 {
1791 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1792 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1793 }
1794 #endif
1795
1796 #if defined(TARGET_PPC64)
1797 /* extsw & extsw. */
1798 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1799
1800 /* cntlzd */
1801 static void gen_cntlzd(DisasContext *ctx)
1802 {
1803 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1804 if (unlikely(Rc(ctx->opcode) != 0))
1805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1806 }
1807
1808 /* cnttzd */
1809 static void gen_cnttzd(DisasContext *ctx)
1810 {
1811 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1812 if (unlikely(Rc(ctx->opcode) != 0)) {
1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1814 }
1815 }
1816
1817 /* darn */
1818 static void gen_darn(DisasContext *ctx)
1819 {
1820 int l = L(ctx->opcode);
1821
1822 if (l == 0) {
1823 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1824 } else if (l <= 2) {
1825 /* Return 64-bit random for both CRN and RRN */
1826 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1827 } else {
1828 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1829 }
1830 }
1831 #endif
1832
1833 /*** Integer rotate ***/
1834
1835 /* rlwimi & rlwimi. */
1836 static void gen_rlwimi(DisasContext *ctx)
1837 {
1838 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1839 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1840 uint32_t sh = SH(ctx->opcode);
1841 uint32_t mb = MB(ctx->opcode);
1842 uint32_t me = ME(ctx->opcode);
1843
1844 if (sh == (31-me) && mb <= me) {
1845 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1846 } else {
1847 target_ulong mask;
1848 TCGv t1;
1849
1850 #if defined(TARGET_PPC64)
1851 mb += 32;
1852 me += 32;
1853 #endif
1854 mask = MASK(mb, me);
1855
1856 t1 = tcg_temp_new();
1857 if (mask <= 0xffffffffu) {
1858 TCGv_i32 t0 = tcg_temp_new_i32();
1859 tcg_gen_trunc_tl_i32(t0, t_rs);
1860 tcg_gen_rotli_i32(t0, t0, sh);
1861 tcg_gen_extu_i32_tl(t1, t0);
1862 tcg_temp_free_i32(t0);
1863 } else {
1864 #if defined(TARGET_PPC64)
1865 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1866 tcg_gen_rotli_i64(t1, t1, sh);
1867 #else
1868 g_assert_not_reached();
1869 #endif
1870 }
1871
1872 tcg_gen_andi_tl(t1, t1, mask);
1873 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1874 tcg_gen_or_tl(t_ra, t_ra, t1);
1875 tcg_temp_free(t1);
1876 }
1877 if (unlikely(Rc(ctx->opcode) != 0)) {
1878 gen_set_Rc0(ctx, t_ra);
1879 }
1880 }
1881
1882 /* rlwinm & rlwinm. */
1883 static void gen_rlwinm(DisasContext *ctx)
1884 {
1885 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1886 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1887 int sh = SH(ctx->opcode);
1888 int mb = MB(ctx->opcode);
1889 int me = ME(ctx->opcode);
1890 int len = me - mb + 1;
1891 int rsh = (32 - sh) & 31;
1892
1893 if (sh != 0 && len > 0 && me == (31 - sh)) {
1894 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1895 } else if (me == 31 && rsh + len <= 32) {
1896 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1897 } else {
1898 target_ulong mask;
1899 #if defined(TARGET_PPC64)
1900 mb += 32;
1901 me += 32;
1902 #endif
1903 mask = MASK(mb, me);
1904 if (sh == 0) {
1905 tcg_gen_andi_tl(t_ra, t_rs, mask);
1906 } else if (mask <= 0xffffffffu) {
1907 TCGv_i32 t0 = tcg_temp_new_i32();
1908 tcg_gen_trunc_tl_i32(t0, t_rs);
1909 tcg_gen_rotli_i32(t0, t0, sh);
1910 tcg_gen_andi_i32(t0, t0, mask);
1911 tcg_gen_extu_i32_tl(t_ra, t0);
1912 tcg_temp_free_i32(t0);
1913 } else {
1914 #if defined(TARGET_PPC64)
1915 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1916 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1917 tcg_gen_andi_i64(t_ra, t_ra, mask);
1918 #else
1919 g_assert_not_reached();
1920 #endif
1921 }
1922 }
1923 if (unlikely(Rc(ctx->opcode) != 0)) {
1924 gen_set_Rc0(ctx, t_ra);
1925 }
1926 }
1927
1928 /* rlwnm & rlwnm. */
1929 static void gen_rlwnm(DisasContext *ctx)
1930 {
1931 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1932 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1933 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1934 uint32_t mb = MB(ctx->opcode);
1935 uint32_t me = ME(ctx->opcode);
1936 target_ulong mask;
1937
1938 #if defined(TARGET_PPC64)
1939 mb += 32;
1940 me += 32;
1941 #endif
1942 mask = MASK(mb, me);
1943
1944 if (mask <= 0xffffffffu) {
1945 TCGv_i32 t0 = tcg_temp_new_i32();
1946 TCGv_i32 t1 = tcg_temp_new_i32();
1947 tcg_gen_trunc_tl_i32(t0, t_rb);
1948 tcg_gen_trunc_tl_i32(t1, t_rs);
1949 tcg_gen_andi_i32(t0, t0, 0x1f);
1950 tcg_gen_rotl_i32(t1, t1, t0);
1951 tcg_gen_extu_i32_tl(t_ra, t1);
1952 tcg_temp_free_i32(t0);
1953 tcg_temp_free_i32(t1);
1954 } else {
1955 #if defined(TARGET_PPC64)
1956 TCGv_i64 t0 = tcg_temp_new_i64();
1957 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1958 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1959 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1960 tcg_temp_free_i64(t0);
1961 #else
1962 g_assert_not_reached();
1963 #endif
1964 }
1965
1966 tcg_gen_andi_tl(t_ra, t_ra, mask);
1967
1968 if (unlikely(Rc(ctx->opcode) != 0)) {
1969 gen_set_Rc0(ctx, t_ra);
1970 }
1971 }
1972
1973 #if defined(TARGET_PPC64)
1974 #define GEN_PPC64_R2(name, opc1, opc2) \
1975 static void glue(gen_, name##0)(DisasContext *ctx) \
1976 { \
1977 gen_##name(ctx, 0); \
1978 } \
1979 \
1980 static void glue(gen_, name##1)(DisasContext *ctx) \
1981 { \
1982 gen_##name(ctx, 1); \
1983 }
1984 #define GEN_PPC64_R4(name, opc1, opc2) \
1985 static void glue(gen_, name##0)(DisasContext *ctx) \
1986 { \
1987 gen_##name(ctx, 0, 0); \
1988 } \
1989 \
1990 static void glue(gen_, name##1)(DisasContext *ctx) \
1991 { \
1992 gen_##name(ctx, 0, 1); \
1993 } \
1994 \
1995 static void glue(gen_, name##2)(DisasContext *ctx) \
1996 { \
1997 gen_##name(ctx, 1, 0); \
1998 } \
1999 \
2000 static void glue(gen_, name##3)(DisasContext *ctx) \
2001 { \
2002 gen_##name(ctx, 1, 1); \
2003 }
2004
2005 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2006 {
2007 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2008 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2009 int len = me - mb + 1;
2010 int rsh = (64 - sh) & 63;
2011
2012 if (sh != 0 && len > 0 && me == (63 - sh)) {
2013 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2014 } else if (me == 63 && rsh + len <= 64) {
2015 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2016 } else {
2017 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2018 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2019 }
2020 if (unlikely(Rc(ctx->opcode) != 0)) {
2021 gen_set_Rc0(ctx, t_ra);
2022 }
2023 }
2024
2025 /* rldicl - rldicl. */
2026 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2027 {
2028 uint32_t sh, mb;
2029
2030 sh = SH(ctx->opcode) | (shn << 5);
2031 mb = MB(ctx->opcode) | (mbn << 5);
2032 gen_rldinm(ctx, mb, 63, sh);
2033 }
2034 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2035
2036 /* rldicr - rldicr. */
2037 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2038 {
2039 uint32_t sh, me;
2040
2041 sh = SH(ctx->opcode) | (shn << 5);
2042 me = MB(ctx->opcode) | (men << 5);
2043 gen_rldinm(ctx, 0, me, sh);
2044 }
2045 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2046
2047 /* rldic - rldic. */
2048 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2049 {
2050 uint32_t sh, mb;
2051
2052 sh = SH(ctx->opcode) | (shn << 5);
2053 mb = MB(ctx->opcode) | (mbn << 5);
2054 gen_rldinm(ctx, mb, 63 - sh, sh);
2055 }
2056 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2057
2058 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2059 {
2060 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2061 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2062 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2063 TCGv t0;
2064
2065 t0 = tcg_temp_new();
2066 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2067 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2068 tcg_temp_free(t0);
2069
2070 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2071 if (unlikely(Rc(ctx->opcode) != 0)) {
2072 gen_set_Rc0(ctx, t_ra);
2073 }
2074 }
2075
2076 /* rldcl - rldcl. */
2077 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2078 {
2079 uint32_t mb;
2080
2081 mb = MB(ctx->opcode) | (mbn << 5);
2082 gen_rldnm(ctx, mb, 63);
2083 }
2084 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2085
2086 /* rldcr - rldcr. */
2087 static inline void gen_rldcr(DisasContext *ctx, int men)
2088 {
2089 uint32_t me;
2090
2091 me = MB(ctx->opcode) | (men << 5);
2092 gen_rldnm(ctx, 0, me);
2093 }
2094 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2095
2096 /* rldimi - rldimi. */
2097 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2098 {
2099 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2100 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2101 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2102 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2103 uint32_t me = 63 - sh;
2104
2105 if (mb <= me) {
2106 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2107 } else {
2108 target_ulong mask = MASK(mb, me);
2109 TCGv t1 = tcg_temp_new();
2110
2111 tcg_gen_rotli_tl(t1, t_rs, sh);
2112 tcg_gen_andi_tl(t1, t1, mask);
2113 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2114 tcg_gen_or_tl(t_ra, t_ra, t1);
2115 tcg_temp_free(t1);
2116 }
2117 if (unlikely(Rc(ctx->opcode) != 0)) {
2118 gen_set_Rc0(ctx, t_ra);
2119 }
2120 }
2121 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2122 #endif
2123
2124 /*** Integer shift ***/
2125
2126 /* slw & slw. */
2127 static void gen_slw(DisasContext *ctx)
2128 {
2129 TCGv t0, t1;
2130
2131 t0 = tcg_temp_new();
2132 /* AND rS with a mask that is 0 when rB >= 0x20 */
2133 #if defined(TARGET_PPC64)
2134 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2135 tcg_gen_sari_tl(t0, t0, 0x3f);
2136 #else
2137 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2138 tcg_gen_sari_tl(t0, t0, 0x1f);
2139 #endif
2140 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2141 t1 = tcg_temp_new();
2142 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2143 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2144 tcg_temp_free(t1);
2145 tcg_temp_free(t0);
2146 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2147 if (unlikely(Rc(ctx->opcode) != 0))
2148 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2149 }
2150
2151 /* sraw & sraw. */
2152 static void gen_sraw(DisasContext *ctx)
2153 {
2154 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2155 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2156 if (unlikely(Rc(ctx->opcode) != 0))
2157 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2158 }
2159
2160 /* srawi & srawi. */
2161 static void gen_srawi(DisasContext *ctx)
2162 {
2163 int sh = SH(ctx->opcode);
2164 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2165 TCGv src = cpu_gpr[rS(ctx->opcode)];
2166 if (sh == 0) {
2167 tcg_gen_ext32s_tl(dst, src);
2168 tcg_gen_movi_tl(cpu_ca, 0);
2169 if (is_isa300(ctx)) {
2170 tcg_gen_movi_tl(cpu_ca32, 0);
2171 }
2172 } else {
2173 TCGv t0;
2174 tcg_gen_ext32s_tl(dst, src);
2175 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2176 t0 = tcg_temp_new();
2177 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2178 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2179 tcg_temp_free(t0);
2180 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2181 if (is_isa300(ctx)) {
2182 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2183 }
2184 tcg_gen_sari_tl(dst, dst, sh);
2185 }
2186 if (unlikely(Rc(ctx->opcode) != 0)) {
2187 gen_set_Rc0(ctx, dst);
2188 }
2189 }
2190
2191 /* srw & srw. */
2192 static void gen_srw(DisasContext *ctx)
2193 {
2194 TCGv t0, t1;
2195
2196 t0 = tcg_temp_new();
2197 /* AND rS with a mask that is 0 when rB >= 0x20 */
2198 #if defined(TARGET_PPC64)
2199 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2200 tcg_gen_sari_tl(t0, t0, 0x3f);
2201 #else
2202 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2203 tcg_gen_sari_tl(t0, t0, 0x1f);
2204 #endif
2205 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2206 tcg_gen_ext32u_tl(t0, t0);
2207 t1 = tcg_temp_new();
2208 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2209 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2210 tcg_temp_free(t1);
2211 tcg_temp_free(t0);
2212 if (unlikely(Rc(ctx->opcode) != 0))
2213 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2214 }
2215
2216 #if defined(TARGET_PPC64)
2217 /* sld & sld. */
2218 static void gen_sld(DisasContext *ctx)
2219 {
2220 TCGv t0, t1;
2221
2222 t0 = tcg_temp_new();
2223 /* AND rS with a mask that is 0 when rB >= 0x40 */
2224 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2225 tcg_gen_sari_tl(t0, t0, 0x3f);
2226 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2227 t1 = tcg_temp_new();
2228 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2229 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2230 tcg_temp_free(t1);
2231 tcg_temp_free(t0);
2232 if (unlikely(Rc(ctx->opcode) != 0))
2233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2234 }
2235
2236 /* srad & srad. */
2237 static void gen_srad(DisasContext *ctx)
2238 {
2239 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2240 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2241 if (unlikely(Rc(ctx->opcode) != 0))
2242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2243 }
2244 /* sradi & sradi. */
2245 static inline void gen_sradi(DisasContext *ctx, int n)
2246 {
2247 int sh = SH(ctx->opcode) + (n << 5);
2248 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2249 TCGv src = cpu_gpr[rS(ctx->opcode)];
2250 if (sh == 0) {
2251 tcg_gen_mov_tl(dst, src);
2252 tcg_gen_movi_tl(cpu_ca, 0);
2253 if (is_isa300(ctx)) {
2254 tcg_gen_movi_tl(cpu_ca32, 0);
2255 }
2256 } else {
2257 TCGv t0;
2258 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2259 t0 = tcg_temp_new();
2260 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2261 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2262 tcg_temp_free(t0);
2263 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2264 if (is_isa300(ctx)) {
2265 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2266 }
2267 tcg_gen_sari_tl(dst, src, sh);
2268 }
2269 if (unlikely(Rc(ctx->opcode) != 0)) {
2270 gen_set_Rc0(ctx, dst);
2271 }
2272 }
2273
2274 static void gen_sradi0(DisasContext *ctx)
2275 {
2276 gen_sradi(ctx, 0);
2277 }
2278
2279 static void gen_sradi1(DisasContext *ctx)
2280 {
2281 gen_sradi(ctx, 1);
2282 }
2283
2284 /* extswsli & extswsli. */
2285 static inline void gen_extswsli(DisasContext *ctx, int n)
2286 {
2287 int sh = SH(ctx->opcode) + (n << 5);
2288 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2289 TCGv src = cpu_gpr[rS(ctx->opcode)];
2290
2291 tcg_gen_ext32s_tl(dst, src);
2292 tcg_gen_shli_tl(dst, dst, sh);
2293 if (unlikely(Rc(ctx->opcode) != 0)) {
2294 gen_set_Rc0(ctx, dst);
2295 }
2296 }
2297
2298 static void gen_extswsli0(DisasContext *ctx)
2299 {
2300 gen_extswsli(ctx, 0);
2301 }
2302
2303 static void gen_extswsli1(DisasContext *ctx)
2304 {
2305 gen_extswsli(ctx, 1);
2306 }
2307
2308 /* srd & srd. */
2309 static void gen_srd(DisasContext *ctx)
2310 {
2311 TCGv t0, t1;
2312
2313 t0 = tcg_temp_new();
2314 /* AND rS with a mask that is 0 when rB >= 0x40 */
2315 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2316 tcg_gen_sari_tl(t0, t0, 0x3f);
2317 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2318 t1 = tcg_temp_new();
2319 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2320 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2321 tcg_temp_free(t1);
2322 tcg_temp_free(t0);
2323 if (unlikely(Rc(ctx->opcode) != 0))
2324 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2325 }
2326 #endif
2327
2328 /*** Addressing modes ***/
2329 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2330 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2331 target_long maskl)
2332 {
2333 target_long simm = SIMM(ctx->opcode);
2334
2335 simm &= ~maskl;
2336 if (rA(ctx->opcode) == 0) {
2337 if (NARROW_MODE(ctx)) {
2338 simm = (uint32_t)simm;
2339 }
2340 tcg_gen_movi_tl(EA, simm);
2341 } else if (likely(simm != 0)) {
2342 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2343 if (NARROW_MODE(ctx)) {
2344 tcg_gen_ext32u_tl(EA, EA);
2345 }
2346 } else {
2347 if (NARROW_MODE(ctx)) {
2348 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2349 } else {
2350 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2351 }
2352 }
2353 }
2354
2355 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2356 {
2357 if (rA(ctx->opcode) == 0) {
2358 if (NARROW_MODE(ctx)) {
2359 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2360 } else {
2361 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2362 }
2363 } else {
2364 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2365 if (NARROW_MODE(ctx)) {
2366 tcg_gen_ext32u_tl(EA, EA);
2367 }
2368 }
2369 }
2370
2371 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2372 {
2373 if (rA(ctx->opcode) == 0) {
2374 tcg_gen_movi_tl(EA, 0);
2375 } else if (NARROW_MODE(ctx)) {
2376 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2377 } else {
2378 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2379 }
2380 }
2381
2382 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2383 target_long val)
2384 {
2385 tcg_gen_addi_tl(ret, arg1, val);
2386 if (NARROW_MODE(ctx)) {
2387 tcg_gen_ext32u_tl(ret, ret);
2388 }
2389 }
2390
2391 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2392 {
2393 TCGLabel *l1 = gen_new_label();
2394 TCGv t0 = tcg_temp_new();
2395 TCGv_i32 t1, t2;
2396 tcg_gen_andi_tl(t0, EA, mask);
2397 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2398 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2399 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2400 gen_update_nip(ctx, ctx->base.pc_next - 4);
2401 gen_helper_raise_exception_err(cpu_env, t1, t2);
2402 tcg_temp_free_i32(t1);
2403 tcg_temp_free_i32(t2);
2404 gen_set_label(l1);
2405 tcg_temp_free(t0);
2406 }
2407
2408 static inline void gen_align_no_le(DisasContext *ctx)
2409 {
2410 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2411 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2412 }
2413
2414 /*** Integer load ***/
2415 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2416 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2417
2418 #define GEN_QEMU_LOAD_TL(ldop, op) \
2419 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2420 TCGv val, \
2421 TCGv addr) \
2422 { \
2423 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2424 }
2425
2426 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2427 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2428 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2429 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2430 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2431
2432 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2433 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2434
2435 #define GEN_QEMU_LOAD_64(ldop, op) \
2436 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2437 TCGv_i64 val, \
2438 TCGv addr) \
2439 { \
2440 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2441 }
2442
2443 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2444 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2445 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2446 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2447 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2448
2449 #if defined(TARGET_PPC64)
2450 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2451 #endif
2452
2453 #define GEN_QEMU_STORE_TL(stop, op) \
2454 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2455 TCGv val, \
2456 TCGv addr) \
2457 { \
2458 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2459 }
2460
2461 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2462 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2463 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2464
2465 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2466 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2467
2468 #define GEN_QEMU_STORE_64(stop, op) \
2469 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2470 TCGv_i64 val, \
2471 TCGv addr) \
2472 { \
2473 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2474 }
2475
2476 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2477 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2478 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2479 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2480
2481 #if defined(TARGET_PPC64)
2482 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2483 #endif
2484
2485 #define GEN_LD(name, ldop, opc, type) \
2486 static void glue(gen_, name)(DisasContext *ctx) \
2487 { \
2488 TCGv EA; \
2489 gen_set_access_type(ctx, ACCESS_INT); \
2490 EA = tcg_temp_new(); \
2491 gen_addr_imm_index(ctx, EA, 0); \
2492 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2493 tcg_temp_free(EA); \
2494 }
2495
2496 #define GEN_LDU(name, ldop, opc, type) \
2497 static void glue(gen_, name##u)(DisasContext *ctx) \
2498 { \
2499 TCGv EA; \
2500 if (unlikely(rA(ctx->opcode) == 0 || \
2501 rA(ctx->opcode) == rD(ctx->opcode))) { \
2502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2503 return; \
2504 } \
2505 gen_set_access_type(ctx, ACCESS_INT); \
2506 EA = tcg_temp_new(); \
2507 if (type == PPC_64B) \
2508 gen_addr_imm_index(ctx, EA, 0x03); \
2509 else \
2510 gen_addr_imm_index(ctx, EA, 0); \
2511 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2513 tcg_temp_free(EA); \
2514 }
2515
2516 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2517 static void glue(gen_, name##ux)(DisasContext *ctx) \
2518 { \
2519 TCGv EA; \
2520 if (unlikely(rA(ctx->opcode) == 0 || \
2521 rA(ctx->opcode) == rD(ctx->opcode))) { \
2522 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2523 return; \
2524 } \
2525 gen_set_access_type(ctx, ACCESS_INT); \
2526 EA = tcg_temp_new(); \
2527 gen_addr_reg_index(ctx, EA); \
2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2530 tcg_temp_free(EA); \
2531 }
2532
2533 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2534 static void glue(gen_, name##x)(DisasContext *ctx) \
2535 { \
2536 TCGv EA; \
2537 chk; \
2538 gen_set_access_type(ctx, ACCESS_INT); \
2539 EA = tcg_temp_new(); \
2540 gen_addr_reg_index(ctx, EA); \
2541 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2542 tcg_temp_free(EA); \
2543 }
2544
2545 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2546 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2547
2548 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2549 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2550
2551 #define GEN_LDS(name, ldop, op, type) \
2552 GEN_LD(name, ldop, op | 0x20, type); \
2553 GEN_LDU(name, ldop, op | 0x21, type); \
2554 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2555 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2556
2557 /* lbz lbzu lbzux lbzx */
2558 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2559 /* lha lhau lhaux lhax */
2560 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2561 /* lhz lhzu lhzux lhzx */
2562 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2563 /* lwz lwzu lwzux lwzx */
2564 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2565 #if defined(TARGET_PPC64)
2566 /* lwaux */
2567 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2568 /* lwax */
2569 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2570 /* ldux */
2571 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2572 /* ldx */
2573 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2574
2575 /* CI load/store variants */
2576 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2577 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2578 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2579 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2580
2581 static void gen_ld(DisasContext *ctx)
2582 {
2583 TCGv EA;
2584 if (Rc(ctx->opcode)) {
2585 if (unlikely(rA(ctx->opcode) == 0 ||
2586 rA(ctx->opcode) == rD(ctx->opcode))) {
2587 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2588 return;
2589 }
2590 }
2591 gen_set_access_type(ctx, ACCESS_INT);
2592 EA = tcg_temp_new();
2593 gen_addr_imm_index(ctx, EA, 0x03);
2594 if (ctx->opcode & 0x02) {
2595 /* lwa (lwau is undefined) */
2596 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2597 } else {
2598 /* ld - ldu */
2599 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2600 }
2601 if (Rc(ctx->opcode))
2602 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2603 tcg_temp_free(EA);
2604 }
2605
2606 /* lq */
2607 static void gen_lq(DisasContext *ctx)
2608 {
2609 int ra, rd;
2610 TCGv EA, hi, lo;
2611
2612 /* lq is a legal user mode instruction starting in ISA 2.07 */
2613 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2614 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2615
2616 if (!legal_in_user_mode && ctx->pr) {
2617 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2618 return;
2619 }
2620
2621 if (!le_is_supported && ctx->le_mode) {
2622 gen_align_no_le(ctx);
2623 return;
2624 }
2625 ra = rA(ctx->opcode);
2626 rd = rD(ctx->opcode);
2627 if (unlikely((rd & 1) || rd == ra)) {
2628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2629 return;
2630 }
2631
2632 gen_set_access_type(ctx, ACCESS_INT);
2633 EA = tcg_temp_new();
2634 gen_addr_imm_index(ctx, EA, 0x0F);
2635
2636 /* Note that the low part is always in RD+1, even in LE mode. */
2637 lo = cpu_gpr[rd + 1];
2638 hi = cpu_gpr[rd];
2639
2640 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2641 #ifdef CONFIG_ATOMIC128
2642 TCGv_i32 oi = tcg_temp_new_i32();
2643 if (ctx->le_mode) {
2644 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2645 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
2646 } else {
2647 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2648 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
2649 }
2650 tcg_temp_free_i32(oi);
2651 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
2652 #else
2653 /* Restart with exclusive lock. */
2654 gen_helper_exit_atomic(cpu_env);
2655 ctx->base.is_jmp = DISAS_NORETURN;
2656 #endif
2657 } else if (ctx->le_mode) {
2658 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2659 gen_addr_add(ctx, EA, EA, 8);
2660 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2661 } else {
2662 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2663 gen_addr_add(ctx, EA, EA, 8);
2664 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2665 }
2666 tcg_temp_free(EA);
2667 }
2668 #endif
2669
2670 /*** Integer store ***/
2671 #define GEN_ST(name, stop, opc, type) \
2672 static void glue(gen_, name)(DisasContext *ctx) \
2673 { \
2674 TCGv EA; \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 gen_addr_imm_index(ctx, EA, 0); \
2678 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2679 tcg_temp_free(EA); \
2680 }
2681
2682 #define GEN_STU(name, stop, opc, type) \
2683 static void glue(gen_, stop##u)(DisasContext *ctx) \
2684 { \
2685 TCGv EA; \
2686 if (unlikely(rA(ctx->opcode) == 0)) { \
2687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2688 return; \
2689 } \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 if (type == PPC_64B) \
2693 gen_addr_imm_index(ctx, EA, 0x03); \
2694 else \
2695 gen_addr_imm_index(ctx, EA, 0); \
2696 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2698 tcg_temp_free(EA); \
2699 }
2700
2701 #define GEN_STUX(name, stop, opc2, opc3, type) \
2702 static void glue(gen_, name##ux)(DisasContext *ctx) \
2703 { \
2704 TCGv EA; \
2705 if (unlikely(rA(ctx->opcode) == 0)) { \
2706 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2707 return; \
2708 } \
2709 gen_set_access_type(ctx, ACCESS_INT); \
2710 EA = tcg_temp_new(); \
2711 gen_addr_reg_index(ctx, EA); \
2712 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2713 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2714 tcg_temp_free(EA); \
2715 }
2716
2717 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2718 static void glue(gen_, name##x)(DisasContext *ctx) \
2719 { \
2720 TCGv EA; \
2721 chk; \
2722 gen_set_access_type(ctx, ACCESS_INT); \
2723 EA = tcg_temp_new(); \
2724 gen_addr_reg_index(ctx, EA); \
2725 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2726 tcg_temp_free(EA); \
2727 }
2728 #define GEN_STX(name, stop, opc2, opc3, type) \
2729 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2730
2731 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2732 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2733
2734 #define GEN_STS(name, stop, op, type) \
2735 GEN_ST(name, stop, op | 0x20, type); \
2736 GEN_STU(name, stop, op | 0x21, type); \
2737 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2738 GEN_STX(name, stop, 0x17, op | 0x00, type)
2739
2740 /* stb stbu stbux stbx */
2741 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2742 /* sth sthu sthux sthx */
2743 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2744 /* stw stwu stwux stwx */
2745 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2746 #if defined(TARGET_PPC64)
2747 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2748 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2749 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2750 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2751 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2752 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2753
2754 static void gen_std(DisasContext *ctx)
2755 {
2756 int rs;
2757 TCGv EA;
2758
2759 rs = rS(ctx->opcode);
2760 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2761 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2762 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2763 TCGv hi, lo;
2764
2765 if (!(ctx->insns_flags & PPC_64BX)) {
2766 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2767 }
2768
2769 if (!legal_in_user_mode && ctx->pr) {
2770 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2771 return;
2772 }
2773
2774 if (!le_is_supported && ctx->le_mode) {
2775 gen_align_no_le(ctx);
2776 return;
2777 }
2778
2779 if (unlikely(rs & 1)) {
2780 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2781 return;
2782 }
2783 gen_set_access_type(ctx, ACCESS_INT);
2784 EA = tcg_temp_new();
2785 gen_addr_imm_index(ctx, EA, 0x03);
2786
2787 /* Note that the low part is always in RS+1, even in LE mode. */
2788 lo = cpu_gpr[rs + 1];
2789 hi = cpu_gpr[rs];
2790
2791 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2792 #ifdef CONFIG_ATOMIC128
2793 TCGv_i32 oi = tcg_temp_new_i32();
2794 if (ctx->le_mode) {
2795 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2796 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
2797 } else {
2798 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2799 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
2800 }
2801 tcg_temp_free_i32(oi);
2802 #else
2803 /* Restart with exclusive lock. */
2804 gen_helper_exit_atomic(cpu_env);
2805 ctx->base.is_jmp = DISAS_NORETURN;
2806 #endif
2807 } else if (ctx->le_mode) {
2808 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2809 gen_addr_add(ctx, EA, EA, 8);
2810 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2811 } else {
2812 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2813 gen_addr_add(ctx, EA, EA, 8);
2814 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2815 }
2816 tcg_temp_free(EA);
2817 } else {
2818 /* std / stdu */
2819 if (Rc(ctx->opcode)) {
2820 if (unlikely(rA(ctx->opcode) == 0)) {
2821 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2822 return;
2823 }
2824 }
2825 gen_set_access_type(ctx, ACCESS_INT);
2826 EA = tcg_temp_new();
2827 gen_addr_imm_index(ctx, EA, 0x03);
2828 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2829 if (Rc(ctx->opcode))
2830 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2831 tcg_temp_free(EA);
2832 }
2833 }
2834 #endif
2835 /*** Integer load and store with byte reverse ***/
2836
2837 /* lhbrx */
2838 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2839
2840 /* lwbrx */
2841 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2842
2843 #if defined(TARGET_PPC64)
2844 /* ldbrx */
2845 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2846 /* stdbrx */
2847 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2848 #endif /* TARGET_PPC64 */
2849
2850 /* sthbrx */
2851 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2852 /* stwbrx */
2853 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2854
2855 /*** Integer load and store multiple ***/
2856
2857 /* lmw */
2858 static void gen_lmw(DisasContext *ctx)
2859 {
2860 TCGv t0;
2861 TCGv_i32 t1;
2862
2863 if (ctx->le_mode) {
2864 gen_align_no_le(ctx);
2865 return;
2866 }
2867 gen_set_access_type(ctx, ACCESS_INT);
2868 t0 = tcg_temp_new();
2869 t1 = tcg_const_i32(rD(ctx->opcode));
2870 gen_addr_imm_index(ctx, t0, 0);
2871 gen_helper_lmw(cpu_env, t0, t1);
2872 tcg_temp_free(t0);
2873 tcg_temp_free_i32(t1);
2874 }
2875
2876 /* stmw */
2877 static void gen_stmw(DisasContext *ctx)
2878 {
2879 TCGv t0;
2880 TCGv_i32 t1;
2881
2882 if (ctx->le_mode) {
2883 gen_align_no_le(ctx);
2884 return;
2885 }
2886 gen_set_access_type(ctx, ACCESS_INT);
2887 t0 = tcg_temp_new();
2888 t1 = tcg_const_i32(rS(ctx->opcode));
2889 gen_addr_imm_index(ctx, t0, 0);
2890 gen_helper_stmw(cpu_env, t0, t1);
2891 tcg_temp_free(t0);
2892 tcg_temp_free_i32(t1);
2893 }
2894
2895 /*** Integer load and store strings ***/
2896
2897 /* lswi */
2898 /* PowerPC32 specification says we must generate an exception if
2899 * rA is in the range of registers to be loaded.
2900 * In an other hand, IBM says this is valid, but rA won't be loaded.
2901 * For now, I'll follow the spec...
2902 */
2903 static void gen_lswi(DisasContext *ctx)
2904 {
2905 TCGv t0;
2906 TCGv_i32 t1, t2;
2907 int nb = NB(ctx->opcode);
2908 int start = rD(ctx->opcode);
2909 int ra = rA(ctx->opcode);
2910 int nr;
2911
2912 if (ctx->le_mode) {
2913 gen_align_no_le(ctx);
2914 return;
2915 }
2916 if (nb == 0)
2917 nb = 32;
2918 nr = DIV_ROUND_UP(nb, 4);
2919 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2921 return;
2922 }
2923 gen_set_access_type(ctx, ACCESS_INT);
2924 t0 = tcg_temp_new();
2925 gen_addr_register(ctx, t0);
2926 t1 = tcg_const_i32(nb);
2927 t2 = tcg_const_i32(start);
2928 gen_helper_lsw(cpu_env, t0, t1, t2);
2929 tcg_temp_free(t0);
2930 tcg_temp_free_i32(t1);
2931 tcg_temp_free_i32(t2);
2932 }
2933
2934 /* lswx */
2935 static void gen_lswx(DisasContext *ctx)
2936 {
2937 TCGv t0;
2938 TCGv_i32 t1, t2, t3;
2939
2940 if (ctx->le_mode) {
2941 gen_align_no_le(ctx);
2942 return;
2943 }
2944 gen_set_access_type(ctx, ACCESS_INT);
2945 t0 = tcg_temp_new();
2946 gen_addr_reg_index(ctx, t0);
2947 t1 = tcg_const_i32(rD(ctx->opcode));
2948 t2 = tcg_const_i32(rA(ctx->opcode));
2949 t3 = tcg_const_i32(rB(ctx->opcode));
2950 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2951 tcg_temp_free(t0);
2952 tcg_temp_free_i32(t1);
2953 tcg_temp_free_i32(t2);
2954 tcg_temp_free_i32(t3);
2955 }
2956
2957 /* stswi */
2958 static void gen_stswi(DisasContext *ctx)
2959 {
2960 TCGv t0;
2961 TCGv_i32 t1, t2;
2962 int nb = NB(ctx->opcode);
2963
2964 if (ctx->le_mode) {
2965 gen_align_no_le(ctx);
2966 return;
2967 }
2968 gen_set_access_type(ctx, ACCESS_INT);
2969 t0 = tcg_temp_new();
2970 gen_addr_register(ctx, t0);
2971 if (nb == 0)
2972 nb = 32;
2973 t1 = tcg_const_i32(nb);
2974 t2 = tcg_const_i32(rS(ctx->opcode));
2975 gen_helper_stsw(cpu_env, t0, t1, t2);
2976 tcg_temp_free(t0);
2977 tcg_temp_free_i32(t1);
2978 tcg_temp_free_i32(t2);
2979 }
2980
2981 /* stswx */
2982 static void gen_stswx(DisasContext *ctx)
2983 {
2984 TCGv t0;
2985 TCGv_i32 t1, t2;
2986
2987 if (ctx->le_mode) {
2988 gen_align_no_le(ctx);
2989 return;
2990 }
2991 gen_set_access_type(ctx, ACCESS_INT);
2992 t0 = tcg_temp_new();
2993 gen_addr_reg_index(ctx, t0);
2994 t1 = tcg_temp_new_i32();
2995 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2996 tcg_gen_andi_i32(t1, t1, 0x7F);
2997 t2 = tcg_const_i32(rS(ctx->opcode));
2998 gen_helper_stsw(cpu_env, t0, t1, t2);
2999 tcg_temp_free(t0);
3000 tcg_temp_free_i32(t1);
3001 tcg_temp_free_i32(t2);
3002 }
3003
3004 /*** Memory synchronisation ***/
3005 /* eieio */
3006 static void gen_eieio(DisasContext *ctx)
3007 {
3008 TCGBar bar = TCG_MO_LD_ST;
3009
3010 /*
3011 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3012 * tell the CPU it is a store-forwarding barrier.
3013 */
3014 if (ctx->opcode & 0x2000000) {
3015 /*
3016 * ISA says that "Reserved fields in instructions are ignored
3017 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3018 * as this is not an instruction software should be using,
3019 * complain to the user.
3020 */
3021 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3022 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3023 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
3024 } else {
3025 bar = TCG_MO_ST_LD;
3026 }
3027 }
3028
3029 tcg_gen_mb(bar | TCG_BAR_SC);
3030 }
3031
3032 #if !defined(CONFIG_USER_ONLY)
3033 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3034 {
3035 TCGv_i32 t;
3036 TCGLabel *l;
3037
3038 if (!ctx->lazy_tlb_flush) {
3039 return;
3040 }
3041 l = gen_new_label();
3042 t = tcg_temp_new_i32();
3043 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3044 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3045 if (global) {
3046 gen_helper_check_tlb_flush_global(cpu_env);
3047 } else {
3048 gen_helper_check_tlb_flush_local(cpu_env);
3049 }
3050 gen_set_label(l);
3051 tcg_temp_free_i32(t);
3052 }
3053 #else
3054 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3055 #endif
3056
3057 /* isync */
3058 static void gen_isync(DisasContext *ctx)
3059 {
3060 /*
3061 * We need to check for a pending TLB flush. This can only happen in
3062 * kernel mode however so check MSR_PR
3063 */
3064 if (!ctx->pr) {
3065 gen_check_tlb_flush(ctx, false);
3066 }
3067 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3068 gen_stop_exception(ctx);
3069 }
3070
3071 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3072
3073 static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
3074 {
3075 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3076 TCGv t0 = tcg_temp_new();
3077
3078 gen_set_access_type(ctx, ACCESS_RES);
3079 gen_addr_reg_index(ctx, t0);
3080 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3081 tcg_gen_mov_tl(cpu_reserve, t0);
3082 tcg_gen_mov_tl(cpu_reserve_val, gpr);
3083 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3084 tcg_temp_free(t0);
3085 }
3086
3087 #define LARX(name, memop) \
3088 static void gen_##name(DisasContext *ctx) \
3089 { \
3090 gen_load_locked(ctx, memop); \
3091 }
3092
3093 /* lwarx */
3094 LARX(lbarx, DEF_MEMOP(MO_UB))
3095 LARX(lharx, DEF_MEMOP(MO_UW))
3096 LARX(lwarx, DEF_MEMOP(MO_UL))
3097
3098 #define LD_ATOMIC(name, memop, tp, op, eop) \
3099 static void gen_##name(DisasContext *ctx) \
3100 { \
3101 int len = MEMOP_GET_SIZE(memop); \
3102 uint32_t gpr_FC = FC(ctx->opcode); \
3103 TCGv EA = tcg_temp_local_new(); \
3104 TCGv_##tp t0, t1; \
3105 \
3106 gen_addr_register(ctx, EA); \
3107 if (len > 1) { \
3108 gen_check_align(ctx, EA, len - 1); \
3109 } \
3110 t0 = tcg_temp_new_##tp(); \
3111 t1 = tcg_temp_new_##tp(); \
3112 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3113 \
3114 switch (gpr_FC) { \
3115 case 0: /* Fetch and add */ \
3116 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3117 break; \
3118 case 1: /* Fetch and xor */ \
3119 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3120 break; \
3121 case 2: /* Fetch and or */ \
3122 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3123 break; \
3124 case 3: /* Fetch and 'and' */ \
3125 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3126 break; \
3127 case 8: /* Swap */ \
3128 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3129 break; \
3130 case 4: /* Fetch and max unsigned */ \
3131 case 5: /* Fetch and max signed */ \
3132 case 6: /* Fetch and min unsigned */ \
3133 case 7: /* Fetch and min signed */ \
3134 case 16: /* compare and swap not equal */ \
3135 case 24: /* Fetch and increment bounded */ \
3136 case 25: /* Fetch and increment equal */ \
3137 case 28: /* Fetch and decrement bounded */ \
3138 gen_invalid(ctx); \
3139 break; \
3140 default: \
3141 /* invoke data storage error handler */ \
3142 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3143 } \
3144 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3145 tcg_temp_free_##tp(t0); \
3146 tcg_temp_free_##tp(t1); \
3147 tcg_temp_free(EA); \
3148 }
3149
3150 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3151 #if defined(TARGET_PPC64)
3152 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3153 #endif
3154
3155 #define ST_ATOMIC(name, memop, tp, op) \
3156 static void gen_##name(DisasContext *ctx) \
3157 { \
3158 int len = MEMOP_GET_SIZE(memop); \
3159 uint32_t gpr_FC = FC(ctx->opcode); \
3160 TCGv EA = tcg_temp_local_new(); \
3161 TCGv_##tp t0, t1; \
3162 \
3163 gen_addr_register(ctx, EA); \
3164 if (len > 1) { \
3165 gen_check_align(ctx, EA, len - 1); \
3166 } \
3167 t0 = tcg_temp_new_##tp(); \
3168 t1 = tcg_temp_new_##tp(); \
3169 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3170 \
3171 switch (gpr_FC) { \
3172 case 0: /* add and Store */ \
3173 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3174 break; \
3175 case 1: /* xor and Store */ \
3176 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3177 break; \
3178 case 2: /* Or and Store */ \
3179 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3180 break; \
3181 case 3: /* 'and' and Store */ \
3182 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3183 break; \
3184 case 4: /* Store max unsigned */ \
3185 case 5: /* Store max signed */ \
3186 case 6: /* Store min unsigned */ \
3187 case 7: /* Store min signed */ \
3188 case 24: /* Store twin */ \
3189 gen_invalid(ctx); \
3190 break; \
3191 default: \
3192 /* invoke data storage error handler */ \
3193 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3194 } \
3195 tcg_temp_free_##tp(t0); \
3196 tcg_temp_free_##tp(t1); \
3197 tcg_temp_free(EA); \
3198 }
3199
3200 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3201 #if defined(TARGET_PPC64)
3202 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3203 #endif
3204
3205 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
3206 {
3207 TCGLabel *l1 = gen_new_label();
3208 TCGLabel *l2 = gen_new_label();
3209 TCGv t0 = tcg_temp_new();
3210 int reg = rS(ctx->opcode);
3211
3212 gen_set_access_type(ctx, ACCESS_RES);
3213 gen_addr_reg_index(ctx, t0);
3214 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3215 tcg_temp_free(t0);
3216
3217 t0 = tcg_temp_new();
3218 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3219 cpu_gpr[reg], ctx->mem_idx,
3220 DEF_MEMOP(memop) | MO_ALIGN);
3221 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3222 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3223 tcg_gen_or_tl(t0, t0, cpu_so);
3224 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3225 tcg_temp_free(t0);
3226 tcg_gen_br(l2);
3227
3228 gen_set_label(l1);
3229
3230 /* Address mismatch implies failure. But we still need to provide the
3231 memory barrier semantics of the instruction. */
3232 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3233 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3234
3235 gen_set_label(l2);
3236 tcg_gen_movi_tl(cpu_reserve, -1);
3237 }
3238
3239 #define STCX(name, memop) \
3240 static void gen_##name(DisasContext *ctx) \
3241 { \
3242 gen_conditional_store(ctx, memop); \
3243 }
3244
3245 STCX(stbcx_, DEF_MEMOP(MO_UB))
3246 STCX(sthcx_, DEF_MEMOP(MO_UW))
3247 STCX(stwcx_, DEF_MEMOP(MO_UL))
3248
3249 #if defined(TARGET_PPC64)
3250 /* ldarx */
3251 LARX(ldarx, DEF_MEMOP(MO_Q))
3252 /* stdcx. */
3253 STCX(stdcx_, DEF_MEMOP(MO_Q))
3254
3255 /* lqarx */
3256 static void gen_lqarx(DisasContext *ctx)
3257 {
3258 int rd = rD(ctx->opcode);
3259 TCGv EA, hi, lo;
3260
3261 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3262 (rd == rB(ctx->opcode)))) {
3263 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3264 return;
3265 }
3266
3267 gen_set_access_type(ctx, ACCESS_RES);
3268 EA = tcg_temp_new();
3269 gen_addr_reg_index(ctx, EA);
3270
3271 /* Note that the low part is always in RD+1, even in LE mode. */
3272 lo = cpu_gpr[rd + 1];
3273 hi = cpu_gpr[rd];
3274
3275 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3276 #ifdef CONFIG_ATOMIC128
3277 TCGv_i32 oi = tcg_temp_new_i32();
3278 if (ctx->le_mode) {
3279 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
3280 ctx->mem_idx));
3281 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3282 } else {
3283 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
3284 ctx->mem_idx));
3285 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3286 }
3287 tcg_temp_free_i32(oi);
3288 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3289 #else
3290 /* Restart with exclusive lock. */
3291 gen_helper_exit_atomic(cpu_env);
3292 ctx->base.is_jmp = DISAS_NORETURN;
3293 tcg_temp_free(EA);
3294 return;
3295 #endif
3296 } else if (ctx->le_mode) {
3297 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
3298 tcg_gen_mov_tl(cpu_reserve, EA);
3299 gen_addr_add(ctx, EA, EA, 8);
3300 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3301 } else {
3302 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
3303 tcg_gen_mov_tl(cpu_reserve, EA);
3304 gen_addr_add(ctx, EA, EA, 8);
3305 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3306 }
3307 tcg_temp_free(EA);
3308
3309 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3310 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3311 }
3312
3313 /* stqcx. */
3314 static void gen_stqcx_(DisasContext *ctx)
3315 {
3316 int rs = rS(ctx->opcode);
3317 TCGv EA, hi, lo;
3318
3319 if (unlikely(rs & 1)) {
3320 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3321 return;
3322 }
3323
3324 gen_set_access_type(ctx, ACCESS_RES);
3325 EA = tcg_temp_new();
3326 gen_addr_reg_index(ctx, EA);
3327
3328 /* Note that the low part is always in RS+1, even in LE mode. */
3329 lo = cpu_gpr[rs + 1];
3330 hi = cpu_gpr[rs];
3331
3332 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3333 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
3334 #ifdef CONFIG_ATOMIC128
3335 if (ctx->le_mode) {
3336 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
3337 } else {
3338 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
3339 }
3340 #else
3341 /* Restart with exclusive lock. */
3342 gen_helper_exit_atomic(cpu_env);
3343 ctx->base.is_jmp = DISAS_NORETURN;
3344 #endif
3345 tcg_temp_free(EA);
3346 tcg_temp_free_i32(oi);
3347 } else {
3348 TCGLabel *lab_fail = gen_new_label();
3349 TCGLabel *lab_over = gen_new_label();
3350 TCGv_i64 t0 = tcg_temp_new_i64();
3351 TCGv_i64 t1 = tcg_temp_new_i64();
3352
3353 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
3354 tcg_temp_free(EA);
3355
3356 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
3357 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3358 ? offsetof(CPUPPCState, reserve_val2)
3359 : offsetof(CPUPPCState, reserve_val)));
3360 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3361
3362 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3363 gen_qemu_ld64_i64(ctx, t0, t0);
3364 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3365 ? offsetof(CPUPPCState, reserve_val)
3366 : offsetof(CPUPPCState, reserve_val2)));
3367 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3368
3369 /* Success */
3370 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
3371 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3372 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
3373
3374 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3375 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3376 tcg_gen_br(lab_over);
3377
3378 gen_set_label(lab_fail);
3379 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3380
3381 gen_set_label(lab_over);
3382 tcg_gen_movi_tl(cpu_reserve, -1);
3383 tcg_temp_free_i64(t0);
3384 tcg_temp_free_i64(t1);
3385 }
3386 }
3387 #endif /* defined(TARGET_PPC64) */
3388
3389 /* sync */
3390 static void gen_sync(DisasContext *ctx)
3391 {
3392 uint32_t l = (ctx->opcode >> 21) & 3;
3393
3394 /*
3395 * We may need to check for a pending TLB flush.
3396 *
3397 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3398 *
3399 * Additionally, this can only happen in kernel mode however so
3400 * check MSR_PR as well.
3401 */
3402 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3403 gen_check_tlb_flush(ctx, true);
3404 }
3405 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3406 }
3407
3408 /* wait */
3409 static void gen_wait(DisasContext *ctx)
3410 {
3411 TCGv_i32 t0 = tcg_const_i32(1);
3412 tcg_gen_st_i32(t0, cpu_env,
3413 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3414 tcg_temp_free_i32(t0);
3415 /* Stop translation, as the CPU is supposed to sleep from now */
3416 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3417 }
3418
3419 #if defined(TARGET_PPC64)
3420 static void gen_doze(DisasContext *ctx)
3421 {
3422 #if defined(CONFIG_USER_ONLY)
3423 GEN_PRIV;
3424 #else
3425 TCGv_i32 t;
3426
3427 CHK_HV;
3428 t = tcg_const_i32(PPC_PM_DOZE);
3429 gen_helper_pminsn(cpu_env, t);
3430 tcg_temp_free_i32(t);
3431 gen_stop_exception(ctx);
3432 #endif /* defined(CONFIG_USER_ONLY) */
3433 }
3434
3435 static void gen_nap(DisasContext *ctx)
3436 {
3437 #if defined(CONFIG_USER_ONLY)
3438 GEN_PRIV;
3439 #else
3440 TCGv_i32 t;
3441
3442 CHK_HV;
3443 t = tcg_const_i32(PPC_PM_NAP);
3444 gen_helper_pminsn(cpu_env, t);
3445 tcg_temp_free_i32(t);
3446 gen_stop_exception(ctx);
3447 #endif /* defined(CONFIG_USER_ONLY) */
3448 }
3449
3450 static void gen_stop(DisasContext *ctx)
3451 {
3452 gen_nap(ctx);
3453 }
3454
3455 static void gen_sleep(DisasContext *ctx)
3456 {
3457 #if defined(CONFIG_USER_ONLY)
3458 GEN_PRIV;
3459 #else
3460 TCGv_i32 t;
3461
3462 CHK_HV;
3463 t = tcg_const_i32(PPC_PM_SLEEP);
3464 gen_helper_pminsn(cpu_env, t);
3465 tcg_temp_free_i32(t);
3466 gen_stop_exception(ctx);
3467 #endif /* defined(CONFIG_USER_ONLY) */
3468 }
3469
3470 static void gen_rvwinkle(DisasContext *ctx)
3471 {
3472 #if defined(CONFIG_USER_ONLY)
3473 GEN_PRIV;
3474 #else
3475 TCGv_i32 t;
3476
3477 CHK_HV;
3478 t = tcg_const_i32(PPC_PM_RVWINKLE);
3479 gen_helper_pminsn(cpu_env, t);
3480 tcg_temp_free_i32(t);
3481 gen_stop_exception(ctx);
3482 #endif /* defined(CONFIG_USER_ONLY) */
3483 }
3484 #endif /* #if defined(TARGET_PPC64) */
3485
3486 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3487 {
3488 #if defined(TARGET_PPC64)
3489 if (ctx->has_cfar)
3490 tcg_gen_movi_tl(cpu_cfar, nip);
3491 #endif
3492 }
3493
3494 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3495 {
3496 if (unlikely(ctx->singlestep_enabled)) {
3497 return false;
3498 }
3499
3500 #ifndef CONFIG_USER_ONLY
3501 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3502 #else
3503 return true;
3504 #endif
3505 }
3506
3507 /*** Branch ***/
3508 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3509 {
3510 if (NARROW_MODE(ctx)) {
3511 dest = (uint32_t) dest;
3512 }
3513 if (use_goto_tb(ctx, dest)) {
3514 tcg_gen_goto_tb(n);
3515 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3516 tcg_gen_exit_tb(ctx->base.tb, n);
3517 } else {
3518 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3519 if (unlikely(ctx->singlestep_enabled)) {
3520 if ((ctx->singlestep_enabled &
3521 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3522 (ctx->exception == POWERPC_EXCP_BRANCH ||
3523 ctx->exception == POWERPC_EXCP_TRACE)) {
3524 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3525 }
3526 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3527 gen_debug_exception(ctx);
3528 }
3529 }
3530 tcg_gen_lookup_and_goto_ptr();
3531 }
3532 }
3533
3534 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3535 {
3536 if (NARROW_MODE(ctx)) {
3537 nip = (uint32_t)nip;
3538 }
3539 tcg_gen_movi_tl(cpu_lr, nip);
3540 }
3541
3542 /* b ba bl bla */
3543 static void gen_b(DisasContext *ctx)
3544 {
3545 target_ulong li, target;
3546
3547 ctx->exception = POWERPC_EXCP_BRANCH;
3548 /* sign extend LI */
3549 li = LI(ctx->opcode);
3550 li = (li ^ 0x02000000) - 0x02000000;
3551 if (likely(AA(ctx->opcode) == 0)) {
3552 target = ctx->base.pc_next + li - 4;
3553 } else {
3554 target = li;
3555 }
3556 if (LK(ctx->opcode)) {
3557 gen_setlr(ctx, ctx->base.pc_next);
3558 }
3559 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3560 gen_goto_tb(ctx, 0, target);
3561 }
3562
3563 #define BCOND_IM 0
3564 #define BCOND_LR 1
3565 #define BCOND_CTR 2
3566 #define BCOND_TAR 3
3567
3568 static void gen_bcond(DisasContext *ctx, int type)
3569 {
3570 uint32_t bo = BO(ctx->opcode);
3571 TCGLabel *l1;
3572 TCGv target;
3573
3574 ctx->exception = POWERPC_EXCP_BRANCH;
3575 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3576 target = tcg_temp_local_new();
3577 if (type == BCOND_CTR)
3578 tcg_gen_mov_tl(target, cpu_ctr);
3579 else if (type == BCOND_TAR)
3580 gen_load_spr(target, SPR_TAR);
3581 else
3582 tcg_gen_mov_tl(target, cpu_lr);
3583 } else {
3584 target = NULL;
3585 }
3586 if (LK(ctx->opcode))
3587 gen_setlr(ctx, ctx->base.pc_next);
3588 l1 = gen_new_label();
3589 if ((bo & 0x4) == 0) {
3590 /* Decrement and test CTR */
3591 TCGv temp = tcg_temp_new();
3592 if (unlikely(type == BCOND_CTR)) {
3593 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3594 return;
3595 }
3596 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3597 if (NARROW_MODE(ctx)) {
3598 tcg_gen_ext32u_tl(temp, cpu_ctr);
3599 } else {
3600 tcg_gen_mov_tl(temp, cpu_ctr);
3601 }
3602 if (bo & 0x2) {
3603 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3604 } else {
3605 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3606 }
3607 tcg_temp_free(temp);
3608 }
3609 if ((bo & 0x10) == 0) {
3610 /* Test CR */
3611 uint32_t bi = BI(ctx->opcode);
3612 uint32_t mask = 0x08 >> (bi & 0x03);
3613 TCGv_i32 temp = tcg_temp_new_i32();
3614
3615 if (bo & 0x8) {
3616 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3617 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3618 } else {
3619 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3620 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3621 }
3622 tcg_temp_free_i32(temp);
3623 }
3624 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3625 if (type == BCOND_IM) {
3626 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3627 if (likely(AA(ctx->opcode) == 0)) {
3628 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
3629 } else {
3630 gen_goto_tb(ctx, 0, li);
3631 }
3632 } else {
3633 if (NARROW_MODE(ctx)) {
3634 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3635 } else {
3636 tcg_gen_andi_tl(cpu_nip, target, ~3);
3637 }
3638 tcg_gen_lookup_and_goto_ptr();
3639 tcg_temp_free(target);
3640 }
3641 if ((bo & 0x14) != 0x14) {
3642 gen_set_label(l1);
3643 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3644 }
3645 }
3646
3647 static void gen_bc(DisasContext *ctx)
3648 {
3649 gen_bcond(ctx, BCOND_IM);
3650 }
3651
3652 static void gen_bcctr(DisasContext *ctx)
3653 {
3654 gen_bcond(ctx, BCOND_CTR);
3655 }
3656
3657 static void gen_bclr(DisasContext *ctx)
3658 {
3659 gen_bcond(ctx, BCOND_LR);
3660 }
3661
3662 static void gen_bctar(DisasContext *ctx)
3663 {
3664 gen_bcond(ctx, BCOND_TAR);
3665 }
3666
3667 /*** Condition register logical ***/
3668 #define GEN_CRLOGIC(name, tcg_op, opc) \
3669 static void glue(gen_, name)(DisasContext *ctx) \
3670 { \
3671 uint8_t bitmask; \
3672 int sh; \
3673 TCGv_i32 t0, t1; \
3674 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3675 t0 = tcg_temp_new_i32(); \
3676 if (sh > 0) \
3677 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3678 else if (sh < 0) \
3679 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3680 else \
3681 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3682 t1 = tcg_temp_new_i32(); \
3683 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3684 if (sh > 0) \
3685 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3686 else if (sh < 0) \
3687 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3688 else \
3689 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3690 tcg_op(t0, t0, t1); \
3691 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3692 tcg_gen_andi_i32(t0, t0, bitmask); \
3693 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3694 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3695 tcg_temp_free_i32(t0); \
3696 tcg_temp_free_i32(t1); \
3697 }
3698
3699 /* crand */
3700 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3701 /* crandc */
3702 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3703 /* creqv */
3704 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3705 /* crnand */
3706 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3707 /* crnor */
3708 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3709 /* cror */
3710 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3711 /* crorc */
3712 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3713 /* crxor */
3714 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3715
3716 /* mcrf */
3717 static void gen_mcrf(DisasContext *ctx)
3718 {
3719 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3720 }
3721
3722 /*** System linkage ***/
3723
3724 /* rfi (supervisor only) */
3725 static void gen_rfi(DisasContext *ctx)
3726 {
3727 #if defined(CONFIG_USER_ONLY)
3728 GEN_PRIV;
3729 #else
3730 /* This instruction doesn't exist anymore on 64-bit server
3731 * processors compliant with arch 2.x
3732 */
3733 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3734 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3735 return;
3736 }
3737 /* Restore CPU state */
3738 CHK_SV;
3739 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3740 gen_helper_rfi(cpu_env);
3741 gen_sync_exception(ctx);
3742 #endif
3743 }
3744
3745 #if defined(TARGET_PPC64)
3746 static void gen_rfid(DisasContext *ctx)
3747 {
3748 #if defined(CONFIG_USER_ONLY)
3749 GEN_PRIV;
3750 #else
3751 /* Restore CPU state */
3752 CHK_SV;
3753 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3754 gen_helper_rfid(cpu_env);
3755 gen_sync_exception(ctx);
3756 #endif
3757 }
3758
3759 static void gen_hrfid(DisasContext *ctx)
3760 {
3761 #if defined(CONFIG_USER_ONLY)
3762 GEN_PRIV;
3763 #else
3764 /* Restore CPU state */
3765 CHK_HV;
3766 gen_helper_hrfid(cpu_env);
3767 gen_sync_exception(ctx);
3768 #endif
3769 }
3770 #endif
3771
3772 /* sc */
3773 #if defined(CONFIG_USER_ONLY)
3774 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3775 #else
3776 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3777 #endif
3778 static void gen_sc(DisasContext *ctx)
3779 {
3780 uint32_t lev;
3781
3782 lev = (ctx->opcode >> 5) & 0x7F;
3783 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3784 }
3785
3786 /*** Trap ***/
3787
3788 /* Check for unconditional traps (always or never) */
3789 static bool check_unconditional_trap(DisasContext *ctx)
3790 {
3791 /* Trap never */
3792 if (TO(ctx->opcode) == 0) {
3793 return true;
3794 }
3795 /* Trap always */
3796 if (TO(ctx->opcode) == 31) {
3797 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3798 return true;
3799 }
3800 return false;
3801 }
3802
3803 /* tw */
3804 static void gen_tw(DisasContext *ctx)
3805 {
3806 TCGv_i32 t0;
3807
3808 if (check_unconditional_trap(ctx)) {
3809 return;
3810 }
3811 t0 = tcg_const_i32(TO(ctx->opcode));
3812 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3813 t0);
3814 tcg_temp_free_i32(t0);
3815 }
3816
3817 /* twi */
3818 static void gen_twi(DisasContext *ctx)
3819 {
3820 TCGv t0;
3821 TCGv_i32 t1;
3822
3823 if (check_unconditional_trap(ctx)) {
3824 return;
3825 }
3826 t0 = tcg_const_tl(SIMM(ctx->opcode));
3827 t1 = tcg_const_i32(TO(ctx->opcode));
3828 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3829 tcg_temp_free(t0);
3830 tcg_temp_free_i32(t1);
3831 }
3832
3833 #if defined(TARGET_PPC64)
3834 /* td */
3835 static void gen_td(DisasContext *ctx)
3836 {
3837 TCGv_i32 t0;
3838
3839 if (check_unconditional_trap(ctx)) {
3840 return;
3841 }
3842 t0 = tcg_const_i32(TO(ctx->opcode));
3843 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3844 t0);
3845 tcg_temp_free_i32(t0);
3846 }
3847
3848 /* tdi */
3849 static void gen_tdi(DisasContext *ctx)
3850 {
3851 TCGv t0;
3852 TCGv_i32 t1;
3853
3854 if (check_unconditional_trap(ctx)) {
3855 return;
3856 }
3857 t0 = tcg_const_tl(SIMM(ctx->opcode));
3858 t1 = tcg_const_i32(TO(ctx->opcode));
3859 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3860 tcg_temp_free(t0);
3861 tcg_temp_free_i32(t1);
3862 }
3863 #endif
3864
3865 /*** Processor control ***/
3866
3867 static void gen_read_xer(DisasContext *ctx, TCGv dst)
3868 {
3869 TCGv t0 = tcg_temp_new();
3870 TCGv t1 = tcg_temp_new();
3871 TCGv t2 = tcg_temp_new();
3872 tcg_gen_mov_tl(dst, cpu_xer);
3873 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3874 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3875 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3876 tcg_gen_or_tl(t0, t0, t1);
3877 tcg_gen_or_tl(dst, dst, t2);
3878 tcg_gen_or_tl(dst, dst, t0);
3879 if (is_isa300(ctx)) {
3880 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3881 tcg_gen_or_tl(dst, dst, t0);
3882 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3883 tcg_gen_or_tl(dst, dst, t0);
3884 }
3885 tcg_temp_free(t0);
3886 tcg_temp_free(t1);
3887 tcg_temp_free(t2);
3888 }
3889
3890 static void gen_write_xer(TCGv src)
3891 {
3892 /* Write all flags, while reading back check for isa300 */
3893 tcg_gen_andi_tl(cpu_xer, src,
3894 ~((1u << XER_SO) |
3895 (1u << XER_OV) | (1u << XER_OV32) |
3896 (1u << XER_CA) | (1u << XER_CA32)));
3897 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3898 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
3899 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3900 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3901 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3902 }
3903
3904 /* mcrxr */
3905 static void gen_mcrxr(DisasContext *ctx)
3906 {
3907 TCGv_i32 t0 = tcg_temp_new_i32();
3908 TCGv_i32 t1 = tcg_temp_new_i32();
3909 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3910
3911 tcg_gen_trunc_tl_i32(t0, cpu_so);
3912 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3913 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3914 tcg_gen_shli_i32(t0, t0, 3);
3915 tcg_gen_shli_i32(t1, t1, 2);
3916 tcg_gen_shli_i32(dst, dst, 1);
3917 tcg_gen_or_i32(dst, dst, t0);
3918 tcg_gen_or_i32(dst, dst, t1);
3919 tcg_temp_free_i32(t0);
3920 tcg_temp_free_i32(t1);
3921
3922 tcg_gen_movi_tl(cpu_so, 0);
3923 tcg_gen_movi_tl(cpu_ov, 0);
3924 tcg_gen_movi_tl(cpu_ca, 0);
3925 }
3926
3927 #ifdef TARGET_PPC64
3928 /* mcrxrx */
3929 static void gen_mcrxrx(DisasContext *ctx)
3930 {
3931 TCGv t0 = tcg_temp_new();
3932 TCGv t1 = tcg_temp_new();
3933 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3934
3935 /* copy OV and OV32 */
3936 tcg_gen_shli_tl(t0, cpu_ov, 1);
3937 tcg_gen_or_tl(t0, t0, cpu_ov32);
3938 tcg_gen_shli_tl(t0, t0, 2);
3939 /* copy CA and CA32 */
3940 tcg_gen_shli_tl(t1, cpu_ca, 1);
3941 tcg_gen_or_tl(t1, t1, cpu_ca32);
3942 tcg_gen_or_tl(t0, t0, t1);
3943 tcg_gen_trunc_tl_i32(dst, t0);
3944 tcg_temp_free(t0);
3945 tcg_temp_free(t1);
3946 }
3947 #endif
3948
3949 /* mfcr mfocrf */
3950 static void gen_mfcr(DisasContext *ctx)
3951 {
3952 uint32_t crm, crn;
3953
3954 if (likely(ctx->opcode & 0x00100000)) {
3955 crm = CRM(ctx->opcode);
3956 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3957 crn = ctz32 (crm);
3958 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3959 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3960 cpu_gpr[rD(ctx->opcode)], crn * 4);
3961 }
3962 } else {
3963 TCGv_i32 t0 = tcg_temp_new_i32();
3964 tcg_gen_mov_i32(t0, cpu_crf[0]);
3965 tcg_gen_shli_i32(t0, t0, 4);
3966 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3967 tcg_gen_shli_i32(t0, t0, 4);
3968 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3969 tcg_gen_shli_i32(t0, t0, 4);
3970 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3971 tcg_gen_shli_i32(t0, t0, 4);
3972 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3973 tcg_gen_shli_i32(t0, t0, 4);
3974 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3975 tcg_gen_shli_i32(t0, t0, 4);
3976 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3977 tcg_gen_shli_i32(t0, t0, 4);
3978 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3979 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3980 tcg_temp_free_i32(t0);
3981 }
3982 }
3983
3984 /* mfmsr */
3985 static void gen_mfmsr(DisasContext *ctx)
3986 {
3987 CHK_SV;
3988 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3989 }
3990
3991 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3992 {
3993 #if 0
3994 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3995 printf("ERROR: try to access SPR %d !\n", sprn);
3996 #endif
3997 }
3998 #define SPR_NOACCESS (&spr_noaccess)
3999
4000 /* mfspr */
4001 static inline void gen_op_mfspr(DisasContext *ctx)
4002 {
4003 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4004 uint32_t sprn = SPR(ctx->opcode);
4005
4006 #if defined(CONFIG_USER_ONLY)
4007 read_cb = ctx->spr_cb[sprn].uea_read;
4008 #else
4009 if (ctx->pr) {
4010 read_cb = ctx->spr_cb[sprn].uea_read;
4011 } else if (ctx->hv) {
4012 read_cb = ctx->spr_cb[sprn].hea_read;
4013 } else {
4014 read_cb = ctx->spr_cb[sprn].oea_read;
4015 }
4016 #endif
4017 if (likely(read_cb != NULL)) {
4018 if (likely(read_cb != SPR_NOACCESS)) {
4019 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4020 } else {
4021 /* Privilege exception */
4022 /* This is a hack to avoid warnings when running Linux:
4023 * this OS breaks the PowerPC virtualisation model,
4024 * allowing userland application to read the PVR
4025 */
4026 if (sprn != SPR_PVR) {
4027 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4028 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4029 ctx->base.pc_next - 4);
4030 }
4031 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4032 }
4033 } else {
4034 /* ISA 2.07 defines these as no-ops */
4035 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4036 (sprn >= 808 && sprn <= 811)) {
4037 /* This is a nop */
4038 return;
4039 }
4040 /* Not defined */
4041 qemu_log_mask(LOG_GUEST_ERROR,
4042 "Trying to read invalid spr %d (0x%03x) at "
4043 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4044
4045 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4046 * it can generate a priv, a hv emu or a no-op
4047 */
4048 if (sprn & 0x10) {
4049 if (ctx->pr) {
4050 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4051 }
4052 } else {
4053 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4054 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4055 }
4056 }
4057 }
4058 }
4059
4060 static void gen_mfspr(DisasContext *ctx)
4061 {
4062 gen_op_mfspr(ctx);
4063 }
4064
4065 /* mftb */
4066 static void gen_mftb(DisasContext *ctx)
4067 {
4068 gen_op_mfspr(ctx);
4069 }
4070
4071 /* mtcrf mtocrf*/
4072 static void gen_mtcrf(DisasContext *ctx)
4073 {
4074 uint32_t crm, crn;
4075
4076 crm = CRM(ctx->opcode);
4077 if (likely((ctx->opcode & 0x00100000))) {
4078 if (crm && ((crm & (crm - 1)) == 0)) {
4079 TCGv_i32 temp = tcg_temp_new_i32();
4080 crn = ctz32 (crm);
4081 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4082 tcg_gen_shri_i32(temp, temp, crn * 4);
4083 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4084 tcg_temp_free_i32(temp);
4085 }
4086 } else {
4087 TCGv_i32 temp = tcg_temp_new_i32();
4088 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4089 for (crn = 0 ; crn < 8 ; crn++) {
4090 if (crm & (1 << crn)) {
4091 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4092 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4093 }
4094 }
4095 tcg_temp_free_i32(temp);
4096 }
4097 }
4098
4099 /* mtmsr */
4100 #if defined(TARGET_PPC64)
4101 static void gen_mtmsrd(DisasContext *ctx)
4102 {
4103 CHK_SV;
4104
4105 #if !defined(CONFIG_USER_ONLY)
4106 if (ctx->opcode & 0x00010000) {
4107 /* Special form that does not need any synchronisation */
4108 TCGv t0 = tcg_temp_new();
4109 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4110 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4111 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4112 tcg_temp_free(t0);
4113 } else {
4114 /* XXX: we need to update nip before the store
4115 * if we enter power saving mode, we will exit the loop
4116 * directly from ppc_store_msr
4117 */
4118 gen_update_nip(ctx, ctx->base.pc_next);
4119 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4120 /* Must stop the translation as machine state (may have) changed */
4121 /* Note that mtmsr is not always defined as context-synchronizing */
4122 gen_stop_exception(ctx);
4123 }
4124 #endif /* !defined(CONFIG_USER_ONLY) */
4125 }
4126 #endif /* defined(TARGET_PPC64) */
4127
4128 static void gen_mtmsr(DisasContext *ctx)
4129 {
4130 CHK_SV;
4131
4132 #if !defined(CONFIG_USER_ONLY)
4133 if (ctx->opcode & 0x00010000) {
4134 /* Special form that does not need any synchronisation */
4135 TCGv t0 = tcg_temp_new();
4136 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4137 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4138 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4139 tcg_temp_free(t0);
4140 } else {
4141 TCGv msr = tcg_temp_new();
4142
4143 /* XXX: we need to update nip before the store
4144 * if we enter power saving mode, we will exit the loop
4145 * directly from ppc_store_msr
4146 */
4147 gen_update_nip(ctx, ctx->base.pc_next);
4148 #if defined(TARGET_PPC64)
4149 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4150 #else
4151 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4152 #endif
4153 gen_helper_store_msr(cpu_env, msr);
4154 tcg_temp_free(msr);
4155 /* Must stop the translation as machine state (may have) changed */
4156 /* Note that mtmsr is not always defined as context-synchronizing */
4157 gen_stop_exception(ctx);
4158 }
4159 #endif
4160 }
4161
4162 /* mtspr */
4163 static void gen_mtspr(DisasContext *ctx)
4164 {
4165 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4166 uint32_t sprn = SPR(ctx->opcode);
4167
4168 #if defined(CONFIG_USER_ONLY)
4169 write_cb = ctx->spr_cb[sprn].uea_write;
4170 #else
4171 if (ctx->pr) {
4172 write_cb = ctx->spr_cb[sprn].uea_write;
4173 } else if (ctx->hv) {
4174 write_cb = ctx->spr_cb[sprn].hea_write;
4175 } else {
4176 write_cb = ctx->spr_cb[sprn].oea_write;
4177 }
4178 #endif
4179 if (likely(write_cb != NULL)) {
4180 if (likely(write_cb != SPR_NOACCESS)) {
4181 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4182 } else {
4183 /* Privilege exception */
4184 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4185 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4186 ctx->base.pc_next - 4);
4187 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4188 }
4189 } else {
4190 /* ISA 2.07 defines these as no-ops */
4191 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4192 (sprn >= 808 && sprn <= 811)) {
4193 /* This is a nop */
4194 return;
4195 }
4196
4197 /* Not defined */
4198 qemu_log_mask(LOG_GUEST_ERROR,
4199 "Trying to write invalid spr %d (0x%03x) at "
4200 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4201
4202
4203 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4204 * it can generate a priv, a hv emu or a no-op
4205 */
4206 if (sprn & 0x10) {
4207 if (ctx->pr) {
4208 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4209 }
4210 } else {
4211 if (ctx->pr || sprn == 0) {
4212 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4213 }
4214 }
4215 }
4216 }
4217
4218 #if defined(TARGET_PPC64)
4219 /* setb */
4220 static void gen_setb(DisasContext *ctx)
4221 {
4222 TCGv_i32 t0 = tcg_temp_new_i32();
4223 TCGv_i32 t8 = tcg_temp_new_i32();
4224 TCGv_i32 tm1 = tcg_temp_new_i32();
4225 int crf = crfS(ctx->opcode);
4226
4227 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4228 tcg_gen_movi_i32(t8, 8);
4229 tcg_gen_movi_i32(tm1, -1);
4230 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4231 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4232
4233 tcg_temp_free_i32(t0);
4234 tcg_temp_free_i32(t8);
4235 tcg_temp_free_i32(tm1);
4236 }
4237 #endif
4238
4239 /*** Cache management ***/
4240
4241 /* dcbf */
4242 static void gen_dcbf(DisasContext *ctx)
4243 {
4244 /* XXX: specification says this is treated as a load by the MMU */
4245 TCGv t0;
4246 gen_set_access_type(ctx, ACCESS_CACHE);
4247 t0 = tcg_temp_new();
4248 gen_addr_reg_index(ctx, t0);
4249 gen_qemu_ld8u(ctx, t0, t0);
4250 tcg_temp_free(t0);
4251 }
4252
4253 /* dcbi (Supervisor only) */
4254 static void gen_dcbi(DisasContext *ctx)
4255 {
4256 #if defined(CONFIG_USER_ONLY)
4257 GEN_PRIV;
4258 #else
4259 TCGv EA, val;
4260
4261 CHK_SV;
4262 EA = tcg_temp_new();
4263 gen_set_access_type(ctx, ACCESS_CACHE);
4264 gen_addr_reg_index(ctx, EA);
4265 val = tcg_temp_new();
4266 /* XXX: specification says this should be treated as a store by the MMU */
4267 gen_qemu_ld8u(ctx, val, EA);
4268 gen_qemu_st8(ctx, val, EA);
4269 tcg_temp_free(val);
4270 tcg_temp_free(EA);
4271 #endif /* defined(CONFIG_USER_ONLY) */
4272 }
4273
4274 /* dcdst */
4275 static void gen_dcbst(DisasContext *ctx)
4276 {
4277 /* XXX: specification say this is treated as a load by the MMU */
4278 TCGv t0;
4279 gen_set_access_type(ctx, ACCESS_CACHE);
4280 t0 = tcg_temp_new();
4281 gen_addr_reg_index(ctx, t0);
4282 gen_qemu_ld8u(ctx, t0, t0);
4283 tcg_temp_free(t0);
4284 }
4285
4286 /* dcbt */
4287 static void gen_dcbt(DisasContext *ctx)
4288 {
4289 /* interpreted as no-op */
4290 /* XXX: specification say this is treated as a load by the MMU
4291 * but does not generate any exception
4292 */
4293 }
4294
4295 /* dcbtst */
4296 static void gen_dcbtst(DisasContext *ctx)
4297 {
4298 /* interpreted as no-op */
4299 /* XXX: specification say this is treated as a load by the MMU
4300 * but does not generate any exception
4301 */
4302 }
4303
4304 /* dcbtls */
4305 static void gen_dcbtls(DisasContext *ctx)
4306 {
4307 /* Always fails locking the cache */
4308 TCGv t0 = tcg_temp_new();
4309 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4310 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4311 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4312 tcg_temp_free(t0);
4313 }
4314
4315 /* dcbz */
4316 static void gen_dcbz(DisasContext *ctx)
4317 {
4318 TCGv tcgv_addr;
4319 TCGv_i32 tcgv_op;
4320
4321 gen_set_access_type(ctx, ACCESS_CACHE);
4322 tcgv_addr = tcg_temp_new();
4323 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4324 gen_addr_reg_index(ctx, tcgv_addr);
4325 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4326 tcg_temp_free(tcgv_addr);
4327 tcg_temp_free_i32(tcgv_op);
4328 }
4329
4330 /* dst / dstt */
4331 static void gen_dst(DisasContext *ctx)
4332 {
4333 if (rA(ctx->opcode) == 0) {
4334 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4335 } else {
4336 /* interpreted as no-op */
4337 }
4338 }
4339
4340 /* dstst /dststt */
4341 static void gen_dstst(DisasContext *ctx)
4342 {
4343 if (rA(ctx->opcode) == 0) {
4344 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4345 } else {
4346 /* interpreted as no-op */
4347 }
4348
4349 }
4350
4351 /* dss / dssall */
4352 static void gen_dss(DisasContext *ctx)
4353 {
4354 /* interpreted as no-op */
4355 }
4356
4357 /* icbi */
4358 static void gen_icbi(DisasContext *ctx)
4359 {
4360 TCGv t0;
4361 gen_set_access_type(ctx, ACCESS_CACHE);
4362 t0 = tcg_temp_new();
4363 gen_addr_reg_index(ctx, t0);
4364 gen_helper_icbi(cpu_env, t0);
4365 tcg_temp_free(t0);
4366 }
4367
4368 /* Optional: */
4369 /* dcba */
4370 static void gen_dcba(DisasContext *ctx)
4371 {
4372 /* interpreted as no-op */
4373 /* XXX: specification say this is treated as a store by the MMU
4374 * but does not generate any exception
4375 */
4376 }
4377
4378 /*** Segment register manipulation ***/
4379 /* Supervisor only: */
4380
4381 /* mfsr */
4382 static void gen_mfsr(DisasContext *ctx)
4383 {
4384 #if defined(CONFIG_USER_ONLY)
4385 GEN_PRIV;
4386 #else
4387 TCGv t0;
4388
4389 CHK_SV;
4390 t0 = tcg_const_tl(SR(ctx->opcode));
4391 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4392 tcg_temp_free(t0);
4393 #endif /* defined(CONFIG_USER_ONLY) */
4394 }
4395
4396 /* mfsrin */
4397 static void gen_mfsrin(DisasContext *ctx)
4398 {
4399 #if defined(CONFIG_USER_ONLY)
4400 GEN_PRIV;
4401 #else
4402 TCGv t0;
4403
4404 CHK_SV;
4405 t0 = tcg_temp_new();
4406 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4407 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4408 tcg_temp_free(t0);
4409 #endif /* defined(CONFIG_USER_ONLY) */
4410 }
4411
4412 /* mtsr */
4413 static void gen_mtsr(DisasContext *ctx)
4414 {
4415 #if defined(CONFIG_USER_ONLY)
4416 GEN_PRIV;
4417 #else
4418 TCGv t0;
4419
4420 CHK_SV;
4421 t0 = tcg_const_tl(SR(ctx->opcode));
4422 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4423 tcg_temp_free(t0);
4424 #endif /* defined(CONFIG_USER_ONLY) */
4425 }
4426
4427 /* mtsrin */
4428 static void gen_mtsrin(DisasContext *ctx)
4429 {
4430 #if defined(CONFIG_USER_ONLY)
4431 GEN_PRIV;
4432 #else
4433 TCGv t0;
4434 CHK_SV;
4435
4436 t0 = tcg_temp_new();
4437 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4438 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4439 tcg_temp_free(t0);
4440 #endif /* defined(CONFIG_USER_ONLY) */
4441 }
4442
4443 #if defined(TARGET_PPC64)
4444 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4445
4446 /* mfsr */
4447 static void gen_mfsr_64b(DisasContext *ctx)
4448 {
4449 #if defined(CONFIG_USER_ONLY)
4450 GEN_PRIV;
4451 #else
4452 TCGv t0;
4453
4454 CHK_SV;
4455 t0 = tcg_const_tl(SR(ctx->opcode));
4456 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4457 tcg_temp_free(t0);
4458 #endif /* defined(CONFIG_USER_ONLY) */
4459 }
4460
4461 /* mfsrin */
4462 static void gen_mfsrin_64b(DisasContext *ctx)
4463 {
4464 #if defined(CONFIG_USER_ONLY)
4465 GEN_PRIV;
4466 #else
4467 TCGv t0;
4468
4469 CHK_SV;
4470 t0 = tcg_temp_new();
4471 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4472 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4473 tcg_temp_free(t0);
4474 #endif /* defined(CONFIG_USER_ONLY) */
4475 }
4476
4477 /* mtsr */
4478 static void gen_mtsr_64b(DisasContext *ctx)
4479 {
4480 #if defined(CONFIG_USER_ONLY)
4481 GEN_PRIV;
4482 #else
4483 TCGv t0;
4484
4485 CHK_SV;
4486 t0 = tcg_const_tl(SR(ctx->opcode));
4487 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4488 tcg_temp_free(t0);
4489 #endif /* defined(CONFIG_USER_ONLY) */
4490 }
4491
4492 /* mtsrin */
4493 static void gen_mtsrin_64b(DisasContext *ctx)
4494 {
4495 #if defined(CONFIG_USER_ONLY)
4496 GEN_PRIV;
4497 #else
4498 TCGv t0;
4499
4500 CHK_SV;
4501 t0 = tcg_temp_new();
4502 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4503 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4504 tcg_temp_free(t0);
4505 #endif /* defined(CONFIG_USER_ONLY) */
4506 }
4507
4508 /* slbmte */
4509 static void gen_slbmte(DisasContext *ctx)
4510 {
4511 #if defined(CONFIG_USER_ONLY)
4512 GEN_PRIV;
4513 #else
4514 CHK_SV;
4515
4516 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4517 cpu_gpr[rS(ctx->opcode)]);
4518 #endif /* defined(CONFIG_USER_ONLY) */
4519 }
4520
4521 static void gen_slbmfee(DisasContext *ctx)
4522 {
4523 #if defined(CONFIG_USER_ONLY)
4524 GEN_PRIV;
4525 #else
4526 CHK_SV;
4527
4528 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4529 cpu_gpr[rB(ctx->opcode)]);
4530 #endif /* defined(CONFIG_USER_ONLY) */
4531 }
4532
4533 static void gen_slbmfev(DisasContext *ctx)
4534 {
4535 #if defined(CONFIG_USER_ONLY)
4536 GEN_PRIV;
4537 #else
4538 CHK_SV;
4539
4540 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4541 cpu_gpr[rB(ctx->opcode)]);
4542 #endif /* defined(CONFIG_USER_ONLY) */
4543 }
4544
4545 static void gen_slbfee_(DisasContext *ctx)
4546 {
4547 #if defined(CONFIG_USER_ONLY)
4548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4549 #else
4550 TCGLabel *l1, *l2;
4551
4552 if (unlikely(ctx->pr)) {
4553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4554 return;
4555 }
4556 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4557 cpu_gpr[rB(ctx->opcode)]);
4558 l1 = gen_new_label();
4559 l2 = gen_new_label();
4560 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4561 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4562 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4563 tcg_gen_br(l2);
4564 gen_set_label(l1);
4565 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4566 gen_set_label(l2);
4567 #endif
4568 }
4569 #endif /* defined(TARGET_PPC64) */
4570
4571 /*** Lookaside buffer management ***/
4572 /* Optional & supervisor only: */
4573
4574 /* tlbia */
4575 static void gen_tlbia(DisasContext *ctx)
4576 {
4577 #if defined(CONFIG_USER_ONLY)
4578 GEN_PRIV;
4579 #else
4580 CHK_HV;
4581
4582 gen_helper_tlbia(cpu_env);
4583 #endif /* defined(CONFIG_USER_ONLY) */
4584 }
4585
4586 /* tlbiel */
4587 static void gen_tlbiel(DisasContext *ctx)
4588 {
4589 #if defined(CONFIG_USER_ONLY)
4590 GEN_PRIV;
4591 #else
4592 CHK_SV;
4593
4594 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4595 #endif /* defined(CONFIG_USER_ONLY) */
4596 }
4597
4598 /* tlbie */
4599 static void gen_tlbie(DisasContext *ctx)
4600 {
4601 #if defined(CONFIG_USER_ONLY)
4602 GEN_PRIV;
4603 #else
4604 TCGv_i32 t1;
4605
4606 if (ctx->gtse) {
4607 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
4608 } else {
4609 CHK_HV; /* Else hypervisor privileged */
4610 }
4611
4612 if (NARROW_MODE(ctx)) {
4613 TCGv t0 = tcg_temp_new();
4614 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4615 gen_helper_tlbie(cpu_env, t0);
4616 tcg_temp_free(t0);
4617 } else {
4618 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4619 }
4620 t1 = tcg_temp_new_i32();
4621 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4622 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4623 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4624 tcg_temp_free_i32(t1);
4625 #endif /* defined(CONFIG_USER_ONLY) */
4626 }
4627
4628 /* tlbsync */
4629 static void gen_tlbsync(DisasContext *ctx)
4630 {
4631 #if defined(CONFIG_USER_ONLY)
4632 GEN_PRIV;
4633 #else
4634
4635 if (ctx->gtse) {
4636 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
4637 } else {
4638 CHK_HV; /* Else hypervisor privileged */
4639 }
4640
4641 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4642 if (ctx->insns_flags & PPC_BOOKE) {
4643 gen_check_tlb_flush(ctx, true);
4644 }
4645 #endif /* defined(CONFIG_USER_ONLY) */
4646 }
4647
4648 #if defined(TARGET_PPC64)
4649 /* slbia */
4650 static void gen_slbia(DisasContext *ctx)
4651 {
4652 #if defined(CONFIG_USER_ONLY)
4653 GEN_PRIV;
4654 #else
4655 CHK_SV;
4656
4657 gen_helper_slbia(cpu_env);
4658 #endif /* defined(CONFIG_USER_ONLY) */
4659 }
4660
4661 /* slbie */
4662 static void gen_slbie(DisasContext *ctx)
4663 {
4664 #if defined(CONFIG_USER_ONLY)
4665 GEN_PRIV;
4666 #else
4667 CHK_SV;
4668
4669 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4670 #endif /* defined(CONFIG_USER_ONLY) */
4671 }
4672
4673 /* slbieg */
4674 static void gen_slbieg(DisasContext *ctx)
4675 {
4676 #if defined(CONFIG_USER_ONLY)
4677 GEN_PRIV;
4678 #else
4679 CHK_SV;
4680
4681 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4682 #endif /* defined(CONFIG_USER_ONLY) */
4683 }
4684
4685 /* slbsync */
4686 static void gen_slbsync(DisasContext *ctx)
4687 {
4688 #if defined(CONFIG_USER_ONLY)
4689 GEN_PRIV;
4690 #else
4691 CHK_SV;
4692 gen_check_tlb_flush(ctx, true);
4693 #endif /* defined(CONFIG_USER_ONLY) */
4694 }
4695
4696 #endif /* defined(TARGET_PPC64) */
4697
4698 /*** External control ***/
4699 /* Optional: */
4700
4701 /* eciwx */
4702 static void gen_eciwx(DisasContext *ctx)
4703 {
4704 TCGv t0;
4705 /* Should check EAR[E] ! */
4706 gen_set_access_type(ctx, ACCESS_EXT);
4707 t0 = tcg_temp_new();
4708 gen_addr_reg_index(ctx, t0);
4709 gen_check_align(ctx, t0, 0x03);
4710 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4711 tcg_temp_free(t0);
4712 }
4713
4714 /* ecowx */
4715 static void gen_ecowx(DisasContext *ctx)
4716 {
4717 TCGv t0;
4718 /* Should check EAR[E] ! */
4719 gen_set_access_type(ctx, ACCESS_EXT);
4720 t0 = tcg_temp_new();
4721 gen_addr_reg_index(ctx, t0);
4722 gen_check_align(ctx, t0, 0x03);
4723 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4724 tcg_temp_free(t0);
4725 }
4726
4727 /* PowerPC 601 specific instructions */
4728
4729 /* abs - abs. */
4730 static void gen_abs(DisasContext *ctx)
4731 {
4732 TCGLabel *l1 = gen_new_label();
4733 TCGLabel *l2 = gen_new_label();
4734 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4735 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4736 tcg_gen_br(l2);
4737 gen_set_label(l1);
4738 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4739 gen_set_label(l2);
4740 if (unlikely(Rc(ctx->opcode) != 0))
4741 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4742 }
4743
4744 /* abso - abso. */
4745 static void gen_abso(DisasContext *ctx)
4746 {
4747 TCGLabel *l1 = gen_new_label();
4748 TCGLabel *l2 = gen_new_label();
4749 TCGLabel *l3 = gen_new_label();
4750 /* Start with XER OV disabled, the most likely case */
4751 tcg_gen_movi_tl(cpu_ov, 0);
4752 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4753 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4754 tcg_gen_movi_tl(cpu_ov, 1);
4755 tcg_gen_movi_tl(cpu_so, 1);
4756 tcg_gen_br(l2);
4757 gen_set_label(l1);
4758 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4759 tcg_gen_br(l3);
4760 gen_set_label(l2);
4761 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4762 gen_set_label(l3);
4763 if (unlikely(Rc(ctx->opcode) != 0))
4764 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4765 }
4766
4767 /* clcs */
4768 static void gen_clcs(DisasContext *ctx)
4769 {
4770 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4771 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4772 tcg_temp_free_i32(t0);
4773 /* Rc=1 sets CR0 to an undefined state */
4774 }
4775
4776 /* div - div. */
4777 static void gen_div(DisasContext *ctx)
4778 {
4779 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4780 cpu_gpr[rB(ctx->opcode)]);
4781 if (unlikely(Rc(ctx->opcode) != 0))
4782 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4783 }
4784
4785 /* divo - divo. */
4786 static void gen_divo(DisasContext *ctx)
4787 {
4788 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4789 cpu_gpr[rB(ctx->opcode)]);
4790 if (unlikely(Rc(ctx->opcode) != 0))
4791 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4792 }
4793
4794 /* divs - divs. */
4795 static void gen_divs(DisasContext *ctx)
4796 {
4797 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4798 cpu_gpr[rB(ctx->opcode)]);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4801 }
4802
4803 /* divso - divso. */
4804 static void gen_divso(DisasContext *ctx)
4805 {
4806 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4807 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4808 if (unlikely(Rc(ctx->opcode) != 0))
4809 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4810 }
4811
4812 /* doz - doz. */
4813 static void gen_doz(DisasContext *ctx)
4814 {
4815 TCGLabel *l1 = gen_new_label();
4816 TCGLabel *l2 = gen_new_label();
4817 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4818 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4819 tcg_gen_br(l2);
4820 gen_set_label(l1);
4821 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4822 gen_set_label(l2);
4823 if (unlikely(Rc(ctx->opcode) != 0))
4824 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4825 }
4826
4827 /* dozo - dozo. */
4828 static void gen_dozo(DisasContext *ctx)
4829 {
4830 TCGLabel *l1 = gen_new_label();
4831 TCGLabel *l2 = gen_new_label();
4832 TCGv t0 = tcg_temp_new();
4833 TCGv t1 = tcg_temp_new();
4834 TCGv t2 = tcg_temp_new();
4835 /* Start with XER OV disabled, the most likely case */
4836 tcg_gen_movi_tl(cpu_ov, 0);
4837 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4838 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4839 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4840 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4841 tcg_gen_andc_tl(t1, t1, t2);
4842 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4843 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4844 tcg_gen_movi_tl(cpu_ov, 1);
4845 tcg_gen_movi_tl(cpu_so, 1);
4846 tcg_gen_br(l2);
4847 gen_set_label(l1);
4848 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4849 gen_set_label(l2);
4850 tcg_temp_free(t0);
4851 tcg_temp_free(t1);
4852 tcg_temp_free(t2);
4853 if (unlikely(Rc(ctx->opcode) != 0))
4854 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4855 }
4856
4857 /* dozi */
4858 static void gen_dozi(DisasContext *ctx)
4859 {
4860 target_long simm = SIMM(ctx->opcode);
4861 TCGLabel *l1 = gen_new_label();
4862 TCGLabel *l2 = gen_new_label();
4863 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4864 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4865 tcg_gen_br(l2);
4866 gen_set_label(l1);
4867 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4868 gen_set_label(l2);
4869 if (unlikely(Rc(ctx->opcode) != 0))
4870 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4871 }
4872
4873 /* lscbx - lscbx. */
4874 static void gen_lscbx(DisasContext *ctx)
4875 {
4876 TCGv t0 = tcg_temp_new();
4877 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4878 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4879 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4880
4881 gen_addr_reg_index(ctx, t0);
4882 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4883 tcg_temp_free_i32(t1);
4884 tcg_temp_free_i32(t2);
4885 tcg_temp_free_i32(t3);
4886 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4887 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4888 if (unlikely(Rc(ctx->opcode) != 0))
4889 gen_set_Rc0(ctx, t0);
4890 tcg_temp_free(t0);
4891 }
4892
4893 /* maskg - maskg. */
4894 static void gen_maskg(DisasContext *ctx)
4895 {
4896 TCGLabel *l1 = gen_new_label();
4897 TCGv t0 = tcg_temp_new();
4898 TCGv t1 = tcg_temp_new();
4899 TCGv t2 = tcg_temp_new();
4900 TCGv t3 = tcg_temp_new();
4901 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4902 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4903 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4904 tcg_gen_addi_tl(t2, t0, 1);
4905 tcg_gen_shr_tl(t2, t3, t2);
4906 tcg_gen_shr_tl(t3, t3, t1);
4907 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4908 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4909 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4910 gen_set_label(l1);
4911 tcg_temp_free(t0);
4912 tcg_temp_free(t1);
4913 tcg_temp_free(t2);
4914 tcg_temp_free(t3);
4915 if (unlikely(Rc(ctx->opcode) != 0))
4916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4917 }
4918
4919 /* maskir - maskir. */
4920 static void gen_maskir(DisasContext *ctx)
4921 {
4922 TCGv t0 = tcg_temp_new();
4923 TCGv t1 = tcg_temp_new();
4924 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4925 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4926 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4927 tcg_temp_free(t0);
4928 tcg_temp_free(t1);
4929 if (unlikely(Rc(ctx->opcode) != 0))
4930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4931 }
4932
4933 /* mul - mul. */
4934 static void gen_mul(DisasContext *ctx)
4935 {
4936 TCGv_i64 t0 = tcg_temp_new_i64();
4937 TCGv_i64 t1 = tcg_temp_new_i64();
4938 TCGv t2 = tcg_temp_new();
4939 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4940 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4941 tcg_gen_mul_i64(t0, t0, t1);
4942 tcg_gen_trunc_i64_tl(t2, t0);
4943 gen_store_spr(SPR_MQ, t2);
4944 tcg_gen_shri_i64(t1, t0, 32);
4945 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4946 tcg_temp_free_i64(t0);
4947 tcg_temp_free_i64(t1);
4948 tcg_temp_free(t2);
4949 if (unlikely(Rc(ctx->opcode) != 0))
4950 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4951 }
4952
4953 /* mulo - mulo. */
4954 static void gen_mulo(DisasContext *ctx)
4955 {
4956 TCGLabel *l1 = gen_new_label();
4957 TCGv_i64 t0 = tcg_temp_new_i64();
4958 TCGv_i64 t1 = tcg_temp_new_i64();
4959 TCGv t2 = tcg_temp_new();
4960 /* Start with XER OV disabled, the most likely case */
4961 tcg_gen_movi_tl(cpu_ov, 0);
4962 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4963 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4964 tcg_gen_mul_i64(t0, t0, t1);
4965 tcg_gen_trunc_i64_tl(t2, t0);
4966 gen_store_spr(SPR_MQ, t2);
4967 tcg_gen_shri_i64(t1, t0, 32);
4968 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4969 tcg_gen_ext32s_i64(t1, t0);
4970 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4971 tcg_gen_movi_tl(cpu_ov, 1);
4972 tcg_gen_movi_tl(cpu_so, 1);
4973 gen_set_label(l1);
4974 tcg_temp_free_i64(t0);
4975 tcg_temp_free_i64(t1);
4976 tcg_temp_free(t2);
4977 if (unlikely(Rc(ctx->opcode) != 0))
4978 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4979 }
4980
4981 /* nabs - nabs. */
4982 static void gen_nabs(DisasContext *ctx)
4983 {
4984 TCGLabel *l1 = gen_new_label();
4985 TCGLabel *l2 = gen_new_label();
4986 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4987 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4988 tcg_gen_br(l2);
4989 gen_set_label(l1);
4990 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4991 gen_set_label(l2);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4994 }
4995
4996 /* nabso - nabso. */
4997 static void gen_nabso(DisasContext *ctx)
4998 {
4999 TCGLabel *l1 = gen_new_label();
5000 TCGLabel *l2 = gen_new_label();
5001 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5002 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5003 tcg_gen_br(l2);
5004 gen_set_label(l1);
5005 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5006 gen_set_label(l2);
5007 /* nabs never overflows */
5008 tcg_gen_movi_tl(cpu_ov, 0);
5009 if (unlikely(Rc(ctx->opcode) != 0))
5010 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5011 }
5012
5013 /* rlmi - rlmi. */
5014 static void gen_rlmi(DisasContext *ctx)
5015 {
5016 uint32_t mb = MB(ctx->opcode);
5017 uint32_t me = ME(ctx->opcode);
5018 TCGv t0 = tcg_temp_new();
5019 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5020 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5021 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5022 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5023 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5024 tcg_temp_free(t0);
5025 if (unlikely(Rc(ctx->opcode) != 0))
5026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5027 }
5028
5029 /* rrib - rrib. */
5030 static void gen_rrib(DisasContext *ctx)
5031 {
5032 TCGv t0 = tcg_temp_new();
5033 TCGv t1 = tcg_temp_new();
5034 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5035 tcg_gen_movi_tl(t1, 0x80000000);
5036 tcg_gen_shr_tl(t1, t1, t0);
5037 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5038 tcg_gen_and_tl(t0, t0, t1);
5039 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5040 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5041 tcg_temp_free(t0);
5042 tcg_temp_free(t1);
5043 if (unlikely(Rc(ctx->opcode) != 0))
5044 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5045 }
5046
5047 /* sle - sle. */
5048 static void gen_sle(DisasContext *ctx)
5049 {
5050 TCGv t0 = tcg_temp_new();
5051 TCGv t1 = tcg_temp_new();
5052 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5053 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5054 tcg_gen_subfi_tl(t1, 32, t1);
5055 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5056 tcg_gen_or_tl(t1, t0, t1);
5057 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5058 gen_store_spr(SPR_MQ, t1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
5061 if (unlikely(Rc(ctx->opcode) != 0))
5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5063 }
5064
5065 /* sleq - sleq. */
5066 static void gen_sleq(DisasContext *ctx)
5067 {
5068 TCGv t0 = tcg_temp_new();
5069 TCGv t1 = tcg_temp_new();
5070 TCGv t2 = tcg_temp_new();
5071 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5072 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5073 tcg_gen_shl_tl(t2, t2, t0);
5074 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5075 gen_load_spr(t1, SPR_MQ);
5076 gen_store_spr(SPR_MQ, t0);
5077 tcg_gen_and_tl(t0, t0, t2);
5078 tcg_gen_andc_tl(t1, t1, t2);
5079 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5085 }
5086
5087 /* sliq - sliq. */
5088 static void gen_sliq(DisasContext *ctx)
5089 {
5090 int sh = SH(ctx->opcode);
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5094 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5095 tcg_gen_or_tl(t1, t0, t1);
5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5097 gen_store_spr(SPR_MQ, t1);
5098 tcg_temp_free(t0);
5099 tcg_temp_free(t1);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5102 }
5103
5104 /* slliq - slliq. */
5105 static void gen_slliq(DisasContext *ctx)
5106 {
5107 int sh = SH(ctx->opcode);
5108 TCGv t0 = tcg_temp_new();
5109 TCGv t1 = tcg_temp_new();
5110 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5111 gen_load_spr(t1, SPR_MQ);
5112 gen_store_spr(SPR_MQ, t0);
5113 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5114 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 tcg_temp_free(t0);
5117 tcg_temp_free(t1);
5118 if (unlikely(Rc(ctx->opcode) != 0))
5119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5120 }
5121
5122 /* sllq - sllq. */
5123 static void gen_sllq(DisasContext *ctx)
5124 {
5125 TCGLabel *l1 = gen_new_label();
5126 TCGLabel *l2 = gen_new_label();
5127 TCGv t0 = tcg_temp_local_new();
5128 TCGv t1 = tcg_temp_local_new();
5129 TCGv t2 = tcg_temp_local_new();
5130 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5132 tcg_gen_shl_tl(t1, t1, t2);
5133 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5134 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5135 gen_load_spr(t0, SPR_MQ);
5136 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5137 tcg_gen_br(l2);
5138 gen_set_label(l1);
5139 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5140 gen_load_spr(t2, SPR_MQ);
5141 tcg_gen_andc_tl(t1, t2, t1);
5142 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5143 gen_set_label(l2);
5144 tcg_temp_free(t0);
5145 tcg_temp_free(t1);
5146 tcg_temp_free(t2);
5147 if (unlikely(Rc(ctx->opcode) != 0))
5148 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5149 }
5150
5151 /* slq - slq. */
5152 static void gen_slq(DisasContext *ctx)
5153 {
5154 TCGLabel *l1 = gen_new_label();
5155 TCGv t0 = tcg_temp_new();
5156 TCGv t1 = tcg_temp_new();
5157 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5158 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5159 tcg_gen_subfi_tl(t1, 32, t1);
5160 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5161 tcg_gen_or_tl(t1, t0, t1);
5162 gen_store_spr(SPR_MQ, t1);
5163 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5164 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5165 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5166 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5167 gen_set_label(l1);
5168 tcg_temp_free(t0);
5169 tcg_temp_free(t1);
5170 if (unlikely(Rc(ctx->opcode) != 0))
5171 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5172 }
5173
5174 /* sraiq - sraiq. */
5175 static void gen_sraiq(DisasContext *ctx)
5176 {
5177 int sh = SH(ctx->opcode);
5178 TCGLabel *l1 = gen_new_label();
5179 TCGv t0 = tcg_temp_new();
5180 TCGv t1 = tcg_temp_new();
5181 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5182 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5183 tcg_gen_or_tl(t0, t0, t1);
5184 gen_store_spr(SPR_MQ, t0);
5185 tcg_gen_movi_tl(cpu_ca, 0);
5186 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5187 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5188 tcg_gen_movi_tl(cpu_ca, 1);
5189 gen_set_label(l1);
5190 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5191 tcg_temp_free(t0);
5192 tcg_temp_free(t1);
5193 if (unlikely(Rc(ctx->opcode) != 0))
5194 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5195 }
5196
5197 /* sraq - sraq. */
5198 static void gen_sraq(DisasContext *ctx)
5199 {
5200 TCGLabel *l1 = gen_new_label();
5201 TCGLabel *l2 = gen_new_label();
5202 TCGv t0 = tcg_temp_new();
5203 TCGv t1 = tcg_temp_local_new();
5204 TCGv t2 = tcg_temp_local_new();
5205 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5206 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5207 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5208 tcg_gen_subfi_tl(t2, 32, t2);
5209 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5210 tcg_gen_or_tl(t0, t0, t2);
5211 gen_store_spr(SPR_MQ, t0);
5212 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5213 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5214 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5215 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5216 gen_set_label(l1);
5217 tcg_temp_free(t0);
5218 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5219 tcg_gen_movi_tl(cpu_ca, 0);
5220 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5221 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5222 tcg_gen_movi_tl(cpu_ca, 1);
5223 gen_set_label(l2);
5224 tcg_temp_free(t1);
5225 tcg_temp_free(t2);
5226 if (unlikely(Rc(ctx->opcode) != 0))
5227 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5228 }
5229
5230 /* sre - sre. */
5231 static void gen_sre(DisasContext *ctx)
5232 {
5233 TCGv t0 = tcg_temp_new();
5234 TCGv t1 = tcg_temp_new();
5235 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5236 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5237 tcg_gen_subfi_tl(t1, 32, t1);
5238 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5239 tcg_gen_or_tl(t1, t0, t1);
5240 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5241 gen_store_spr(SPR_MQ, t1);
5242 tcg_temp_free(t0);
5243 tcg_temp_free(t1);
5244 if (unlikely(Rc(ctx->opcode) != 0))
5245 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5246 }
5247
5248 /* srea - srea. */
5249 static void gen_srea(DisasContext *ctx)
5250 {
5251 TCGv t0 = tcg_temp_new();
5252 TCGv t1 = tcg_temp_new();
5253 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5254 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5255 gen_store_spr(SPR_MQ, t0);
5256 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5257 tcg_temp_free(t0);
5258 tcg_temp_free(t1);
5259 if (unlikely(Rc(ctx->opcode) != 0))
5260 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5261 }
5262
5263 /* sreq */
5264 static void gen_sreq(DisasContext *ctx)
5265 {
5266 TCGv t0 = tcg_temp_new();
5267 TCGv t1 = tcg_temp_new();
5268 TCGv t2 = tcg_temp_new();
5269 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5270 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5271 tcg_gen_shr_tl(t1, t1, t0);
5272 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5273 gen_load_spr(t2, SPR_MQ);
5274 gen_store_spr(SPR_MQ, t0);
5275 tcg_gen_and_tl(t0, t0, t1);
5276 tcg_gen_andc_tl(t2, t2, t1);
5277 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5278 tcg_temp_free(t0);
5279 tcg_temp_free(t1);
5280 tcg_temp_free(t2);
5281 if (unlikely(Rc(ctx->opcode) != 0))
5282 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5283 }
5284
5285 /* sriq */
5286 static void gen_sriq(DisasContext *ctx)
5287 {
5288 int sh = SH(ctx->opcode);
5289 TCGv t0 = tcg_temp_new();
5290 TCGv t1 = tcg_temp_new();
5291 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5292 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5293 tcg_gen_or_tl(t1, t0, t1);
5294 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5295 gen_store_spr(SPR_MQ, t1);
5296 tcg_temp_free(t0);
5297 tcg_temp_free(t1);
5298 if (unlikely(Rc(ctx->opcode) != 0))
5299 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5300 }
5301
5302 /* srliq */
5303 static void gen_srliq(DisasContext *ctx)
5304 {
5305 int sh = SH(ctx->opcode);
5306 TCGv t0 = tcg_temp_new();
5307 TCGv t1 = tcg_temp_new();
5308 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5309 gen_load_spr(t1, SPR_MQ);
5310 gen_store_spr(SPR_MQ, t0);
5311 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5312 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5313 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5314 tcg_temp_free(t0);
5315 tcg_temp_free(t1);
5316 if (unlikely(Rc(ctx->opcode) != 0))
5317 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5318 }
5319
5320 /* srlq */
5321 static void gen_srlq(DisasContext *ctx)
5322 {
5323 TCGLabel *l1 = gen_new_label();
5324 TCGLabel *l2 = gen_new_label();
5325 TCGv t0 = tcg_temp_local_new();
5326 TCGv t1 = tcg_temp_local_new();
5327 TCGv t2 = tcg_temp_local_new();
5328 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5329 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5330 tcg_gen_shr_tl(t2, t1, t2);
5331 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5332 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5333 gen_load_spr(t0, SPR_MQ);
5334 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5335 tcg_gen_br(l2);
5336 gen_set_label(l1);
5337 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5338 tcg_gen_and_tl(t0, t0, t2);
5339 gen_load_spr(t1, SPR_MQ);
5340 tcg_gen_andc_tl(t1, t1, t2);
5341 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5342 gen_set_label(l2);
5343 tcg_temp_free(t0);
5344 tcg_temp_free(t1);
5345 tcg_temp_free(t2);
5346 if (unlikely(Rc(ctx->opcode) != 0))
5347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5348 }
5349
5350 /* srq */
5351 static void gen_srq(DisasContext *ctx)
5352 {
5353 TCGLabel *l1 = gen_new_label();
5354 TCGv t0 = tcg_temp_new();
5355 TCGv t1 = tcg_temp_new();
5356 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5357 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5358 tcg_gen_subfi_tl(t1, 32, t1);
5359 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5360 tcg_gen_or_tl(t1, t0, t1);
5361 gen_store_spr(SPR_MQ, t1);
5362 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5363 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5364 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5365 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5366 gen_set_label(l1);
5367 tcg_temp_free(t0);
5368 tcg_temp_free(t1);
5369 if (unlikely(Rc(ctx->opcode) != 0))
5370 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5371 }
5372
5373 /* PowerPC 602 specific instructions */
5374
5375 /* dsa */
5376 static void gen_dsa(DisasContext *ctx)
5377 {
5378 /* XXX: TODO */
5379 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5380 }
5381
5382 /* esa */
5383 static void gen_esa(DisasContext *ctx)
5384 {
5385 /* XXX: TODO */
5386 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5387 }
5388
5389 /* mfrom */
5390 static void gen_mfrom(DisasContext *ctx)
5391 {
5392 #if defined(CONFIG_USER_ONLY)
5393 GEN_PRIV;
5394 #else
5395 CHK_SV;
5396 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5397 #endif /* defined(CONFIG_USER_ONLY) */
5398 }
5399
5400 /* 602 - 603 - G2 TLB management */
5401
5402 /* tlbld */
5403 static void gen_tlbld_6xx(DisasContext *ctx)
5404 {
5405 #if defined(CONFIG_USER_ONLY)
5406 GEN_PRIV;
5407 #else
5408 CHK_SV;
5409 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5410 #endif /* defined(CONFIG_USER_ONLY) */
5411 }
5412
5413 /* tlbli */
5414 static void gen_tlbli_6xx(DisasContext *ctx)
5415 {
5416 #if defined(CONFIG_USER_ONLY)
5417 GEN_PRIV;
5418 #else
5419 CHK_SV;
5420 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5421 #endif /* defined(CONFIG_USER_ONLY) */
5422 }
5423
5424 /* 74xx TLB management */
5425
5426 /* tlbld */
5427 static void gen_tlbld_74xx(DisasContext *ctx)
5428 {
5429 #if defined(CONFIG_USER_ONLY)
5430 GEN_PRIV;
5431 #else
5432 CHK_SV;
5433 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5434 #endif /* defined(CONFIG_USER_ONLY) */
5435 }
5436
5437 /* tlbli */
5438 static void gen_tlbli_74xx(DisasContext *ctx)
5439 {
5440 #if defined(CONFIG_USER_ONLY)
5441 GEN_PRIV;
5442 #else
5443 CHK_SV;
5444 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5445 #endif /* defined(CONFIG_USER_ONLY) */
5446 }
5447
5448 /* POWER instructions not in PowerPC 601 */
5449
5450 /* clf */
5451 static void gen_clf(DisasContext *ctx)
5452 {
5453 /* Cache line flush: implemented as no-op */
5454 }
5455
5456 /* cli */
5457 static void gen_cli(DisasContext *ctx)
5458 {
5459 #if defined(CONFIG_USER_ONLY)
5460 GEN_PRIV;
5461 #else
5462 /* Cache line invalidate: privileged and treated as no-op */
5463 CHK_SV;
5464 #endif /* defined(CONFIG_USER_ONLY) */
5465 }
5466
5467 /* dclst */
5468 static void gen_dclst(DisasContext *ctx)
5469 {
5470 /* Data cache line store: treated as no-op */
5471 }
5472
5473 static void gen_mfsri(DisasContext *ctx)
5474 {
5475 #if defined(CONFIG_USER_ONLY)
5476 GEN_PRIV;
5477 #else
5478 int ra = rA(ctx->opcode);
5479 int rd = rD(ctx->opcode);
5480 TCGv t0;
5481
5482 CHK_SV;
5483 t0 = tcg_temp_new();
5484 gen_addr_reg_index(ctx, t0);
5485 tcg_gen_extract_tl(t0, t0, 28, 4);
5486 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5487 tcg_temp_free(t0);
5488 if (ra != 0 && ra != rd)
5489 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5490 #endif /* defined(CONFIG_USER_ONLY) */
5491 }
5492
5493 static void gen_rac(DisasContext *ctx)
5494 {
5495 #if defined(CONFIG_USER_ONLY)
5496 GEN_PRIV;
5497 #else
5498 TCGv t0;
5499
5500 CHK_SV;
5501 t0 = tcg_temp_new();
5502 gen_addr_reg_index(ctx, t0);
5503 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5504 tcg_temp_free(t0);
5505 #endif /* defined(CONFIG_USER_ONLY) */
5506 }
5507
5508 static void gen_rfsvc(DisasContext *ctx)
5509 {
5510 #if defined(CONFIG_USER_ONLY)
5511 GEN_PRIV;
5512 #else
5513 CHK_SV;
5514
5515 gen_helper_rfsvc(cpu_env);
5516 gen_sync_exception(ctx);
5517 #endif /* defined(CONFIG_USER_ONLY) */
5518 }
5519
5520 /* svc is not implemented for now */
5521
5522 /* BookE specific instructions */
5523
5524 /* XXX: not implemented on 440 ? */
5525 static void gen_mfapidi(DisasContext *ctx)
5526 {
5527 /* XXX: TODO */
5528 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5529 }
5530
5531 /* XXX: not implemented on 440 ? */
5532 static void gen_tlbiva(DisasContext *ctx)
5533 {
5534 #if defined(CONFIG_USER_ONLY)
5535 GEN_PRIV;
5536 #else
5537 TCGv t0;
5538
5539 CHK_SV;
5540 t0 = tcg_temp_new();
5541 gen_addr_reg_index(ctx, t0);
5542 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5543 tcg_temp_free(t0);
5544 #endif /* defined(CONFIG_USER_ONLY) */
5545 }
5546
5547 /* All 405 MAC instructions are translated here */
5548 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5549 int ra, int rb, int rt, int Rc)
5550 {
5551 TCGv t0, t1;
5552
5553 t0 = tcg_temp_local_new();
5554 t1 = tcg_temp_local_new();
5555
5556 switch (opc3 & 0x0D) {
5557 case 0x05:
5558 /* macchw - macchw. - macchwo - macchwo. */
5559 /* macchws - macchws. - macchwso - macchwso. */
5560 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5561 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5562 /* mulchw - mulchw. */
5563 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5564 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5565 tcg_gen_ext16s_tl(t1, t1);
5566 break;
5567 case 0x04:
5568 /* macchwu - macchwu. - macchwuo - macchwuo. */
5569 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5570 /* mulchwu - mulchwu. */
5571 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5572 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5573 tcg_gen_ext16u_tl(t1, t1);
5574 break;
5575 case 0x01:
5576 /* machhw - machhw. - machhwo - machhwo. */
5577 /* machhws - machhws. - machhwso - machhwso. */
5578 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5579 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5580 /* mulhhw - mulhhw. */
5581 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5582 tcg_gen_ext16s_tl(t0, t0);
5583 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5584 tcg_gen_ext16s_tl(t1, t1);
5585 break;
5586 case 0x00:
5587 /* machhwu - machhwu. - machhwuo - machhwuo. */
5588 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5589 /* mulhhwu - mulhhwu. */
5590 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5591 tcg_gen_ext16u_tl(t0, t0);
5592 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5593 tcg_gen_ext16u_tl(t1, t1);
5594 break;
5595 case 0x0D:
5596 /* maclhw - maclhw. - maclhwo - maclhwo. */
5597 /* maclhws - maclhws. - maclhwso - maclhwso. */
5598 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5599 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5600 /* mullhw - mullhw. */
5601 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5602 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5603 break;
5604 case 0x0C:
5605 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5606 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5607 /* mullhwu - mullhwu. */
5608 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5609 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5610 break;
5611 }
5612 if (opc2 & 0x04) {
5613 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5614 tcg_gen_mul_tl(t1, t0, t1);
5615 if (opc2 & 0x02) {
5616 /* nmultiply-and-accumulate (0x0E) */
5617 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5618 } else {
5619 /* multiply-and-accumulate (0x0C) */
5620 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5621 }
5622
5623 if (opc3 & 0x12) {
5624 /* Check overflow and/or saturate */
5625 TCGLabel *l1 = gen_new_label();
5626
5627 if (opc3 & 0x10) {
5628 /* Start with XER OV disabled, the most likely case */
5629 tcg_gen_movi_tl(cpu_ov, 0);
5630 }
5631 if (opc3 & 0x01) {
5632 /* Signed */
5633 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5634 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5635 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5636 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5637 if (opc3 & 0x02) {
5638 /* Saturate */
5639 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5640 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5641 }
5642 } else {
5643 /* Unsigned */
5644 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5645 if (opc3 & 0x02) {
5646 /* Saturate */
5647 tcg_gen_movi_tl(t0, UINT32_MAX);
5648 }
5649 }
5650 if (opc3 & 0x10) {
5651 /* Check overflow */
5652 tcg_gen_movi_tl(cpu_ov, 1);
5653 tcg_gen_movi_tl(cpu_so, 1);
5654 }
5655 gen_set_label(l1);
5656 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5657 }
5658 } else {
5659 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5660 }
5661 tcg_temp_free(t0);
5662 tcg_temp_free(t1);
5663 if (unlikely(Rc) != 0) {
5664 /* Update Rc0 */
5665 gen_set_Rc0(ctx, cpu_gpr[rt]);
5666 }
5667 }
5668
5669 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5670 static void glue(gen_, name)(DisasContext *ctx) \
5671 { \
5672 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5673 rD(ctx->opcode), Rc(ctx->opcode)); \
5674 }
5675
5676 /* macchw - macchw. */
5677 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5678 /* macchwo - macchwo. */
5679 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5680 /* macchws - macchws. */
5681 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5682 /* macchwso - macchwso. */
5683 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5684 /* macchwsu - macchwsu. */
5685 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5686 /* macchwsuo - macchwsuo. */
5687 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5688 /* macchwu - macchwu. */
5689 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5690 /* macchwuo - macchwuo. */
5691 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5692 /* machhw - machhw. */
5693 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5694 /* machhwo - machhwo. */
5695 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5696 /* machhws - machhws. */
5697 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5698 /* machhwso - machhwso. */
5699 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5700 /* machhwsu - machhwsu. */
5701 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5702 /* machhwsuo - machhwsuo. */
5703 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5704 /* machhwu - machhwu. */
5705 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5706 /* machhwuo - machhwuo. */
5707 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5708 /* maclhw - maclhw. */
5709 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5710 /* maclhwo - maclhwo. */
5711 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5712 /* maclhws - maclhws. */
5713 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5714 /* maclhwso - maclhwso. */
5715 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5716 /* maclhwu - maclhwu. */
5717 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5718 /* maclhwuo - maclhwuo. */
5719 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5720 /* maclhwsu - maclhwsu. */
5721 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5722 /* maclhwsuo - maclhwsuo. */
5723 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5724 /* nmacchw - nmacchw. */
5725 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5726 /* nmacchwo - nmacchwo. */
5727 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5728 /* nmacchws - nmacchws. */
5729 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5730 /* nmacchwso - nmacchwso. */
5731 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5732 /* nmachhw - nmachhw. */
5733 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5734 /* nmachhwo - nmachhwo. */
5735 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5736 /* nmachhws - nmachhws. */
5737 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5738 /* nmachhwso - nmachhwso. */
5739 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5740 /* nmaclhw - nmaclhw. */
5741 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5742 /* nmaclhwo - nmaclhwo. */
5743 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5744 /* nmaclhws - nmaclhws. */
5745 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5746 /* nmaclhwso - nmaclhwso. */
5747 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5748
5749 /* mulchw - mulchw. */
5750 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5751 /* mulchwu - mulchwu. */
5752 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5753 /* mulhhw - mulhhw. */
5754 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5755 /* mulhhwu - mulhhwu. */
5756 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5757 /* mullhw - mullhw. */
5758 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5759 /* mullhwu - mullhwu. */
5760 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5761
5762 /* mfdcr */
5763 static void gen_mfdcr(DisasContext *ctx)
5764 {
5765 #if defined(CONFIG_USER_ONLY)
5766 GEN_PRIV;
5767 #else
5768 TCGv dcrn;
5769
5770 CHK_SV;
5771 dcrn = tcg_const_tl(SPR(ctx->opcode));
5772 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5773 tcg_temp_free(dcrn);
5774 #endif /* defined(CONFIG_USER_ONLY) */
5775 }
5776
5777 /* mtdcr */
5778 static void gen_mtdcr(DisasContext *ctx)
5779 {
5780 #if defined(CONFIG_USER_ONLY)
5781 GEN_PRIV;
5782 #else
5783 TCGv dcrn;
5784
5785 CHK_SV;
5786 dcrn = tcg_const_tl(SPR(ctx->opcode));
5787 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5788 tcg_temp_free(dcrn);
5789 #endif /* defined(CONFIG_USER_ONLY) */
5790 }
5791
5792 /* mfdcrx */
5793 /* XXX: not implemented on 440 ? */
5794 static void gen_mfdcrx(DisasContext *ctx)
5795 {
5796 #if defined(CONFIG_USER_ONLY)
5797 GEN_PRIV;
5798 #else
5799 CHK_SV;
5800 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5801 cpu_gpr[rA(ctx->opcode)]);
5802 /* Note: Rc update flag set leads to undefined state of Rc0 */
5803 #endif /* defined(CONFIG_USER_ONLY) */
5804 }
5805
5806 /* mtdcrx */
5807 /* XXX: not implemented on 440 ? */
5808 static void gen_mtdcrx(DisasContext *ctx)
5809 {
5810 #if defined(CONFIG_USER_ONLY)
5811 GEN_PRIV;
5812 #else
5813 CHK_SV;
5814 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5815 cpu_gpr[rS(ctx->opcode)]);
5816 /* Note: Rc update flag set leads to undefined state of Rc0 */
5817 #endif /* defined(CONFIG_USER_ONLY) */
5818 }
5819
5820 /* mfdcrux (PPC 460) : user-mode access to DCR */
5821 static void gen_mfdcrux(DisasContext *ctx)
5822 {
5823 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5824 cpu_gpr[rA(ctx->opcode)]);
5825 /* Note: Rc update flag set leads to undefined state of Rc0 */
5826 }
5827
5828 /* mtdcrux (PPC 460) : user-mode access to DCR */
5829 static void gen_mtdcrux(DisasContext *ctx)
5830 {
5831 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5832 cpu_gpr[rS(ctx->opcode)]);
5833 /* Note: Rc update flag set leads to undefined state of Rc0 */
5834 }
5835
5836 /* dccci */
5837 static void gen_dccci(DisasContext *ctx)
5838 {
5839 CHK_SV;
5840 /* interpreted as no-op */
5841 }
5842
5843 /* dcread */
5844 static void gen_dcread(DisasContext *ctx)
5845 {
5846 #if defined(CONFIG_USER_ONLY)
5847 GEN_PRIV;
5848 #else
5849 TCGv EA, val;
5850
5851 CHK_SV;
5852 gen_set_access_type(ctx, ACCESS_CACHE);
5853 EA = tcg_temp_new();
5854 gen_addr_reg_index(ctx, EA);
5855 val = tcg_temp_new();
5856 gen_qemu_ld32u(ctx, val, EA);
5857 tcg_temp_free(val);
5858 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5859 tcg_temp_free(EA);
5860 #endif /* defined(CONFIG_USER_ONLY) */
5861 }
5862
5863 /* icbt */
5864 static void gen_icbt_40x(DisasContext *ctx)
5865 {
5866 /* interpreted as no-op */
5867 /* XXX: specification say this is treated as a load by the MMU
5868 * but does not generate any exception
5869 */
5870 }
5871
5872 /* iccci */
5873 static void gen_iccci(DisasContext *ctx)
5874 {
5875 CHK_SV;
5876 /* interpreted as no-op */
5877 }
5878
5879 /* icread */
5880 static void gen_icread(DisasContext *ctx)
5881 {
5882 CHK_SV;
5883 /* interpreted as no-op */
5884 }
5885
5886 /* rfci (supervisor only) */
5887 static void gen_rfci_40x(DisasContext *ctx)
5888 {
5889 #if defined(CONFIG_USER_ONLY)
5890 GEN_PRIV;
5891 #else
5892 CHK_SV;
5893 /* Restore CPU state */
5894 gen_helper_40x_rfci(cpu_env);
5895 gen_sync_exception(ctx);
5896 #endif /* defined(CONFIG_USER_ONLY) */
5897 }
5898
5899 static void gen_rfci(DisasContext *ctx)
5900 {
5901 #if defined(CONFIG_USER_ONLY)
5902 GEN_PRIV;
5903 #else
5904 CHK_SV;
5905 /* Restore CPU state */
5906 gen_helper_rfci(cpu_env);
5907 gen_sync_exception(ctx);
5908 #endif /* defined(CONFIG_USER_ONLY) */
5909 }
5910
5911 /* BookE specific */
5912
5913 /* XXX: not implemented on 440 ? */
5914 static void gen_rfdi(DisasContext *ctx)
5915 {
5916 #if defined(CONFIG_USER_ONLY)
5917 GEN_PRIV;
5918 #else
5919 CHK_SV;
5920 /* Restore CPU state */
5921 gen_helper_rfdi(cpu_env);
5922 gen_sync_exception(ctx);
5923 #endif /* defined(CONFIG_USER_ONLY) */
5924 }
5925
5926 /* XXX: not implemented on 440 ? */
5927 static void gen_rfmci(DisasContext *ctx)
5928 {
5929 #if defined(CONFIG_USER_ONLY)
5930 GEN_PRIV;
5931 #else
5932 CHK_SV;
5933 /* Restore CPU state */
5934 gen_helper_rfmci(cpu_env);
5935 gen_sync_exception(ctx);
5936 #endif /* defined(CONFIG_USER_ONLY) */
5937 }
5938
5939 /* TLB management - PowerPC 405 implementation */
5940
5941 /* tlbre */
5942 static void gen_tlbre_40x(DisasContext *ctx)
5943 {
5944 #if defined(CONFIG_USER_ONLY)
5945 GEN_PRIV;
5946 #else
5947 CHK_SV;
5948 switch (rB(ctx->opcode)) {
5949 case 0:
5950 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5951 cpu_gpr[rA(ctx->opcode)]);
5952 break;
5953 case 1:
5954 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5955 cpu_gpr[rA(ctx->opcode)]);
5956 break;
5957 default:
5958 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5959 break;
5960 }
5961 #endif /* defined(CONFIG_USER_ONLY) */
5962 }
5963
5964 /* tlbsx - tlbsx. */
5965 static void gen_tlbsx_40x(DisasContext *ctx)
5966 {
5967 #if defined(CONFIG_USER_ONLY)
5968 GEN_PRIV;
5969 #else
5970 TCGv t0;
5971
5972 CHK_SV;
5973 t0 = tcg_temp_new();
5974 gen_addr_reg_index(ctx, t0);
5975 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5976 tcg_temp_free(t0);
5977 if (Rc(ctx->opcode)) {
5978 TCGLabel *l1 = gen_new_label();
5979 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5980 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5981 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5982 gen_set_label(l1);
5983 }
5984 #endif /* defined(CONFIG_USER_ONLY) */
5985 }
5986
5987 /* tlbwe */
5988 static void gen_tlbwe_40x(DisasContext *ctx)
5989 {
5990 #if defined(CONFIG_USER_ONLY)
5991 GEN_PRIV;
5992 #else
5993 CHK_SV;
5994
5995 switch (rB(ctx->opcode)) {
5996 case 0:
5997 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5998 cpu_gpr[rS(ctx->opcode)]);
5999 break;
6000 case 1:
6001 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6002 cpu_gpr[rS(ctx->opcode)]);
6003 break;
6004 default:
6005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6006 break;
6007 }
6008 #endif /* defined(CONFIG_USER_ONLY) */
6009 }
6010
6011 /* TLB management - PowerPC 440 implementation */
6012
6013 /* tlbre */
6014 static void gen_tlbre_440(DisasContext *ctx)
6015 {
6016 #if defined(CONFIG_USER_ONLY)
6017 GEN_PRIV;
6018 #else
6019 CHK_SV;
6020
6021 switch (rB(ctx->opcode)) {
6022 case 0:
6023 case 1:
6024 case 2:
6025 {
6026 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6027 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6028 t0, cpu_gpr[rA(ctx->opcode)]);
6029 tcg_temp_free_i32(t0);
6030 }
6031 break;
6032 default:
6033 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6034 break;
6035 }
6036 #endif /* defined(CONFIG_USER_ONLY) */
6037 }
6038
6039 /* tlbsx - tlbsx. */
6040 static void gen_tlbsx_440(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 GEN_PRIV;
6044 #else
6045 TCGv t0;
6046
6047 CHK_SV;
6048 t0 = tcg_temp_new();
6049 gen_addr_reg_index(ctx, t0);
6050 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6051 tcg_temp_free(t0);
6052 if (Rc(ctx->opcode)) {
6053 TCGLabel *l1 = gen_new_label();
6054 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6055 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6056 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6057 gen_set_label(l1);
6058 }
6059 #endif /* defined(CONFIG_USER_ONLY) */
6060 }
6061
6062 /* tlbwe */
6063 static void gen_tlbwe_440(DisasContext *ctx)
6064 {
6065 #if defined(CONFIG_USER_ONLY)
6066 GEN_PRIV;
6067 #else
6068 CHK_SV;
6069 switch (rB(ctx->opcode)) {
6070 case 0:
6071 case 1:
6072 case 2:
6073 {
6074 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6075 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6076 cpu_gpr[rS(ctx->opcode)]);
6077 tcg_temp_free_i32(t0);
6078 }
6079 break;
6080 default:
6081 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6082 break;
6083 }
6084 #endif /* defined(CONFIG_USER_ONLY) */
6085 }
6086
6087 /* TLB management - PowerPC BookE 2.06 implementation */
6088
6089 /* tlbre */
6090 static void gen_tlbre_booke206(DisasContext *ctx)
6091 {
6092 #if defined(CONFIG_USER_ONLY)
6093 GEN_PRIV;
6094 #else
6095 CHK_SV;
6096 gen_helper_booke206_tlbre(cpu_env);
6097 #endif /* defined(CONFIG_USER_ONLY) */
6098 }
6099
6100 /* tlbsx - tlbsx. */
6101 static void gen_tlbsx_booke206(DisasContext *ctx)
6102 {
6103 #if defined(CONFIG_USER_ONLY)
6104 GEN_PRIV;
6105 #else
6106 TCGv t0;
6107
6108 CHK_SV;
6109 if (rA(ctx->opcode)) {
6110 t0 = tcg_temp_new();
6111 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6112 } else {
6113 t0 = tcg_const_tl(0);
6114 }
6115
6116 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6117 gen_helper_booke206_tlbsx(cpu_env, t0);
6118 tcg_temp_free(t0);
6119 #endif /* defined(CONFIG_USER_ONLY) */
6120 }
6121
6122 /* tlbwe */
6123 static void gen_tlbwe_booke206(DisasContext *ctx)
6124 {
6125 #if defined(CONFIG_USER_ONLY)
6126 GEN_PRIV;
6127 #else
6128 CHK_SV;
6129 gen_helper_booke206_tlbwe(cpu_env);
6130 #endif /* defined(CONFIG_USER_ONLY) */
6131 }
6132
6133 static void gen_tlbivax_booke206(DisasContext *ctx)
6134 {
6135 #if defined(CONFIG_USER_ONLY)
6136 GEN_PRIV;
6137 #else
6138 TCGv t0;
6139
6140 CHK_SV;
6141 t0 = tcg_temp_new();
6142 gen_addr_reg_index(ctx, t0);
6143 gen_helper_booke206_tlbivax(cpu_env, t0);
6144 tcg_temp_free(t0);
6145 #endif /* defined(CONFIG_USER_ONLY) */
6146 }
6147
6148 static void gen_tlbilx_booke206(DisasContext *ctx)
6149 {
6150 #if defined(CONFIG_USER_ONLY)
6151 GEN_PRIV;
6152 #else
6153 TCGv t0;
6154
6155 CHK_SV;
6156 t0 = tcg_temp_new();
6157 gen_addr_reg_index(ctx, t0);
6158
6159 switch((ctx->opcode >> 21) & 0x3) {
6160 case 0:
6161 gen_helper_booke206_tlbilx0(cpu_env, t0);
6162 break;
6163 case 1:
6164 gen_helper_booke206_tlbilx1(cpu_env, t0);
6165 break;
6166 case 3:
6167 gen_helper_booke206_tlbilx3(cpu_env, t0);
6168 break;
6169 default:
6170 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6171 break;
6172 }
6173
6174 tcg_temp_free(t0);
6175 #endif /* defined(CONFIG_USER_ONLY) */
6176 }
6177
6178
6179 /* wrtee */
6180 static void gen_wrtee(DisasContext *ctx)
6181 {
6182 #if defined(CONFIG_USER_ONLY)
6183 GEN_PRIV;
6184 #else
6185 TCGv t0;
6186
6187 CHK_SV;
6188 t0 = tcg_temp_new();
6189 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6190 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6191 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6192 tcg_temp_free(t0);
6193 /* Stop translation to have a chance to raise an exception
6194 * if we just set msr_ee to 1
6195 */
6196 gen_stop_exception(ctx);
6197 #endif /* defined(CONFIG_USER_ONLY) */
6198 }
6199
6200 /* wrteei */
6201 static void gen_wrteei(DisasContext *ctx)
6202 {
6203 #if defined(CONFIG_USER_ONLY)
6204 GEN_PRIV;
6205 #else
6206 CHK_SV;
6207 if (ctx->opcode & 0x00008000) {
6208 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6209 /* Stop translation to have a chance to raise an exception */
6210 gen_stop_exception(ctx);
6211 } else {
6212 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6213 }
6214 #endif /* defined(CONFIG_USER_ONLY) */
6215 }
6216
6217 /* PowerPC 440 specific instructions */
6218
6219 /* dlmzb */
6220 static void gen_dlmzb(DisasContext *ctx)
6221 {
6222 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6223 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6224 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6225 tcg_temp_free_i32(t0);
6226 }
6227
6228 /* mbar replaces eieio on 440 */
6229 static void gen_mbar(DisasContext *ctx)
6230 {
6231 /* interpreted as no-op */
6232 }
6233
6234 /* msync replaces sync on 440 */
6235 static void gen_msync_4xx(DisasContext *ctx)
6236 {
6237 /* interpreted as no-op */
6238 }
6239
6240 /* icbt */
6241 static void gen_icbt_440(DisasContext *ctx)
6242 {
6243 /* interpreted as no-op */
6244 /* XXX: specification say this is treated as a load by the MMU
6245 * but does not generate any exception
6246 */
6247 }
6248
6249 /* Embedded.Processor Control */
6250
6251 static void gen_msgclr(DisasContext *ctx)
6252 {
6253 #if defined(CONFIG_USER_ONLY)
6254 GEN_PRIV;
6255 #else
6256 CHK_HV;
6257 /* 64-bit server processors compliant with arch 2.x */
6258 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6259 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6260 } else {
6261 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6262 }
6263 #endif /* defined(CONFIG_USER_ONLY) */
6264 }
6265
6266 static void gen_msgsnd(DisasContext *ctx)
6267 {
6268 #if defined(CONFIG_USER_ONLY)
6269 GEN_PRIV;
6270 #else
6271 CHK_HV;
6272 /* 64-bit server processors compliant with arch 2.x */
6273 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6274 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6275 } else {
6276 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6277 }
6278 #endif /* defined(CONFIG_USER_ONLY) */
6279 }
6280
6281 static void gen_msgsync(DisasContext *ctx)
6282 {
6283 #if defined(CONFIG_USER_ONLY)
6284 GEN_PRIV;
6285 #else
6286 CHK_HV;
6287 #endif /* defined(CONFIG_USER_ONLY) */
6288 /* interpreted as no-op */
6289 }
6290
6291 #if defined(TARGET_PPC64)
6292 static void gen_maddld(DisasContext *ctx)
6293 {
6294 TCGv_i64 t1 = tcg_temp_new_i64();
6295
6296 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6297 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6298 tcg_temp_free_i64(t1);
6299 }
6300
6301 /* maddhd maddhdu */
6302 static void gen_maddhd_maddhdu(DisasContext *ctx)
6303 {
6304 TCGv_i64 lo = tcg_temp_new_i64();
6305 TCGv_i64 hi = tcg_temp_new_i64();
6306 TCGv_i64 t1 = tcg_temp_new_i64();
6307
6308 if (Rc(ctx->opcode)) {
6309 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6310 cpu_gpr[rB(ctx->opcode)]);
6311 tcg_gen_movi_i64(t1, 0);
6312 } else {
6313 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6314 cpu_gpr[rB(ctx->opcode)]);
6315 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6316 }
6317 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6318 cpu_gpr[rC(ctx->opcode)], t1);
6319 tcg_temp_free_i64(lo);
6320 tcg_temp_free_i64(hi);
6321 tcg_temp_free_i64(t1);
6322 }
6323 #endif /* defined(TARGET_PPC64) */
6324
6325 static void gen_tbegin(DisasContext *ctx)
6326 {
6327 if (unlikely(!ctx->tm_enabled)) {
6328 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6329 return;
6330 }
6331 gen_helper_tbegin(cpu_env);
6332 }
6333
6334 #define GEN_TM_NOOP(name) \
6335 static inline void gen_##name(DisasContext *ctx) \
6336 { \
6337 if (unlikely(!ctx->tm_enabled)) { \
6338 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6339 return; \
6340 } \
6341 /* Because tbegin always fails in QEMU, these user \
6342 * space instructions all have a simple implementation: \
6343 * \
6344 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6345 * = 0b0 || 0b00 || 0b0 \
6346 */ \
6347 tcg_gen_movi_i32(cpu_crf[0], 0); \
6348 }
6349
6350 GEN_TM_NOOP(tend);
6351 GEN_TM_NOOP(tabort);
6352 GEN_TM_NOOP(tabortwc);
6353 GEN_TM_NOOP(tabortwci);
6354 GEN_TM_NOOP(tabortdc);
6355 GEN_TM_NOOP(tabortdci);
6356 GEN_TM_NOOP(tsr);
6357 static inline void gen_cp_abort(DisasContext *ctx)
6358 {
6359 // Do Nothing
6360 }
6361
6362 #define GEN_CP_PASTE_NOOP(name) \
6363 static inline void gen_##name(DisasContext *ctx) \
6364 { \
6365 /* Generate invalid exception until \
6366 * we have an implementation of the copy \
6367 * paste facility \
6368 */ \
6369 gen_invalid(ctx); \
6370 }
6371
6372 GEN_CP_PASTE_NOOP(copy)
6373 GEN_CP_PASTE_NOOP(paste)
6374
6375 static void gen_tcheck(DisasContext *ctx)
6376 {
6377 if (unlikely(!ctx->tm_enabled)) {
6378 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6379 return;
6380 }
6381 /* Because tbegin always fails, the tcheck implementation
6382 * is simple:
6383 *
6384 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6385 * = 0b1 || 0b00 || 0b0
6386 */
6387 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6388 }
6389
6390 #if defined(CONFIG_USER_ONLY)
6391 #define GEN_TM_PRIV_NOOP(name) \
6392 static inline void gen_##name(DisasContext *ctx) \
6393 { \
6394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6395 }
6396
6397 #else
6398
6399 #define GEN_TM_PRIV_NOOP(name) \
6400 static inline void gen_##name(DisasContext *ctx) \
6401 { \
6402 CHK_SV; \
6403 if (unlikely(!ctx->tm_enabled)) { \
6404 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6405 return; \
6406 } \
6407 /* Because tbegin always fails, the implementation is \
6408 * simple: \
6409 * \
6410 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6411 * = 0b0 || 0b00 | 0b0 \
6412 */ \
6413 tcg_gen_movi_i32(cpu_crf[0], 0); \
6414 }
6415
6416 #endif
6417
6418 GEN_TM_PRIV_NOOP(treclaim);
6419 GEN_TM_PRIV_NOOP(trechkpt);
6420
6421 #include "translate/fp-impl.inc.c"
6422
6423 #include "translate/vmx-impl.inc.c"
6424
6425 #include "translate/vsx-impl.inc.c"
6426
6427 #include "translate/dfp-impl.inc.c"
6428
6429 #include "translate/spe-impl.inc.c"
6430
6431 /* Handles lfdp, lxsd, lxssp */
6432 static void gen_dform39(DisasContext *ctx)
6433 {
6434 switch (ctx->opcode & 0x3) {
6435 case 0: /* lfdp */
6436 if (ctx->insns_flags2 & PPC2_ISA205) {
6437 return gen_lfdp(ctx);
6438 }
6439 break;
6440 case 2: /* lxsd */
6441 if (ctx->insns_flags2 & PPC2_ISA300) {
6442 return gen_lxsd(ctx);
6443 }
6444 break;
6445 case 3: /* lxssp */
6446 if (ctx->insns_flags2 & PPC2_ISA300) {
6447 return gen_lxssp(ctx);
6448 }
6449 break;
6450 }
6451 return gen_invalid(ctx);
6452 }
6453
6454 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6455 static void gen_dform3D(DisasContext *ctx)
6456 {
6457 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6458 switch (ctx->opcode & 0x7) {
6459 case 1: /* lxv */
6460 if (ctx->insns_flags2 & PPC2_ISA300) {
6461 return gen_lxv(ctx);
6462 }
6463 break;
6464 case 5: /* stxv */
6465 if (ctx->insns_flags2 & PPC2_ISA300) {
6466 return gen_stxv(ctx);
6467 }
6468 break;
6469 }
6470 } else { /* DS-FORM */
6471 switch (ctx->opcode & 0x3) {
6472 case 0: /* stfdp */
6473 if (ctx->insns_flags2 & PPC2_ISA205) {
6474 return gen_stfdp(ctx);
6475 }
6476 break;
6477 case 2: /* stxsd */
6478 if (ctx->insns_flags2 & PPC2_ISA300) {
6479 return gen_stxsd(ctx);
6480 }
6481 break;
6482 case 3: /* stxssp */
6483 if (ctx->insns_flags2 & PPC2_ISA300) {
6484 return gen_stxssp(ctx);
6485 }
6486 break;
6487 }
6488 }
6489 return gen_invalid(ctx);
6490 }
6491
6492 static opcode_t opcodes[] = {
6493 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6494 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6495 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6496 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6497 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6498 #if defined(TARGET_PPC64)
6499 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6500 #endif
6501 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6502 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6503 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6504 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6505 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6506 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6507 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6508 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6509 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6510 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6511 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6512 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6513 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6514 #if defined(TARGET_PPC64)
6515 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6516 #endif
6517 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6518 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6519 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6520 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6521 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6522 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6523 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6524 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6525 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6526 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6527 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6528 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6529 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6530 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6531 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6532 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6533 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6534 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6535 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6536 #if defined(TARGET_PPC64)
6537 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6538 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6539 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6540 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6541 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6542 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6543 #endif
6544 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6545 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6546 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6547 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6548 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6549 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6550 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6551 #if defined(TARGET_PPC64)
6552 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6553 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6554 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6555 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6556 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6557 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6558 PPC_NONE, PPC2_ISA300),
6559 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6560 PPC_NONE, PPC2_ISA300),
6561 #endif
6562 #if defined(TARGET_PPC64)
6563 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6564 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6565 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6566 #endif
6567 /* handles lfdp, lxsd, lxssp */
6568 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6569 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6570 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6571 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6572 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6573 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6574 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6575 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6576 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6577 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6578 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6579 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6580 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6581 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6582 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6583 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6584 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6585 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6586 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6587 #if defined(TARGET_PPC64)
6588 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6589 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6590 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6591 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6592 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6593 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6594 #endif
6595 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6596 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6597 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6598 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6599 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6600 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6601 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6602 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6603 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6604 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6605 #if defined(TARGET_PPC64)
6606 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6607 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6608 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6609 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6610 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6611 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6612 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6613 #endif
6614 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6615 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6616 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6617 #if defined(TARGET_PPC64)
6618 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6619 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6620 #endif
6621 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6622 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6623 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6624 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6625 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6626 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6627 #if defined(TARGET_PPC64)
6628 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6629 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6630 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6631 #endif
6632 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6633 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6634 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6635 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6636 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6637 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6638 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6639 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6640 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6641 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6642 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6643 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6644 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6645 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6646 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6647 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6648 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6649 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6650 #if defined(TARGET_PPC64)
6651 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6652 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6653 PPC_SEGMENT_64B),
6654 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6655 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6656 PPC_SEGMENT_64B),
6657 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6658 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6659 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6660 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6661 #endif
6662 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6663 /* XXX Those instructions will need to be handled differently for
6664 * different ISA versions */
6665 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6666 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6667 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6668 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6669 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6670 #if defined(TARGET_PPC64)
6671 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6672 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6673 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6674 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6675 #endif
6676 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6677 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6678 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6679 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6680 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6681 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6682 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6683 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6684 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6685 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6686 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6687 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6688 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6689 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6690 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6691 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6692 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6693 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6694 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6695 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6696 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6697 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6698 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6699 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6700 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6701 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6702 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6703 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6704 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6705 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6706 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6707 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6708 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6709 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6710 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6711 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6712 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6713 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6714 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6715 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6716 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6717 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6718 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6719 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6720 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6721 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6722 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6723 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6724 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6725 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6726 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6727 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6728 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6729 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6730 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6731 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6732 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6733 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6734 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6735 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6736 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6737 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6738 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6739 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6740 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6741 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6742 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6743 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6744 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6745 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6746 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6747 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6748 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6749 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6750 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6751 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6752 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6753 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6754 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6755 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6756 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6757 PPC_NONE, PPC2_BOOKE206),
6758 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6759 PPC_NONE, PPC2_BOOKE206),
6760 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6761 PPC_NONE, PPC2_BOOKE206),
6762 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6763 PPC_NONE, PPC2_BOOKE206),
6764 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6765 PPC_NONE, PPC2_BOOKE206),
6766 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6767 PPC_NONE, PPC2_PRCNTL),
6768 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6769 PPC_NONE, PPC2_PRCNTL),
6770 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
6771 PPC_NONE, PPC2_PRCNTL),
6772 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6773 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6774 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6775 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6776 PPC_BOOKE, PPC2_BOOKE206),
6777 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6778 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6779 PPC_BOOKE, PPC2_BOOKE206),
6780 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
6781 PPC_440_SPEC),
6782 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6783 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6784 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6785 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6786 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6787 #if defined(TARGET_PPC64)
6788 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6789 PPC2_ISA300),
6790 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6791 #endif
6792
6793 #undef GEN_INT_ARITH_ADD
6794 #undef GEN_INT_ARITH_ADD_CONST
6795 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6796 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6797 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6798 add_ca, compute_ca, compute_ov) \
6799 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6800 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6801 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6802 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6803 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6804 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6805 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6806 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6807 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6808 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6809 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6810
6811 #undef GEN_INT_ARITH_DIVW
6812 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6813 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6814 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6815 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6816 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6817 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6818 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6819 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6820 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6821 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6822 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6823 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6824
6825 #if defined(TARGET_PPC64)
6826 #undef GEN_INT_ARITH_DIVD
6827 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6828 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6829 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6830 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6831 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6832 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6833
6834 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6835 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6836 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6837 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6838 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6839 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6840
6841 #undef GEN_INT_ARITH_MUL_HELPER
6842 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6843 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6844 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6845 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6846 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6847 #endif
6848
6849 #undef GEN_INT_ARITH_SUBF
6850 #undef GEN_INT_ARITH_SUBF_CONST
6851 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6852 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6853 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6854 add_ca, compute_ca, compute_ov) \
6855 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6856 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6857 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6858 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6859 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6860 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6861 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6862 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6863 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6864 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6865 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6866
6867 #undef GEN_LOGICAL1
6868 #undef GEN_LOGICAL2
6869 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6870 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6871 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6872 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6873 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6874 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6875 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6876 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6877 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6878 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6879 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6880 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6881 #if defined(TARGET_PPC64)
6882 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6883 #endif
6884
6885 #if defined(TARGET_PPC64)
6886 #undef GEN_PPC64_R2
6887 #undef GEN_PPC64_R4
6888 #define GEN_PPC64_R2(name, opc1, opc2) \
6889 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6890 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6891 PPC_64B)
6892 #define GEN_PPC64_R4(name, opc1, opc2) \
6893 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6894 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6895 PPC_64B), \
6896 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6897 PPC_64B), \
6898 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6899 PPC_64B)
6900 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6901 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6902 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6903 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6904 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6905 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6906 #endif
6907
6908 #undef GEN_LD
6909 #undef GEN_LDU
6910 #undef GEN_LDUX
6911 #undef GEN_LDX_E
6912 #undef GEN_LDS
6913 #define GEN_LD(name, ldop, opc, type) \
6914 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6915 #define GEN_LDU(name, ldop, opc, type) \
6916 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6917 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6918 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6919 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6920 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6921 #define GEN_LDS(name, ldop, op, type) \
6922 GEN_LD(name, ldop, op | 0x20, type) \
6923 GEN_LDU(name, ldop, op | 0x21, type) \
6924 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6925 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6926
6927 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6928 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6929 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6930 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6931 #if defined(TARGET_PPC64)
6932 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6933 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6934 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6935 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6936 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6937
6938 /* HV/P7 and later only */
6939 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6940 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6941 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6942 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6943 #endif
6944 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6945 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6946
6947 #undef GEN_ST
6948 #undef GEN_STU
6949 #undef GEN_STUX
6950 #undef GEN_STX_E
6951 #undef GEN_STS
6952 #define GEN_ST(name, stop, opc, type) \
6953 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6954 #define GEN_STU(name, stop, opc, type) \
6955 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6956 #define GEN_STUX(name, stop, opc2, opc3, type) \
6957 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6958 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6959 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6960 #define GEN_STS(name, stop, op, type) \
6961 GEN_ST(name, stop, op | 0x20, type) \
6962 GEN_STU(name, stop, op | 0x21, type) \
6963 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6964 GEN_STX(name, stop, 0x17, op | 0x00, type)
6965
6966 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6967 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6968 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6969 #if defined(TARGET_PPC64)
6970 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6971 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6972 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6973 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6974 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6975 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6976 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6977 #endif
6978 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6979 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6980
6981 #undef GEN_CRLOGIC
6982 #define GEN_CRLOGIC(name, tcg_op, opc) \
6983 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6984 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6985 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6986 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6987 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6988 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6989 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6990 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6991 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6992
6993 #undef GEN_MAC_HANDLER
6994 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6995 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6996 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6997 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6998 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6999 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
7000 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
7001 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
7002 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
7003 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
7004 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
7005 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
7006 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
7007 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
7008 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
7009 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
7010 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
7011 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
7012 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
7013 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
7014 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
7015 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
7016 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
7017 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
7018 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
7019 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
7020 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
7021 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
7022 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
7023 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
7024 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
7025 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
7026 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
7027 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
7028 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
7029 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
7030 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
7031 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
7032 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
7033 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
7034 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
7035 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
7036 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
7037 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
7038
7039 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7040 PPC_NONE, PPC2_TM),
7041 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7042 PPC_NONE, PPC2_TM),
7043 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7044 PPC_NONE, PPC2_TM),
7045 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7046 PPC_NONE, PPC2_TM),
7047 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7048 PPC_NONE, PPC2_TM),
7049 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7050 PPC_NONE, PPC2_TM),
7051 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7052 PPC_NONE, PPC2_TM),
7053 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7054 PPC_NONE, PPC2_TM),
7055 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7056 PPC_NONE, PPC2_TM),
7057 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7058 PPC_NONE, PPC2_TM),
7059 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7060 PPC_NONE, PPC2_TM),
7061
7062 #include "translate/fp-ops.inc.c"
7063
7064 #include "translate/vmx-ops.inc.c"
7065
7066 #include "translate/vsx-ops.inc.c"
7067
7068 #include "translate/dfp-ops.inc.c"
7069
7070 #include "translate/spe-ops.inc.c"
7071 };
7072
7073 #include "helper_regs.h"
7074 #include "translate_init.inc.c"
7075
7076 /*****************************************************************************/
7077 /* Misc PowerPC helpers */
7078 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
7079 int flags)
7080 {
7081 #define RGPL 4
7082 #define RFPL 4
7083
7084 PowerPCCPU *cpu = POWERPC_CPU(cs);
7085 CPUPPCState *env = &cpu->env;
7086 int i;
7087
7088 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7089 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7090 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7091 cs->cpu_index);
7092 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7093 TARGET_FMT_lx " iidx %d didx %d\n",
7094 env->msr, env->spr[SPR_HID0],
7095 env->hflags, env->immu_idx, env->dmmu_idx);
7096 #if !defined(NO_TIMER_DUMP)
7097 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7098 #if !defined(CONFIG_USER_ONLY)
7099 " DECR %08" PRIu32
7100 #endif
7101 "\n",
7102 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7103 #if !defined(CONFIG_USER_ONLY)
7104 , cpu_ppc_load_decr(env)
7105 #endif
7106 );
7107 #endif
7108 for (i = 0; i < 32; i++) {
7109 if ((i & (RGPL - 1)) == 0)
7110 cpu_fprintf(f, "GPR%02d", i);
7111 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7112 if ((i & (RGPL - 1)) == (RGPL - 1))
7113 cpu_fprintf(f, "\n");
7114 }
7115 cpu_fprintf(f, "CR ");
7116 for (i = 0; i < 8; i++)
7117 cpu_fprintf(f, "%01x", env->crf[i]);
7118 cpu_fprintf(f, " [");
7119 for (i = 0; i < 8; i++) {
7120 char a = '-';
7121 if (env->crf[i] & 0x08)
7122 a = 'L';
7123 else if (env->crf[i] & 0x04)
7124 a = 'G';
7125 else if (env->crf[i] & 0x02)
7126 a = 'E';
7127 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7128 }
7129 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7130 env->reserve_addr);
7131
7132 if (flags & CPU_DUMP_FPU) {
7133 for (i = 0; i < 32; i++) {
7134 if ((i & (RFPL - 1)) == 0) {
7135 cpu_fprintf(f, "FPR%02d", i);
7136 }
7137 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7138 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7139 cpu_fprintf(f, "\n");
7140 }
7141 }
7142 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7143 }
7144
7145 #if !defined(CONFIG_USER_ONLY)
7146 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7147 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7148 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7149 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7150
7151 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7152 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7153 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7154 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7155
7156 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7157 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7158 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7159 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7160
7161 #if defined(TARGET_PPC64)
7162 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7163 env->excp_model == POWERPC_EXCP_POWER8) {
7164 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7165 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7166 }
7167 #endif
7168 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7169 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7170 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7171 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7172 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7173
7174 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7175 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7176 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7177 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7178
7179 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7180 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7181 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7182 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7183
7184 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7185 " EPR " TARGET_FMT_lx "\n",
7186 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7187 env->spr[SPR_BOOKE_EPR]);
7188
7189 /* FSL-specific */
7190 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7191 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7192 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7193 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7194
7195 /*
7196 * IVORs are left out as they are large and do not change often --
7197 * they can be read with "p $ivor0", "p $ivor1", etc.
7198 */
7199 }
7200
7201 #if defined(TARGET_PPC64)
7202 if (env->flags & POWERPC_FLAG_CFAR) {
7203 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7204 }
7205 #endif
7206
7207 if (env->spr_cb[SPR_LPCR].name)
7208 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7209
7210 switch (env->mmu_model) {
7211 case POWERPC_MMU_32B:
7212 case POWERPC_MMU_601:
7213 case POWERPC_MMU_SOFT_6xx:
7214 case POWERPC_MMU_SOFT_74xx:
7215 #if defined(TARGET_PPC64)
7216 case POWERPC_MMU_64B:
7217 case POWERPC_MMU_2_03:
7218 case POWERPC_MMU_2_06:
7219 case POWERPC_MMU_2_07:
7220 case POWERPC_MMU_3_00:
7221 #endif
7222 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7223 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7224 }
7225 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7226 cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7227 }
7228 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7229 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7230 break;
7231 case POWERPC_MMU_BOOKE206:
7232 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7233 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7234 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7235 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7236
7237 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7238 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7239 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7240 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7241
7242 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7243 " TLB1CFG " TARGET_FMT_lx "\n",
7244 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7245 env->spr[SPR_BOOKE_TLB1CFG]);
7246 break;
7247 default:
7248 break;
7249 }
7250 #endif
7251
7252 #undef RGPL
7253 #undef RFPL
7254 }
7255
7256 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7257 fprintf_function cpu_fprintf, int flags)
7258 {
7259 #if defined(DO_PPC_STATISTICS)
7260 PowerPCCPU *cpu = POWERPC_CPU(cs);
7261 opc_handler_t **t1, **t2, **t3, *handler;
7262 int op1, op2, op3;
7263
7264 t1 = cpu->env.opcodes;
7265 for (op1 = 0; op1 < 64; op1++) {
7266 handler = t1[op1];
7267 if (is_indirect_opcode(handler)) {
7268 t2 = ind_table(handler);
7269 for (op2 = 0; op2 < 32; op2++) {
7270 handler = t2[op2];
7271 if (is_indirect_opcode(handler)) {
7272 t3 = ind_table(handler);
7273 for (op3 = 0; op3 < 32; op3++) {
7274 handler = t3[op3];
7275 if (handler->count == 0)
7276 continue;
7277 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7278 "%016" PRIx64 " %" PRId64 "\n",
7279 op1, op2, op3, op1, (op3 << 5) | op2,
7280 handler->oname,
7281 handler->count, handler->count);
7282 }
7283 } else {
7284 if (handler->count == 0)
7285 continue;
7286 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7287 "%016" PRIx64 " %" PRId64 "\n",
7288 op1, op2, op1, op2, handler->oname,
7289 handler->count, handler->count);
7290 }
7291 }
7292 } else {
7293 if (handler->count == 0)
7294 continue;
7295 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7296 " %" PRId64 "\n",
7297 op1, op1, handler->oname,
7298 handler->count, handler->count);
7299 }
7300 }
7301 #endif
7302 }
7303
7304 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7305 {
7306 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7307 CPUPPCState *env = cs->env_ptr;
7308 int bound;
7309
7310 ctx->exception = POWERPC_EXCP_NONE;
7311 ctx->spr_cb = env->spr_cb;
7312 ctx->pr = msr_pr;
7313 ctx->mem_idx = env->dmmu_idx;
7314 ctx->dr = msr_dr;
7315 #if !defined(CONFIG_USER_ONLY)
7316 ctx->hv = msr_hv || !env->has_hv_mode;
7317 #endif
7318 ctx->insns_flags = env->insns_flags;
7319 ctx->insns_flags2 = env->insns_flags2;
7320 ctx->access_type = -1;
7321 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7322 ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
7323 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7324 #if defined(TARGET_PPC64)
7325 ctx->sf_mode = msr_is_64bit(env, env->msr);
7326 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7327 #endif
7328 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7329 || env->mmu_model == POWERPC_MMU_601
7330 || (env->mmu_model & POWERPC_MMU_64B);
7331
7332 ctx->fpu_enabled = !!msr_fp;
7333 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7334 ctx->spe_enabled = !!msr_spe;
7335 else
7336 ctx->spe_enabled = false;
7337 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7338 ctx->altivec_enabled = !!msr_vr;
7339 else
7340 ctx->altivec_enabled = false;
7341 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7342 ctx->vsx_enabled = !!msr_vsx;
7343 } else {
7344 ctx->vsx_enabled = false;
7345 }
7346 #if defined(TARGET_PPC64)
7347 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7348 ctx->tm_enabled = !!msr_tm;
7349 } else {
7350 ctx->tm_enabled = false;
7351 }
7352 #endif
7353 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7354 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7355 ctx->singlestep_enabled = CPU_SINGLE_STEP;
7356 else
7357 ctx->singlestep_enabled = 0;
7358 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7359 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7360 if (unlikely(ctx->base.singlestep_enabled)) {
7361 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7362 }
7363 #if defined (DO_SINGLE_STEP) && 0
7364 /* Single step trace mode */
7365 msr_se = 1;
7366 #endif
7367
7368 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
7369 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
7370 }
7371
7372 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7373 {
7374 }
7375
7376 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7377 {
7378 tcg_gen_insn_start(dcbase->pc_next);
7379 }
7380
7381 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
7382 const CPUBreakpoint *bp)
7383 {
7384 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7385
7386 gen_debug_exception(ctx);
7387 /* The address covered by the breakpoint must be included in
7388 [tb->pc, tb->pc + tb->size) in order to for it to be
7389 properly cleared -- thus we increment the PC here so that
7390 the logic setting tb->size below does the right thing. */
7391 ctx->base.pc_next += 4;
7392 return true;
7393 }
7394
7395 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7396 {
7397 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7398 CPUPPCState *env = cs->env_ptr;
7399 opc_handler_t **table, *handler;
7400
7401 LOG_DISAS("----------------\n");
7402 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7403 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7404
7405 if (unlikely(need_byteswap(ctx))) {
7406 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next));
7407 } else {
7408 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
7409 }
7410 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7411 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
7412 opc3(ctx->opcode), opc4(ctx->opcode),
7413 ctx->le_mode ? "little" : "big");
7414 ctx->base.pc_next += 4;
7415 table = env->opcodes;
7416 handler = table[opc1(ctx->opcode)];
7417 if (is_indirect_opcode(handler)) {
7418 table = ind_table(handler);
7419 handler = table[opc2(ctx->opcode)];
7420 if (is_indirect_opcode(handler)) {
7421 table = ind_table(handler);
7422 handler = table[opc3(ctx->opcode)];
7423 if (is_indirect_opcode(handler)) {
7424 table = ind_table(handler);
7425 handler = table[opc4(ctx->opcode)];
7426 }
7427 }
7428 }
7429 /* Is opcode *REALLY* valid ? */
7430 if (unlikely(handler->handler == &gen_invalid)) {
7431 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7432 "%02x - %02x - %02x - %02x (%08x) "
7433 TARGET_FMT_lx " %d\n",
7434 opc1(ctx->opcode), opc2(ctx->opcode),
7435 opc3(ctx->opcode), opc4(ctx->opcode),
7436 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
7437 } else {
7438 uint32_t inval;
7439
7440 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7441 && Rc(ctx->opcode))) {
7442 inval = handler->inval2;
7443 } else {
7444 inval = handler->inval1;
7445 }
7446
7447 if (unlikely((ctx->opcode & inval) != 0)) {
7448 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7449 "%02x - %02x - %02x - %02x (%08x) "
7450 TARGET_FMT_lx "\n", ctx->opcode & inval,
7451 opc1(ctx->opcode), opc2(ctx->opcode),
7452 opc3(ctx->opcode), opc4(ctx->opcode),
7453 ctx->opcode, ctx->base.pc_next - 4);
7454 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7455 ctx->base.is_jmp = DISAS_NORETURN;
7456 return;
7457 }
7458 }
7459 (*(handler->handler))(ctx);
7460 #if defined(DO_PPC_STATISTICS)
7461 handler->count++;
7462 #endif
7463 /* Check trace mode exceptions */
7464 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
7465 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
7466 ctx->exception != POWERPC_SYSCALL &&
7467 ctx->exception != POWERPC_EXCP_TRAP &&
7468 ctx->exception != POWERPC_EXCP_BRANCH)) {
7469 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next);
7470 }
7471
7472 if (tcg_check_temp_count()) {
7473 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7474 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
7475 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
7476 }
7477
7478 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
7479 DISAS_NEXT : DISAS_NORETURN;
7480 }
7481
7482 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7483 {
7484 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7485
7486 if (ctx->exception == POWERPC_EXCP_NONE) {
7487 gen_goto_tb(ctx, 0, ctx->base.pc_next);
7488 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
7489 if (unlikely(ctx->base.singlestep_enabled)) {
7490 gen_debug_exception(ctx);
7491 }
7492 /* Generate the return instruction */
7493 tcg_gen_exit_tb(NULL, 0);
7494 }
7495 }
7496
7497 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
7498 {
7499 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
7500 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
7501 }
7502
7503 static const TranslatorOps ppc_tr_ops = {
7504 .init_disas_context = ppc_tr_init_disas_context,
7505 .tb_start = ppc_tr_tb_start,
7506 .insn_start = ppc_tr_insn_start,
7507 .breakpoint_check = ppc_tr_breakpoint_check,
7508 .translate_insn = ppc_tr_translate_insn,
7509 .tb_stop = ppc_tr_tb_stop,
7510 .disas_log = ppc_tr_disas_log,
7511 };
7512
7513 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
7514 {
7515 DisasContext ctx;
7516
7517 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
7518 }
7519
7520 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7521 target_ulong *data)
7522 {
7523 env->nip = data[0];
7524 }
Ray Wang's QEMU Repository