2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "trace-tcg.h"
34 #include "exec/translator.h"
38 #define CPU_SINGLE_STEP 0x1
39 #define CPU_BRANCH_STEP 0x2
40 #define GDBSTUB_SINGLE_STEP 0x4
42 /* Include definitions for instructions classes and implementations flags */
43 //#define PPC_DEBUG_DISAS
44 //#define DO_PPC_STATISTICS
46 #ifdef PPC_DEBUG_DISAS
47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
49 # define LOG_DISAS(...) do { } while (0)
51 /*****************************************************************************/
52 /* Code translation helpers */
54 /* global register indexes */
55 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
61 static TCGv cpu_gpr
[32];
62 static TCGv cpu_gprh
[32];
63 static TCGv_i64 cpu_fpr
[32];
64 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
65 static TCGv_i64 cpu_vsr
[32];
66 static TCGv_i32 cpu_crf
[8];
71 #if defined(TARGET_PPC64)
74 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
, cpu_ov32
, cpu_ca32
;
75 static TCGv cpu_reserve
;
76 static TCGv cpu_reserve_val
;
77 static TCGv cpu_fpscr
;
78 static TCGv_i32 cpu_access_type
;
80 #include "exec/gen-icount.h"
82 void ppc_translate_init(void)
86 size_t cpu_reg_names_size
;
89 cpu_reg_names_size
= sizeof(cpu_reg_names
);
91 for (i
= 0; i
< 8; i
++) {
92 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
93 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
94 offsetof(CPUPPCState
, crf
[i
]), p
);
96 cpu_reg_names_size
-= 5;
99 for (i
= 0; i
< 32; i
++) {
100 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
101 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
102 offsetof(CPUPPCState
, gpr
[i
]), p
);
103 p
+= (i
< 10) ? 3 : 4;
104 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
105 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
106 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
107 offsetof(CPUPPCState
, gprh
[i
]), p
);
108 p
+= (i
< 10) ? 4 : 5;
109 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
111 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
112 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
113 offsetof(CPUPPCState
, fpr
[i
]), p
);
114 p
+= (i
< 10) ? 4 : 5;
115 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
117 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
118 #ifdef HOST_WORDS_BIGENDIAN
119 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
120 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
122 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
123 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
125 p
+= (i
< 10) ? 6 : 7;
126 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
128 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
129 #ifdef HOST_WORDS_BIGENDIAN
130 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
131 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
133 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
134 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
136 p
+= (i
< 10) ? 6 : 7;
137 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
138 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
139 cpu_vsr
[i
] = tcg_global_mem_new_i64(cpu_env
,
140 offsetof(CPUPPCState
, vsr
[i
]), p
);
141 p
+= (i
< 10) ? 5 : 6;
142 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
145 cpu_nip
= tcg_global_mem_new(cpu_env
,
146 offsetof(CPUPPCState
, nip
), "nip");
148 cpu_msr
= tcg_global_mem_new(cpu_env
,
149 offsetof(CPUPPCState
, msr
), "msr");
151 cpu_ctr
= tcg_global_mem_new(cpu_env
,
152 offsetof(CPUPPCState
, ctr
), "ctr");
154 cpu_lr
= tcg_global_mem_new(cpu_env
,
155 offsetof(CPUPPCState
, lr
), "lr");
157 #if defined(TARGET_PPC64)
158 cpu_cfar
= tcg_global_mem_new(cpu_env
,
159 offsetof(CPUPPCState
, cfar
), "cfar");
162 cpu_xer
= tcg_global_mem_new(cpu_env
,
163 offsetof(CPUPPCState
, xer
), "xer");
164 cpu_so
= tcg_global_mem_new(cpu_env
,
165 offsetof(CPUPPCState
, so
), "SO");
166 cpu_ov
= tcg_global_mem_new(cpu_env
,
167 offsetof(CPUPPCState
, ov
), "OV");
168 cpu_ca
= tcg_global_mem_new(cpu_env
,
169 offsetof(CPUPPCState
, ca
), "CA");
170 cpu_ov32
= tcg_global_mem_new(cpu_env
,
171 offsetof(CPUPPCState
, ov32
), "OV32");
172 cpu_ca32
= tcg_global_mem_new(cpu_env
,
173 offsetof(CPUPPCState
, ca32
), "CA32");
175 cpu_reserve
= tcg_global_mem_new(cpu_env
,
176 offsetof(CPUPPCState
, reserve_addr
),
178 cpu_reserve_val
= tcg_global_mem_new(cpu_env
,
179 offsetof(CPUPPCState
, reserve_val
),
182 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
183 offsetof(CPUPPCState
, fpscr
), "fpscr");
185 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
186 offsetof(CPUPPCState
, access_type
), "access_type");
189 /* internal defines */
190 struct DisasContext
{
191 DisasContextBase base
;
194 /* Routine used to access memory */
195 bool pr
, hv
, dr
, le_mode
;
197 bool need_access_type
;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask
;
202 #if defined(TARGET_PPC64)
207 bool altivec_enabled
;
212 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled
;
214 uint64_t insns_flags
;
215 uint64_t insns_flags2
;
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext
*ctx
)
221 #if defined(TARGET_WORDS_BIGENDIAN)
224 return !ctx
->le_mode
;
228 /* True when active word size < size of target_long. */
230 # define NARROW_MODE(C) (!(C)->sf_mode)
232 # define NARROW_MODE(C) 0
235 struct opc_handler_t
{
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
240 /* instruction type */
242 /* extended instruction type */
245 void (*handler
)(DisasContext
*ctx
);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
249 #if defined(DO_PPC_STATISTICS)
254 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
256 if (ctx
->need_access_type
&& ctx
->access_type
!= access_type
) {
257 tcg_gen_movi_i32(cpu_access_type
, access_type
);
258 ctx
->access_type
= access_type
;
262 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
264 if (NARROW_MODE(ctx
)) {
267 tcg_gen_movi_tl(cpu_nip
, nip
);
270 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
277 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
278 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
280 t0
= tcg_const_i32(excp
);
281 t1
= tcg_const_i32(error
);
282 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
283 tcg_temp_free_i32(t0
);
284 tcg_temp_free_i32(t1
);
285 ctx
->exception
= (excp
);
288 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
295 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
296 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
298 t0
= tcg_const_i32(excp
);
299 gen_helper_raise_exception(cpu_env
, t0
);
300 tcg_temp_free_i32(t0
);
301 ctx
->exception
= (excp
);
304 static void gen_exception_nip(DisasContext
*ctx
, uint32_t excp
,
309 gen_update_nip(ctx
, nip
);
310 t0
= tcg_const_i32(excp
);
311 gen_helper_raise_exception(cpu_env
, t0
);
312 tcg_temp_free_i32(t0
);
313 ctx
->exception
= (excp
);
316 static void gen_debug_exception(DisasContext
*ctx
)
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
323 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
324 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
325 gen_update_nip(ctx
, ctx
->base
.pc_next
);
327 t0
= tcg_const_i32(EXCP_DEBUG
);
328 gen_helper_raise_exception(cpu_env
, t0
);
329 tcg_temp_free_i32(t0
);
332 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
338 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
340 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
343 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext
*ctx
)
352 gen_update_nip(ctx
, ctx
->base
.pc_next
);
353 ctx
->exception
= POWERPC_EXCP_STOP
;
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext
*ctx
)
360 ctx
->exception
= POWERPC_EXCP_SYNC
;
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
379 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
380 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
382 typedef struct opcode_t
{
383 unsigned char opc1
, opc2
, opc3
, opc4
;
384 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
385 unsigned char pad
[4];
387 opc_handler_t handler
;
391 /* Helpers for priv. check */
394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
397 #if defined(CONFIG_USER_ONLY)
398 #define CHK_HV GEN_PRIV
399 #define CHK_SV GEN_PRIV
400 #define CHK_HVRM GEN_PRIV
404 if (unlikely(ctx->pr || !ctx->hv)) { \
410 if (unlikely(ctx->pr)) { \
416 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
424 /*****************************************************************************/
425 /* PowerPC instructions table */
427 #if defined(DO_PPC_STATISTICS)
428 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
438 .handler = &gen_##name, \
439 .oname = stringify(name), \
441 .oname = stringify(name), \
443 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
454 .handler = &gen_##name, \
455 .oname = stringify(name), \
457 .oname = stringify(name), \
459 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
469 .handler = &gen_##name, \
474 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
484 .handler = &gen_##name, \
485 .oname = stringify(name), \
487 .oname = stringify(name), \
489 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
499 .handler = &gen_##name, \
505 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
515 .handler = &gen_##name, \
517 .oname = stringify(name), \
519 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
530 .handler = &gen_##name, \
532 .oname = stringify(name), \
534 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
544 .handler = &gen_##name, \
548 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
558 .handler = &gen_##name, \
560 .oname = stringify(name), \
562 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
572 .handler = &gen_##name, \
578 /* SPR load/store helpers */
579 static inline void gen_load_spr(TCGv t
, int reg
)
581 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
584 static inline void gen_store_spr(int reg
, TCGv t
)
586 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
589 /* Invalid instruction */
590 static void gen_invalid(DisasContext
*ctx
)
592 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
595 static opc_handler_t invalid_handler
= {
596 .inval1
= 0xFFFFFFFF,
597 .inval2
= 0xFFFFFFFF,
600 .handler
= gen_invalid
,
603 /*** Integer comparison ***/
605 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
607 TCGv t0
= tcg_temp_new();
608 TCGv t1
= tcg_temp_new();
609 TCGv_i32 t
= tcg_temp_new_i32();
611 tcg_gen_movi_tl(t0
, CRF_EQ
);
612 tcg_gen_movi_tl(t1
, CRF_LT
);
613 tcg_gen_movcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
, t1
, t0
);
614 tcg_gen_movi_tl(t1
, CRF_GT
);
615 tcg_gen_movcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
, t1
, t0
);
617 tcg_gen_trunc_tl_i32(t
, t0
);
618 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
619 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t
);
623 tcg_temp_free_i32(t
);
626 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
628 TCGv t0
= tcg_const_tl(arg1
);
629 gen_op_cmp(arg0
, t0
, s
, crf
);
633 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
639 tcg_gen_ext32s_tl(t0
, arg0
);
640 tcg_gen_ext32s_tl(t1
, arg1
);
642 tcg_gen_ext32u_tl(t0
, arg0
);
643 tcg_gen_ext32u_tl(t1
, arg1
);
645 gen_op_cmp(t0
, t1
, s
, crf
);
650 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
652 TCGv t0
= tcg_const_tl(arg1
);
653 gen_op_cmp32(arg0
, t0
, s
, crf
);
657 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
659 if (NARROW_MODE(ctx
)) {
660 gen_op_cmpi32(reg
, 0, 1, 0);
662 gen_op_cmpi(reg
, 0, 1, 0);
667 static void gen_cmp(DisasContext
*ctx
)
669 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
670 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
671 1, crfD(ctx
->opcode
));
673 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
674 1, crfD(ctx
->opcode
));
679 static void gen_cmpi(DisasContext
*ctx
)
681 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
682 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
683 1, crfD(ctx
->opcode
));
685 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
686 1, crfD(ctx
->opcode
));
691 static void gen_cmpl(DisasContext
*ctx
)
693 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
694 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
695 0, crfD(ctx
->opcode
));
697 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
698 0, crfD(ctx
->opcode
));
703 static void gen_cmpli(DisasContext
*ctx
)
705 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
706 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
707 0, crfD(ctx
->opcode
));
709 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
710 0, crfD(ctx
->opcode
));
714 /* cmprb - range comparison: isupper, isaplha, islower*/
715 static void gen_cmprb(DisasContext
*ctx
)
717 TCGv_i32 src1
= tcg_temp_new_i32();
718 TCGv_i32 src2
= tcg_temp_new_i32();
719 TCGv_i32 src2lo
= tcg_temp_new_i32();
720 TCGv_i32 src2hi
= tcg_temp_new_i32();
721 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
723 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
724 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
726 tcg_gen_andi_i32(src1
, src1
, 0xFF);
727 tcg_gen_ext8u_i32(src2lo
, src2
);
728 tcg_gen_shri_i32(src2
, src2
, 8);
729 tcg_gen_ext8u_i32(src2hi
, src2
);
731 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
732 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
733 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
735 if (ctx
->opcode
& 0x00200000) {
736 tcg_gen_shri_i32(src2
, src2
, 8);
737 tcg_gen_ext8u_i32(src2lo
, src2
);
738 tcg_gen_shri_i32(src2
, src2
, 8);
739 tcg_gen_ext8u_i32(src2hi
, src2
);
740 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
741 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
742 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
743 tcg_gen_or_i32(crf
, crf
, src2lo
);
745 tcg_gen_shli_i32(crf
, crf
, CRF_GT_BIT
);
746 tcg_temp_free_i32(src1
);
747 tcg_temp_free_i32(src2
);
748 tcg_temp_free_i32(src2lo
);
749 tcg_temp_free_i32(src2hi
);
752 #if defined(TARGET_PPC64)
754 static void gen_cmpeqb(DisasContext
*ctx
)
756 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
757 cpu_gpr
[rB(ctx
->opcode
)]);
761 /* isel (PowerPC 2.03 specification) */
762 static void gen_isel(DisasContext
*ctx
)
764 uint32_t bi
= rC(ctx
->opcode
);
765 uint32_t mask
= 0x08 >> (bi
& 0x03);
766 TCGv t0
= tcg_temp_new();
769 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
770 tcg_gen_andi_tl(t0
, t0
, mask
);
772 zr
= tcg_const_tl(0);
773 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
774 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
775 cpu_gpr
[rB(ctx
->opcode
)]);
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext
*ctx
)
783 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
784 cpu_gpr
[rB(ctx
->opcode
)]);
787 /*** Integer arithmetic ***/
789 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
790 TCGv arg1
, TCGv arg2
, int sub
)
792 TCGv t0
= tcg_temp_new();
794 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
795 tcg_gen_xor_tl(t0
, arg1
, arg2
);
797 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
799 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
802 if (NARROW_MODE(ctx
)) {
803 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, 31, 1);
804 if (is_isa300(ctx
)) {
805 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
808 if (is_isa300(ctx
)) {
809 tcg_gen_extract_tl(cpu_ov32
, cpu_ov
, 31, 1);
811 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1, 1);
813 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
816 static inline void gen_op_arith_compute_ca32(DisasContext
*ctx
,
817 TCGv res
, TCGv arg0
, TCGv arg1
,
822 if (!is_isa300(ctx
)) {
828 tcg_gen_eqv_tl(t0
, arg0
, arg1
);
830 tcg_gen_xor_tl(t0
, arg0
, arg1
);
832 tcg_gen_xor_tl(t0
, t0
, res
);
833 tcg_gen_extract_tl(cpu_ca32
, t0
, 32, 1);
837 /* Common add function */
838 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
839 TCGv arg2
, bool add_ca
, bool compute_ca
,
840 bool compute_ov
, bool compute_rc0
)
844 if (compute_ca
|| compute_ov
) {
849 if (NARROW_MODE(ctx
)) {
850 /* Caution: a non-obvious corner case of the spec is that we
851 must produce the *entire* 64-bit addition, but produce the
852 carry into bit 32. */
853 TCGv t1
= tcg_temp_new();
854 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
855 tcg_gen_add_tl(t0
, arg1
, arg2
);
857 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
859 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
861 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
862 if (is_isa300(ctx
)) {
863 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
866 TCGv zero
= tcg_const_tl(0);
868 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
869 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
871 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
873 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, 0);
877 tcg_gen_add_tl(t0
, arg1
, arg2
);
879 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
884 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
886 if (unlikely(compute_rc0
)) {
887 gen_set_Rc0(ctx
, t0
);
891 tcg_gen_mov_tl(ret
, t0
);
895 /* Add functions with two operands */
896 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
899 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
900 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
901 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
903 /* Add functions with one operand and one immediate */
904 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
905 add_ca, compute_ca, compute_ov) \
906 static void glue(gen_, name)(DisasContext *ctx) \
908 TCGv t0 = tcg_const_tl(const_val); \
909 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
910 cpu_gpr[rA(ctx->opcode)], t0, \
911 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
915 /* add add. addo addo. */
916 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
917 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
918 /* addc addc. addco addco. */
919 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
920 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
921 /* adde adde. addeo addeo. */
922 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
923 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
924 /* addme addme. addmeo addmeo. */
925 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
926 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
927 /* addze addze. addzeo addzeo.*/
928 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
929 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
931 static void gen_addi(DisasContext
*ctx
)
933 target_long simm
= SIMM(ctx
->opcode
);
935 if (rA(ctx
->opcode
) == 0) {
937 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
939 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
940 cpu_gpr
[rA(ctx
->opcode
)], simm
);
944 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
946 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
947 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
948 c
, 0, 1, 0, compute_rc0
);
952 static void gen_addic(DisasContext
*ctx
)
954 gen_op_addic(ctx
, 0);
957 static void gen_addic_(DisasContext
*ctx
)
959 gen_op_addic(ctx
, 1);
963 static void gen_addis(DisasContext
*ctx
)
965 target_long simm
= SIMM(ctx
->opcode
);
967 if (rA(ctx
->opcode
) == 0) {
969 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
971 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
972 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
977 static void gen_addpcis(DisasContext
*ctx
)
979 target_long d
= DX(ctx
->opcode
);
981 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->base
.pc_next
+ (d
<< 16));
984 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
985 TCGv arg2
, int sign
, int compute_ov
)
987 TCGv_i32 t0
= tcg_temp_new_i32();
988 TCGv_i32 t1
= tcg_temp_new_i32();
989 TCGv_i32 t2
= tcg_temp_new_i32();
990 TCGv_i32 t3
= tcg_temp_new_i32();
992 tcg_gen_trunc_tl_i32(t0
, arg1
);
993 tcg_gen_trunc_tl_i32(t1
, arg2
);
995 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
996 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
997 tcg_gen_and_i32(t2
, t2
, t3
);
998 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
999 tcg_gen_or_i32(t2
, t2
, t3
);
1000 tcg_gen_movi_i32(t3
, 0);
1001 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1002 tcg_gen_div_i32(t3
, t0
, t1
);
1003 tcg_gen_extu_i32_tl(ret
, t3
);
1005 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t1
, 0);
1006 tcg_gen_movi_i32(t3
, 0);
1007 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1008 tcg_gen_divu_i32(t3
, t0
, t1
);
1009 tcg_gen_extu_i32_tl(ret
, t3
);
1012 tcg_gen_extu_i32_tl(cpu_ov
, t2
);
1013 if (is_isa300(ctx
)) {
1014 tcg_gen_extu_i32_tl(cpu_ov32
, t2
);
1016 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1018 tcg_temp_free_i32(t0
);
1019 tcg_temp_free_i32(t1
);
1020 tcg_temp_free_i32(t2
);
1021 tcg_temp_free_i32(t3
);
1023 if (unlikely(Rc(ctx
->opcode
) != 0))
1024 gen_set_Rc0(ctx
, ret
);
1027 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1028 static void glue(gen_, name)(DisasContext *ctx) \
1030 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1031 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1032 sign, compute_ov); \
1034 /* divwu divwu. divwuo divwuo. */
1035 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1036 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1037 /* divw divw. divwo divwo. */
1038 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1039 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1041 /* div[wd]eu[o][.] */
1042 #define GEN_DIVE(name, hlpr, compute_ov) \
1043 static void gen_##name(DisasContext *ctx) \
1045 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1046 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1047 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1048 tcg_temp_free_i32(t0); \
1049 if (unlikely(Rc(ctx->opcode) != 0)) { \
1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1054 GEN_DIVE(divweu
, divweu
, 0);
1055 GEN_DIVE(divweuo
, divweu
, 1);
1056 GEN_DIVE(divwe
, divwe
, 0);
1057 GEN_DIVE(divweo
, divwe
, 1);
1059 #if defined(TARGET_PPC64)
1060 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1061 TCGv arg2
, int sign
, int compute_ov
)
1063 TCGv_i64 t0
= tcg_temp_new_i64();
1064 TCGv_i64 t1
= tcg_temp_new_i64();
1065 TCGv_i64 t2
= tcg_temp_new_i64();
1066 TCGv_i64 t3
= tcg_temp_new_i64();
1068 tcg_gen_mov_i64(t0
, arg1
);
1069 tcg_gen_mov_i64(t1
, arg2
);
1071 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1072 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1073 tcg_gen_and_i64(t2
, t2
, t3
);
1074 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1075 tcg_gen_or_i64(t2
, t2
, t3
);
1076 tcg_gen_movi_i64(t3
, 0);
1077 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1078 tcg_gen_div_i64(ret
, t0
, t1
);
1080 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t1
, 0);
1081 tcg_gen_movi_i64(t3
, 0);
1082 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1083 tcg_gen_divu_i64(ret
, t0
, t1
);
1086 tcg_gen_mov_tl(cpu_ov
, t2
);
1087 if (is_isa300(ctx
)) {
1088 tcg_gen_mov_tl(cpu_ov32
, t2
);
1090 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1092 tcg_temp_free_i64(t0
);
1093 tcg_temp_free_i64(t1
);
1094 tcg_temp_free_i64(t2
);
1095 tcg_temp_free_i64(t3
);
1097 if (unlikely(Rc(ctx
->opcode
) != 0))
1098 gen_set_Rc0(ctx
, ret
);
1101 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1102 static void glue(gen_, name)(DisasContext *ctx) \
1104 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1105 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1106 sign, compute_ov); \
1108 /* divdu divdu. divduo divduo. */
1109 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1110 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1111 /* divd divd. divdo divdo. */
1112 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1113 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1115 GEN_DIVE(divdeu
, divdeu
, 0);
1116 GEN_DIVE(divdeuo
, divdeu
, 1);
1117 GEN_DIVE(divde
, divde
, 0);
1118 GEN_DIVE(divdeo
, divde
, 1);
1121 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1122 TCGv arg2
, int sign
)
1124 TCGv_i32 t0
= tcg_temp_new_i32();
1125 TCGv_i32 t1
= tcg_temp_new_i32();
1127 tcg_gen_trunc_tl_i32(t0
, arg1
);
1128 tcg_gen_trunc_tl_i32(t1
, arg2
);
1130 TCGv_i32 t2
= tcg_temp_new_i32();
1131 TCGv_i32 t3
= tcg_temp_new_i32();
1132 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1133 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1134 tcg_gen_and_i32(t2
, t2
, t3
);
1135 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1136 tcg_gen_or_i32(t2
, t2
, t3
);
1137 tcg_gen_movi_i32(t3
, 0);
1138 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1139 tcg_gen_rem_i32(t3
, t0
, t1
);
1140 tcg_gen_ext_i32_tl(ret
, t3
);
1141 tcg_temp_free_i32(t2
);
1142 tcg_temp_free_i32(t3
);
1144 TCGv_i32 t2
= tcg_const_i32(1);
1145 TCGv_i32 t3
= tcg_const_i32(0);
1146 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1147 tcg_gen_remu_i32(t3
, t0
, t1
);
1148 tcg_gen_extu_i32_tl(ret
, t3
);
1149 tcg_temp_free_i32(t2
);
1150 tcg_temp_free_i32(t3
);
1152 tcg_temp_free_i32(t0
);
1153 tcg_temp_free_i32(t1
);
1156 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1157 static void glue(gen_, name)(DisasContext *ctx) \
1159 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1164 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1165 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1167 #if defined(TARGET_PPC64)
1168 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1169 TCGv arg2
, int sign
)
1171 TCGv_i64 t0
= tcg_temp_new_i64();
1172 TCGv_i64 t1
= tcg_temp_new_i64();
1174 tcg_gen_mov_i64(t0
, arg1
);
1175 tcg_gen_mov_i64(t1
, arg2
);
1177 TCGv_i64 t2
= tcg_temp_new_i64();
1178 TCGv_i64 t3
= tcg_temp_new_i64();
1179 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1180 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1181 tcg_gen_and_i64(t2
, t2
, t3
);
1182 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1183 tcg_gen_or_i64(t2
, t2
, t3
);
1184 tcg_gen_movi_i64(t3
, 0);
1185 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1186 tcg_gen_rem_i64(ret
, t0
, t1
);
1187 tcg_temp_free_i64(t2
);
1188 tcg_temp_free_i64(t3
);
1190 TCGv_i64 t2
= tcg_const_i64(1);
1191 TCGv_i64 t3
= tcg_const_i64(0);
1192 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1193 tcg_gen_remu_i64(ret
, t0
, t1
);
1194 tcg_temp_free_i64(t2
);
1195 tcg_temp_free_i64(t3
);
1197 tcg_temp_free_i64(t0
);
1198 tcg_temp_free_i64(t1
);
1201 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1202 static void glue(gen_, name)(DisasContext *ctx) \
1204 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1209 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1210 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1214 static void gen_mulhw(DisasContext
*ctx
)
1216 TCGv_i32 t0
= tcg_temp_new_i32();
1217 TCGv_i32 t1
= tcg_temp_new_i32();
1219 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1220 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1221 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1222 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1223 tcg_temp_free_i32(t0
);
1224 tcg_temp_free_i32(t1
);
1225 if (unlikely(Rc(ctx
->opcode
) != 0))
1226 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1229 /* mulhwu mulhwu. */
1230 static void gen_mulhwu(DisasContext
*ctx
)
1232 TCGv_i32 t0
= tcg_temp_new_i32();
1233 TCGv_i32 t1
= tcg_temp_new_i32();
1235 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1236 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1237 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1238 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1239 tcg_temp_free_i32(t0
);
1240 tcg_temp_free_i32(t1
);
1241 if (unlikely(Rc(ctx
->opcode
) != 0))
1242 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1246 static void gen_mullw(DisasContext
*ctx
)
1248 #if defined(TARGET_PPC64)
1250 t0
= tcg_temp_new_i64();
1251 t1
= tcg_temp_new_i64();
1252 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1253 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1254 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1258 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1259 cpu_gpr
[rB(ctx
->opcode
)]);
1261 if (unlikely(Rc(ctx
->opcode
) != 0))
1262 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1265 /* mullwo mullwo. */
1266 static void gen_mullwo(DisasContext
*ctx
)
1268 TCGv_i32 t0
= tcg_temp_new_i32();
1269 TCGv_i32 t1
= tcg_temp_new_i32();
1271 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1272 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1273 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1274 #if defined(TARGET_PPC64)
1275 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1277 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1280 tcg_gen_sari_i32(t0
, t0
, 31);
1281 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1282 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1283 if (is_isa300(ctx
)) {
1284 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1286 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1288 tcg_temp_free_i32(t0
);
1289 tcg_temp_free_i32(t1
);
1290 if (unlikely(Rc(ctx
->opcode
) != 0))
1291 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1295 static void gen_mulli(DisasContext
*ctx
)
1297 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1301 #if defined(TARGET_PPC64)
1303 static void gen_mulhd(DisasContext
*ctx
)
1305 TCGv lo
= tcg_temp_new();
1306 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1307 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1309 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1310 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1314 /* mulhdu mulhdu. */
1315 static void gen_mulhdu(DisasContext
*ctx
)
1317 TCGv lo
= tcg_temp_new();
1318 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1319 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1321 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1322 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1327 static void gen_mulld(DisasContext
*ctx
)
1329 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1330 cpu_gpr
[rB(ctx
->opcode
)]);
1331 if (unlikely(Rc(ctx
->opcode
) != 0))
1332 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1335 /* mulldo mulldo. */
1336 static void gen_mulldo(DisasContext
*ctx
)
1338 TCGv_i64 t0
= tcg_temp_new_i64();
1339 TCGv_i64 t1
= tcg_temp_new_i64();
1341 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1342 cpu_gpr
[rB(ctx
->opcode
)]);
1343 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1345 tcg_gen_sari_i64(t0
, t0
, 63);
1346 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1347 if (is_isa300(ctx
)) {
1348 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1350 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1352 tcg_temp_free_i64(t0
);
1353 tcg_temp_free_i64(t1
);
1355 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1356 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1361 /* Common subf function */
1362 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1363 TCGv arg2
, bool add_ca
, bool compute_ca
,
1364 bool compute_ov
, bool compute_rc0
)
1368 if (compute_ca
|| compute_ov
) {
1369 t0
= tcg_temp_new();
1373 /* dest = ~arg1 + arg2 [+ ca]. */
1374 if (NARROW_MODE(ctx
)) {
1375 /* Caution: a non-obvious corner case of the spec is that we
1376 must produce the *entire* 64-bit addition, but produce the
1377 carry into bit 32. */
1378 TCGv inv1
= tcg_temp_new();
1379 TCGv t1
= tcg_temp_new();
1380 tcg_gen_not_tl(inv1
, arg1
);
1382 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1384 tcg_gen_addi_tl(t0
, arg2
, 1);
1386 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1387 tcg_gen_add_tl(t0
, t0
, inv1
);
1388 tcg_temp_free(inv1
);
1389 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1391 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
1392 if (is_isa300(ctx
)) {
1393 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
1395 } else if (add_ca
) {
1396 TCGv zero
, inv1
= tcg_temp_new();
1397 tcg_gen_not_tl(inv1
, arg1
);
1398 zero
= tcg_const_tl(0);
1399 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1400 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1401 gen_op_arith_compute_ca32(ctx
, t0
, inv1
, arg2
, 0);
1402 tcg_temp_free(zero
);
1403 tcg_temp_free(inv1
);
1405 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1406 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1407 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, 1);
1409 } else if (add_ca
) {
1410 /* Since we're ignoring carry-out, we can simplify the
1411 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1412 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1413 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1414 tcg_gen_subi_tl(t0
, t0
, 1);
1416 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1420 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1422 if (unlikely(compute_rc0
)) {
1423 gen_set_Rc0(ctx
, t0
);
1427 tcg_gen_mov_tl(ret
, t0
);
1431 /* Sub functions with Two operands functions */
1432 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1433 static void glue(gen_, name)(DisasContext *ctx) \
1435 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1436 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1437 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1439 /* Sub functions with one operand and one immediate */
1440 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1441 add_ca, compute_ca, compute_ov) \
1442 static void glue(gen_, name)(DisasContext *ctx) \
1444 TCGv t0 = tcg_const_tl(const_val); \
1445 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1446 cpu_gpr[rA(ctx->opcode)], t0, \
1447 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1448 tcg_temp_free(t0); \
1450 /* subf subf. subfo subfo. */
1451 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1452 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1453 /* subfc subfc. subfco subfco. */
1454 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1455 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1456 /* subfe subfe. subfeo subfo. */
1457 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1458 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1459 /* subfme subfme. subfmeo subfmeo. */
1460 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1461 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1462 /* subfze subfze. subfzeo subfzeo.*/
1463 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1464 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1467 static void gen_subfic(DisasContext
*ctx
)
1469 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1470 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1475 /* neg neg. nego nego. */
1476 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1478 TCGv zero
= tcg_const_tl(0);
1479 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1480 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1481 tcg_temp_free(zero
);
1484 static void gen_neg(DisasContext
*ctx
)
1486 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1487 if (unlikely(Rc(ctx
->opcode
))) {
1488 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1492 static void gen_nego(DisasContext
*ctx
)
1494 gen_op_arith_neg(ctx
, 1);
1497 /*** Integer logical ***/
1498 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1499 static void glue(gen_, name)(DisasContext *ctx) \
1501 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1502 cpu_gpr[rB(ctx->opcode)]); \
1503 if (unlikely(Rc(ctx->opcode) != 0)) \
1504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1507 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1508 static void glue(gen_, name)(DisasContext *ctx) \
1510 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1511 if (unlikely(Rc(ctx->opcode) != 0)) \
1512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1516 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1518 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1521 static void gen_andi_(DisasContext
*ctx
)
1523 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1524 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1528 static void gen_andis_(DisasContext
*ctx
)
1530 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1531 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1535 static void gen_cntlzw(DisasContext
*ctx
)
1537 TCGv_i32 t
= tcg_temp_new_i32();
1539 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1540 tcg_gen_clzi_i32(t
, t
, 32);
1541 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1542 tcg_temp_free_i32(t
);
1544 if (unlikely(Rc(ctx
->opcode
) != 0))
1545 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1549 static void gen_cnttzw(DisasContext
*ctx
)
1551 TCGv_i32 t
= tcg_temp_new_i32();
1553 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1554 tcg_gen_ctzi_i32(t
, t
, 32);
1555 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1556 tcg_temp_free_i32(t
);
1558 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1559 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1564 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1565 /* extsb & extsb. */
1566 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1567 /* extsh & extsh. */
1568 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1570 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1572 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1574 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1575 static void gen_pause(DisasContext
*ctx
)
1577 TCGv_i32 t0
= tcg_const_i32(0);
1578 tcg_gen_st_i32(t0
, cpu_env
,
1579 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1580 tcg_temp_free_i32(t0
);
1582 /* Stop translation, this gives other CPUs a chance to run */
1583 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
1585 #endif /* defined(TARGET_PPC64) */
1588 static void gen_or(DisasContext
*ctx
)
1592 rs
= rS(ctx
->opcode
);
1593 ra
= rA(ctx
->opcode
);
1594 rb
= rB(ctx
->opcode
);
1595 /* Optimisation for mr. ri case */
1596 if (rs
!= ra
|| rs
!= rb
) {
1598 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1600 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1601 if (unlikely(Rc(ctx
->opcode
) != 0))
1602 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1603 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1604 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1605 #if defined(TARGET_PPC64)
1606 } else if (rs
!= 0) { /* 0 is nop */
1611 /* Set process priority to low */
1615 /* Set process priority to medium-low */
1619 /* Set process priority to normal */
1622 #if !defined(CONFIG_USER_ONLY)
1625 /* Set process priority to very low */
1631 /* Set process priority to medium-hight */
1637 /* Set process priority to high */
1642 if (ctx
->hv
&& !ctx
->pr
) {
1643 /* Set process priority to very high */
1652 TCGv t0
= tcg_temp_new();
1653 gen_load_spr(t0
, SPR_PPR
);
1654 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1655 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1656 gen_store_spr(SPR_PPR
, t0
);
1659 #if !defined(CONFIG_USER_ONLY)
1660 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1661 * CPU and the kernel hangs. This applies to all encodings other
1662 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1663 * and all currently undefined.
1671 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1674 static void gen_xor(DisasContext
*ctx
)
1676 /* Optimisation for "set to zero" case */
1677 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1678 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1680 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1681 if (unlikely(Rc(ctx
->opcode
) != 0))
1682 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1686 static void gen_ori(DisasContext
*ctx
)
1688 target_ulong uimm
= UIMM(ctx
->opcode
);
1690 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1693 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1697 static void gen_oris(DisasContext
*ctx
)
1699 target_ulong uimm
= UIMM(ctx
->opcode
);
1701 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1705 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1709 static void gen_xori(DisasContext
*ctx
)
1711 target_ulong uimm
= UIMM(ctx
->opcode
);
1713 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1717 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1721 static void gen_xoris(DisasContext
*ctx
)
1723 target_ulong uimm
= UIMM(ctx
->opcode
);
1725 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1729 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1732 /* popcntb : PowerPC 2.03 specification */
1733 static void gen_popcntb(DisasContext
*ctx
)
1735 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1738 static void gen_popcntw(DisasContext
*ctx
)
1740 #if defined(TARGET_PPC64)
1741 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1743 tcg_gen_ctpop_i32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1747 #if defined(TARGET_PPC64)
1748 /* popcntd: PowerPC 2.06 specification */
1749 static void gen_popcntd(DisasContext
*ctx
)
1751 tcg_gen_ctpop_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1755 /* prtyw: PowerPC 2.05 specification */
1756 static void gen_prtyw(DisasContext
*ctx
)
1758 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1759 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1760 TCGv t0
= tcg_temp_new();
1761 tcg_gen_shri_tl(t0
, rs
, 16);
1762 tcg_gen_xor_tl(ra
, rs
, t0
);
1763 tcg_gen_shri_tl(t0
, ra
, 8);
1764 tcg_gen_xor_tl(ra
, ra
, t0
);
1765 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1769 #if defined(TARGET_PPC64)
1770 /* prtyd: PowerPC 2.05 specification */
1771 static void gen_prtyd(DisasContext
*ctx
)
1773 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1774 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1775 TCGv t0
= tcg_temp_new();
1776 tcg_gen_shri_tl(t0
, rs
, 32);
1777 tcg_gen_xor_tl(ra
, rs
, t0
);
1778 tcg_gen_shri_tl(t0
, ra
, 16);
1779 tcg_gen_xor_tl(ra
, ra
, t0
);
1780 tcg_gen_shri_tl(t0
, ra
, 8);
1781 tcg_gen_xor_tl(ra
, ra
, t0
);
1782 tcg_gen_andi_tl(ra
, ra
, 1);
1787 #if defined(TARGET_PPC64)
1789 static void gen_bpermd(DisasContext
*ctx
)
1791 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1792 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1796 #if defined(TARGET_PPC64)
1797 /* extsw & extsw. */
1798 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1801 static void gen_cntlzd(DisasContext
*ctx
)
1803 tcg_gen_clzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1804 if (unlikely(Rc(ctx
->opcode
) != 0))
1805 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1809 static void gen_cnttzd(DisasContext
*ctx
)
1811 tcg_gen_ctzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1812 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1813 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1818 static void gen_darn(DisasContext
*ctx
)
1820 int l
= L(ctx
->opcode
);
1823 gen_helper_darn32(cpu_gpr
[rD(ctx
->opcode
)]);
1824 } else if (l
<= 2) {
1825 /* Return 64-bit random for both CRN and RRN */
1826 gen_helper_darn64(cpu_gpr
[rD(ctx
->opcode
)]);
1828 tcg_gen_movi_i64(cpu_gpr
[rD(ctx
->opcode
)], -1);
1833 /*** Integer rotate ***/
1835 /* rlwimi & rlwimi. */
1836 static void gen_rlwimi(DisasContext
*ctx
)
1838 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1839 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1840 uint32_t sh
= SH(ctx
->opcode
);
1841 uint32_t mb
= MB(ctx
->opcode
);
1842 uint32_t me
= ME(ctx
->opcode
);
1844 if (sh
== (31-me
) && mb
<= me
) {
1845 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1850 #if defined(TARGET_PPC64)
1854 mask
= MASK(mb
, me
);
1856 t1
= tcg_temp_new();
1857 if (mask
<= 0xffffffffu
) {
1858 TCGv_i32 t0
= tcg_temp_new_i32();
1859 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1860 tcg_gen_rotli_i32(t0
, t0
, sh
);
1861 tcg_gen_extu_i32_tl(t1
, t0
);
1862 tcg_temp_free_i32(t0
);
1864 #if defined(TARGET_PPC64)
1865 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1866 tcg_gen_rotli_i64(t1
, t1
, sh
);
1868 g_assert_not_reached();
1872 tcg_gen_andi_tl(t1
, t1
, mask
);
1873 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1874 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1877 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1878 gen_set_Rc0(ctx
, t_ra
);
1882 /* rlwinm & rlwinm. */
1883 static void gen_rlwinm(DisasContext
*ctx
)
1885 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1886 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1887 int sh
= SH(ctx
->opcode
);
1888 int mb
= MB(ctx
->opcode
);
1889 int me
= ME(ctx
->opcode
);
1890 int len
= me
- mb
+ 1;
1891 int rsh
= (32 - sh
) & 31;
1893 if (sh
!= 0 && len
> 0 && me
== (31 - sh
)) {
1894 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
1895 } else if (me
== 31 && rsh
+ len
<= 32) {
1896 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
1899 #if defined(TARGET_PPC64)
1903 mask
= MASK(mb
, me
);
1905 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
1906 } else if (mask
<= 0xffffffffu
) {
1907 TCGv_i32 t0
= tcg_temp_new_i32();
1908 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1909 tcg_gen_rotli_i32(t0
, t0
, sh
);
1910 tcg_gen_andi_i32(t0
, t0
, mask
);
1911 tcg_gen_extu_i32_tl(t_ra
, t0
);
1912 tcg_temp_free_i32(t0
);
1914 #if defined(TARGET_PPC64)
1915 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1916 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1917 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1919 g_assert_not_reached();
1923 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1924 gen_set_Rc0(ctx
, t_ra
);
1928 /* rlwnm & rlwnm. */
1929 static void gen_rlwnm(DisasContext
*ctx
)
1931 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1932 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1933 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1934 uint32_t mb
= MB(ctx
->opcode
);
1935 uint32_t me
= ME(ctx
->opcode
);
1938 #if defined(TARGET_PPC64)
1942 mask
= MASK(mb
, me
);
1944 if (mask
<= 0xffffffffu
) {
1945 TCGv_i32 t0
= tcg_temp_new_i32();
1946 TCGv_i32 t1
= tcg_temp_new_i32();
1947 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1948 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1949 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1950 tcg_gen_rotl_i32(t1
, t1
, t0
);
1951 tcg_gen_extu_i32_tl(t_ra
, t1
);
1952 tcg_temp_free_i32(t0
);
1953 tcg_temp_free_i32(t1
);
1955 #if defined(TARGET_PPC64)
1956 TCGv_i64 t0
= tcg_temp_new_i64();
1957 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
1958 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1959 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
1960 tcg_temp_free_i64(t0
);
1962 g_assert_not_reached();
1966 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
1968 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1969 gen_set_Rc0(ctx
, t_ra
);
1973 #if defined(TARGET_PPC64)
1974 #define GEN_PPC64_R2(name, opc1, opc2) \
1975 static void glue(gen_, name##0)(DisasContext *ctx) \
1977 gen_##name(ctx, 0); \
1980 static void glue(gen_, name##1)(DisasContext *ctx) \
1982 gen_##name(ctx, 1); \
1984 #define GEN_PPC64_R4(name, opc1, opc2) \
1985 static void glue(gen_, name##0)(DisasContext *ctx) \
1987 gen_##name(ctx, 0, 0); \
1990 static void glue(gen_, name##1)(DisasContext *ctx) \
1992 gen_##name(ctx, 0, 1); \
1995 static void glue(gen_, name##2)(DisasContext *ctx) \
1997 gen_##name(ctx, 1, 0); \
2000 static void glue(gen_, name##3)(DisasContext *ctx) \
2002 gen_##name(ctx, 1, 1); \
2005 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2007 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2008 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2009 int len
= me
- mb
+ 1;
2010 int rsh
= (64 - sh
) & 63;
2012 if (sh
!= 0 && len
> 0 && me
== (63 - sh
)) {
2013 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2014 } else if (me
== 63 && rsh
+ len
<= 64) {
2015 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2017 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2018 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2020 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2021 gen_set_Rc0(ctx
, t_ra
);
2025 /* rldicl - rldicl. */
2026 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2030 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2031 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2032 gen_rldinm(ctx
, mb
, 63, sh
);
2034 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2036 /* rldicr - rldicr. */
2037 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2041 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2042 me
= MB(ctx
->opcode
) | (men
<< 5);
2043 gen_rldinm(ctx
, 0, me
, sh
);
2045 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2047 /* rldic - rldic. */
2048 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2052 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2053 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2054 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2056 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2058 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2060 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2061 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2062 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2065 t0
= tcg_temp_new();
2066 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2067 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2070 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2071 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2072 gen_set_Rc0(ctx
, t_ra
);
2076 /* rldcl - rldcl. */
2077 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2081 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2082 gen_rldnm(ctx
, mb
, 63);
2084 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2086 /* rldcr - rldcr. */
2087 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2091 me
= MB(ctx
->opcode
) | (men
<< 5);
2092 gen_rldnm(ctx
, 0, me
);
2094 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2096 /* rldimi - rldimi. */
2097 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2099 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2100 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2101 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2102 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2103 uint32_t me
= 63 - sh
;
2106 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2108 target_ulong mask
= MASK(mb
, me
);
2109 TCGv t1
= tcg_temp_new();
2111 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2112 tcg_gen_andi_tl(t1
, t1
, mask
);
2113 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2114 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2117 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2118 gen_set_Rc0(ctx
, t_ra
);
2121 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2124 /*** Integer shift ***/
2127 static void gen_slw(DisasContext
*ctx
)
2131 t0
= tcg_temp_new();
2132 /* AND rS with a mask that is 0 when rB >= 0x20 */
2133 #if defined(TARGET_PPC64)
2134 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2135 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2137 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2138 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2140 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2141 t1
= tcg_temp_new();
2142 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2143 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2146 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2147 if (unlikely(Rc(ctx
->opcode
) != 0))
2148 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2152 static void gen_sraw(DisasContext
*ctx
)
2154 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2155 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2156 if (unlikely(Rc(ctx
->opcode
) != 0))
2157 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2160 /* srawi & srawi. */
2161 static void gen_srawi(DisasContext
*ctx
)
2163 int sh
= SH(ctx
->opcode
);
2164 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2165 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2167 tcg_gen_ext32s_tl(dst
, src
);
2168 tcg_gen_movi_tl(cpu_ca
, 0);
2169 if (is_isa300(ctx
)) {
2170 tcg_gen_movi_tl(cpu_ca32
, 0);
2174 tcg_gen_ext32s_tl(dst
, src
);
2175 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2176 t0
= tcg_temp_new();
2177 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2178 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2180 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2181 if (is_isa300(ctx
)) {
2182 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2184 tcg_gen_sari_tl(dst
, dst
, sh
);
2186 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2187 gen_set_Rc0(ctx
, dst
);
2192 static void gen_srw(DisasContext
*ctx
)
2196 t0
= tcg_temp_new();
2197 /* AND rS with a mask that is 0 when rB >= 0x20 */
2198 #if defined(TARGET_PPC64)
2199 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2200 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2202 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2203 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2205 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2206 tcg_gen_ext32u_tl(t0
, t0
);
2207 t1
= tcg_temp_new();
2208 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2209 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2212 if (unlikely(Rc(ctx
->opcode
) != 0))
2213 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2216 #if defined(TARGET_PPC64)
2218 static void gen_sld(DisasContext
*ctx
)
2222 t0
= tcg_temp_new();
2223 /* AND rS with a mask that is 0 when rB >= 0x40 */
2224 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2225 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2226 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2227 t1
= tcg_temp_new();
2228 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2229 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2232 if (unlikely(Rc(ctx
->opcode
) != 0))
2233 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2237 static void gen_srad(DisasContext
*ctx
)
2239 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2240 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2241 if (unlikely(Rc(ctx
->opcode
) != 0))
2242 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2244 /* sradi & sradi. */
2245 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2247 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2248 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2249 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2251 tcg_gen_mov_tl(dst
, src
);
2252 tcg_gen_movi_tl(cpu_ca
, 0);
2253 if (is_isa300(ctx
)) {
2254 tcg_gen_movi_tl(cpu_ca32
, 0);
2258 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2259 t0
= tcg_temp_new();
2260 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2261 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2263 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2264 if (is_isa300(ctx
)) {
2265 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2267 tcg_gen_sari_tl(dst
, src
, sh
);
2269 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2270 gen_set_Rc0(ctx
, dst
);
2274 static void gen_sradi0(DisasContext
*ctx
)
2279 static void gen_sradi1(DisasContext
*ctx
)
2284 /* extswsli & extswsli. */
2285 static inline void gen_extswsli(DisasContext
*ctx
, int n
)
2287 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2288 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2289 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2291 tcg_gen_ext32s_tl(dst
, src
);
2292 tcg_gen_shli_tl(dst
, dst
, sh
);
2293 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2294 gen_set_Rc0(ctx
, dst
);
2298 static void gen_extswsli0(DisasContext
*ctx
)
2300 gen_extswsli(ctx
, 0);
2303 static void gen_extswsli1(DisasContext
*ctx
)
2305 gen_extswsli(ctx
, 1);
2309 static void gen_srd(DisasContext
*ctx
)
2313 t0
= tcg_temp_new();
2314 /* AND rS with a mask that is 0 when rB >= 0x40 */
2315 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2316 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2317 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2318 t1
= tcg_temp_new();
2319 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2320 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2323 if (unlikely(Rc(ctx
->opcode
) != 0))
2324 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2328 /*** Addressing modes ***/
2329 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2330 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2333 target_long simm
= SIMM(ctx
->opcode
);
2336 if (rA(ctx
->opcode
) == 0) {
2337 if (NARROW_MODE(ctx
)) {
2338 simm
= (uint32_t)simm
;
2340 tcg_gen_movi_tl(EA
, simm
);
2341 } else if (likely(simm
!= 0)) {
2342 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2343 if (NARROW_MODE(ctx
)) {
2344 tcg_gen_ext32u_tl(EA
, EA
);
2347 if (NARROW_MODE(ctx
)) {
2348 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2350 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2355 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2357 if (rA(ctx
->opcode
) == 0) {
2358 if (NARROW_MODE(ctx
)) {
2359 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2361 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2364 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2365 if (NARROW_MODE(ctx
)) {
2366 tcg_gen_ext32u_tl(EA
, EA
);
2371 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2373 if (rA(ctx
->opcode
) == 0) {
2374 tcg_gen_movi_tl(EA
, 0);
2375 } else if (NARROW_MODE(ctx
)) {
2376 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2378 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2382 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2385 tcg_gen_addi_tl(ret
, arg1
, val
);
2386 if (NARROW_MODE(ctx
)) {
2387 tcg_gen_ext32u_tl(ret
, ret
);
2391 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2393 TCGLabel
*l1
= gen_new_label();
2394 TCGv t0
= tcg_temp_new();
2396 tcg_gen_andi_tl(t0
, EA
, mask
);
2397 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2398 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2399 t2
= tcg_const_i32(ctx
->opcode
& 0x03FF0000);
2400 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
2401 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2402 tcg_temp_free_i32(t1
);
2403 tcg_temp_free_i32(t2
);
2408 static inline void gen_align_no_le(DisasContext
*ctx
)
2410 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
,
2411 (ctx
->opcode
& 0x03FF0000) | POWERPC_EXCP_ALIGN_LE
);
2414 /*** Integer load ***/
2415 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2416 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2418 #define GEN_QEMU_LOAD_TL(ldop, op) \
2419 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2423 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2426 GEN_QEMU_LOAD_TL(ld8u
, DEF_MEMOP(MO_UB
))
2427 GEN_QEMU_LOAD_TL(ld16u
, DEF_MEMOP(MO_UW
))
2428 GEN_QEMU_LOAD_TL(ld16s
, DEF_MEMOP(MO_SW
))
2429 GEN_QEMU_LOAD_TL(ld32u
, DEF_MEMOP(MO_UL
))
2430 GEN_QEMU_LOAD_TL(ld32s
, DEF_MEMOP(MO_SL
))
2432 GEN_QEMU_LOAD_TL(ld16ur
, BSWAP_MEMOP(MO_UW
))
2433 GEN_QEMU_LOAD_TL(ld32ur
, BSWAP_MEMOP(MO_UL
))
2435 #define GEN_QEMU_LOAD_64(ldop, op) \
2436 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2440 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2443 GEN_QEMU_LOAD_64(ld8u
, DEF_MEMOP(MO_UB
))
2444 GEN_QEMU_LOAD_64(ld16u
, DEF_MEMOP(MO_UW
))
2445 GEN_QEMU_LOAD_64(ld32u
, DEF_MEMOP(MO_UL
))
2446 GEN_QEMU_LOAD_64(ld32s
, DEF_MEMOP(MO_SL
))
2447 GEN_QEMU_LOAD_64(ld64
, DEF_MEMOP(MO_Q
))
2449 #if defined(TARGET_PPC64)
2450 GEN_QEMU_LOAD_64(ld64ur
, BSWAP_MEMOP(MO_Q
))
2453 #define GEN_QEMU_STORE_TL(stop, op) \
2454 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2458 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2461 GEN_QEMU_STORE_TL(st8
, DEF_MEMOP(MO_UB
))
2462 GEN_QEMU_STORE_TL(st16
, DEF_MEMOP(MO_UW
))
2463 GEN_QEMU_STORE_TL(st32
, DEF_MEMOP(MO_UL
))
2465 GEN_QEMU_STORE_TL(st16r
, BSWAP_MEMOP(MO_UW
))
2466 GEN_QEMU_STORE_TL(st32r
, BSWAP_MEMOP(MO_UL
))
2468 #define GEN_QEMU_STORE_64(stop, op) \
2469 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2473 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2476 GEN_QEMU_STORE_64(st8
, DEF_MEMOP(MO_UB
))
2477 GEN_QEMU_STORE_64(st16
, DEF_MEMOP(MO_UW
))
2478 GEN_QEMU_STORE_64(st32
, DEF_MEMOP(MO_UL
))
2479 GEN_QEMU_STORE_64(st64
, DEF_MEMOP(MO_Q
))
2481 #if defined(TARGET_PPC64)
2482 GEN_QEMU_STORE_64(st64r
, BSWAP_MEMOP(MO_Q
))
2485 #define GEN_LD(name, ldop, opc, type) \
2486 static void glue(gen_, name)(DisasContext *ctx) \
2489 gen_set_access_type(ctx, ACCESS_INT); \
2490 EA = tcg_temp_new(); \
2491 gen_addr_imm_index(ctx, EA, 0); \
2492 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2493 tcg_temp_free(EA); \
2496 #define GEN_LDU(name, ldop, opc, type) \
2497 static void glue(gen_, name##u)(DisasContext *ctx) \
2500 if (unlikely(rA(ctx->opcode) == 0 || \
2501 rA(ctx->opcode) == rD(ctx->opcode))) { \
2502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2505 gen_set_access_type(ctx, ACCESS_INT); \
2506 EA = tcg_temp_new(); \
2507 if (type == PPC_64B) \
2508 gen_addr_imm_index(ctx, EA, 0x03); \
2510 gen_addr_imm_index(ctx, EA, 0); \
2511 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2513 tcg_temp_free(EA); \
2516 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2517 static void glue(gen_, name##ux)(DisasContext *ctx) \
2520 if (unlikely(rA(ctx->opcode) == 0 || \
2521 rA(ctx->opcode) == rD(ctx->opcode))) { \
2522 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2525 gen_set_access_type(ctx, ACCESS_INT); \
2526 EA = tcg_temp_new(); \
2527 gen_addr_reg_index(ctx, EA); \
2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2530 tcg_temp_free(EA); \
2533 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2534 static void glue(gen_, name##x)(DisasContext *ctx) \
2538 gen_set_access_type(ctx, ACCESS_INT); \
2539 EA = tcg_temp_new(); \
2540 gen_addr_reg_index(ctx, EA); \
2541 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2542 tcg_temp_free(EA); \
2545 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2546 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2548 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2549 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2551 #define GEN_LDS(name, ldop, op, type) \
2552 GEN_LD(name, ldop, op | 0x20, type); \
2553 GEN_LDU(name, ldop, op | 0x21, type); \
2554 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2555 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2557 /* lbz lbzu lbzux lbzx */
2558 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2559 /* lha lhau lhaux lhax */
2560 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2561 /* lhz lhzu lhzux lhzx */
2562 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2563 /* lwz lwzu lwzux lwzx */
2564 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2565 #if defined(TARGET_PPC64)
2567 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2569 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2571 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
);
2573 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
);
2575 /* CI load/store variants */
2576 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
2577 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2578 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2579 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2581 static void gen_ld(DisasContext
*ctx
)
2584 if (Rc(ctx
->opcode
)) {
2585 if (unlikely(rA(ctx
->opcode
) == 0 ||
2586 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2587 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2591 gen_set_access_type(ctx
, ACCESS_INT
);
2592 EA
= tcg_temp_new();
2593 gen_addr_imm_index(ctx
, EA
, 0x03);
2594 if (ctx
->opcode
& 0x02) {
2595 /* lwa (lwau is undefined) */
2596 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2599 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2601 if (Rc(ctx
->opcode
))
2602 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2607 static void gen_lq(DisasContext
*ctx
)
2612 /* lq is a legal user mode instruction starting in ISA 2.07 */
2613 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2614 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2616 if (!legal_in_user_mode
&& ctx
->pr
) {
2617 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2621 if (!le_is_supported
&& ctx
->le_mode
) {
2622 gen_align_no_le(ctx
);
2625 ra
= rA(ctx
->opcode
);
2626 rd
= rD(ctx
->opcode
);
2627 if (unlikely((rd
& 1) || rd
== ra
)) {
2628 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2632 gen_set_access_type(ctx
, ACCESS_INT
);
2633 EA
= tcg_temp_new();
2634 gen_addr_imm_index(ctx
, EA
, 0x0F);
2636 /* Note that the low part is always in RD+1, even in LE mode. */
2637 lo
= cpu_gpr
[rd
+ 1];
2640 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2641 #ifdef CONFIG_ATOMIC128
2642 TCGv_i32 oi
= tcg_temp_new_i32();
2644 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2645 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
2647 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2648 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
2650 tcg_temp_free_i32(oi
);
2651 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
2653 /* Restart with exclusive lock. */
2654 gen_helper_exit_atomic(cpu_env
);
2655 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2657 } else if (ctx
->le_mode
) {
2658 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2659 gen_addr_add(ctx
, EA
, EA
, 8);
2660 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2662 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2663 gen_addr_add(ctx
, EA
, EA
, 8);
2664 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2670 /*** Integer store ***/
2671 #define GEN_ST(name, stop, opc, type) \
2672 static void glue(gen_, name)(DisasContext *ctx) \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 gen_addr_imm_index(ctx, EA, 0); \
2678 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2679 tcg_temp_free(EA); \
2682 #define GEN_STU(name, stop, opc, type) \
2683 static void glue(gen_, stop##u)(DisasContext *ctx) \
2686 if (unlikely(rA(ctx->opcode) == 0)) { \
2687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 if (type == PPC_64B) \
2693 gen_addr_imm_index(ctx, EA, 0x03); \
2695 gen_addr_imm_index(ctx, EA, 0); \
2696 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2698 tcg_temp_free(EA); \
2701 #define GEN_STUX(name, stop, opc2, opc3, type) \
2702 static void glue(gen_, name##ux)(DisasContext *ctx) \
2705 if (unlikely(rA(ctx->opcode) == 0)) { \
2706 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2709 gen_set_access_type(ctx, ACCESS_INT); \
2710 EA = tcg_temp_new(); \
2711 gen_addr_reg_index(ctx, EA); \
2712 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2713 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2714 tcg_temp_free(EA); \
2717 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2718 static void glue(gen_, name##x)(DisasContext *ctx) \
2722 gen_set_access_type(ctx, ACCESS_INT); \
2723 EA = tcg_temp_new(); \
2724 gen_addr_reg_index(ctx, EA); \
2725 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2726 tcg_temp_free(EA); \
2728 #define GEN_STX(name, stop, opc2, opc3, type) \
2729 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2731 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2732 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2734 #define GEN_STS(name, stop, op, type) \
2735 GEN_ST(name, stop, op | 0x20, type); \
2736 GEN_STU(name, stop, op | 0x21, type); \
2737 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2738 GEN_STX(name, stop, 0x17, op | 0x00, type)
2740 /* stb stbu stbux stbx */
2741 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2742 /* sth sthu sthux sthx */
2743 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2744 /* stw stwu stwux stwx */
2745 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2746 #if defined(TARGET_PPC64)
2747 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
);
2748 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
);
2749 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
2750 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2751 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2752 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2754 static void gen_std(DisasContext
*ctx
)
2759 rs
= rS(ctx
->opcode
);
2760 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2761 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2762 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2765 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2766 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2769 if (!legal_in_user_mode
&& ctx
->pr
) {
2770 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2774 if (!le_is_supported
&& ctx
->le_mode
) {
2775 gen_align_no_le(ctx
);
2779 if (unlikely(rs
& 1)) {
2780 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2783 gen_set_access_type(ctx
, ACCESS_INT
);
2784 EA
= tcg_temp_new();
2785 gen_addr_imm_index(ctx
, EA
, 0x03);
2787 /* Note that the low part is always in RS+1, even in LE mode. */
2788 lo
= cpu_gpr
[rs
+ 1];
2791 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2792 #ifdef CONFIG_ATOMIC128
2793 TCGv_i32 oi
= tcg_temp_new_i32();
2795 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2796 gen_helper_stq_le_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2798 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2799 gen_helper_stq_be_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2801 tcg_temp_free_i32(oi
);
2803 /* Restart with exclusive lock. */
2804 gen_helper_exit_atomic(cpu_env
);
2805 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2807 } else if (ctx
->le_mode
) {
2808 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2809 gen_addr_add(ctx
, EA
, EA
, 8);
2810 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2812 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2813 gen_addr_add(ctx
, EA
, EA
, 8);
2814 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2819 if (Rc(ctx
->opcode
)) {
2820 if (unlikely(rA(ctx
->opcode
) == 0)) {
2821 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2825 gen_set_access_type(ctx
, ACCESS_INT
);
2826 EA
= tcg_temp_new();
2827 gen_addr_imm_index(ctx
, EA
, 0x03);
2828 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2829 if (Rc(ctx
->opcode
))
2830 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2835 /*** Integer load and store with byte reverse ***/
2838 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2841 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2843 #if defined(TARGET_PPC64)
2845 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2847 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2848 #endif /* TARGET_PPC64 */
2851 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2853 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2855 /*** Integer load and store multiple ***/
2858 static void gen_lmw(DisasContext
*ctx
)
2864 gen_align_no_le(ctx
);
2867 gen_set_access_type(ctx
, ACCESS_INT
);
2868 t0
= tcg_temp_new();
2869 t1
= tcg_const_i32(rD(ctx
->opcode
));
2870 gen_addr_imm_index(ctx
, t0
, 0);
2871 gen_helper_lmw(cpu_env
, t0
, t1
);
2873 tcg_temp_free_i32(t1
);
2877 static void gen_stmw(DisasContext
*ctx
)
2883 gen_align_no_le(ctx
);
2886 gen_set_access_type(ctx
, ACCESS_INT
);
2887 t0
= tcg_temp_new();
2888 t1
= tcg_const_i32(rS(ctx
->opcode
));
2889 gen_addr_imm_index(ctx
, t0
, 0);
2890 gen_helper_stmw(cpu_env
, t0
, t1
);
2892 tcg_temp_free_i32(t1
);
2895 /*** Integer load and store strings ***/
2898 /* PowerPC32 specification says we must generate an exception if
2899 * rA is in the range of registers to be loaded.
2900 * In an other hand, IBM says this is valid, but rA won't be loaded.
2901 * For now, I'll follow the spec...
2903 static void gen_lswi(DisasContext
*ctx
)
2907 int nb
= NB(ctx
->opcode
);
2908 int start
= rD(ctx
->opcode
);
2909 int ra
= rA(ctx
->opcode
);
2913 gen_align_no_le(ctx
);
2918 nr
= DIV_ROUND_UP(nb
, 4);
2919 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
2920 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2923 gen_set_access_type(ctx
, ACCESS_INT
);
2924 t0
= tcg_temp_new();
2925 gen_addr_register(ctx
, t0
);
2926 t1
= tcg_const_i32(nb
);
2927 t2
= tcg_const_i32(start
);
2928 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2930 tcg_temp_free_i32(t1
);
2931 tcg_temp_free_i32(t2
);
2935 static void gen_lswx(DisasContext
*ctx
)
2938 TCGv_i32 t1
, t2
, t3
;
2941 gen_align_no_le(ctx
);
2944 gen_set_access_type(ctx
, ACCESS_INT
);
2945 t0
= tcg_temp_new();
2946 gen_addr_reg_index(ctx
, t0
);
2947 t1
= tcg_const_i32(rD(ctx
->opcode
));
2948 t2
= tcg_const_i32(rA(ctx
->opcode
));
2949 t3
= tcg_const_i32(rB(ctx
->opcode
));
2950 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
2952 tcg_temp_free_i32(t1
);
2953 tcg_temp_free_i32(t2
);
2954 tcg_temp_free_i32(t3
);
2958 static void gen_stswi(DisasContext
*ctx
)
2962 int nb
= NB(ctx
->opcode
);
2965 gen_align_no_le(ctx
);
2968 gen_set_access_type(ctx
, ACCESS_INT
);
2969 t0
= tcg_temp_new();
2970 gen_addr_register(ctx
, t0
);
2973 t1
= tcg_const_i32(nb
);
2974 t2
= tcg_const_i32(rS(ctx
->opcode
));
2975 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2977 tcg_temp_free_i32(t1
);
2978 tcg_temp_free_i32(t2
);
2982 static void gen_stswx(DisasContext
*ctx
)
2988 gen_align_no_le(ctx
);
2991 gen_set_access_type(ctx
, ACCESS_INT
);
2992 t0
= tcg_temp_new();
2993 gen_addr_reg_index(ctx
, t0
);
2994 t1
= tcg_temp_new_i32();
2995 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
2996 tcg_gen_andi_i32(t1
, t1
, 0x7F);
2997 t2
= tcg_const_i32(rS(ctx
->opcode
));
2998 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3000 tcg_temp_free_i32(t1
);
3001 tcg_temp_free_i32(t2
);
3004 /*** Memory synchronisation ***/
3006 static void gen_eieio(DisasContext
*ctx
)
3008 TCGBar bar
= TCG_MO_LD_ST
;
3011 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3012 * tell the CPU it is a store-forwarding barrier.
3014 if (ctx
->opcode
& 0x2000000) {
3016 * ISA says that "Reserved fields in instructions are ignored
3017 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3018 * as this is not an instruction software should be using,
3019 * complain to the user.
3021 if (!(ctx
->insns_flags2
& PPC2_ISA300
)) {
3022 qemu_log_mask(LOG_GUEST_ERROR
, "invalid eieio using bit 6 at @"
3023 TARGET_FMT_lx
"\n", ctx
->base
.pc_next
- 4);
3029 tcg_gen_mb(bar
| TCG_BAR_SC
);
3032 #if !defined(CONFIG_USER_ONLY)
3033 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
)
3038 if (!ctx
->lazy_tlb_flush
) {
3041 l
= gen_new_label();
3042 t
= tcg_temp_new_i32();
3043 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3044 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3046 gen_helper_check_tlb_flush_global(cpu_env
);
3048 gen_helper_check_tlb_flush_local(cpu_env
);
3051 tcg_temp_free_i32(t
);
3054 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
) { }
3058 static void gen_isync(DisasContext
*ctx
)
3061 * We need to check for a pending TLB flush. This can only happen in
3062 * kernel mode however so check MSR_PR
3065 gen_check_tlb_flush(ctx
, false);
3067 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3068 gen_stop_exception(ctx
);
3071 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3073 static void gen_load_locked(DisasContext
*ctx
, TCGMemOp memop
)
3075 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3076 TCGv t0
= tcg_temp_new();
3078 gen_set_access_type(ctx
, ACCESS_RES
);
3079 gen_addr_reg_index(ctx
, t0
);
3080 tcg_gen_qemu_ld_tl(gpr
, t0
, ctx
->mem_idx
, memop
| MO_ALIGN
);
3081 tcg_gen_mov_tl(cpu_reserve
, t0
);
3082 tcg_gen_mov_tl(cpu_reserve_val
, gpr
);
3083 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3087 #define LARX(name, memop) \
3088 static void gen_##name(DisasContext *ctx) \
3090 gen_load_locked(ctx, memop); \
3094 LARX(lbarx
, DEF_MEMOP(MO_UB
))
3095 LARX(lharx
, DEF_MEMOP(MO_UW
))
3096 LARX(lwarx
, DEF_MEMOP(MO_UL
))
3098 #define LD_ATOMIC(name, memop, tp, op, eop) \
3099 static void gen_##name(DisasContext *ctx) \
3101 int len = MEMOP_GET_SIZE(memop); \
3102 uint32_t gpr_FC = FC(ctx->opcode); \
3103 TCGv EA = tcg_temp_local_new(); \
3106 gen_addr_register(ctx, EA); \
3108 gen_check_align(ctx, EA, len - 1); \
3110 t0 = tcg_temp_new_##tp(); \
3111 t1 = tcg_temp_new_##tp(); \
3112 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3115 case 0: /* Fetch and add */ \
3116 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3118 case 1: /* Fetch and xor */ \
3119 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3121 case 2: /* Fetch and or */ \
3122 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3124 case 3: /* Fetch and 'and' */ \
3125 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3127 case 8: /* Swap */ \
3128 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3130 case 4: /* Fetch and max unsigned */ \
3131 case 5: /* Fetch and max signed */ \
3132 case 6: /* Fetch and min unsigned */ \
3133 case 7: /* Fetch and min signed */ \
3134 case 16: /* compare and swap not equal */ \
3135 case 24: /* Fetch and increment bounded */ \
3136 case 25: /* Fetch and increment equal */ \
3137 case 28: /* Fetch and decrement bounded */ \
3141 /* invoke data storage error handler */ \
3142 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3144 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3145 tcg_temp_free_##tp(t0); \
3146 tcg_temp_free_##tp(t1); \
3147 tcg_temp_free(EA); \
3150 LD_ATOMIC(lwat
, DEF_MEMOP(MO_UL
), i32
, trunc_tl_i32
, extu_i32_tl
)
3151 #if defined(TARGET_PPC64)
3152 LD_ATOMIC(ldat
, DEF_MEMOP(MO_Q
), i64
, mov_i64
, mov_i64
)
3155 #define ST_ATOMIC(name, memop, tp, op) \
3156 static void gen_##name(DisasContext *ctx) \
3158 int len = MEMOP_GET_SIZE(memop); \
3159 uint32_t gpr_FC = FC(ctx->opcode); \
3160 TCGv EA = tcg_temp_local_new(); \
3163 gen_addr_register(ctx, EA); \
3165 gen_check_align(ctx, EA, len - 1); \
3167 t0 = tcg_temp_new_##tp(); \
3168 t1 = tcg_temp_new_##tp(); \
3169 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3172 case 0: /* add and Store */ \
3173 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3175 case 1: /* xor and Store */ \
3176 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3178 case 2: /* Or and Store */ \
3179 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3181 case 3: /* 'and' and Store */ \
3182 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3184 case 4: /* Store max unsigned */ \
3185 case 5: /* Store max signed */ \
3186 case 6: /* Store min unsigned */ \
3187 case 7: /* Store min signed */ \
3188 case 24: /* Store twin */ \
3192 /* invoke data storage error handler */ \
3193 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3195 tcg_temp_free_##tp(t0); \
3196 tcg_temp_free_##tp(t1); \
3197 tcg_temp_free(EA); \
3200 ST_ATOMIC(stwat
, DEF_MEMOP(MO_UL
), i32
, trunc_tl_i32
)
3201 #if defined(TARGET_PPC64)
3202 ST_ATOMIC(stdat
, DEF_MEMOP(MO_Q
), i64
, mov_i64
)
3205 static void gen_conditional_store(DisasContext
*ctx
, TCGMemOp memop
)
3207 TCGLabel
*l1
= gen_new_label();
3208 TCGLabel
*l2
= gen_new_label();
3209 TCGv t0
= tcg_temp_new();
3210 int reg
= rS(ctx
->opcode
);
3212 gen_set_access_type(ctx
, ACCESS_RES
);
3213 gen_addr_reg_index(ctx
, t0
);
3214 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3217 t0
= tcg_temp_new();
3218 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_reserve
, cpu_reserve_val
,
3219 cpu_gpr
[reg
], ctx
->mem_idx
,
3220 DEF_MEMOP(memop
) | MO_ALIGN
);
3221 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_reserve_val
);
3222 tcg_gen_shli_tl(t0
, t0
, CRF_EQ_BIT
);
3223 tcg_gen_or_tl(t0
, t0
, cpu_so
);
3224 tcg_gen_trunc_tl_i32(cpu_crf
[0], t0
);
3230 /* Address mismatch implies failure. But we still need to provide the
3231 memory barrier semantics of the instruction. */
3232 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3233 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3236 tcg_gen_movi_tl(cpu_reserve
, -1);
3239 #define STCX(name, memop) \
3240 static void gen_##name(DisasContext *ctx) \
3242 gen_conditional_store(ctx, memop); \
3245 STCX(stbcx_
, DEF_MEMOP(MO_UB
))
3246 STCX(sthcx_
, DEF_MEMOP(MO_UW
))
3247 STCX(stwcx_
, DEF_MEMOP(MO_UL
))
3249 #if defined(TARGET_PPC64)
3251 LARX(ldarx
, DEF_MEMOP(MO_Q
))
3253 STCX(stdcx_
, DEF_MEMOP(MO_Q
))
3256 static void gen_lqarx(DisasContext
*ctx
)
3258 int rd
= rD(ctx
->opcode
);
3261 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3262 (rd
== rB(ctx
->opcode
)))) {
3263 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3267 gen_set_access_type(ctx
, ACCESS_RES
);
3268 EA
= tcg_temp_new();
3269 gen_addr_reg_index(ctx
, EA
);
3271 /* Note that the low part is always in RD+1, even in LE mode. */
3272 lo
= cpu_gpr
[rd
+ 1];
3275 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3276 #ifdef CONFIG_ATOMIC128
3277 TCGv_i32 oi
= tcg_temp_new_i32();
3279 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
| MO_ALIGN_16
,
3281 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
3283 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
| MO_ALIGN_16
,
3285 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
3287 tcg_temp_free_i32(oi
);
3288 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
3290 /* Restart with exclusive lock. */
3291 gen_helper_exit_atomic(cpu_env
);
3292 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3296 } else if (ctx
->le_mode
) {
3297 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
| MO_ALIGN_16
);
3298 tcg_gen_mov_tl(cpu_reserve
, EA
);
3299 gen_addr_add(ctx
, EA
, EA
, 8);
3300 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
3302 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
| MO_ALIGN_16
);
3303 tcg_gen_mov_tl(cpu_reserve
, EA
);
3304 gen_addr_add(ctx
, EA
, EA
, 8);
3305 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
3309 tcg_gen_st_tl(hi
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3310 tcg_gen_st_tl(lo
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3314 static void gen_stqcx_(DisasContext
*ctx
)
3316 int rs
= rS(ctx
->opcode
);
3319 if (unlikely(rs
& 1)) {
3320 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3324 gen_set_access_type(ctx
, ACCESS_RES
);
3325 EA
= tcg_temp_new();
3326 gen_addr_reg_index(ctx
, EA
);
3328 /* Note that the low part is always in RS+1, even in LE mode. */
3329 lo
= cpu_gpr
[rs
+ 1];
3332 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3333 TCGv_i32 oi
= tcg_const_i32(DEF_MEMOP(MO_Q
) | MO_ALIGN_16
);
3334 #ifdef CONFIG_ATOMIC128
3336 gen_helper_stqcx_le_parallel(cpu_crf
[0], cpu_env
, EA
, lo
, hi
, oi
);
3338 gen_helper_stqcx_le_parallel(cpu_crf
[0], cpu_env
, EA
, lo
, hi
, oi
);
3341 /* Restart with exclusive lock. */
3342 gen_helper_exit_atomic(cpu_env
);
3343 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3346 tcg_temp_free_i32(oi
);
3348 TCGLabel
*lab_fail
= gen_new_label();
3349 TCGLabel
*lab_over
= gen_new_label();
3350 TCGv_i64 t0
= tcg_temp_new_i64();
3351 TCGv_i64 t1
= tcg_temp_new_i64();
3353 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, lab_fail
);
3356 gen_qemu_ld64_i64(ctx
, t0
, cpu_reserve
);
3357 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3358 ? offsetof(CPUPPCState
, reserve_val2
)
3359 : offsetof(CPUPPCState
, reserve_val
)));
3360 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3362 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3363 gen_qemu_ld64_i64(ctx
, t0
, t0
);
3364 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3365 ? offsetof(CPUPPCState
, reserve_val
)
3366 : offsetof(CPUPPCState
, reserve_val2
)));
3367 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3370 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? lo
: hi
, cpu_reserve
);
3371 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3372 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? hi
: lo
, t0
);
3374 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3375 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
3376 tcg_gen_br(lab_over
);
3378 gen_set_label(lab_fail
);
3379 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3381 gen_set_label(lab_over
);
3382 tcg_gen_movi_tl(cpu_reserve
, -1);
3383 tcg_temp_free_i64(t0
);
3384 tcg_temp_free_i64(t1
);
3387 #endif /* defined(TARGET_PPC64) */
3390 static void gen_sync(DisasContext
*ctx
)
3392 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3395 * We may need to check for a pending TLB flush.
3397 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3399 * Additionally, this can only happen in kernel mode however so
3400 * check MSR_PR as well.
3402 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3403 gen_check_tlb_flush(ctx
, true);
3405 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3409 static void gen_wait(DisasContext
*ctx
)
3411 TCGv_i32 t0
= tcg_const_i32(1);
3412 tcg_gen_st_i32(t0
, cpu_env
,
3413 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3414 tcg_temp_free_i32(t0
);
3415 /* Stop translation, as the CPU is supposed to sleep from now */
3416 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3419 #if defined(TARGET_PPC64)
3420 static void gen_doze(DisasContext
*ctx
)
3422 #if defined(CONFIG_USER_ONLY)
3428 t
= tcg_const_i32(PPC_PM_DOZE
);
3429 gen_helper_pminsn(cpu_env
, t
);
3430 tcg_temp_free_i32(t
);
3431 gen_stop_exception(ctx
);
3432 #endif /* defined(CONFIG_USER_ONLY) */
3435 static void gen_nap(DisasContext
*ctx
)
3437 #if defined(CONFIG_USER_ONLY)
3443 t
= tcg_const_i32(PPC_PM_NAP
);
3444 gen_helper_pminsn(cpu_env
, t
);
3445 tcg_temp_free_i32(t
);
3446 gen_stop_exception(ctx
);
3447 #endif /* defined(CONFIG_USER_ONLY) */
3450 static void gen_stop(DisasContext
*ctx
)
3455 static void gen_sleep(DisasContext
*ctx
)
3457 #if defined(CONFIG_USER_ONLY)
3463 t
= tcg_const_i32(PPC_PM_SLEEP
);
3464 gen_helper_pminsn(cpu_env
, t
);
3465 tcg_temp_free_i32(t
);
3466 gen_stop_exception(ctx
);
3467 #endif /* defined(CONFIG_USER_ONLY) */
3470 static void gen_rvwinkle(DisasContext
*ctx
)
3472 #if defined(CONFIG_USER_ONLY)
3478 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3479 gen_helper_pminsn(cpu_env
, t
);
3480 tcg_temp_free_i32(t
);
3481 gen_stop_exception(ctx
);
3482 #endif /* defined(CONFIG_USER_ONLY) */
3484 #endif /* #if defined(TARGET_PPC64) */
3486 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3488 #if defined(TARGET_PPC64)
3490 tcg_gen_movi_tl(cpu_cfar
, nip
);
3494 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3496 if (unlikely(ctx
->singlestep_enabled
)) {
3500 #ifndef CONFIG_USER_ONLY
3501 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3508 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3510 if (NARROW_MODE(ctx
)) {
3511 dest
= (uint32_t) dest
;
3513 if (use_goto_tb(ctx
, dest
)) {
3515 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3516 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
3518 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3519 if (unlikely(ctx
->singlestep_enabled
)) {
3520 if ((ctx
->singlestep_enabled
&
3521 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3522 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3523 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3524 gen_exception_nip(ctx
, POWERPC_EXCP_TRACE
, dest
);
3526 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3527 gen_debug_exception(ctx
);
3530 tcg_gen_lookup_and_goto_ptr();
3534 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3536 if (NARROW_MODE(ctx
)) {
3537 nip
= (uint32_t)nip
;
3539 tcg_gen_movi_tl(cpu_lr
, nip
);
3543 static void gen_b(DisasContext
*ctx
)
3545 target_ulong li
, target
;
3547 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3548 /* sign extend LI */
3549 li
= LI(ctx
->opcode
);
3550 li
= (li
^ 0x02000000) - 0x02000000;
3551 if (likely(AA(ctx
->opcode
) == 0)) {
3552 target
= ctx
->base
.pc_next
+ li
- 4;
3556 if (LK(ctx
->opcode
)) {
3557 gen_setlr(ctx
, ctx
->base
.pc_next
);
3559 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3560 gen_goto_tb(ctx
, 0, target
);
3568 static void gen_bcond(DisasContext
*ctx
, int type
)
3570 uint32_t bo
= BO(ctx
->opcode
);
3574 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3575 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3576 target
= tcg_temp_local_new();
3577 if (type
== BCOND_CTR
)
3578 tcg_gen_mov_tl(target
, cpu_ctr
);
3579 else if (type
== BCOND_TAR
)
3580 gen_load_spr(target
, SPR_TAR
);
3582 tcg_gen_mov_tl(target
, cpu_lr
);
3586 if (LK(ctx
->opcode
))
3587 gen_setlr(ctx
, ctx
->base
.pc_next
);
3588 l1
= gen_new_label();
3589 if ((bo
& 0x4) == 0) {
3590 /* Decrement and test CTR */
3591 TCGv temp
= tcg_temp_new();
3592 if (unlikely(type
== BCOND_CTR
)) {
3593 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3596 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3597 if (NARROW_MODE(ctx
)) {
3598 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3600 tcg_gen_mov_tl(temp
, cpu_ctr
);
3603 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3605 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3607 tcg_temp_free(temp
);
3609 if ((bo
& 0x10) == 0) {
3611 uint32_t bi
= BI(ctx
->opcode
);
3612 uint32_t mask
= 0x08 >> (bi
& 0x03);
3613 TCGv_i32 temp
= tcg_temp_new_i32();
3616 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3617 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3619 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3620 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3622 tcg_temp_free_i32(temp
);
3624 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3625 if (type
== BCOND_IM
) {
3626 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3627 if (likely(AA(ctx
->opcode
) == 0)) {
3628 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ li
- 4);
3630 gen_goto_tb(ctx
, 0, li
);
3633 if (NARROW_MODE(ctx
)) {
3634 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3636 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3638 tcg_gen_lookup_and_goto_ptr();
3639 tcg_temp_free(target
);
3641 if ((bo
& 0x14) != 0x14) {
3643 gen_goto_tb(ctx
, 1, ctx
->base
.pc_next
);
3647 static void gen_bc(DisasContext
*ctx
)
3649 gen_bcond(ctx
, BCOND_IM
);
3652 static void gen_bcctr(DisasContext
*ctx
)
3654 gen_bcond(ctx
, BCOND_CTR
);
3657 static void gen_bclr(DisasContext
*ctx
)
3659 gen_bcond(ctx
, BCOND_LR
);
3662 static void gen_bctar(DisasContext
*ctx
)
3664 gen_bcond(ctx
, BCOND_TAR
);
3667 /*** Condition register logical ***/
3668 #define GEN_CRLOGIC(name, tcg_op, opc) \
3669 static void glue(gen_, name)(DisasContext *ctx) \
3674 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3675 t0 = tcg_temp_new_i32(); \
3677 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3679 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3681 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3682 t1 = tcg_temp_new_i32(); \
3683 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3685 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3687 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3689 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3690 tcg_op(t0, t0, t1); \
3691 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3692 tcg_gen_andi_i32(t0, t0, bitmask); \
3693 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3694 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3695 tcg_temp_free_i32(t0); \
3696 tcg_temp_free_i32(t1); \
3700 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3702 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3704 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3706 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3708 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3710 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3712 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3714 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3717 static void gen_mcrf(DisasContext
*ctx
)
3719 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3722 /*** System linkage ***/
3724 /* rfi (supervisor only) */
3725 static void gen_rfi(DisasContext
*ctx
)
3727 #if defined(CONFIG_USER_ONLY)
3730 /* This instruction doesn't exist anymore on 64-bit server
3731 * processors compliant with arch 2.x
3733 if (ctx
->insns_flags
& PPC_SEGMENT_64B
) {
3734 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3737 /* Restore CPU state */
3739 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3740 gen_helper_rfi(cpu_env
);
3741 gen_sync_exception(ctx
);
3745 #if defined(TARGET_PPC64)
3746 static void gen_rfid(DisasContext
*ctx
)
3748 #if defined(CONFIG_USER_ONLY)
3751 /* Restore CPU state */
3753 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3754 gen_helper_rfid(cpu_env
);
3755 gen_sync_exception(ctx
);
3759 static void gen_hrfid(DisasContext
*ctx
)
3761 #if defined(CONFIG_USER_ONLY)
3764 /* Restore CPU state */
3766 gen_helper_hrfid(cpu_env
);
3767 gen_sync_exception(ctx
);
3773 #if defined(CONFIG_USER_ONLY)
3774 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3776 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3778 static void gen_sc(DisasContext
*ctx
)
3782 lev
= (ctx
->opcode
>> 5) & 0x7F;
3783 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3788 /* Check for unconditional traps (always or never) */
3789 static bool check_unconditional_trap(DisasContext
*ctx
)
3792 if (TO(ctx
->opcode
) == 0) {
3796 if (TO(ctx
->opcode
) == 31) {
3797 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
3804 static void gen_tw(DisasContext
*ctx
)
3808 if (check_unconditional_trap(ctx
)) {
3811 t0
= tcg_const_i32(TO(ctx
->opcode
));
3812 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3814 tcg_temp_free_i32(t0
);
3818 static void gen_twi(DisasContext
*ctx
)
3823 if (check_unconditional_trap(ctx
)) {
3826 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3827 t1
= tcg_const_i32(TO(ctx
->opcode
));
3828 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3830 tcg_temp_free_i32(t1
);
3833 #if defined(TARGET_PPC64)
3835 static void gen_td(DisasContext
*ctx
)
3839 if (check_unconditional_trap(ctx
)) {
3842 t0
= tcg_const_i32(TO(ctx
->opcode
));
3843 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3845 tcg_temp_free_i32(t0
);
3849 static void gen_tdi(DisasContext
*ctx
)
3854 if (check_unconditional_trap(ctx
)) {
3857 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3858 t1
= tcg_const_i32(TO(ctx
->opcode
));
3859 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3861 tcg_temp_free_i32(t1
);
3865 /*** Processor control ***/
3867 static void gen_read_xer(DisasContext
*ctx
, TCGv dst
)
3869 TCGv t0
= tcg_temp_new();
3870 TCGv t1
= tcg_temp_new();
3871 TCGv t2
= tcg_temp_new();
3872 tcg_gen_mov_tl(dst
, cpu_xer
);
3873 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
3874 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
3875 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
3876 tcg_gen_or_tl(t0
, t0
, t1
);
3877 tcg_gen_or_tl(dst
, dst
, t2
);
3878 tcg_gen_or_tl(dst
, dst
, t0
);
3879 if (is_isa300(ctx
)) {
3880 tcg_gen_shli_tl(t0
, cpu_ov32
, XER_OV32
);
3881 tcg_gen_or_tl(dst
, dst
, t0
);
3882 tcg_gen_shli_tl(t0
, cpu_ca32
, XER_CA32
);
3883 tcg_gen_or_tl(dst
, dst
, t0
);
3890 static void gen_write_xer(TCGv src
)
3892 /* Write all flags, while reading back check for isa300 */
3893 tcg_gen_andi_tl(cpu_xer
, src
,
3895 (1u << XER_OV
) | (1u << XER_OV32
) |
3896 (1u << XER_CA
) | (1u << XER_CA32
)));
3897 tcg_gen_extract_tl(cpu_ov32
, src
, XER_OV32
, 1);
3898 tcg_gen_extract_tl(cpu_ca32
, src
, XER_CA32
, 1);
3899 tcg_gen_extract_tl(cpu_so
, src
, XER_SO
, 1);
3900 tcg_gen_extract_tl(cpu_ov
, src
, XER_OV
, 1);
3901 tcg_gen_extract_tl(cpu_ca
, src
, XER_CA
, 1);
3905 static void gen_mcrxr(DisasContext
*ctx
)
3907 TCGv_i32 t0
= tcg_temp_new_i32();
3908 TCGv_i32 t1
= tcg_temp_new_i32();
3909 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3911 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
3912 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
3913 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
3914 tcg_gen_shli_i32(t0
, t0
, 3);
3915 tcg_gen_shli_i32(t1
, t1
, 2);
3916 tcg_gen_shli_i32(dst
, dst
, 1);
3917 tcg_gen_or_i32(dst
, dst
, t0
);
3918 tcg_gen_or_i32(dst
, dst
, t1
);
3919 tcg_temp_free_i32(t0
);
3920 tcg_temp_free_i32(t1
);
3922 tcg_gen_movi_tl(cpu_so
, 0);
3923 tcg_gen_movi_tl(cpu_ov
, 0);
3924 tcg_gen_movi_tl(cpu_ca
, 0);
3929 static void gen_mcrxrx(DisasContext
*ctx
)
3931 TCGv t0
= tcg_temp_new();
3932 TCGv t1
= tcg_temp_new();
3933 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3935 /* copy OV and OV32 */
3936 tcg_gen_shli_tl(t0
, cpu_ov
, 1);
3937 tcg_gen_or_tl(t0
, t0
, cpu_ov32
);
3938 tcg_gen_shli_tl(t0
, t0
, 2);
3939 /* copy CA and CA32 */
3940 tcg_gen_shli_tl(t1
, cpu_ca
, 1);
3941 tcg_gen_or_tl(t1
, t1
, cpu_ca32
);
3942 tcg_gen_or_tl(t0
, t0
, t1
);
3943 tcg_gen_trunc_tl_i32(dst
, t0
);
3950 static void gen_mfcr(DisasContext
*ctx
)
3954 if (likely(ctx
->opcode
& 0x00100000)) {
3955 crm
= CRM(ctx
->opcode
);
3956 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3958 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3959 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3960 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3963 TCGv_i32 t0
= tcg_temp_new_i32();
3964 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3965 tcg_gen_shli_i32(t0
, t0
, 4);
3966 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3967 tcg_gen_shli_i32(t0
, t0
, 4);
3968 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3969 tcg_gen_shli_i32(t0
, t0
, 4);
3970 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3971 tcg_gen_shli_i32(t0
, t0
, 4);
3972 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3973 tcg_gen_shli_i32(t0
, t0
, 4);
3974 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3975 tcg_gen_shli_i32(t0
, t0
, 4);
3976 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3977 tcg_gen_shli_i32(t0
, t0
, 4);
3978 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3979 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3980 tcg_temp_free_i32(t0
);
3985 static void gen_mfmsr(DisasContext
*ctx
)
3988 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3991 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
3994 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3995 printf("ERROR: try to access SPR %d !\n", sprn
);
3998 #define SPR_NOACCESS (&spr_noaccess)
4001 static inline void gen_op_mfspr(DisasContext
*ctx
)
4003 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4004 uint32_t sprn
= SPR(ctx
->opcode
);
4006 #if defined(CONFIG_USER_ONLY)
4007 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4010 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4011 } else if (ctx
->hv
) {
4012 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4014 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4017 if (likely(read_cb
!= NULL
)) {
4018 if (likely(read_cb
!= SPR_NOACCESS
)) {
4019 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4021 /* Privilege exception */
4022 /* This is a hack to avoid warnings when running Linux:
4023 * this OS breaks the PowerPC virtualisation model,
4024 * allowing userland application to read the PVR
4026 if (sprn
!= SPR_PVR
) {
4027 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to read privileged spr "
4028 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4029 ctx
->base
.pc_next
- 4);
4031 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4034 /* ISA 2.07 defines these as no-ops */
4035 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4036 (sprn
>= 808 && sprn
<= 811)) {
4041 qemu_log_mask(LOG_GUEST_ERROR
,
4042 "Trying to read invalid spr %d (0x%03x) at "
4043 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4045 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4046 * it can generate a priv, a hv emu or a no-op
4050 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4053 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
4054 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4060 static void gen_mfspr(DisasContext
*ctx
)
4066 static void gen_mftb(DisasContext
*ctx
)
4072 static void gen_mtcrf(DisasContext
*ctx
)
4076 crm
= CRM(ctx
->opcode
);
4077 if (likely((ctx
->opcode
& 0x00100000))) {
4078 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4079 TCGv_i32 temp
= tcg_temp_new_i32();
4081 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4082 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4083 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4084 tcg_temp_free_i32(temp
);
4087 TCGv_i32 temp
= tcg_temp_new_i32();
4088 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4089 for (crn
= 0 ; crn
< 8 ; crn
++) {
4090 if (crm
& (1 << crn
)) {
4091 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4092 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4095 tcg_temp_free_i32(temp
);
4100 #if defined(TARGET_PPC64)
4101 static void gen_mtmsrd(DisasContext
*ctx
)
4105 #if !defined(CONFIG_USER_ONLY)
4106 if (ctx
->opcode
& 0x00010000) {
4107 /* Special form that does not need any synchronisation */
4108 TCGv t0
= tcg_temp_new();
4109 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4110 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4111 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4114 /* XXX: we need to update nip before the store
4115 * if we enter power saving mode, we will exit the loop
4116 * directly from ppc_store_msr
4118 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4119 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4120 /* Must stop the translation as machine state (may have) changed */
4121 /* Note that mtmsr is not always defined as context-synchronizing */
4122 gen_stop_exception(ctx
);
4124 #endif /* !defined(CONFIG_USER_ONLY) */
4126 #endif /* defined(TARGET_PPC64) */
4128 static void gen_mtmsr(DisasContext
*ctx
)
4132 #if !defined(CONFIG_USER_ONLY)
4133 if (ctx
->opcode
& 0x00010000) {
4134 /* Special form that does not need any synchronisation */
4135 TCGv t0
= tcg_temp_new();
4136 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4137 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4138 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4141 TCGv msr
= tcg_temp_new();
4143 /* XXX: we need to update nip before the store
4144 * if we enter power saving mode, we will exit the loop
4145 * directly from ppc_store_msr
4147 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4148 #if defined(TARGET_PPC64)
4149 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4151 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4153 gen_helper_store_msr(cpu_env
, msr
);
4155 /* Must stop the translation as machine state (may have) changed */
4156 /* Note that mtmsr is not always defined as context-synchronizing */
4157 gen_stop_exception(ctx
);
4163 static void gen_mtspr(DisasContext
*ctx
)
4165 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4166 uint32_t sprn
= SPR(ctx
->opcode
);
4168 #if defined(CONFIG_USER_ONLY)
4169 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4172 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4173 } else if (ctx
->hv
) {
4174 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4176 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4179 if (likely(write_cb
!= NULL
)) {
4180 if (likely(write_cb
!= SPR_NOACCESS
)) {
4181 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4183 /* Privilege exception */
4184 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to write privileged spr "
4185 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4186 ctx
->base
.pc_next
- 4);
4187 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4190 /* ISA 2.07 defines these as no-ops */
4191 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4192 (sprn
>= 808 && sprn
<= 811)) {
4198 qemu_log_mask(LOG_GUEST_ERROR
,
4199 "Trying to write invalid spr %d (0x%03x) at "
4200 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4203 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4204 * it can generate a priv, a hv emu or a no-op
4208 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4211 if (ctx
->pr
|| sprn
== 0) {
4212 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4218 #if defined(TARGET_PPC64)
4220 static void gen_setb(DisasContext
*ctx
)
4222 TCGv_i32 t0
= tcg_temp_new_i32();
4223 TCGv_i32 t8
= tcg_temp_new_i32();
4224 TCGv_i32 tm1
= tcg_temp_new_i32();
4225 int crf
= crfS(ctx
->opcode
);
4227 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
4228 tcg_gen_movi_i32(t8
, 8);
4229 tcg_gen_movi_i32(tm1
, -1);
4230 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
4231 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4233 tcg_temp_free_i32(t0
);
4234 tcg_temp_free_i32(t8
);
4235 tcg_temp_free_i32(tm1
);
4239 /*** Cache management ***/
4242 static void gen_dcbf(DisasContext
*ctx
)
4244 /* XXX: specification says this is treated as a load by the MMU */
4246 gen_set_access_type(ctx
, ACCESS_CACHE
);
4247 t0
= tcg_temp_new();
4248 gen_addr_reg_index(ctx
, t0
);
4249 gen_qemu_ld8u(ctx
, t0
, t0
);
4253 /* dcbi (Supervisor only) */
4254 static void gen_dcbi(DisasContext
*ctx
)
4256 #if defined(CONFIG_USER_ONLY)
4262 EA
= tcg_temp_new();
4263 gen_set_access_type(ctx
, ACCESS_CACHE
);
4264 gen_addr_reg_index(ctx
, EA
);
4265 val
= tcg_temp_new();
4266 /* XXX: specification says this should be treated as a store by the MMU */
4267 gen_qemu_ld8u(ctx
, val
, EA
);
4268 gen_qemu_st8(ctx
, val
, EA
);
4271 #endif /* defined(CONFIG_USER_ONLY) */
4275 static void gen_dcbst(DisasContext
*ctx
)
4277 /* XXX: specification say this is treated as a load by the MMU */
4279 gen_set_access_type(ctx
, ACCESS_CACHE
);
4280 t0
= tcg_temp_new();
4281 gen_addr_reg_index(ctx
, t0
);
4282 gen_qemu_ld8u(ctx
, t0
, t0
);
4287 static void gen_dcbt(DisasContext
*ctx
)
4289 /* interpreted as no-op */
4290 /* XXX: specification say this is treated as a load by the MMU
4291 * but does not generate any exception
4296 static void gen_dcbtst(DisasContext
*ctx
)
4298 /* interpreted as no-op */
4299 /* XXX: specification say this is treated as a load by the MMU
4300 * but does not generate any exception
4305 static void gen_dcbtls(DisasContext
*ctx
)
4307 /* Always fails locking the cache */
4308 TCGv t0
= tcg_temp_new();
4309 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4310 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4311 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4316 static void gen_dcbz(DisasContext
*ctx
)
4321 gen_set_access_type(ctx
, ACCESS_CACHE
);
4322 tcgv_addr
= tcg_temp_new();
4323 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4324 gen_addr_reg_index(ctx
, tcgv_addr
);
4325 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_op
);
4326 tcg_temp_free(tcgv_addr
);
4327 tcg_temp_free_i32(tcgv_op
);
4331 static void gen_dst(DisasContext
*ctx
)
4333 if (rA(ctx
->opcode
) == 0) {
4334 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4336 /* interpreted as no-op */
4341 static void gen_dstst(DisasContext
*ctx
)
4343 if (rA(ctx
->opcode
) == 0) {
4344 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4346 /* interpreted as no-op */
4352 static void gen_dss(DisasContext
*ctx
)
4354 /* interpreted as no-op */
4358 static void gen_icbi(DisasContext
*ctx
)
4361 gen_set_access_type(ctx
, ACCESS_CACHE
);
4362 t0
= tcg_temp_new();
4363 gen_addr_reg_index(ctx
, t0
);
4364 gen_helper_icbi(cpu_env
, t0
);
4370 static void gen_dcba(DisasContext
*ctx
)
4372 /* interpreted as no-op */
4373 /* XXX: specification say this is treated as a store by the MMU
4374 * but does not generate any exception
4378 /*** Segment register manipulation ***/
4379 /* Supervisor only: */
4382 static void gen_mfsr(DisasContext
*ctx
)
4384 #if defined(CONFIG_USER_ONLY)
4390 t0
= tcg_const_tl(SR(ctx
->opcode
));
4391 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4393 #endif /* defined(CONFIG_USER_ONLY) */
4397 static void gen_mfsrin(DisasContext
*ctx
)
4399 #if defined(CONFIG_USER_ONLY)
4405 t0
= tcg_temp_new();
4406 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4407 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4409 #endif /* defined(CONFIG_USER_ONLY) */
4413 static void gen_mtsr(DisasContext
*ctx
)
4415 #if defined(CONFIG_USER_ONLY)
4421 t0
= tcg_const_tl(SR(ctx
->opcode
));
4422 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4424 #endif /* defined(CONFIG_USER_ONLY) */
4428 static void gen_mtsrin(DisasContext
*ctx
)
4430 #if defined(CONFIG_USER_ONLY)
4436 t0
= tcg_temp_new();
4437 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4438 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4440 #endif /* defined(CONFIG_USER_ONLY) */
4443 #if defined(TARGET_PPC64)
4444 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4447 static void gen_mfsr_64b(DisasContext
*ctx
)
4449 #if defined(CONFIG_USER_ONLY)
4455 t0
= tcg_const_tl(SR(ctx
->opcode
));
4456 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4458 #endif /* defined(CONFIG_USER_ONLY) */
4462 static void gen_mfsrin_64b(DisasContext
*ctx
)
4464 #if defined(CONFIG_USER_ONLY)
4470 t0
= tcg_temp_new();
4471 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4472 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4474 #endif /* defined(CONFIG_USER_ONLY) */
4478 static void gen_mtsr_64b(DisasContext
*ctx
)
4480 #if defined(CONFIG_USER_ONLY)
4486 t0
= tcg_const_tl(SR(ctx
->opcode
));
4487 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4489 #endif /* defined(CONFIG_USER_ONLY) */
4493 static void gen_mtsrin_64b(DisasContext
*ctx
)
4495 #if defined(CONFIG_USER_ONLY)
4501 t0
= tcg_temp_new();
4502 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4503 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4505 #endif /* defined(CONFIG_USER_ONLY) */
4509 static void gen_slbmte(DisasContext
*ctx
)
4511 #if defined(CONFIG_USER_ONLY)
4516 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4517 cpu_gpr
[rS(ctx
->opcode
)]);
4518 #endif /* defined(CONFIG_USER_ONLY) */
4521 static void gen_slbmfee(DisasContext
*ctx
)
4523 #if defined(CONFIG_USER_ONLY)
4528 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4529 cpu_gpr
[rB(ctx
->opcode
)]);
4530 #endif /* defined(CONFIG_USER_ONLY) */
4533 static void gen_slbmfev(DisasContext
*ctx
)
4535 #if defined(CONFIG_USER_ONLY)
4540 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4541 cpu_gpr
[rB(ctx
->opcode
)]);
4542 #endif /* defined(CONFIG_USER_ONLY) */
4545 static void gen_slbfee_(DisasContext
*ctx
)
4547 #if defined(CONFIG_USER_ONLY)
4548 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4552 if (unlikely(ctx
->pr
)) {
4553 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4556 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4557 cpu_gpr
[rB(ctx
->opcode
)]);
4558 l1
= gen_new_label();
4559 l2
= gen_new_label();
4560 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4561 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4562 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
4565 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4569 #endif /* defined(TARGET_PPC64) */
4571 /*** Lookaside buffer management ***/
4572 /* Optional & supervisor only: */
4575 static void gen_tlbia(DisasContext
*ctx
)
4577 #if defined(CONFIG_USER_ONLY)
4582 gen_helper_tlbia(cpu_env
);
4583 #endif /* defined(CONFIG_USER_ONLY) */
4587 static void gen_tlbiel(DisasContext
*ctx
)
4589 #if defined(CONFIG_USER_ONLY)
4594 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4595 #endif /* defined(CONFIG_USER_ONLY) */
4599 static void gen_tlbie(DisasContext
*ctx
)
4601 #if defined(CONFIG_USER_ONLY)
4607 CHK_SV
; /* If gtse is set then tlbie is supervisor privileged */
4609 CHK_HV
; /* Else hypervisor privileged */
4612 if (NARROW_MODE(ctx
)) {
4613 TCGv t0
= tcg_temp_new();
4614 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4615 gen_helper_tlbie(cpu_env
, t0
);
4618 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4620 t1
= tcg_temp_new_i32();
4621 tcg_gen_ld_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4622 tcg_gen_ori_i32(t1
, t1
, TLB_NEED_GLOBAL_FLUSH
);
4623 tcg_gen_st_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4624 tcg_temp_free_i32(t1
);
4625 #endif /* defined(CONFIG_USER_ONLY) */
4629 static void gen_tlbsync(DisasContext
*ctx
)
4631 #if defined(CONFIG_USER_ONLY)
4636 CHK_SV
; /* If gtse is set then tlbsync is supervisor privileged */
4638 CHK_HV
; /* Else hypervisor privileged */
4641 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4642 if (ctx
->insns_flags
& PPC_BOOKE
) {
4643 gen_check_tlb_flush(ctx
, true);
4645 #endif /* defined(CONFIG_USER_ONLY) */
4648 #if defined(TARGET_PPC64)
4650 static void gen_slbia(DisasContext
*ctx
)
4652 #if defined(CONFIG_USER_ONLY)
4657 gen_helper_slbia(cpu_env
);
4658 #endif /* defined(CONFIG_USER_ONLY) */
4662 static void gen_slbie(DisasContext
*ctx
)
4664 #if defined(CONFIG_USER_ONLY)
4669 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4670 #endif /* defined(CONFIG_USER_ONLY) */
4674 static void gen_slbieg(DisasContext
*ctx
)
4676 #if defined(CONFIG_USER_ONLY)
4681 gen_helper_slbieg(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4682 #endif /* defined(CONFIG_USER_ONLY) */
4686 static void gen_slbsync(DisasContext
*ctx
)
4688 #if defined(CONFIG_USER_ONLY)
4692 gen_check_tlb_flush(ctx
, true);
4693 #endif /* defined(CONFIG_USER_ONLY) */
4696 #endif /* defined(TARGET_PPC64) */
4698 /*** External control ***/
4702 static void gen_eciwx(DisasContext
*ctx
)
4705 /* Should check EAR[E] ! */
4706 gen_set_access_type(ctx
, ACCESS_EXT
);
4707 t0
= tcg_temp_new();
4708 gen_addr_reg_index(ctx
, t0
);
4709 gen_check_align(ctx
, t0
, 0x03);
4710 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4715 static void gen_ecowx(DisasContext
*ctx
)
4718 /* Should check EAR[E] ! */
4719 gen_set_access_type(ctx
, ACCESS_EXT
);
4720 t0
= tcg_temp_new();
4721 gen_addr_reg_index(ctx
, t0
);
4722 gen_check_align(ctx
, t0
, 0x03);
4723 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4727 /* PowerPC 601 specific instructions */
4730 static void gen_abs(DisasContext
*ctx
)
4732 TCGLabel
*l1
= gen_new_label();
4733 TCGLabel
*l2
= gen_new_label();
4734 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4735 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4738 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4740 if (unlikely(Rc(ctx
->opcode
) != 0))
4741 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4745 static void gen_abso(DisasContext
*ctx
)
4747 TCGLabel
*l1
= gen_new_label();
4748 TCGLabel
*l2
= gen_new_label();
4749 TCGLabel
*l3
= gen_new_label();
4750 /* Start with XER OV disabled, the most likely case */
4751 tcg_gen_movi_tl(cpu_ov
, 0);
4752 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4753 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4754 tcg_gen_movi_tl(cpu_ov
, 1);
4755 tcg_gen_movi_tl(cpu_so
, 1);
4758 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4761 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4763 if (unlikely(Rc(ctx
->opcode
) != 0))
4764 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4768 static void gen_clcs(DisasContext
*ctx
)
4770 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4771 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4772 tcg_temp_free_i32(t0
);
4773 /* Rc=1 sets CR0 to an undefined state */
4777 static void gen_div(DisasContext
*ctx
)
4779 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4780 cpu_gpr
[rB(ctx
->opcode
)]);
4781 if (unlikely(Rc(ctx
->opcode
) != 0))
4782 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4786 static void gen_divo(DisasContext
*ctx
)
4788 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4789 cpu_gpr
[rB(ctx
->opcode
)]);
4790 if (unlikely(Rc(ctx
->opcode
) != 0))
4791 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4795 static void gen_divs(DisasContext
*ctx
)
4797 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4798 cpu_gpr
[rB(ctx
->opcode
)]);
4799 if (unlikely(Rc(ctx
->opcode
) != 0))
4800 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4803 /* divso - divso. */
4804 static void gen_divso(DisasContext
*ctx
)
4806 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4807 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4808 if (unlikely(Rc(ctx
->opcode
) != 0))
4809 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4813 static void gen_doz(DisasContext
*ctx
)
4815 TCGLabel
*l1
= gen_new_label();
4816 TCGLabel
*l2
= gen_new_label();
4817 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4818 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4821 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4823 if (unlikely(Rc(ctx
->opcode
) != 0))
4824 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4828 static void gen_dozo(DisasContext
*ctx
)
4830 TCGLabel
*l1
= gen_new_label();
4831 TCGLabel
*l2
= gen_new_label();
4832 TCGv t0
= tcg_temp_new();
4833 TCGv t1
= tcg_temp_new();
4834 TCGv t2
= tcg_temp_new();
4835 /* Start with XER OV disabled, the most likely case */
4836 tcg_gen_movi_tl(cpu_ov
, 0);
4837 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4838 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4839 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4840 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4841 tcg_gen_andc_tl(t1
, t1
, t2
);
4842 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4843 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4844 tcg_gen_movi_tl(cpu_ov
, 1);
4845 tcg_gen_movi_tl(cpu_so
, 1);
4848 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4853 if (unlikely(Rc(ctx
->opcode
) != 0))
4854 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4858 static void gen_dozi(DisasContext
*ctx
)
4860 target_long simm
= SIMM(ctx
->opcode
);
4861 TCGLabel
*l1
= gen_new_label();
4862 TCGLabel
*l2
= gen_new_label();
4863 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4864 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4867 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4869 if (unlikely(Rc(ctx
->opcode
) != 0))
4870 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4873 /* lscbx - lscbx. */
4874 static void gen_lscbx(DisasContext
*ctx
)
4876 TCGv t0
= tcg_temp_new();
4877 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4878 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4879 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4881 gen_addr_reg_index(ctx
, t0
);
4882 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4883 tcg_temp_free_i32(t1
);
4884 tcg_temp_free_i32(t2
);
4885 tcg_temp_free_i32(t3
);
4886 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4887 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4888 if (unlikely(Rc(ctx
->opcode
) != 0))
4889 gen_set_Rc0(ctx
, t0
);
4893 /* maskg - maskg. */
4894 static void gen_maskg(DisasContext
*ctx
)
4896 TCGLabel
*l1
= gen_new_label();
4897 TCGv t0
= tcg_temp_new();
4898 TCGv t1
= tcg_temp_new();
4899 TCGv t2
= tcg_temp_new();
4900 TCGv t3
= tcg_temp_new();
4901 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4902 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4903 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4904 tcg_gen_addi_tl(t2
, t0
, 1);
4905 tcg_gen_shr_tl(t2
, t3
, t2
);
4906 tcg_gen_shr_tl(t3
, t3
, t1
);
4907 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4908 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4909 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4915 if (unlikely(Rc(ctx
->opcode
) != 0))
4916 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4919 /* maskir - maskir. */
4920 static void gen_maskir(DisasContext
*ctx
)
4922 TCGv t0
= tcg_temp_new();
4923 TCGv t1
= tcg_temp_new();
4924 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4925 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4926 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4929 if (unlikely(Rc(ctx
->opcode
) != 0))
4930 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4934 static void gen_mul(DisasContext
*ctx
)
4936 TCGv_i64 t0
= tcg_temp_new_i64();
4937 TCGv_i64 t1
= tcg_temp_new_i64();
4938 TCGv t2
= tcg_temp_new();
4939 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4940 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4941 tcg_gen_mul_i64(t0
, t0
, t1
);
4942 tcg_gen_trunc_i64_tl(t2
, t0
);
4943 gen_store_spr(SPR_MQ
, t2
);
4944 tcg_gen_shri_i64(t1
, t0
, 32);
4945 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4946 tcg_temp_free_i64(t0
);
4947 tcg_temp_free_i64(t1
);
4949 if (unlikely(Rc(ctx
->opcode
) != 0))
4950 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4954 static void gen_mulo(DisasContext
*ctx
)
4956 TCGLabel
*l1
= gen_new_label();
4957 TCGv_i64 t0
= tcg_temp_new_i64();
4958 TCGv_i64 t1
= tcg_temp_new_i64();
4959 TCGv t2
= tcg_temp_new();
4960 /* Start with XER OV disabled, the most likely case */
4961 tcg_gen_movi_tl(cpu_ov
, 0);
4962 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4963 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4964 tcg_gen_mul_i64(t0
, t0
, t1
);
4965 tcg_gen_trunc_i64_tl(t2
, t0
);
4966 gen_store_spr(SPR_MQ
, t2
);
4967 tcg_gen_shri_i64(t1
, t0
, 32);
4968 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4969 tcg_gen_ext32s_i64(t1
, t0
);
4970 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4971 tcg_gen_movi_tl(cpu_ov
, 1);
4972 tcg_gen_movi_tl(cpu_so
, 1);
4974 tcg_temp_free_i64(t0
);
4975 tcg_temp_free_i64(t1
);
4977 if (unlikely(Rc(ctx
->opcode
) != 0))
4978 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4982 static void gen_nabs(DisasContext
*ctx
)
4984 TCGLabel
*l1
= gen_new_label();
4985 TCGLabel
*l2
= gen_new_label();
4986 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4987 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4990 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4992 if (unlikely(Rc(ctx
->opcode
) != 0))
4993 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4996 /* nabso - nabso. */
4997 static void gen_nabso(DisasContext
*ctx
)
4999 TCGLabel
*l1
= gen_new_label();
5000 TCGLabel
*l2
= gen_new_label();
5001 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5002 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5005 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5007 /* nabs never overflows */
5008 tcg_gen_movi_tl(cpu_ov
, 0);
5009 if (unlikely(Rc(ctx
->opcode
) != 0))
5010 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5014 static void gen_rlmi(DisasContext
*ctx
)
5016 uint32_t mb
= MB(ctx
->opcode
);
5017 uint32_t me
= ME(ctx
->opcode
);
5018 TCGv t0
= tcg_temp_new();
5019 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5020 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5021 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5022 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
5023 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5025 if (unlikely(Rc(ctx
->opcode
) != 0))
5026 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5030 static void gen_rrib(DisasContext
*ctx
)
5032 TCGv t0
= tcg_temp_new();
5033 TCGv t1
= tcg_temp_new();
5034 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5035 tcg_gen_movi_tl(t1
, 0x80000000);
5036 tcg_gen_shr_tl(t1
, t1
, t0
);
5037 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5038 tcg_gen_and_tl(t0
, t0
, t1
);
5039 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5040 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5043 if (unlikely(Rc(ctx
->opcode
) != 0))
5044 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5048 static void gen_sle(DisasContext
*ctx
)
5050 TCGv t0
= tcg_temp_new();
5051 TCGv t1
= tcg_temp_new();
5052 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5053 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5054 tcg_gen_subfi_tl(t1
, 32, t1
);
5055 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5056 tcg_gen_or_tl(t1
, t0
, t1
);
5057 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5058 gen_store_spr(SPR_MQ
, t1
);
5061 if (unlikely(Rc(ctx
->opcode
) != 0))
5062 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5066 static void gen_sleq(DisasContext
*ctx
)
5068 TCGv t0
= tcg_temp_new();
5069 TCGv t1
= tcg_temp_new();
5070 TCGv t2
= tcg_temp_new();
5071 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5072 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5073 tcg_gen_shl_tl(t2
, t2
, t0
);
5074 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5075 gen_load_spr(t1
, SPR_MQ
);
5076 gen_store_spr(SPR_MQ
, t0
);
5077 tcg_gen_and_tl(t0
, t0
, t2
);
5078 tcg_gen_andc_tl(t1
, t1
, t2
);
5079 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5083 if (unlikely(Rc(ctx
->opcode
) != 0))
5084 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5088 static void gen_sliq(DisasContext
*ctx
)
5090 int sh
= SH(ctx
->opcode
);
5091 TCGv t0
= tcg_temp_new();
5092 TCGv t1
= tcg_temp_new();
5093 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5094 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5095 tcg_gen_or_tl(t1
, t0
, t1
);
5096 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5097 gen_store_spr(SPR_MQ
, t1
);
5100 if (unlikely(Rc(ctx
->opcode
) != 0))
5101 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5104 /* slliq - slliq. */
5105 static void gen_slliq(DisasContext
*ctx
)
5107 int sh
= SH(ctx
->opcode
);
5108 TCGv t0
= tcg_temp_new();
5109 TCGv t1
= tcg_temp_new();
5110 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5111 gen_load_spr(t1
, SPR_MQ
);
5112 gen_store_spr(SPR_MQ
, t0
);
5113 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5114 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5115 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5118 if (unlikely(Rc(ctx
->opcode
) != 0))
5119 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5123 static void gen_sllq(DisasContext
*ctx
)
5125 TCGLabel
*l1
= gen_new_label();
5126 TCGLabel
*l2
= gen_new_label();
5127 TCGv t0
= tcg_temp_local_new();
5128 TCGv t1
= tcg_temp_local_new();
5129 TCGv t2
= tcg_temp_local_new();
5130 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5131 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5132 tcg_gen_shl_tl(t1
, t1
, t2
);
5133 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5134 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5135 gen_load_spr(t0
, SPR_MQ
);
5136 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5139 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5140 gen_load_spr(t2
, SPR_MQ
);
5141 tcg_gen_andc_tl(t1
, t2
, t1
);
5142 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5147 if (unlikely(Rc(ctx
->opcode
) != 0))
5148 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5152 static void gen_slq(DisasContext
*ctx
)
5154 TCGLabel
*l1
= gen_new_label();
5155 TCGv t0
= tcg_temp_new();
5156 TCGv t1
= tcg_temp_new();
5157 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5158 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5159 tcg_gen_subfi_tl(t1
, 32, t1
);
5160 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5161 tcg_gen_or_tl(t1
, t0
, t1
);
5162 gen_store_spr(SPR_MQ
, t1
);
5163 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5164 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5165 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5166 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5170 if (unlikely(Rc(ctx
->opcode
) != 0))
5171 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5174 /* sraiq - sraiq. */
5175 static void gen_sraiq(DisasContext
*ctx
)
5177 int sh
= SH(ctx
->opcode
);
5178 TCGLabel
*l1
= gen_new_label();
5179 TCGv t0
= tcg_temp_new();
5180 TCGv t1
= tcg_temp_new();
5181 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5182 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5183 tcg_gen_or_tl(t0
, t0
, t1
);
5184 gen_store_spr(SPR_MQ
, t0
);
5185 tcg_gen_movi_tl(cpu_ca
, 0);
5186 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5187 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5188 tcg_gen_movi_tl(cpu_ca
, 1);
5190 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5193 if (unlikely(Rc(ctx
->opcode
) != 0))
5194 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5198 static void gen_sraq(DisasContext
*ctx
)
5200 TCGLabel
*l1
= gen_new_label();
5201 TCGLabel
*l2
= gen_new_label();
5202 TCGv t0
= tcg_temp_new();
5203 TCGv t1
= tcg_temp_local_new();
5204 TCGv t2
= tcg_temp_local_new();
5205 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5206 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5207 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5208 tcg_gen_subfi_tl(t2
, 32, t2
);
5209 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5210 tcg_gen_or_tl(t0
, t0
, t2
);
5211 gen_store_spr(SPR_MQ
, t0
);
5212 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5213 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5214 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5215 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5218 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5219 tcg_gen_movi_tl(cpu_ca
, 0);
5220 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5221 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5222 tcg_gen_movi_tl(cpu_ca
, 1);
5226 if (unlikely(Rc(ctx
->opcode
) != 0))
5227 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5231 static void gen_sre(DisasContext
*ctx
)
5233 TCGv t0
= tcg_temp_new();
5234 TCGv t1
= tcg_temp_new();
5235 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5236 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5237 tcg_gen_subfi_tl(t1
, 32, t1
);
5238 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5239 tcg_gen_or_tl(t1
, t0
, t1
);
5240 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5241 gen_store_spr(SPR_MQ
, t1
);
5244 if (unlikely(Rc(ctx
->opcode
) != 0))
5245 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5249 static void gen_srea(DisasContext
*ctx
)
5251 TCGv t0
= tcg_temp_new();
5252 TCGv t1
= tcg_temp_new();
5253 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5254 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5255 gen_store_spr(SPR_MQ
, t0
);
5256 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5259 if (unlikely(Rc(ctx
->opcode
) != 0))
5260 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5264 static void gen_sreq(DisasContext
*ctx
)
5266 TCGv t0
= tcg_temp_new();
5267 TCGv t1
= tcg_temp_new();
5268 TCGv t2
= tcg_temp_new();
5269 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5270 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5271 tcg_gen_shr_tl(t1
, t1
, t0
);
5272 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5273 gen_load_spr(t2
, SPR_MQ
);
5274 gen_store_spr(SPR_MQ
, t0
);
5275 tcg_gen_and_tl(t0
, t0
, t1
);
5276 tcg_gen_andc_tl(t2
, t2
, t1
);
5277 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5281 if (unlikely(Rc(ctx
->opcode
) != 0))
5282 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5286 static void gen_sriq(DisasContext
*ctx
)
5288 int sh
= SH(ctx
->opcode
);
5289 TCGv t0
= tcg_temp_new();
5290 TCGv t1
= tcg_temp_new();
5291 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5292 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5293 tcg_gen_or_tl(t1
, t0
, t1
);
5294 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5295 gen_store_spr(SPR_MQ
, t1
);
5298 if (unlikely(Rc(ctx
->opcode
) != 0))
5299 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5303 static void gen_srliq(DisasContext
*ctx
)
5305 int sh
= SH(ctx
->opcode
);
5306 TCGv t0
= tcg_temp_new();
5307 TCGv t1
= tcg_temp_new();
5308 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5309 gen_load_spr(t1
, SPR_MQ
);
5310 gen_store_spr(SPR_MQ
, t0
);
5311 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5312 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5313 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5316 if (unlikely(Rc(ctx
->opcode
) != 0))
5317 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5321 static void gen_srlq(DisasContext
*ctx
)
5323 TCGLabel
*l1
= gen_new_label();
5324 TCGLabel
*l2
= gen_new_label();
5325 TCGv t0
= tcg_temp_local_new();
5326 TCGv t1
= tcg_temp_local_new();
5327 TCGv t2
= tcg_temp_local_new();
5328 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5329 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5330 tcg_gen_shr_tl(t2
, t1
, t2
);
5331 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5332 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5333 gen_load_spr(t0
, SPR_MQ
);
5334 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5337 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5338 tcg_gen_and_tl(t0
, t0
, t2
);
5339 gen_load_spr(t1
, SPR_MQ
);
5340 tcg_gen_andc_tl(t1
, t1
, t2
);
5341 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5346 if (unlikely(Rc(ctx
->opcode
) != 0))
5347 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5351 static void gen_srq(DisasContext
*ctx
)
5353 TCGLabel
*l1
= gen_new_label();
5354 TCGv t0
= tcg_temp_new();
5355 TCGv t1
= tcg_temp_new();
5356 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5357 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5358 tcg_gen_subfi_tl(t1
, 32, t1
);
5359 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5360 tcg_gen_or_tl(t1
, t0
, t1
);
5361 gen_store_spr(SPR_MQ
, t1
);
5362 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5363 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5364 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5365 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5369 if (unlikely(Rc(ctx
->opcode
) != 0))
5370 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5373 /* PowerPC 602 specific instructions */
5376 static void gen_dsa(DisasContext
*ctx
)
5379 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5383 static void gen_esa(DisasContext
*ctx
)
5386 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5390 static void gen_mfrom(DisasContext
*ctx
)
5392 #if defined(CONFIG_USER_ONLY)
5396 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5397 #endif /* defined(CONFIG_USER_ONLY) */
5400 /* 602 - 603 - G2 TLB management */
5403 static void gen_tlbld_6xx(DisasContext
*ctx
)
5405 #if defined(CONFIG_USER_ONLY)
5409 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5410 #endif /* defined(CONFIG_USER_ONLY) */
5414 static void gen_tlbli_6xx(DisasContext
*ctx
)
5416 #if defined(CONFIG_USER_ONLY)
5420 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5421 #endif /* defined(CONFIG_USER_ONLY) */
5424 /* 74xx TLB management */
5427 static void gen_tlbld_74xx(DisasContext
*ctx
)
5429 #if defined(CONFIG_USER_ONLY)
5433 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5434 #endif /* defined(CONFIG_USER_ONLY) */
5438 static void gen_tlbli_74xx(DisasContext
*ctx
)
5440 #if defined(CONFIG_USER_ONLY)
5444 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5445 #endif /* defined(CONFIG_USER_ONLY) */
5448 /* POWER instructions not in PowerPC 601 */
5451 static void gen_clf(DisasContext
*ctx
)
5453 /* Cache line flush: implemented as no-op */
5457 static void gen_cli(DisasContext
*ctx
)
5459 #if defined(CONFIG_USER_ONLY)
5462 /* Cache line invalidate: privileged and treated as no-op */
5464 #endif /* defined(CONFIG_USER_ONLY) */
5468 static void gen_dclst(DisasContext
*ctx
)
5470 /* Data cache line store: treated as no-op */
5473 static void gen_mfsri(DisasContext
*ctx
)
5475 #if defined(CONFIG_USER_ONLY)
5478 int ra
= rA(ctx
->opcode
);
5479 int rd
= rD(ctx
->opcode
);
5483 t0
= tcg_temp_new();
5484 gen_addr_reg_index(ctx
, t0
);
5485 tcg_gen_extract_tl(t0
, t0
, 28, 4);
5486 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5488 if (ra
!= 0 && ra
!= rd
)
5489 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5490 #endif /* defined(CONFIG_USER_ONLY) */
5493 static void gen_rac(DisasContext
*ctx
)
5495 #if defined(CONFIG_USER_ONLY)
5501 t0
= tcg_temp_new();
5502 gen_addr_reg_index(ctx
, t0
);
5503 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5505 #endif /* defined(CONFIG_USER_ONLY) */
5508 static void gen_rfsvc(DisasContext
*ctx
)
5510 #if defined(CONFIG_USER_ONLY)
5515 gen_helper_rfsvc(cpu_env
);
5516 gen_sync_exception(ctx
);
5517 #endif /* defined(CONFIG_USER_ONLY) */
5520 /* svc is not implemented for now */
5522 /* BookE specific instructions */
5524 /* XXX: not implemented on 440 ? */
5525 static void gen_mfapidi(DisasContext
*ctx
)
5528 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5531 /* XXX: not implemented on 440 ? */
5532 static void gen_tlbiva(DisasContext
*ctx
)
5534 #if defined(CONFIG_USER_ONLY)
5540 t0
= tcg_temp_new();
5541 gen_addr_reg_index(ctx
, t0
);
5542 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5544 #endif /* defined(CONFIG_USER_ONLY) */
5547 /* All 405 MAC instructions are translated here */
5548 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5549 int ra
, int rb
, int rt
, int Rc
)
5553 t0
= tcg_temp_local_new();
5554 t1
= tcg_temp_local_new();
5556 switch (opc3
& 0x0D) {
5558 /* macchw - macchw. - macchwo - macchwo. */
5559 /* macchws - macchws. - macchwso - macchwso. */
5560 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5561 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5562 /* mulchw - mulchw. */
5563 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5564 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5565 tcg_gen_ext16s_tl(t1
, t1
);
5568 /* macchwu - macchwu. - macchwuo - macchwuo. */
5569 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5570 /* mulchwu - mulchwu. */
5571 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5572 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5573 tcg_gen_ext16u_tl(t1
, t1
);
5576 /* machhw - machhw. - machhwo - machhwo. */
5577 /* machhws - machhws. - machhwso - machhwso. */
5578 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5579 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5580 /* mulhhw - mulhhw. */
5581 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5582 tcg_gen_ext16s_tl(t0
, t0
);
5583 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5584 tcg_gen_ext16s_tl(t1
, t1
);
5587 /* machhwu - machhwu. - machhwuo - machhwuo. */
5588 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5589 /* mulhhwu - mulhhwu. */
5590 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5591 tcg_gen_ext16u_tl(t0
, t0
);
5592 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5593 tcg_gen_ext16u_tl(t1
, t1
);
5596 /* maclhw - maclhw. - maclhwo - maclhwo. */
5597 /* maclhws - maclhws. - maclhwso - maclhwso. */
5598 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5599 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5600 /* mullhw - mullhw. */
5601 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5602 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5605 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5606 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5607 /* mullhwu - mullhwu. */
5608 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5609 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5613 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5614 tcg_gen_mul_tl(t1
, t0
, t1
);
5616 /* nmultiply-and-accumulate (0x0E) */
5617 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5619 /* multiply-and-accumulate (0x0C) */
5620 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5624 /* Check overflow and/or saturate */
5625 TCGLabel
*l1
= gen_new_label();
5628 /* Start with XER OV disabled, the most likely case */
5629 tcg_gen_movi_tl(cpu_ov
, 0);
5633 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5634 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5635 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5636 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5639 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5640 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5644 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5647 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5651 /* Check overflow */
5652 tcg_gen_movi_tl(cpu_ov
, 1);
5653 tcg_gen_movi_tl(cpu_so
, 1);
5656 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5659 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5663 if (unlikely(Rc
) != 0) {
5665 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5669 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5670 static void glue(gen_, name)(DisasContext *ctx) \
5672 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5673 rD(ctx->opcode), Rc(ctx->opcode)); \
5676 /* macchw - macchw. */
5677 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5678 /* macchwo - macchwo. */
5679 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5680 /* macchws - macchws. */
5681 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5682 /* macchwso - macchwso. */
5683 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5684 /* macchwsu - macchwsu. */
5685 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5686 /* macchwsuo - macchwsuo. */
5687 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5688 /* macchwu - macchwu. */
5689 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5690 /* macchwuo - macchwuo. */
5691 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5692 /* machhw - machhw. */
5693 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5694 /* machhwo - machhwo. */
5695 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5696 /* machhws - machhws. */
5697 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5698 /* machhwso - machhwso. */
5699 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5700 /* machhwsu - machhwsu. */
5701 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5702 /* machhwsuo - machhwsuo. */
5703 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5704 /* machhwu - machhwu. */
5705 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5706 /* machhwuo - machhwuo. */
5707 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5708 /* maclhw - maclhw. */
5709 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5710 /* maclhwo - maclhwo. */
5711 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5712 /* maclhws - maclhws. */
5713 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5714 /* maclhwso - maclhwso. */
5715 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5716 /* maclhwu - maclhwu. */
5717 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5718 /* maclhwuo - maclhwuo. */
5719 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5720 /* maclhwsu - maclhwsu. */
5721 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5722 /* maclhwsuo - maclhwsuo. */
5723 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5724 /* nmacchw - nmacchw. */
5725 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5726 /* nmacchwo - nmacchwo. */
5727 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5728 /* nmacchws - nmacchws. */
5729 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5730 /* nmacchwso - nmacchwso. */
5731 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5732 /* nmachhw - nmachhw. */
5733 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5734 /* nmachhwo - nmachhwo. */
5735 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5736 /* nmachhws - nmachhws. */
5737 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5738 /* nmachhwso - nmachhwso. */
5739 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5740 /* nmaclhw - nmaclhw. */
5741 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5742 /* nmaclhwo - nmaclhwo. */
5743 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5744 /* nmaclhws - nmaclhws. */
5745 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5746 /* nmaclhwso - nmaclhwso. */
5747 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5749 /* mulchw - mulchw. */
5750 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5751 /* mulchwu - mulchwu. */
5752 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5753 /* mulhhw - mulhhw. */
5754 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5755 /* mulhhwu - mulhhwu. */
5756 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5757 /* mullhw - mullhw. */
5758 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5759 /* mullhwu - mullhwu. */
5760 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5763 static void gen_mfdcr(DisasContext
*ctx
)
5765 #if defined(CONFIG_USER_ONLY)
5771 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5772 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5773 tcg_temp_free(dcrn
);
5774 #endif /* defined(CONFIG_USER_ONLY) */
5778 static void gen_mtdcr(DisasContext
*ctx
)
5780 #if defined(CONFIG_USER_ONLY)
5786 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5787 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5788 tcg_temp_free(dcrn
);
5789 #endif /* defined(CONFIG_USER_ONLY) */
5793 /* XXX: not implemented on 440 ? */
5794 static void gen_mfdcrx(DisasContext
*ctx
)
5796 #if defined(CONFIG_USER_ONLY)
5800 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5801 cpu_gpr
[rA(ctx
->opcode
)]);
5802 /* Note: Rc update flag set leads to undefined state of Rc0 */
5803 #endif /* defined(CONFIG_USER_ONLY) */
5807 /* XXX: not implemented on 440 ? */
5808 static void gen_mtdcrx(DisasContext
*ctx
)
5810 #if defined(CONFIG_USER_ONLY)
5814 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5815 cpu_gpr
[rS(ctx
->opcode
)]);
5816 /* Note: Rc update flag set leads to undefined state of Rc0 */
5817 #endif /* defined(CONFIG_USER_ONLY) */
5820 /* mfdcrux (PPC 460) : user-mode access to DCR */
5821 static void gen_mfdcrux(DisasContext
*ctx
)
5823 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5824 cpu_gpr
[rA(ctx
->opcode
)]);
5825 /* Note: Rc update flag set leads to undefined state of Rc0 */
5828 /* mtdcrux (PPC 460) : user-mode access to DCR */
5829 static void gen_mtdcrux(DisasContext
*ctx
)
5831 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5832 cpu_gpr
[rS(ctx
->opcode
)]);
5833 /* Note: Rc update flag set leads to undefined state of Rc0 */
5837 static void gen_dccci(DisasContext
*ctx
)
5840 /* interpreted as no-op */
5844 static void gen_dcread(DisasContext
*ctx
)
5846 #if defined(CONFIG_USER_ONLY)
5852 gen_set_access_type(ctx
, ACCESS_CACHE
);
5853 EA
= tcg_temp_new();
5854 gen_addr_reg_index(ctx
, EA
);
5855 val
= tcg_temp_new();
5856 gen_qemu_ld32u(ctx
, val
, EA
);
5858 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5860 #endif /* defined(CONFIG_USER_ONLY) */
5864 static void gen_icbt_40x(DisasContext
*ctx
)
5866 /* interpreted as no-op */
5867 /* XXX: specification say this is treated as a load by the MMU
5868 * but does not generate any exception
5873 static void gen_iccci(DisasContext
*ctx
)
5876 /* interpreted as no-op */
5880 static void gen_icread(DisasContext
*ctx
)
5883 /* interpreted as no-op */
5886 /* rfci (supervisor only) */
5887 static void gen_rfci_40x(DisasContext
*ctx
)
5889 #if defined(CONFIG_USER_ONLY)
5893 /* Restore CPU state */
5894 gen_helper_40x_rfci(cpu_env
);
5895 gen_sync_exception(ctx
);
5896 #endif /* defined(CONFIG_USER_ONLY) */
5899 static void gen_rfci(DisasContext
*ctx
)
5901 #if defined(CONFIG_USER_ONLY)
5905 /* Restore CPU state */
5906 gen_helper_rfci(cpu_env
);
5907 gen_sync_exception(ctx
);
5908 #endif /* defined(CONFIG_USER_ONLY) */
5911 /* BookE specific */
5913 /* XXX: not implemented on 440 ? */
5914 static void gen_rfdi(DisasContext
*ctx
)
5916 #if defined(CONFIG_USER_ONLY)
5920 /* Restore CPU state */
5921 gen_helper_rfdi(cpu_env
);
5922 gen_sync_exception(ctx
);
5923 #endif /* defined(CONFIG_USER_ONLY) */
5926 /* XXX: not implemented on 440 ? */
5927 static void gen_rfmci(DisasContext
*ctx
)
5929 #if defined(CONFIG_USER_ONLY)
5933 /* Restore CPU state */
5934 gen_helper_rfmci(cpu_env
);
5935 gen_sync_exception(ctx
);
5936 #endif /* defined(CONFIG_USER_ONLY) */
5939 /* TLB management - PowerPC 405 implementation */
5942 static void gen_tlbre_40x(DisasContext
*ctx
)
5944 #if defined(CONFIG_USER_ONLY)
5948 switch (rB(ctx
->opcode
)) {
5950 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5951 cpu_gpr
[rA(ctx
->opcode
)]);
5954 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5955 cpu_gpr
[rA(ctx
->opcode
)]);
5958 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5961 #endif /* defined(CONFIG_USER_ONLY) */
5964 /* tlbsx - tlbsx. */
5965 static void gen_tlbsx_40x(DisasContext
*ctx
)
5967 #if defined(CONFIG_USER_ONLY)
5973 t0
= tcg_temp_new();
5974 gen_addr_reg_index(ctx
, t0
);
5975 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5977 if (Rc(ctx
->opcode
)) {
5978 TCGLabel
*l1
= gen_new_label();
5979 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5980 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5981 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5984 #endif /* defined(CONFIG_USER_ONLY) */
5988 static void gen_tlbwe_40x(DisasContext
*ctx
)
5990 #if defined(CONFIG_USER_ONLY)
5995 switch (rB(ctx
->opcode
)) {
5997 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5998 cpu_gpr
[rS(ctx
->opcode
)]);
6001 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6002 cpu_gpr
[rS(ctx
->opcode
)]);
6005 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6008 #endif /* defined(CONFIG_USER_ONLY) */
6011 /* TLB management - PowerPC 440 implementation */
6014 static void gen_tlbre_440(DisasContext
*ctx
)
6016 #if defined(CONFIG_USER_ONLY)
6021 switch (rB(ctx
->opcode
)) {
6026 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6027 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6028 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6029 tcg_temp_free_i32(t0
);
6033 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6036 #endif /* defined(CONFIG_USER_ONLY) */
6039 /* tlbsx - tlbsx. */
6040 static void gen_tlbsx_440(DisasContext
*ctx
)
6042 #if defined(CONFIG_USER_ONLY)
6048 t0
= tcg_temp_new();
6049 gen_addr_reg_index(ctx
, t0
);
6050 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6052 if (Rc(ctx
->opcode
)) {
6053 TCGLabel
*l1
= gen_new_label();
6054 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6055 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6056 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6059 #endif /* defined(CONFIG_USER_ONLY) */
6063 static void gen_tlbwe_440(DisasContext
*ctx
)
6065 #if defined(CONFIG_USER_ONLY)
6069 switch (rB(ctx
->opcode
)) {
6074 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6075 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6076 cpu_gpr
[rS(ctx
->opcode
)]);
6077 tcg_temp_free_i32(t0
);
6081 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6084 #endif /* defined(CONFIG_USER_ONLY) */
6087 /* TLB management - PowerPC BookE 2.06 implementation */
6090 static void gen_tlbre_booke206(DisasContext
*ctx
)
6092 #if defined(CONFIG_USER_ONLY)
6096 gen_helper_booke206_tlbre(cpu_env
);
6097 #endif /* defined(CONFIG_USER_ONLY) */
6100 /* tlbsx - tlbsx. */
6101 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6103 #if defined(CONFIG_USER_ONLY)
6109 if (rA(ctx
->opcode
)) {
6110 t0
= tcg_temp_new();
6111 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6113 t0
= tcg_const_tl(0);
6116 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6117 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6119 #endif /* defined(CONFIG_USER_ONLY) */
6123 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6125 #if defined(CONFIG_USER_ONLY)
6129 gen_helper_booke206_tlbwe(cpu_env
);
6130 #endif /* defined(CONFIG_USER_ONLY) */
6133 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6135 #if defined(CONFIG_USER_ONLY)
6141 t0
= tcg_temp_new();
6142 gen_addr_reg_index(ctx
, t0
);
6143 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6145 #endif /* defined(CONFIG_USER_ONLY) */
6148 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6150 #if defined(CONFIG_USER_ONLY)
6156 t0
= tcg_temp_new();
6157 gen_addr_reg_index(ctx
, t0
);
6159 switch((ctx
->opcode
>> 21) & 0x3) {
6161 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6164 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6167 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6170 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6175 #endif /* defined(CONFIG_USER_ONLY) */
6180 static void gen_wrtee(DisasContext
*ctx
)
6182 #if defined(CONFIG_USER_ONLY)
6188 t0
= tcg_temp_new();
6189 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6190 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6191 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6193 /* Stop translation to have a chance to raise an exception
6194 * if we just set msr_ee to 1
6196 gen_stop_exception(ctx
);
6197 #endif /* defined(CONFIG_USER_ONLY) */
6201 static void gen_wrteei(DisasContext
*ctx
)
6203 #if defined(CONFIG_USER_ONLY)
6207 if (ctx
->opcode
& 0x00008000) {
6208 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6209 /* Stop translation to have a chance to raise an exception */
6210 gen_stop_exception(ctx
);
6212 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6214 #endif /* defined(CONFIG_USER_ONLY) */
6217 /* PowerPC 440 specific instructions */
6220 static void gen_dlmzb(DisasContext
*ctx
)
6222 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6223 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6224 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6225 tcg_temp_free_i32(t0
);
6228 /* mbar replaces eieio on 440 */
6229 static void gen_mbar(DisasContext
*ctx
)
6231 /* interpreted as no-op */
6234 /* msync replaces sync on 440 */
6235 static void gen_msync_4xx(DisasContext
*ctx
)
6237 /* interpreted as no-op */
6241 static void gen_icbt_440(DisasContext
*ctx
)
6243 /* interpreted as no-op */
6244 /* XXX: specification say this is treated as a load by the MMU
6245 * but does not generate any exception
6249 /* Embedded.Processor Control */
6251 static void gen_msgclr(DisasContext
*ctx
)
6253 #if defined(CONFIG_USER_ONLY)
6257 /* 64-bit server processors compliant with arch 2.x */
6258 if (ctx
->insns_flags
& PPC_SEGMENT_64B
) {
6259 gen_helper_book3s_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6261 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6263 #endif /* defined(CONFIG_USER_ONLY) */
6266 static void gen_msgsnd(DisasContext
*ctx
)
6268 #if defined(CONFIG_USER_ONLY)
6272 /* 64-bit server processors compliant with arch 2.x */
6273 if (ctx
->insns_flags
& PPC_SEGMENT_64B
) {
6274 gen_helper_book3s_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6276 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6278 #endif /* defined(CONFIG_USER_ONLY) */
6281 static void gen_msgsync(DisasContext
*ctx
)
6283 #if defined(CONFIG_USER_ONLY)
6287 #endif /* defined(CONFIG_USER_ONLY) */
6288 /* interpreted as no-op */
6291 #if defined(TARGET_PPC64)
6292 static void gen_maddld(DisasContext
*ctx
)
6294 TCGv_i64 t1
= tcg_temp_new_i64();
6296 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6297 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6298 tcg_temp_free_i64(t1
);
6301 /* maddhd maddhdu */
6302 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6304 TCGv_i64 lo
= tcg_temp_new_i64();
6305 TCGv_i64 hi
= tcg_temp_new_i64();
6306 TCGv_i64 t1
= tcg_temp_new_i64();
6308 if (Rc(ctx
->opcode
)) {
6309 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6310 cpu_gpr
[rB(ctx
->opcode
)]);
6311 tcg_gen_movi_i64(t1
, 0);
6313 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6314 cpu_gpr
[rB(ctx
->opcode
)]);
6315 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6317 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6318 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6319 tcg_temp_free_i64(lo
);
6320 tcg_temp_free_i64(hi
);
6321 tcg_temp_free_i64(t1
);
6323 #endif /* defined(TARGET_PPC64) */
6325 static void gen_tbegin(DisasContext
*ctx
)
6327 if (unlikely(!ctx
->tm_enabled
)) {
6328 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6331 gen_helper_tbegin(cpu_env
);
6334 #define GEN_TM_NOOP(name) \
6335 static inline void gen_##name(DisasContext *ctx) \
6337 if (unlikely(!ctx->tm_enabled)) { \
6338 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6341 /* Because tbegin always fails in QEMU, these user \
6342 * space instructions all have a simple implementation: \
6344 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6345 * = 0b0 || 0b00 || 0b0 \
6347 tcg_gen_movi_i32(cpu_crf[0], 0); \
6351 GEN_TM_NOOP(tabort
);
6352 GEN_TM_NOOP(tabortwc
);
6353 GEN_TM_NOOP(tabortwci
);
6354 GEN_TM_NOOP(tabortdc
);
6355 GEN_TM_NOOP(tabortdci
);
6357 static inline void gen_cp_abort(DisasContext
*ctx
)
6362 #define GEN_CP_PASTE_NOOP(name) \
6363 static inline void gen_##name(DisasContext *ctx) \
6365 /* Generate invalid exception until \
6366 * we have an implementation of the copy \
6372 GEN_CP_PASTE_NOOP(copy
)
6373 GEN_CP_PASTE_NOOP(paste
)
6375 static void gen_tcheck(DisasContext
*ctx
)
6377 if (unlikely(!ctx
->tm_enabled
)) {
6378 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6381 /* Because tbegin always fails, the tcheck implementation
6384 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6385 * = 0b1 || 0b00 || 0b0
6387 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
6390 #if defined(CONFIG_USER_ONLY)
6391 #define GEN_TM_PRIV_NOOP(name) \
6392 static inline void gen_##name(DisasContext *ctx) \
6394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6399 #define GEN_TM_PRIV_NOOP(name) \
6400 static inline void gen_##name(DisasContext *ctx) \
6403 if (unlikely(!ctx->tm_enabled)) { \
6404 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6407 /* Because tbegin always fails, the implementation is \
6410 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6411 * = 0b0 || 0b00 | 0b0 \
6413 tcg_gen_movi_i32(cpu_crf[0], 0); \
6418 GEN_TM_PRIV_NOOP(treclaim
);
6419 GEN_TM_PRIV_NOOP(trechkpt
);
6421 #include "translate/fp-impl.inc.c"
6423 #include "translate/vmx-impl.inc.c"
6425 #include "translate/vsx-impl.inc.c"
6427 #include "translate/dfp-impl.inc.c"
6429 #include "translate/spe-impl.inc.c"
6431 /* Handles lfdp, lxsd, lxssp */
6432 static void gen_dform39(DisasContext
*ctx
)
6434 switch (ctx
->opcode
& 0x3) {
6436 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6437 return gen_lfdp(ctx
);
6441 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6442 return gen_lxsd(ctx
);
6446 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6447 return gen_lxssp(ctx
);
6451 return gen_invalid(ctx
);
6454 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6455 static void gen_dform3D(DisasContext
*ctx
)
6457 if ((ctx
->opcode
& 3) == 1) { /* DQ-FORM */
6458 switch (ctx
->opcode
& 0x7) {
6460 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6461 return gen_lxv(ctx
);
6465 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6466 return gen_stxv(ctx
);
6470 } else { /* DS-FORM */
6471 switch (ctx
->opcode
& 0x3) {
6473 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6474 return gen_stfdp(ctx
);
6478 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6479 return gen_stxsd(ctx
);
6482 case 3: /* stxssp */
6483 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6484 return gen_stxssp(ctx
);
6489 return gen_invalid(ctx
);
6492 static opcode_t opcodes
[] = {
6493 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
6494 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
6495 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6496 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER
),
6497 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6498 #if defined(TARGET_PPC64)
6499 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
6501 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
6502 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
6503 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
6504 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6505 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6506 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6507 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6508 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6509 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
6510 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
6511 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
6512 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
6513 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6514 #if defined(TARGET_PPC64)
6515 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
6517 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
6518 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
6519 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6520 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6521 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6522 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
6523 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6524 GEN_HANDLER_E(copy
, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE
, PPC2_ISA300
),
6525 GEN_HANDLER_E(cp_abort
, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6526 GEN_HANDLER_E(paste
, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE
, PPC2_ISA300
),
6527 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
6528 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
6529 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6530 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6531 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6532 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6533 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
6534 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
6535 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6536 #if defined(TARGET_PPC64)
6537 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
6538 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
6539 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6540 GEN_HANDLER_E(darn
, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE
, PPC2_ISA300
),
6541 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6542 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
6544 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6545 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6546 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6547 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
6548 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
6549 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
6550 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
6551 #if defined(TARGET_PPC64)
6552 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
6553 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
6554 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
6555 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
6556 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
6557 GEN_HANDLER2_E(extswsli0
, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6558 PPC_NONE
, PPC2_ISA300
),
6559 GEN_HANDLER2_E(extswsli1
, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6560 PPC_NONE
, PPC2_ISA300
),
6562 #if defined(TARGET_PPC64)
6563 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6564 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
6565 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6567 /* handles lfdp, lxsd, lxssp */
6568 GEN_HANDLER_E(dform39
, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6569 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6570 GEN_HANDLER_E(dform3D
, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6571 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6572 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6573 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
6574 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
6575 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
6576 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
6577 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO
),
6578 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
6579 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6580 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6581 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
6582 GEN_HANDLER_E(lwat
, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6583 GEN_HANDLER_E(stwat
, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6584 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6585 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6586 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
6587 #if defined(TARGET_PPC64)
6588 GEN_HANDLER_E(ldat
, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6589 GEN_HANDLER_E(stdat
, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6590 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
6591 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6592 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
6593 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6595 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
6596 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
6597 GEN_HANDLER_E(wait
, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE
, PPC2_ISA300
),
6598 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6599 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6600 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
6601 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
6602 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE
, PPC2_BCTAR_ISA207
),
6603 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
6604 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
6605 #if defined(TARGET_PPC64)
6606 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
6607 GEN_HANDLER_E(stop
, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6608 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6609 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6610 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6611 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6612 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
6614 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
6615 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
6616 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6617 #if defined(TARGET_PPC64)
6618 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
6619 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6621 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
6622 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
6623 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
6624 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
6625 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
6626 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
6627 #if defined(TARGET_PPC64)
6628 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
6629 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
6630 GEN_HANDLER_E(mcrxrx
, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE
, PPC2_ISA300
),
6632 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
6633 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
6634 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
6635 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
6636 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
6637 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
6638 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
6639 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
6640 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
6641 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
6642 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC
),
6643 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
6644 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
6645 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
6646 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
6647 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
6648 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
6649 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
6650 #if defined(TARGET_PPC64)
6651 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
6652 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6654 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
6655 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6657 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
6658 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
6659 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
6660 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
6662 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
6663 /* XXX Those instructions will need to be handled differently for
6664 * different ISA versions */
6665 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
6666 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
6667 GEN_HANDLER_E(tlbiel
, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6668 GEN_HANDLER_E(tlbie
, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6669 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
6670 #if defined(TARGET_PPC64)
6671 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
6672 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
6673 GEN_HANDLER_E(slbieg
, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE
, PPC2_ISA300
),
6674 GEN_HANDLER_E(slbsync
, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6676 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
6677 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
6678 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
6679 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
6680 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
6681 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
6682 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
6683 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
6684 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
6685 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
6686 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
6687 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
6688 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
6689 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
6690 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
6691 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
6692 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
6693 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
6694 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
6695 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
6696 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
6697 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
6698 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
6699 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
6700 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
6701 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
6702 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
6703 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
6704 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
6705 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
6706 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
6707 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
6708 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
6709 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
6710 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
6711 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
6712 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
6713 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
6714 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
6715 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
6716 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
6717 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
6718 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
6719 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
6720 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
6721 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
6722 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
6723 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
6724 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
6725 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6726 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6727 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
6728 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
6729 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6730 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6731 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
6732 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
6733 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
6734 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
6735 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
6736 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
6737 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
6738 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
6739 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
6740 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
6741 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
6742 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
6743 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
6744 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
6745 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
6746 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
6747 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
6748 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
6749 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
6750 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
6751 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
6752 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
6753 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
6754 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
6755 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
6756 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6757 PPC_NONE
, PPC2_BOOKE206
),
6758 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6759 PPC_NONE
, PPC2_BOOKE206
),
6760 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6761 PPC_NONE
, PPC2_BOOKE206
),
6762 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6763 PPC_NONE
, PPC2_BOOKE206
),
6764 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6765 PPC_NONE
, PPC2_BOOKE206
),
6766 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6767 PPC_NONE
, PPC2_PRCNTL
),
6768 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6769 PPC_NONE
, PPC2_PRCNTL
),
6770 GEN_HANDLER2_E(msgsync
, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
6771 PPC_NONE
, PPC2_PRCNTL
),
6772 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
6773 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
6774 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
6775 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
6776 PPC_BOOKE
, PPC2_BOOKE206
),
6777 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
6778 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6779 PPC_BOOKE
, PPC2_BOOKE206
),
6780 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
6782 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
6783 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
6784 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
6785 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
6786 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
6787 #if defined(TARGET_PPC64)
6788 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
6790 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6793 #undef GEN_INT_ARITH_ADD
6794 #undef GEN_INT_ARITH_ADD_CONST
6795 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6796 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6797 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6798 add_ca, compute_ca, compute_ov) \
6799 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6800 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
6801 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
6802 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
6803 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
6804 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
6805 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
6806 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
6807 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
6808 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
6809 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
6811 #undef GEN_INT_ARITH_DIVW
6812 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6813 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6814 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
6815 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
6816 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
6817 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
6818 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6819 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6820 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6821 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6822 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6823 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6825 #if defined(TARGET_PPC64)
6826 #undef GEN_INT_ARITH_DIVD
6827 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6828 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6829 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
6830 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
6831 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
6832 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
6834 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6835 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6836 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6837 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6838 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6839 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6841 #undef GEN_INT_ARITH_MUL_HELPER
6842 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6843 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6844 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
6845 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
6846 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
6849 #undef GEN_INT_ARITH_SUBF
6850 #undef GEN_INT_ARITH_SUBF_CONST
6851 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6852 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6853 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6854 add_ca, compute_ca, compute_ov) \
6855 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6856 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
6857 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
6858 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
6859 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
6860 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
6861 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
6862 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
6863 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
6864 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
6865 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
6869 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6870 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6871 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6872 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6873 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
6874 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
6875 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
6876 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
6877 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
6878 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
6879 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
6880 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
6881 #if defined(TARGET_PPC64)
6882 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
6885 #if defined(TARGET_PPC64)
6888 #define GEN_PPC64_R2(name, opc1, opc2) \
6889 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6890 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6892 #define GEN_PPC64_R4(name, opc1, opc2) \
6893 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6894 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6896 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6898 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6900 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
6901 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
6902 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
6903 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
6904 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
6905 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
6913 #define GEN_LD(name, ldop, opc, type) \
6914 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6915 #define GEN_LDU(name, ldop, opc, type) \
6916 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6917 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6918 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6919 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6920 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6921 #define GEN_LDS(name, ldop, op, type) \
6922 GEN_LD(name, ldop, op | 0x20, type) \
6923 GEN_LDU(name, ldop, op | 0x21, type) \
6924 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6925 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6927 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
6928 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
6929 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
6930 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
6931 #if defined(TARGET_PPC64)
6932 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
6933 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
6934 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
)
6935 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
)
6936 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
6938 /* HV/P7 and later only */
6939 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
6940 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
6941 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
6942 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
6944 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
6945 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
6952 #define GEN_ST(name, stop, opc, type) \
6953 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6954 #define GEN_STU(name, stop, opc, type) \
6955 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6956 #define GEN_STUX(name, stop, opc2, opc3, type) \
6957 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6958 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6959 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6960 #define GEN_STS(name, stop, op, type) \
6961 GEN_ST(name, stop, op | 0x20, type) \
6962 GEN_STU(name, stop, op | 0x21, type) \
6963 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6964 GEN_STX(name, stop, 0x17, op | 0x00, type)
6966 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
6967 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
6968 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
6969 #if defined(TARGET_PPC64)
6970 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
)
6971 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
)
6972 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
6973 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
6974 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
6975 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
6976 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
6978 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
6979 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
6982 #define GEN_CRLOGIC(name, tcg_op, opc) \
6983 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6984 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
6985 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
6986 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
6987 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
6988 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
6989 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
6990 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
6991 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
6993 #undef GEN_MAC_HANDLER
6994 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6995 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6996 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
6997 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
6998 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
6999 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
7000 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
7001 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
7002 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
7003 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
7004 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
7005 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
7006 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
7007 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
7008 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
7009 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
7010 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
7011 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
7012 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
7013 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
7014 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
7015 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
7016 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
7017 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
7018 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
7019 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
7020 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
7021 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
7022 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
7023 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
7024 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
7025 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
7026 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
7027 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
7028 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
7029 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
7030 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
7031 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
7032 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
7033 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
7034 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
7035 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
7036 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
7037 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
7039 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7041 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7043 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7045 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7047 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7049 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7051 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7053 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7055 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7057 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7059 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7062 #include "translate/fp-ops.inc.c"
7064 #include "translate/vmx-ops.inc.c"
7066 #include "translate/vsx-ops.inc.c"
7068 #include "translate/dfp-ops.inc.c"
7070 #include "translate/spe-ops.inc.c"
7073 #include "helper_regs.h"
7074 #include "translate_init.inc.c"
7076 /*****************************************************************************/
7077 /* Misc PowerPC helpers */
7078 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
7084 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7085 CPUPPCState
*env
= &cpu
->env
;
7088 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
7089 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
7090 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
7092 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
7093 TARGET_FMT_lx
" iidx %d didx %d\n",
7094 env
->msr
, env
->spr
[SPR_HID0
],
7095 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
7096 #if !defined(NO_TIMER_DUMP)
7097 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7098 #if !defined(CONFIG_USER_ONLY)
7102 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7103 #if !defined(CONFIG_USER_ONLY)
7104 , cpu_ppc_load_decr(env
)
7108 for (i
= 0; i
< 32; i
++) {
7109 if ((i
& (RGPL
- 1)) == 0)
7110 cpu_fprintf(f
, "GPR%02d", i
);
7111 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7112 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
7113 cpu_fprintf(f
, "\n");
7115 cpu_fprintf(f
, "CR ");
7116 for (i
= 0; i
< 8; i
++)
7117 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
7118 cpu_fprintf(f
, " [");
7119 for (i
= 0; i
< 8; i
++) {
7121 if (env
->crf
[i
] & 0x08)
7123 else if (env
->crf
[i
] & 0x04)
7125 else if (env
->crf
[i
] & 0x02)
7127 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7129 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
7132 if (flags
& CPU_DUMP_FPU
) {
7133 for (i
= 0; i
< 32; i
++) {
7134 if ((i
& (RFPL
- 1)) == 0) {
7135 cpu_fprintf(f
, "FPR%02d", i
);
7137 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
7138 if ((i
& (RFPL
- 1)) == (RFPL
- 1)) {
7139 cpu_fprintf(f
, "\n");
7142 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7145 #if !defined(CONFIG_USER_ONLY)
7146 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7147 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7148 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7149 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7151 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7152 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7153 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7154 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7156 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7157 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7158 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7159 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7161 #if defined(TARGET_PPC64)
7162 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
7163 env
->excp_model
== POWERPC_EXCP_POWER8
) {
7164 cpu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7165 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7168 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
7169 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7170 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7171 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7172 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7174 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7175 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7176 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7177 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7179 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7180 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7181 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7182 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7184 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7185 " EPR " TARGET_FMT_lx
"\n",
7186 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7187 env
->spr
[SPR_BOOKE_EPR
]);
7190 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7191 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7192 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7193 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7196 * IVORs are left out as they are large and do not change often --
7197 * they can be read with "p $ivor0", "p $ivor1", etc.
7201 #if defined(TARGET_PPC64)
7202 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7203 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7207 if (env
->spr_cb
[SPR_LPCR
].name
)
7208 cpu_fprintf(f
, " LPCR " TARGET_FMT_lx
"\n", env
->spr
[SPR_LPCR
]);
7210 switch (env
->mmu_model
) {
7211 case POWERPC_MMU_32B
:
7212 case POWERPC_MMU_601
:
7213 case POWERPC_MMU_SOFT_6xx
:
7214 case POWERPC_MMU_SOFT_74xx
:
7215 #if defined(TARGET_PPC64)
7216 case POWERPC_MMU_64B
:
7217 case POWERPC_MMU_2_03
:
7218 case POWERPC_MMU_2_06
:
7219 case POWERPC_MMU_2_07
:
7220 case POWERPC_MMU_3_00
:
7222 if (env
->spr_cb
[SPR_SDR1
].name
) { /* SDR1 Exists */
7223 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" ", env
->spr
[SPR_SDR1
]);
7225 if (env
->spr_cb
[SPR_PTCR
].name
) { /* PTCR Exists */
7226 cpu_fprintf(f
, " PTCR " TARGET_FMT_lx
" ", env
->spr
[SPR_PTCR
]);
7228 cpu_fprintf(f
, " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx
"\n",
7229 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7231 case POWERPC_MMU_BOOKE206
:
7232 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7233 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7234 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7235 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7237 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7238 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7239 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7240 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7242 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7243 " TLB1CFG " TARGET_FMT_lx
"\n",
7244 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7245 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7256 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
7257 fprintf_function cpu_fprintf
, int flags
)
7259 #if defined(DO_PPC_STATISTICS)
7260 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7261 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7264 t1
= cpu
->env
.opcodes
;
7265 for (op1
= 0; op1
< 64; op1
++) {
7267 if (is_indirect_opcode(handler
)) {
7268 t2
= ind_table(handler
);
7269 for (op2
= 0; op2
< 32; op2
++) {
7271 if (is_indirect_opcode(handler
)) {
7272 t3
= ind_table(handler
);
7273 for (op3
= 0; op3
< 32; op3
++) {
7275 if (handler
->count
== 0)
7277 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
7278 "%016" PRIx64
" %" PRId64
"\n",
7279 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7281 handler
->count
, handler
->count
);
7284 if (handler
->count
== 0)
7286 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
7287 "%016" PRIx64
" %" PRId64
"\n",
7288 op1
, op2
, op1
, op2
, handler
->oname
,
7289 handler
->count
, handler
->count
);
7293 if (handler
->count
== 0)
7295 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
7297 op1
, op1
, handler
->oname
,
7298 handler
->count
, handler
->count
);
7304 static void ppc_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
7306 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7307 CPUPPCState
*env
= cs
->env_ptr
;
7310 ctx
->exception
= POWERPC_EXCP_NONE
;
7311 ctx
->spr_cb
= env
->spr_cb
;
7313 ctx
->mem_idx
= env
->dmmu_idx
;
7315 #if !defined(CONFIG_USER_ONLY)
7316 ctx
->hv
= msr_hv
|| !env
->has_hv_mode
;
7318 ctx
->insns_flags
= env
->insns_flags
;
7319 ctx
->insns_flags2
= env
->insns_flags2
;
7320 ctx
->access_type
= -1;
7321 ctx
->need_access_type
= !(env
->mmu_model
& POWERPC_MMU_64B
);
7322 ctx
->le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
7323 ctx
->default_tcg_memop_mask
= ctx
->le_mode
? MO_LE
: MO_BE
;
7324 #if defined(TARGET_PPC64)
7325 ctx
->sf_mode
= msr_is_64bit(env
, env
->msr
);
7326 ctx
->has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
7328 ctx
->lazy_tlb_flush
= env
->mmu_model
== POWERPC_MMU_32B
7329 || env
->mmu_model
== POWERPC_MMU_601
7330 || (env
->mmu_model
& POWERPC_MMU_64B
);
7332 ctx
->fpu_enabled
= !!msr_fp
;
7333 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
7334 ctx
->spe_enabled
= !!msr_spe
;
7336 ctx
->spe_enabled
= false;
7337 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
7338 ctx
->altivec_enabled
= !!msr_vr
;
7340 ctx
->altivec_enabled
= false;
7341 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
7342 ctx
->vsx_enabled
= !!msr_vsx
;
7344 ctx
->vsx_enabled
= false;
7346 #if defined(TARGET_PPC64)
7347 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
7348 ctx
->tm_enabled
= !!msr_tm
;
7350 ctx
->tm_enabled
= false;
7353 ctx
->gtse
= !!(env
->spr
[SPR_LPCR
] & LPCR_GTSE
);
7354 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
7355 ctx
->singlestep_enabled
= CPU_SINGLE_STEP
;
7357 ctx
->singlestep_enabled
= 0;
7358 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
7359 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
7360 if (unlikely(ctx
->base
.singlestep_enabled
)) {
7361 ctx
->singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7363 #if defined (DO_SINGLE_STEP) && 0
7364 /* Single step trace mode */
7368 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
7369 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
7372 static void ppc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
7376 static void ppc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
7378 tcg_gen_insn_start(dcbase
->pc_next
);
7381 static bool ppc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
7382 const CPUBreakpoint
*bp
)
7384 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7386 gen_debug_exception(ctx
);
7387 /* The address covered by the breakpoint must be included in
7388 [tb->pc, tb->pc + tb->size) in order to for it to be
7389 properly cleared -- thus we increment the PC here so that
7390 the logic setting tb->size below does the right thing. */
7391 ctx
->base
.pc_next
+= 4;
7395 static void ppc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
7397 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7398 CPUPPCState
*env
= cs
->env_ptr
;
7399 opc_handler_t
**table
, *handler
;
7401 LOG_DISAS("----------------\n");
7402 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
7403 ctx
->base
.pc_next
, ctx
->mem_idx
, (int)msr_ir
);
7405 if (unlikely(need_byteswap(ctx
))) {
7406 ctx
->opcode
= bswap32(cpu_ldl_code(env
, ctx
->base
.pc_next
));
7408 ctx
->opcode
= cpu_ldl_code(env
, ctx
->base
.pc_next
);
7410 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7411 ctx
->opcode
, opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7412 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7413 ctx
->le_mode
? "little" : "big");
7414 ctx
->base
.pc_next
+= 4;
7415 table
= env
->opcodes
;
7416 handler
= table
[opc1(ctx
->opcode
)];
7417 if (is_indirect_opcode(handler
)) {
7418 table
= ind_table(handler
);
7419 handler
= table
[opc2(ctx
->opcode
)];
7420 if (is_indirect_opcode(handler
)) {
7421 table
= ind_table(handler
);
7422 handler
= table
[opc3(ctx
->opcode
)];
7423 if (is_indirect_opcode(handler
)) {
7424 table
= ind_table(handler
);
7425 handler
= table
[opc4(ctx
->opcode
)];
7429 /* Is opcode *REALLY* valid ? */
7430 if (unlikely(handler
->handler
== &gen_invalid
)) {
7431 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
7432 "%02x - %02x - %02x - %02x (%08x) "
7433 TARGET_FMT_lx
" %d\n",
7434 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7435 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7436 ctx
->opcode
, ctx
->base
.pc_next
- 4, (int)msr_ir
);
7440 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
)
7441 && Rc(ctx
->opcode
))) {
7442 inval
= handler
->inval2
;
7444 inval
= handler
->inval1
;
7447 if (unlikely((ctx
->opcode
& inval
) != 0)) {
7448 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
7449 "%02x - %02x - %02x - %02x (%08x) "
7450 TARGET_FMT_lx
"\n", ctx
->opcode
& inval
,
7451 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7452 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7453 ctx
->opcode
, ctx
->base
.pc_next
- 4);
7454 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
7455 ctx
->base
.is_jmp
= DISAS_NORETURN
;
7459 (*(handler
->handler
))(ctx
);
7460 #if defined(DO_PPC_STATISTICS)
7463 /* Check trace mode exceptions */
7464 if (unlikely(ctx
->singlestep_enabled
& CPU_SINGLE_STEP
&&
7465 (ctx
->base
.pc_next
<= 0x100 || ctx
->base
.pc_next
> 0xF00) &&
7466 ctx
->exception
!= POWERPC_SYSCALL
&&
7467 ctx
->exception
!= POWERPC_EXCP_TRAP
&&
7468 ctx
->exception
!= POWERPC_EXCP_BRANCH
)) {
7469 gen_exception_nip(ctx
, POWERPC_EXCP_TRACE
, ctx
->base
.pc_next
);
7472 if (tcg_check_temp_count()) {
7473 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7474 "temporaries\n", opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7475 opc3(ctx
->opcode
), opc4(ctx
->opcode
), ctx
->opcode
);
7478 ctx
->base
.is_jmp
= ctx
->exception
== POWERPC_EXCP_NONE
?
7479 DISAS_NEXT
: DISAS_NORETURN
;
7482 static void ppc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
7484 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7486 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
7487 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
7488 } else if (ctx
->exception
!= POWERPC_EXCP_BRANCH
) {
7489 if (unlikely(ctx
->base
.singlestep_enabled
)) {
7490 gen_debug_exception(ctx
);
7492 /* Generate the return instruction */
7493 tcg_gen_exit_tb(NULL
, 0);
7497 static void ppc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
7499 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
7500 log_target_disas(cs
, dcbase
->pc_first
, dcbase
->tb
->size
);
7503 static const TranslatorOps ppc_tr_ops
= {
7504 .init_disas_context
= ppc_tr_init_disas_context
,
7505 .tb_start
= ppc_tr_tb_start
,
7506 .insn_start
= ppc_tr_insn_start
,
7507 .breakpoint_check
= ppc_tr_breakpoint_check
,
7508 .translate_insn
= ppc_tr_translate_insn
,
7509 .tb_stop
= ppc_tr_tb_stop
,
7510 .disas_log
= ppc_tr_disas_log
,
7513 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
7517 translator_loop(&ppc_tr_ops
, &ctx
.base
, cs
, tb
);
7520 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,