pcie_aer: Don't trigger a LSI if none are defined
[qemu/rayw.git] / target / hexagon / gen_dectree_import.c
blobee354677fd64e642c04462b28ce426d95d0472e9
1 /*
2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 * This program generates the encodings file that is processed by
20 * the dectree.py script to produce the decoding tree. We use the C
21 * preprocessor to manipulate the files imported from the Hexagon
22 * architecture library.
24 #include <stdio.h>
25 #include <string.h>
26 #include "opcodes.h"
28 #define STRINGIZE(X) #X
30 const char * const opcode_names[] = {
31 #define OPCODE(IID) STRINGIZE(IID)
32 #include "opcodes_def_generated.h.inc"
33 NULL
34 #undef OPCODE
38 * Process the instruction definitions
39 * Scalar core instructions have the following form
40 * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(),
41 * "Add 32-bit registers",
42 * { RdV=RsV+RtV;})
43 * HVX instructions have the following form
44 * EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)",
45 * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX,A_CVI_LATE),
46 * "Insert Word Scalar into Vector",
47 * VxV.uw[0] = RtV;)
49 const char * const opcode_syntax[XX_LAST_OPCODE] = {
50 #define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
51 [TAG] = BEH,
52 #define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
53 [TAG] = BEH,
54 #include "imported/allidefs.def"
55 #undef Q6INSN
56 #undef EXTINSN
59 const char * const opcode_rregs[] = {
60 #define REGINFO(TAG, REGINFO, RREGS, WREGS) RREGS,
61 #define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */
62 #include "op_regs_generated.h.inc"
63 NULL
64 #undef REGINFO
65 #undef IMMINFO
68 const char * const opcode_wregs[] = {
69 #define REGINFO(TAG, REGINFO, RREGS, WREGS) WREGS,
70 #define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */
71 #include "op_regs_generated.h.inc"
72 NULL
73 #undef REGINFO
74 #undef IMMINFO
77 const OpcodeEncoding opcode_encodings[] = {
78 #define DEF_ENC32(TAG, ENCSTR) \
79 [TAG] = { .encoding = ENCSTR },
80 #define DEF_ENC_SUBINSN(TAG, CLASS, ENCSTR) \
81 [TAG] = { .encoding = ENCSTR, .enc_class = CLASS },
82 #define DEF_EXT_ENC(TAG, CLASS, ENCSTR) \
83 [TAG] = { .encoding = ENCSTR, .enc_class = CLASS },
84 #include "imported/encode.def"
85 #undef DEF_ENC32
86 #undef DEF_ENC_SUBINSN
87 #undef DEF_EXT_ENC
90 static const char * const opcode_enc_class_names[XX_LAST_ENC_CLASS] = {
91 "NORMAL",
92 "16BIT",
93 "SUBINSN_A",
94 "SUBINSN_L1",
95 "SUBINSN_L2",
96 "SUBINSN_S1",
97 "SUBINSN_S2",
98 "EXT_noext",
99 "EXT_mmvec",
102 static const char *get_opcode_enc(int opcode)
104 const char *tmp = opcode_encodings[opcode].encoding;
105 if (tmp == NULL) {
106 tmp = "MISSING ENCODING";
108 return tmp;
111 static const char *get_opcode_enc_class(int opcode)
113 const char *tmp = opcode_encodings[opcode].encoding;
114 if (tmp == NULL) {
115 const char *test = "V6_"; /* HVX */
116 const char *name = opcode_names[opcode];
117 if (strncmp(name, test, strlen(test)) == 0) {
118 return "EXT_mmvec";
121 return opcode_enc_class_names[opcode_encodings[opcode].enc_class];
124 static void gen_iset_table(FILE *out)
126 int i;
128 fprintf(out, "iset = {\n");
129 for (i = 0; i < XX_LAST_OPCODE; i++) {
130 fprintf(out, "\t\'%s\' : {\n", opcode_names[i]);
131 fprintf(out, "\t\t\'tag\' : \'%s\',\n", opcode_names[i]);
132 fprintf(out, "\t\t\'syntax\' : \'%s\',\n", opcode_syntax[i]);
133 fprintf(out, "\t\t\'rregs\' : \'%s\',\n", opcode_rregs[i]);
134 fprintf(out, "\t\t\'wregs\' : \'%s\',\n", opcode_wregs[i]);
135 fprintf(out, "\t\t\'enc\' : \'%s\',\n", get_opcode_enc(i));
136 fprintf(out, "\t\t\'enc_class\' : \'%s\',\n", get_opcode_enc_class(i));
137 fprintf(out, "\t},\n");
139 fprintf(out, "};\n\n");
142 static void gen_tags_list(FILE *out)
144 int i;
146 fprintf(out, "tags = [\n");
147 for (i = 0; i < XX_LAST_OPCODE; i++) {
148 fprintf(out, "\t\'%s\',\n", opcode_names[i]);
150 fprintf(out, "];\n\n");
153 static void gen_enc_ext_spaces_table(FILE *out)
155 fprintf(out, "enc_ext_spaces = {\n");
156 #define DEF_EXT_SPACE(SPACEID, ENCSTR) \
157 fprintf(out, "\t\'%s\' : \'%s\',\n", #SPACEID, ENCSTR);
158 #include "imported/encode.def"
159 #undef DEF_EXT_SPACE
160 fprintf(out, "};\n\n");
163 static void gen_subinsn_groupings_table(FILE *out)
165 fprintf(out, "subinsn_groupings = {\n");
166 #define DEF_PACKED32(TAG, TYPEA, TYPEB, ENCSTR) \
167 do { \
168 fprintf(out, "\t\'%s\' : {\n", #TAG); \
169 fprintf(out, "\t\t\'name\' : \'%s\',\n", #TAG); \
170 fprintf(out, "\t\t\'class_a\' : \'%s\',\n", #TYPEA); \
171 fprintf(out, "\t\t\'class_b\' : \'%s\',\n", #TYPEB); \
172 fprintf(out, "\t\t\'enc\' : \'%s\',\n", ENCSTR); \
173 fprintf(out, "\t},\n"); \
174 } while (0);
175 #include "imported/encode.def"
176 #undef DEF_PACKED32
177 fprintf(out, "};\n\n");
180 int main(int argc, char *argv[])
182 FILE *outfile;
184 if (argc != 2) {
185 fprintf(stderr, "Usage: gen_dectree_import ouptputfile\n");
186 return 1;
188 outfile = fopen(argv[1], "w");
189 if (outfile == NULL) {
190 fprintf(stderr, "Cannot open %s for writing\n", argv[1]);
191 return 1;
194 gen_iset_table(outfile);
195 gen_tags_list(outfile);
196 gen_enc_ext_spaces_table(outfile);
197 gen_subinsn_groupings_table(outfile);
199 fclose(outfile);
200 return 0;