2 * UniCore32 virtual CPU header
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
12 #ifndef UNICORE32_CPU_H
13 #define UNICORE32_CPU_H
15 #define TARGET_LONG_BITS 32
16 #define TARGET_PAGE_BITS 12
18 #define TARGET_PHYS_ADDR_SPACE_BITS 32
19 #define TARGET_VIRT_ADDR_SPACE_BITS 32
21 #define CPUArchState struct CPUUniCore32State
23 #include "qemu-common.h"
25 #include "exec/cpu-defs.h"
26 #include "fpu/softfloat.h"
28 #define NB_MMU_MODES 2
30 typedef struct CPUUniCore32State
{
31 /* Regs for current mode. */
33 /* Frequently accessed ASR bits are stored separately for efficiently.
34 This contains all the other bits. Use asr_{read,write} to access
36 uint32_t uncached_asr
;
39 /* Banked registers. */
40 uint32_t banked_bsr
[6];
41 uint32_t banked_r29
[6];
42 uint32_t banked_r30
[6];
44 /* asr flag cache for faster execution */
45 uint32_t CF
; /* 0 or 1 */
46 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
47 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
48 uint32_t ZF
; /* Z set if zero. */
50 /* System control coprocessor (cp0) */
53 uint32_t c0_cachetype
;
54 uint32_t c1_sys
; /* System control register. */
55 uint32_t c2_base
; /* MMU translation table base. */
56 uint32_t c3_faultstatus
; /* Fault status registers. */
57 uint32_t c4_faultaddr
; /* Fault address registers. */
58 uint32_t c5_cacheop
; /* Cache operation registers. */
59 uint32_t c6_tlbop
; /* TLB operation registers. */
62 /* UniCore-F64 coprocessor state. */
66 float_status fp_status
;
71 /* Internal CPU feature flags. */
78 * @env: #CPUUniCore32State
87 CPUUniCore32State env
;
90 static inline UniCore32CPU
*uc32_env_get_cpu(CPUUniCore32State
*env
)
92 return container_of(env
, UniCore32CPU
, env
);
95 #define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
97 #define ENV_OFFSET offsetof(UniCore32CPU, env)
99 void uc32_cpu_do_interrupt(CPUState
*cpu
);
100 bool uc32_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
101 void uc32_cpu_dump_state(CPUState
*cpu
, FILE *f
,
102 fprintf_function cpu_fprintf
, int flags
);
103 hwaddr
uc32_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
106 #define ASR_MODE_USER (0x10)
107 #define ASR_MODE_INTR (0x12)
108 #define ASR_MODE_PRIV (0x13)
109 #define ASR_MODE_TRAP (0x17)
110 #define ASR_MODE_EXTN (0x1b)
111 #define ASR_MODE_SUSR (0x1f)
112 #define ASR_I (1 << 7)
113 #define ASR_V (1 << 28)
114 #define ASR_C (1 << 29)
115 #define ASR_Z (1 << 30)
116 #define ASR_N (1 << 31)
117 #define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
118 #define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
120 #define UC32_EXCP_PRIV (1)
121 #define UC32_EXCP_ITRAP (2)
122 #define UC32_EXCP_DTRAP (3)
123 #define UC32_EXCP_INTR (4)
125 /* Return the current ASR value. */
126 target_ulong
cpu_asr_read(CPUUniCore32State
*env1
);
127 /* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
128 void cpu_asr_write(CPUUniCore32State
*env1
, target_ulong val
, target_ulong mask
);
130 /* UniCore-F64 system registers. */
131 #define UC32_UCF64_FPSCR (31)
132 #define UCF64_FPSCR_MASK (0x27ffffff)
133 #define UCF64_FPSCR_RND_MASK (0x7)
134 #define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
135 #define UCF64_FPSCR_TRAPEN_MASK (0x7f)
136 #define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
137 #define UCF64_FPSCR_FLAG_MASK (0x3ff)
138 #define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
139 #define UCF64_FPSCR_FLAG_ZERO (1 << 17)
140 #define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
141 #define UCF64_FPSCR_FLAG_INVALID (1 << 19)
142 #define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
143 #define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
144 #define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
145 #define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
146 #define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
147 #define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
148 #define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
150 #define UC32_HWCAP_CMOV 4 /* 1 << 2 */
151 #define UC32_HWCAP_UCF64 8 /* 1 << 3 */
153 #define cpu_signal_handler uc32_cpu_signal_handler
155 int uc32_cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
);
157 /* MMU modes definitions */
158 #define MMU_MODE0_SUFFIX _kernel
159 #define MMU_MODE1_SUFFIX _user
160 #define MMU_USER_IDX 1
161 static inline int cpu_mmu_index(CPUUniCore32State
*env
, bool ifetch
)
163 return (env
->uncached_asr
& ASR_M
) == ASR_MODE_USER
? 1 : 0;
166 #include "exec/cpu-all.h"
168 UniCore32CPU
*uc32_cpu_init(const char *cpu_model
);
170 #define cpu_init(cpu_model) CPU(uc32_cpu_init(cpu_model))
172 static inline void cpu_get_tb_cpu_state(CPUUniCore32State
*env
, target_ulong
*pc
,
173 target_ulong
*cs_base
, uint32_t *flags
)
178 if ((env
->uncached_asr
& ASR_M
) != ASR_MODE_USER
) {
183 int uc32_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
185 void uc32_translate_init(void);
186 void switch_mode(CPUUniCore32State
*, int);
188 #endif /* UNICORE32_CPU_H */