tests: Use qpci_mem{read,write} in ivshmem-test
[qemu/rayw.git] / target-ppc / excp_helper.c
blob53c407576bfc21300ec8411496e9bf581aba3d85
1 /*
2 * PowerPC exception emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "exec/cpu_ldst.h"
25 #include "helper_regs.h"
27 //#define DEBUG_OP
28 //#define DEBUG_SOFTWARE_TLB
29 //#define DEBUG_EXCEPTIONS
31 #ifdef DEBUG_EXCEPTIONS
32 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
33 #else
34 # define LOG_EXCP(...) do { } while (0)
35 #endif
37 /*****************************************************************************/
38 /* PowerPC Hypercall emulation */
40 void (*cpu_ppc_hypercall)(PowerPCCPU *);
42 /*****************************************************************************/
43 /* Exception processing */
44 #if defined(CONFIG_USER_ONLY)
45 void ppc_cpu_do_interrupt(CPUState *cs)
47 PowerPCCPU *cpu = POWERPC_CPU(cs);
48 CPUPPCState *env = &cpu->env;
50 cs->exception_index = POWERPC_EXCP_NONE;
51 env->error_code = 0;
54 static void ppc_hw_interrupt(CPUPPCState *env)
56 CPUState *cs = CPU(ppc_env_get_cpu(env));
58 cs->exception_index = POWERPC_EXCP_NONE;
59 env->error_code = 0;
61 #else /* defined(CONFIG_USER_ONLY) */
62 static inline void dump_syscall(CPUPPCState *env)
64 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
65 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
66 " nip=" TARGET_FMT_lx "\n",
67 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
68 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
69 ppc_dump_gpr(env, 6), env->nip);
72 /* Note that this function should be greatly optimized
73 * when called with a constant excp, from ppc_hw_interrupt
75 static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
77 CPUState *cs = CPU(cpu);
78 CPUPPCState *env = &cpu->env;
79 target_ulong msr, new_msr, vector;
80 int srr0, srr1, asrr0, asrr1, lev, ail;
81 bool lpes0;
83 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
84 " => %08x (%02x)\n", env->nip, excp, env->error_code);
86 /* new srr1 value excluding must-be-zero bits */
87 if (excp_model == POWERPC_EXCP_BOOKE) {
88 msr = env->msr;
89 } else {
90 msr = env->msr & ~0x783f0000ULL;
93 /* new interrupt handler msr preserves existing HV and ME unless
94 * explicitly overriden
96 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
98 /* target registers */
99 srr0 = SPR_SRR0;
100 srr1 = SPR_SRR1;
101 asrr0 = -1;
102 asrr1 = -1;
104 /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */
105 if (env->in_pm_state) {
106 env->in_pm_state = false;
108 /* Pretend to be returning from doze always as we don't lose state */
109 msr |= (0x1ull << (63 - 47));
111 /* Non-machine check are routed to 0x100 with a wakeup cause
112 * encoded in SRR1
114 if (excp != POWERPC_EXCP_MCHECK) {
115 switch (excp) {
116 case POWERPC_EXCP_RESET:
117 msr |= 0x4ull << (63 - 45);
118 break;
119 case POWERPC_EXCP_EXTERNAL:
120 msr |= 0x8ull << (63 - 45);
121 break;
122 case POWERPC_EXCP_DECR:
123 msr |= 0x6ull << (63 - 45);
124 break;
125 case POWERPC_EXCP_SDOOR:
126 msr |= 0x5ull << (63 - 45);
127 break;
128 case POWERPC_EXCP_SDOOR_HV:
129 msr |= 0x3ull << (63 - 45);
130 break;
131 case POWERPC_EXCP_HV_MAINT:
132 msr |= 0xaull << (63 - 45);
133 break;
134 default:
135 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
136 excp);
138 excp = POWERPC_EXCP_RESET;
142 /* Exception targetting modifiers
144 * LPES0 is supported on POWER7/8
145 * LPES1 is not supported (old iSeries mode)
147 * On anything else, we behave as if LPES0 is 1
148 * (externals don't alter MSR:HV)
150 * AIL is initialized here but can be cleared by
151 * selected exceptions
153 #if defined(TARGET_PPC64)
154 if (excp_model == POWERPC_EXCP_POWER7 ||
155 excp_model == POWERPC_EXCP_POWER8) {
156 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
157 if (excp_model == POWERPC_EXCP_POWER8) {
158 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
159 } else {
160 ail = 0;
162 } else
163 #endif /* defined(TARGET_PPC64) */
165 lpes0 = true;
166 ail = 0;
169 /* Hypervisor emulation assistance interrupt only exists on server
170 * arch 2.05 server or later. We also don't want to generate it if
171 * we don't have HVB in msr_mask (PAPR mode).
173 if (excp == POWERPC_EXCP_HV_EMU
174 #if defined(TARGET_PPC64)
175 && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
176 #endif /* defined(TARGET_PPC64) */
179 excp = POWERPC_EXCP_PROGRAM;
182 switch (excp) {
183 case POWERPC_EXCP_NONE:
184 /* Should never happen */
185 return;
186 case POWERPC_EXCP_CRITICAL: /* Critical input */
187 switch (excp_model) {
188 case POWERPC_EXCP_40x:
189 srr0 = SPR_40x_SRR2;
190 srr1 = SPR_40x_SRR3;
191 break;
192 case POWERPC_EXCP_BOOKE:
193 srr0 = SPR_BOOKE_CSRR0;
194 srr1 = SPR_BOOKE_CSRR1;
195 break;
196 case POWERPC_EXCP_G2:
197 break;
198 default:
199 goto excp_invalid;
201 break;
202 case POWERPC_EXCP_MCHECK: /* Machine check exception */
203 if (msr_me == 0) {
204 /* Machine check exception is not enabled.
205 * Enter checkstop state.
207 fprintf(stderr, "Machine check while not allowed. "
208 "Entering checkstop state\n");
209 if (qemu_log_separate()) {
210 qemu_log("Machine check while not allowed. "
211 "Entering checkstop state\n");
213 cs->halted = 1;
214 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
216 new_msr |= (target_ulong)MSR_HVB;
217 ail = 0;
219 /* machine check exceptions don't have ME set */
220 new_msr &= ~((target_ulong)1 << MSR_ME);
222 /* XXX: should also have something loaded in DAR / DSISR */
223 switch (excp_model) {
224 case POWERPC_EXCP_40x:
225 srr0 = SPR_40x_SRR2;
226 srr1 = SPR_40x_SRR3;
227 break;
228 case POWERPC_EXCP_BOOKE:
229 /* FIXME: choose one or the other based on CPU type */
230 srr0 = SPR_BOOKE_MCSRR0;
231 srr1 = SPR_BOOKE_MCSRR1;
232 asrr0 = SPR_BOOKE_CSRR0;
233 asrr1 = SPR_BOOKE_CSRR1;
234 break;
235 default:
236 break;
238 break;
239 case POWERPC_EXCP_DSI: /* Data storage exception */
240 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
241 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
242 break;
243 case POWERPC_EXCP_ISI: /* Instruction storage exception */
244 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
245 "\n", msr, env->nip);
246 msr |= env->error_code;
247 break;
248 case POWERPC_EXCP_EXTERNAL: /* External input */
249 cs = CPU(cpu);
251 if (!lpes0) {
252 new_msr |= (target_ulong)MSR_HVB;
253 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
254 srr0 = SPR_HSRR0;
255 srr1 = SPR_HSRR1;
257 if (env->mpic_proxy) {
258 /* IACK the IRQ on delivery */
259 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
261 break;
262 case POWERPC_EXCP_ALIGN: /* Alignment exception */
263 /* Get rS/rD and rA from faulting opcode */
264 /* Note: the opcode fields will not be set properly for a direct
265 * store load/store, but nobody cares as nobody actually uses
266 * direct store segments.
268 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
269 break;
270 case POWERPC_EXCP_PROGRAM: /* Program exception */
271 switch (env->error_code & ~0xF) {
272 case POWERPC_EXCP_FP:
273 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
274 LOG_EXCP("Ignore floating point exception\n");
275 cs->exception_index = POWERPC_EXCP_NONE;
276 env->error_code = 0;
277 return;
280 /* FP exceptions always have NIP pointing to the faulting
281 * instruction, so always use store_next and claim we are
282 * precise in the MSR.
284 msr |= 0x00100000;
285 break;
286 case POWERPC_EXCP_INVAL:
287 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
288 msr |= 0x00080000;
289 env->spr[SPR_BOOKE_ESR] = ESR_PIL;
290 break;
291 case POWERPC_EXCP_PRIV:
292 msr |= 0x00040000;
293 env->spr[SPR_BOOKE_ESR] = ESR_PPR;
294 break;
295 case POWERPC_EXCP_TRAP:
296 msr |= 0x00020000;
297 env->spr[SPR_BOOKE_ESR] = ESR_PTR;
298 break;
299 default:
300 /* Should never occur */
301 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
302 env->error_code);
303 break;
305 break;
306 case POWERPC_EXCP_SYSCALL: /* System call exception */
307 dump_syscall(env);
308 lev = env->error_code;
310 /* We need to correct the NIP which in this case is supposed
311 * to point to the next instruction
313 env->nip += 4;
315 /* "PAPR mode" built-in hypercall emulation */
316 if ((lev == 1) && cpu_ppc_hypercall) {
317 cpu_ppc_hypercall(cpu);
318 return;
320 if (lev == 1) {
321 new_msr |= (target_ulong)MSR_HVB;
323 break;
324 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
325 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
326 case POWERPC_EXCP_DECR: /* Decrementer exception */
327 break;
328 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
329 /* FIT on 4xx */
330 LOG_EXCP("FIT exception\n");
331 break;
332 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
333 LOG_EXCP("WDT exception\n");
334 switch (excp_model) {
335 case POWERPC_EXCP_BOOKE:
336 srr0 = SPR_BOOKE_CSRR0;
337 srr1 = SPR_BOOKE_CSRR1;
338 break;
339 default:
340 break;
342 break;
343 case POWERPC_EXCP_DTLB: /* Data TLB error */
344 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
345 break;
346 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
347 switch (excp_model) {
348 case POWERPC_EXCP_BOOKE:
349 /* FIXME: choose one or the other based on CPU type */
350 srr0 = SPR_BOOKE_DSRR0;
351 srr1 = SPR_BOOKE_DSRR1;
352 asrr0 = SPR_BOOKE_CSRR0;
353 asrr1 = SPR_BOOKE_CSRR1;
354 break;
355 default:
356 break;
358 /* XXX: TODO */
359 cpu_abort(cs, "Debug exception is not implemented yet !\n");
360 break;
361 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
362 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
363 break;
364 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
365 /* XXX: TODO */
366 cpu_abort(cs, "Embedded floating point data exception "
367 "is not implemented yet !\n");
368 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
369 break;
370 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
371 /* XXX: TODO */
372 cpu_abort(cs, "Embedded floating point round exception "
373 "is not implemented yet !\n");
374 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
375 break;
376 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
377 /* XXX: TODO */
378 cpu_abort(cs,
379 "Performance counter exception is not implemented yet !\n");
380 break;
381 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
382 break;
383 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
384 srr0 = SPR_BOOKE_CSRR0;
385 srr1 = SPR_BOOKE_CSRR1;
386 break;
387 case POWERPC_EXCP_RESET: /* System reset exception */
388 /* A power-saving exception sets ME, otherwise it is unchanged */
389 if (msr_pow) {
390 /* indicate that we resumed from power save mode */
391 msr |= 0x10000;
392 new_msr |= ((target_ulong)1 << MSR_ME);
395 new_msr |= (target_ulong)MSR_HVB;
396 ail = 0;
397 break;
398 case POWERPC_EXCP_DSEG: /* Data segment exception */
399 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
400 case POWERPC_EXCP_TRACE: /* Trace exception */
401 break;
402 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
403 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
404 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
405 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
406 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
407 case POWERPC_EXCP_HV_EMU:
408 srr0 = SPR_HSRR0;
409 srr1 = SPR_HSRR1;
410 new_msr |= (target_ulong)MSR_HVB;
411 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
412 break;
413 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
414 case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
415 case POWERPC_EXCP_FU: /* Facility unavailable exception */
416 break;
417 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
418 LOG_EXCP("PIT exception\n");
419 break;
420 case POWERPC_EXCP_IO: /* IO error exception */
421 /* XXX: TODO */
422 cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
423 break;
424 case POWERPC_EXCP_RUNM: /* Run mode exception */
425 /* XXX: TODO */
426 cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
427 break;
428 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
429 /* XXX: TODO */
430 cpu_abort(cs, "602 emulation trap exception "
431 "is not implemented yet !\n");
432 break;
433 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
434 switch (excp_model) {
435 case POWERPC_EXCP_602:
436 case POWERPC_EXCP_603:
437 case POWERPC_EXCP_603E:
438 case POWERPC_EXCP_G2:
439 goto tlb_miss_tgpr;
440 case POWERPC_EXCP_7x5:
441 goto tlb_miss;
442 case POWERPC_EXCP_74xx:
443 goto tlb_miss_74xx;
444 default:
445 cpu_abort(cs, "Invalid instruction TLB miss exception\n");
446 break;
448 break;
449 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
450 switch (excp_model) {
451 case POWERPC_EXCP_602:
452 case POWERPC_EXCP_603:
453 case POWERPC_EXCP_603E:
454 case POWERPC_EXCP_G2:
455 goto tlb_miss_tgpr;
456 case POWERPC_EXCP_7x5:
457 goto tlb_miss;
458 case POWERPC_EXCP_74xx:
459 goto tlb_miss_74xx;
460 default:
461 cpu_abort(cs, "Invalid data load TLB miss exception\n");
462 break;
464 break;
465 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
466 switch (excp_model) {
467 case POWERPC_EXCP_602:
468 case POWERPC_EXCP_603:
469 case POWERPC_EXCP_603E:
470 case POWERPC_EXCP_G2:
471 tlb_miss_tgpr:
472 /* Swap temporary saved registers with GPRs */
473 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
474 new_msr |= (target_ulong)1 << MSR_TGPR;
475 hreg_swap_gpr_tgpr(env);
477 goto tlb_miss;
478 case POWERPC_EXCP_7x5:
479 tlb_miss:
480 #if defined(DEBUG_SOFTWARE_TLB)
481 if (qemu_log_enabled()) {
482 const char *es;
483 target_ulong *miss, *cmp;
484 int en;
486 if (excp == POWERPC_EXCP_IFTLB) {
487 es = "I";
488 en = 'I';
489 miss = &env->spr[SPR_IMISS];
490 cmp = &env->spr[SPR_ICMP];
491 } else {
492 if (excp == POWERPC_EXCP_DLTLB) {
493 es = "DL";
494 } else {
495 es = "DS";
497 en = 'D';
498 miss = &env->spr[SPR_DMISS];
499 cmp = &env->spr[SPR_DCMP];
501 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
502 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
503 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
504 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
505 env->error_code);
507 #endif
508 msr |= env->crf[0] << 28;
509 msr |= env->error_code; /* key, D/I, S/L bits */
510 /* Set way using a LRU mechanism */
511 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
512 break;
513 case POWERPC_EXCP_74xx:
514 tlb_miss_74xx:
515 #if defined(DEBUG_SOFTWARE_TLB)
516 if (qemu_log_enabled()) {
517 const char *es;
518 target_ulong *miss, *cmp;
519 int en;
521 if (excp == POWERPC_EXCP_IFTLB) {
522 es = "I";
523 en = 'I';
524 miss = &env->spr[SPR_TLBMISS];
525 cmp = &env->spr[SPR_PTEHI];
526 } else {
527 if (excp == POWERPC_EXCP_DLTLB) {
528 es = "DL";
529 } else {
530 es = "DS";
532 en = 'D';
533 miss = &env->spr[SPR_TLBMISS];
534 cmp = &env->spr[SPR_PTEHI];
536 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
537 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
538 env->error_code);
540 #endif
541 msr |= env->error_code; /* key bit */
542 break;
543 default:
544 cpu_abort(cs, "Invalid data store TLB miss exception\n");
545 break;
547 break;
548 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
549 /* XXX: TODO */
550 cpu_abort(cs, "Floating point assist exception "
551 "is not implemented yet !\n");
552 break;
553 case POWERPC_EXCP_DABR: /* Data address breakpoint */
554 /* XXX: TODO */
555 cpu_abort(cs, "DABR exception is not implemented yet !\n");
556 break;
557 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
558 /* XXX: TODO */
559 cpu_abort(cs, "IABR exception is not implemented yet !\n");
560 break;
561 case POWERPC_EXCP_SMI: /* System management interrupt */
562 /* XXX: TODO */
563 cpu_abort(cs, "SMI exception is not implemented yet !\n");
564 break;
565 case POWERPC_EXCP_THERM: /* Thermal interrupt */
566 /* XXX: TODO */
567 cpu_abort(cs, "Thermal management exception "
568 "is not implemented yet !\n");
569 break;
570 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
571 /* XXX: TODO */
572 cpu_abort(cs,
573 "Performance counter exception is not implemented yet !\n");
574 break;
575 case POWERPC_EXCP_VPUA: /* Vector assist exception */
576 /* XXX: TODO */
577 cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
578 break;
579 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
580 /* XXX: TODO */
581 cpu_abort(cs,
582 "970 soft-patch exception is not implemented yet !\n");
583 break;
584 case POWERPC_EXCP_MAINT: /* Maintenance exception */
585 /* XXX: TODO */
586 cpu_abort(cs,
587 "970 maintenance exception is not implemented yet !\n");
588 break;
589 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
590 /* XXX: TODO */
591 cpu_abort(cs, "Maskable external exception "
592 "is not implemented yet !\n");
593 break;
594 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
595 /* XXX: TODO */
596 cpu_abort(cs, "Non maskable external exception "
597 "is not implemented yet !\n");
598 break;
599 default:
600 excp_invalid:
601 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
602 break;
605 /* Save PC */
606 env->spr[srr0] = env->nip;
608 /* Save MSR */
609 env->spr[srr1] = msr;
611 /* Sanity check */
612 if (!(env->msr_mask & MSR_HVB) && (srr0 == SPR_HSRR0)) {
613 cpu_abort(cs, "Trying to deliver HV exception %d with "
614 "no HV support\n", excp);
617 /* If any alternate SRR register are defined, duplicate saved values */
618 if (asrr0 != -1) {
619 env->spr[asrr0] = env->spr[srr0];
621 if (asrr1 != -1) {
622 env->spr[asrr1] = env->spr[srr1];
625 /* Sort out endianness of interrupt, this differs depending on the
626 * CPU, the HV mode, etc...
628 #ifdef TARGET_PPC64
629 if (excp_model == POWERPC_EXCP_POWER7) {
630 if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
631 new_msr |= (target_ulong)1 << MSR_LE;
633 } else if (excp_model == POWERPC_EXCP_POWER8) {
634 if (new_msr & MSR_HVB) {
635 if (env->spr[SPR_HID0] & HID0_HILE) {
636 new_msr |= (target_ulong)1 << MSR_LE;
638 } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
639 new_msr |= (target_ulong)1 << MSR_LE;
641 } else if (msr_ile) {
642 new_msr |= (target_ulong)1 << MSR_LE;
644 #else
645 if (msr_ile) {
646 new_msr |= (target_ulong)1 << MSR_LE;
648 #endif
650 /* Jump to handler */
651 vector = env->excp_vectors[excp];
652 if (vector == (target_ulong)-1ULL) {
653 cpu_abort(cs, "Raised an exception without defined vector %d\n",
654 excp);
656 vector |= env->excp_prefix;
658 /* AIL only works if there is no HV transition and we are running with
659 * translations enabled
661 if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
662 ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
663 ail = 0;
665 /* Handle AIL */
666 if (ail) {
667 new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
668 switch(ail) {
669 case AIL_0001_8000:
670 vector |= 0x18000;
671 break;
672 case AIL_C000_0000_0000_4000:
673 vector |= 0xc000000000004000ull;
674 break;
675 default:
676 cpu_abort(cs, "Invalid AIL combination %d\n", ail);
677 break;
681 #if defined(TARGET_PPC64)
682 if (excp_model == POWERPC_EXCP_BOOKE) {
683 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
684 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
685 new_msr |= (target_ulong)1 << MSR_CM;
686 } else {
687 vector = (uint32_t)vector;
689 } else {
690 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
691 vector = (uint32_t)vector;
692 } else {
693 new_msr |= (target_ulong)1 << MSR_SF;
696 #endif
697 /* We don't use hreg_store_msr here as already have treated
698 * any special case that could occur. Just store MSR and update hflags
700 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
701 * will prevent setting of the HV bit which some exceptions might need
702 * to do.
704 env->msr = new_msr & env->msr_mask;
705 hreg_compute_hflags(env);
706 env->nip = vector;
707 /* Reset exception state */
708 cs->exception_index = POWERPC_EXCP_NONE;
709 env->error_code = 0;
711 /* Any interrupt is context synchronizing, check if TCG TLB
712 * needs a delayed flush on ppc64
714 check_tlb_flush(env, false);
717 void ppc_cpu_do_interrupt(CPUState *cs)
719 PowerPCCPU *cpu = POWERPC_CPU(cs);
720 CPUPPCState *env = &cpu->env;
722 powerpc_excp(cpu, env->excp_model, cs->exception_index);
725 static void ppc_hw_interrupt(CPUPPCState *env)
727 PowerPCCPU *cpu = ppc_env_get_cpu(env);
728 #if 0
729 CPUState *cs = CPU(cpu);
731 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
732 __func__, env, env->pending_interrupts,
733 cs->interrupt_request, (int)msr_me, (int)msr_ee);
734 #endif
735 /* External reset */
736 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
737 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
738 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
739 return;
741 /* Machine check exception */
742 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
743 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
744 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
745 return;
747 #if 0 /* TODO */
748 /* External debug exception */
749 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
750 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
751 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
752 return;
754 #endif
755 /* Hypervisor decrementer exception */
756 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
757 /* LPCR will be clear when not supported so this will work */
758 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
759 if ((msr_ee != 0 || msr_hv == 0) && hdice) {
760 /* HDEC clears on delivery */
761 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
762 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
763 return;
766 /* Extermal interrupt can ignore MSR:EE under some circumstances */
767 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
768 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
769 if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
770 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
771 return;
774 if (msr_ce != 0) {
775 /* External critical interrupt */
776 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
777 /* Taking a critical external interrupt does not clear the external
778 * critical interrupt status
780 #if 0
781 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
782 #endif
783 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
784 return;
787 if (msr_ee != 0) {
788 /* Watchdog timer on embedded PowerPC */
789 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
790 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
791 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
792 return;
794 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
795 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
796 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
797 return;
799 /* Fixed interval timer on embedded PowerPC */
800 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
801 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
802 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
803 return;
805 /* Programmable interval timer on embedded PowerPC */
806 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
807 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
808 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
809 return;
811 /* Decrementer exception */
812 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
813 if (ppc_decr_clear_on_delivery(env)) {
814 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
816 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
817 return;
819 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
820 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
821 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
822 return;
824 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
825 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
826 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
827 return;
829 /* Thermal interrupt */
830 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
831 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
832 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
833 return;
838 void ppc_cpu_do_system_reset(CPUState *cs)
840 PowerPCCPU *cpu = POWERPC_CPU(cs);
841 CPUPPCState *env = &cpu->env;
843 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
845 #endif /* !CONFIG_USER_ONLY */
847 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
849 PowerPCCPU *cpu = POWERPC_CPU(cs);
850 CPUPPCState *env = &cpu->env;
852 if (interrupt_request & CPU_INTERRUPT_HARD) {
853 ppc_hw_interrupt(env);
854 if (env->pending_interrupts == 0) {
855 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
857 return true;
859 return false;
862 #if defined(DEBUG_OP)
863 static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
865 qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
866 TARGET_FMT_lx "\n", RA, msr);
868 #endif
870 /*****************************************************************************/
871 /* Exceptions processing helpers */
873 void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
874 uint32_t error_code, uintptr_t raddr)
876 CPUState *cs = CPU(ppc_env_get_cpu(env));
878 cs->exception_index = exception;
879 env->error_code = error_code;
880 cpu_loop_exit_restore(cs, raddr);
883 void raise_exception_err(CPUPPCState *env, uint32_t exception,
884 uint32_t error_code)
886 raise_exception_err_ra(env, exception, error_code, 0);
889 void raise_exception(CPUPPCState *env, uint32_t exception)
891 raise_exception_err_ra(env, exception, 0, 0);
894 void raise_exception_ra(CPUPPCState *env, uint32_t exception,
895 uintptr_t raddr)
897 raise_exception_err_ra(env, exception, 0, raddr);
900 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
901 uint32_t error_code)
903 raise_exception_err_ra(env, exception, error_code, 0);
906 void helper_raise_exception(CPUPPCState *env, uint32_t exception)
908 raise_exception_err_ra(env, exception, 0, 0);
911 #if !defined(CONFIG_USER_ONLY)
912 void helper_store_msr(CPUPPCState *env, target_ulong val)
914 uint32_t excp = hreg_store_msr(env, val, 0);
916 if (excp != 0) {
917 CPUState *cs = CPU(ppc_env_get_cpu(env));
918 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
919 raise_exception(env, excp);
923 #if defined(TARGET_PPC64)
924 void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
926 CPUState *cs;
928 cs = CPU(ppc_env_get_cpu(env));
929 cs->halted = 1;
930 env->in_pm_state = true;
932 /* The architecture specifies that HDEC interrupts are
933 * discarded in PM states
935 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
937 /* Technically, nap doesn't set EE, but if we don't set it
938 * then ppc_hw_interrupt() won't deliver. We could add some
939 * other tests there based on LPCR but it's simpler to just
940 * whack EE in. It will be cleared by the 0x100 at wakeup
941 * anyway. It will still be observable by the guest in SRR1
942 * but this doesn't seem to be a problem.
944 env->msr |= (1ull << MSR_EE);
945 raise_exception(env, EXCP_HLT);
947 #endif /* defined(TARGET_PPC64) */
949 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
951 CPUState *cs = CPU(ppc_env_get_cpu(env));
953 /* MSR:POW cannot be set by any form of rfi */
954 msr &= ~(1ULL << MSR_POW);
956 #if defined(TARGET_PPC64)
957 /* Switching to 32-bit ? Crop the nip */
958 if (!msr_is_64bit(env, msr)) {
959 nip = (uint32_t)nip;
961 #else
962 nip = (uint32_t)nip;
963 #endif
964 /* XXX: beware: this is false if VLE is supported */
965 env->nip = nip & ~((target_ulong)0x00000003);
966 hreg_store_msr(env, msr, 1);
967 #if defined(DEBUG_OP)
968 cpu_dump_rfi(env->nip, env->msr);
969 #endif
970 /* No need to raise an exception here,
971 * as rfi is always the last insn of a TB
973 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
975 /* Context synchronizing: check if TCG TLB needs flush */
976 check_tlb_flush(env, false);
979 void helper_rfi(CPUPPCState *env)
981 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
984 #define MSR_BOOK3S_MASK
985 #if defined(TARGET_PPC64)
986 void helper_rfid(CPUPPCState *env)
988 /* The architeture defines a number of rules for which bits
989 * can change but in practice, we handle this in hreg_store_msr()
990 * which will be called by do_rfi(), so there is no need to filter
991 * here
993 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
996 void helper_hrfid(CPUPPCState *env)
998 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
1000 #endif
1002 /*****************************************************************************/
1003 /* Embedded PowerPC specific helpers */
1004 void helper_40x_rfci(CPUPPCState *env)
1006 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
1009 void helper_rfci(CPUPPCState *env)
1011 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
1014 void helper_rfdi(CPUPPCState *env)
1016 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
1017 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
1020 void helper_rfmci(CPUPPCState *env)
1022 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
1023 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
1025 #endif
1027 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1028 uint32_t flags)
1030 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1031 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1032 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1033 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1034 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1035 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
1036 POWERPC_EXCP_TRAP, GETPC());
1040 #if defined(TARGET_PPC64)
1041 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1042 uint32_t flags)
1044 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1045 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1046 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1047 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1048 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
1049 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
1050 POWERPC_EXCP_TRAP, GETPC());
1053 #endif
1055 #if !defined(CONFIG_USER_ONLY)
1056 /*****************************************************************************/
1057 /* PowerPC 601 specific instructions (POWER bridge) */
1059 void helper_rfsvc(CPUPPCState *env)
1061 do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
1064 /* Embedded.Processor Control */
1065 static int dbell2irq(target_ulong rb)
1067 int msg = rb & DBELL_TYPE_MASK;
1068 int irq = -1;
1070 switch (msg) {
1071 case DBELL_TYPE_DBELL:
1072 irq = PPC_INTERRUPT_DOORBELL;
1073 break;
1074 case DBELL_TYPE_DBELL_CRIT:
1075 irq = PPC_INTERRUPT_CDOORBELL;
1076 break;
1077 case DBELL_TYPE_G_DBELL:
1078 case DBELL_TYPE_G_DBELL_CRIT:
1079 case DBELL_TYPE_G_DBELL_MC:
1080 /* XXX implement */
1081 default:
1082 break;
1085 return irq;
1088 void helper_msgclr(CPUPPCState *env, target_ulong rb)
1090 int irq = dbell2irq(rb);
1092 if (irq < 0) {
1093 return;
1096 env->pending_interrupts &= ~(1 << irq);
1099 void helper_msgsnd(target_ulong rb)
1101 int irq = dbell2irq(rb);
1102 int pir = rb & DBELL_PIRTAG_MASK;
1103 CPUState *cs;
1105 if (irq < 0) {
1106 return;
1109 CPU_FOREACH(cs) {
1110 PowerPCCPU *cpu = POWERPC_CPU(cs);
1111 CPUPPCState *cenv = &cpu->env;
1113 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
1114 cenv->pending_interrupts |= 1 << irq;
1115 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1119 #endif