target-i386/smm_helper.c

   1 /*
   2  *  x86 SMM helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/log.h"
  24
  25 /* SMM support */
  26
  27 #if defined(CONFIG_USER_ONLY)
  28
  29 void do_smm_enter(X86CPU *cpu)
  30 {
  31 }
  32
  33 void helper_rsm(CPUX86State *env)
  34 {
  35 }
  36
  37 #else
  38
  39 #ifdef TARGET_X86_64
  40 #define SMM_REVISION_ID 0x00020064
  41 #else
  42 #define SMM_REVISION_ID 0x00020000
  43 #endif
  44
  45 void cpu_smm_update(X86CPU *cpu)
  46 {
  47     CPUX86State *env = &cpu->env;
  48     bool smm_enabled = (env->hflags & HF_SMM_MASK);
  49
  50     if (cpu->smram) {
  51         memory_region_set_enabled(cpu->smram, smm_enabled);
  52     }
  53 }
  54
  55 void do_smm_enter(X86CPU *cpu)
  56 {
  57     CPUX86State *env = &cpu->env;
  58     CPUState *cs = CPU(cpu);
  59     target_ulong sm_state;
  60     SegmentCache *dt;
  61     int i, offset;
  62
  63     qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
  64     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
  65
  66     env->hflags |= HF_SMM_MASK;
  67     if (env->hflags2 & HF2_NMI_MASK) {
  68         env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
  69     } else {
  70         env->hflags2 |= HF2_NMI_MASK;
  71     }
  72     cpu_smm_update(cpu);
  73
  74     sm_state = env->smbase + 0x8000;
  75
  76 #ifdef TARGET_X86_64
  77     for (i = 0; i < 6; i++) {
  78         dt = &env->segs[i];
  79         offset = 0x7e00 + i * 16;
  80         x86_stw_phys(cs, sm_state + offset, dt->selector);
  81         x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
  82         x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
  83         x86_stq_phys(cs, sm_state + offset + 8, dt->base);
  84     }
  85
  86     x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
  87     x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
  88
  89     x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
  90     x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
  91     x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
  92     x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
  93
  94     x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
  95     x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
  96
  97     x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
  98     x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
  99     x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
 100     x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
 101
 102     /* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
 103        is saved at offset 7ED0.  Vol 3, 34.4.1.1, Table 32-2, has
 104        7EA0-7ED7 as "reserved".  What's this, and what's really
 105        supposed to happen?  */
 106     x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
 107
 108     x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
 109     x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
 110     x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
 111     x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
 112     x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
 113     x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
 114     x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
 115     x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
 116     for (i = 8; i < 16; i++) {
 117         x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
 118     }
 119     x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
 120     x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
 121     x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
 122     x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
 123
 124     x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
 125     x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
 126     x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
 127
 128     x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 129     x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
 130 #else
 131     x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
 132     x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
 133     x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
 134     x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
 135     x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
 136     x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
 137     x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
 138     x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
 139     x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
 140     x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
 141     x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
 142     x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
 143     x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
 144     x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
 145
 146     x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
 147     x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
 148     x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
 149     x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
 150
 151     x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
 152     x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
 153     x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
 154     x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
 155
 156     x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
 157     x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
 158
 159     x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
 160     x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
 161
 162     for (i = 0; i < 6; i++) {
 163         dt = &env->segs[i];
 164         if (i < 3) {
 165             offset = 0x7f84 + i * 12;
 166         } else {
 167             offset = 0x7f2c + (i - 3) * 12;
 168         }
 169         x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
 170         x86_stl_phys(cs, sm_state + offset + 8, dt->base);
 171         x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
 172         x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
 173     }
 174     x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
 175
 176     x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 177     x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
 178 #endif
 179     /* init SMM cpu state */
 180
 181 #ifdef TARGET_X86_64
 182     cpu_load_efer(env, 0);
 183 #endif
 184     cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
 185                               DF_MASK));
 186     env->eip = 0x00008000;
 187     cpu_x86_update_cr0(env,
 188                        env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
 189                                       CR0_PG_MASK));
 190     cpu_x86_update_cr4(env, 0);
 191     env->dr[7] = 0x00000400;
 192
 193     cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
 194                            0xffffffff,
 195                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 196                            DESC_G_MASK | DESC_A_MASK);
 197     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
 198                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 199                            DESC_G_MASK | DESC_A_MASK);
 200     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
 201                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 202                            DESC_G_MASK | DESC_A_MASK);
 203     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
 204                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 205                            DESC_G_MASK | DESC_A_MASK);
 206     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
 207                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 208                            DESC_G_MASK | DESC_A_MASK);
 209     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
 210                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 211                            DESC_G_MASK | DESC_A_MASK);
 212 }
 213
 214 void helper_rsm(CPUX86State *env)
 215 {
 216     X86CPU *cpu = x86_env_get_cpu(env);
 217     CPUState *cs = CPU(cpu);
 218     target_ulong sm_state;
 219     int i, offset;
 220     uint32_t val;
 221
 222     sm_state = env->smbase + 0x8000;
 223 #ifdef TARGET_X86_64
 224     cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
 225
 226     env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
 227     env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
 228
 229     env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
 230     env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
 231     env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
 232     env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
 233
 234     env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
 235     env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
 236
 237     env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
 238     env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
 239     env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
 240     env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
 241
 242     env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
 243     env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
 244     env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
 245     env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
 246     env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
 247     env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
 248     env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
 249     env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
 250     for (i = 8; i < 16; i++) {
 251         env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
 252     }
 253     env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
 254     cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
 255                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 256     env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
 257     env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
 258
 259     cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
 260     cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
 261     cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
 262
 263     for (i = 0; i < 6; i++) {
 264         offset = 0x7e00 + i * 16;
 265         cpu_x86_load_seg_cache(env, i,
 266                                x86_lduw_phys(cs, sm_state + offset),
 267                                x86_ldq_phys(cs, sm_state + offset + 8),
 268                                x86_ldl_phys(cs, sm_state + offset + 4),
 269                                (x86_lduw_phys(cs, sm_state + offset + 2) &
 270                                 0xf0ff) << 8);
 271     }
 272
 273     val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 274     if (val & 0x20000) {
 275         env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
 276     }
 277 #else
 278     cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
 279     cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
 280     cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
 281                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 282     env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
 283     env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
 284     env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
 285     env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
 286     env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
 287     env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
 288     env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
 289     env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
 290     env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
 291     env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
 292     env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
 293
 294     env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
 295     env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
 296     env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
 297     env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
 298
 299     env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
 300     env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
 301     env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
 302     env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
 303
 304     env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
 305     env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
 306
 307     env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
 308     env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
 309
 310     for (i = 0; i < 6; i++) {
 311         if (i < 3) {
 312             offset = 0x7f84 + i * 12;
 313         } else {
 314             offset = 0x7f2c + (i - 3) * 12;
 315         }
 316         cpu_x86_load_seg_cache(env, i,
 317                                x86_ldl_phys(cs,
 318                                         sm_state + 0x7fa8 + i * 4) & 0xffff,
 319                                x86_ldl_phys(cs, sm_state + offset + 8),
 320                                x86_ldl_phys(cs, sm_state + offset + 4),
 321                                (x86_ldl_phys(cs,
 322                                          sm_state + offset) & 0xf0ff) << 8);
 323     }
 324     cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
 325
 326     val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 327     if (val & 0x20000) {
 328         env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
 329     }
 330 #endif
 331     if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
 332         env->hflags2 &= ~HF2_NMI_MASK;
 333     }
 334     env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
 335     env->hflags &= ~HF_SMM_MASK;
 336     cpu_smm_update(cpu);
 337
 338     qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
 339     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
 340 }
 341
 342 #endif /* !CONFIG_USER_ONLY */