hw/arm_sysctl.c

   1 /*
   2  * Status and system control registers for ARM RealView/Versatile boards.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw.h"
  11 #include "qemu/timer.h"
  12 #include "sysbus.h"
  13 #include "primecell.h"
  14 #include "sysemu/sysemu.h"
  15
  16 #define LOCK_VALUE 0xa05f
  17
  18 typedef struct {
  19     SysBusDevice busdev;
  20     MemoryRegion iomem;
  21     qemu_irq pl110_mux_ctrl;
  22
  23     uint32_t sys_id;
  24     uint32_t leds;
  25     uint16_t lockval;
  26     uint32_t cfgdata1;
  27     uint32_t cfgdata2;
  28     uint32_t flags;
  29     uint32_t nvflags;
  30     uint32_t resetlevel;
  31     uint32_t proc_id;
  32     uint32_t sys_mci;
  33     uint32_t sys_cfgdata;
  34     uint32_t sys_cfgctrl;
  35     uint32_t sys_cfgstat;
  36     uint32_t sys_clcd;
  37 } arm_sysctl_state;
  38
  39 static const VMStateDescription vmstate_arm_sysctl = {
  40     .name = "realview_sysctl",
  41     .version_id = 3,
  42     .minimum_version_id = 1,
  43     .fields = (VMStateField[]) {
  44         VMSTATE_UINT32(leds, arm_sysctl_state),
  45         VMSTATE_UINT16(lockval, arm_sysctl_state),
  46         VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
  47         VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
  48         VMSTATE_UINT32(flags, arm_sysctl_state),
  49         VMSTATE_UINT32(nvflags, arm_sysctl_state),
  50         VMSTATE_UINT32(resetlevel, arm_sysctl_state),
  51         VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
  52         VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
  53         VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
  54         VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
  55         VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
  56         VMSTATE_END_OF_LIST()
  57     }
  58 };
  59
  60 /* The PB926 actually uses a different format for
  61  * its SYS_ID register. Fortunately the bits which are
  62  * board type on later boards are distinct.
  63  */
  64 #define BOARD_ID_PB926 0x100
  65 #define BOARD_ID_EB 0x140
  66 #define BOARD_ID_PBA8 0x178
  67 #define BOARD_ID_PBX 0x182
  68 #define BOARD_ID_VEXPRESS 0x190
  69
  70 static int board_id(arm_sysctl_state *s)
  71 {
  72     /* Extract the board ID field from the SYS_ID register value */
  73     return (s->sys_id >> 16) & 0xfff;
  74 }
  75
  76 static void arm_sysctl_reset(DeviceState *d)
  77 {
  78     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
  79
  80     s->leds = 0;
  81     s->lockval = 0;
  82     s->cfgdata1 = 0;
  83     s->cfgdata2 = 0;
  84     s->flags = 0;
  85     s->resetlevel = 0;
  86     if (board_id(s) == BOARD_ID_VEXPRESS) {
  87         /* On VExpress this register will RAZ/WI */
  88         s->sys_clcd = 0;
  89     } else {
  90         /* All others: CLCDID 0x1f, indicating VGA */
  91         s->sys_clcd = 0x1f00;
  92     }
  93 }
  94
  95 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
  96                                 unsigned size)
  97 {
  98     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
  99
 100     switch (offset) {
 101     case 0x00: /* ID */
 102         return s->sys_id;
 103     case 0x04: /* SW */
 104         /* General purpose hardware switches.
 105            We don't have a useful way of exposing these to the user.  */
 106         return 0;
 107     case 0x08: /* LED */
 108         return s->leds;
 109     case 0x20: /* LOCK */
 110         return s->lockval;
 111     case 0x0c: /* OSC0 */
 112     case 0x10: /* OSC1 */
 113     case 0x14: /* OSC2 */
 114     case 0x18: /* OSC3 */
 115     case 0x1c: /* OSC4 */
 116     case 0x24: /* 100HZ */
 117         /* ??? Implement these.  */
 118         return 0;
 119     case 0x28: /* CFGDATA1 */
 120         return s->cfgdata1;
 121     case 0x2c: /* CFGDATA2 */
 122         return s->cfgdata2;
 123     case 0x30: /* FLAGS */
 124         return s->flags;
 125     case 0x38: /* NVFLAGS */
 126         return s->nvflags;
 127     case 0x40: /* RESETCTL */
 128         if (board_id(s) == BOARD_ID_VEXPRESS) {
 129             /* reserved: RAZ/WI */
 130             return 0;
 131         }
 132         return s->resetlevel;
 133     case 0x44: /* PCICTL */
 134         return 1;
 135     case 0x48: /* MCI */
 136         return s->sys_mci;
 137     case 0x4c: /* FLASH */
 138         return 0;
 139     case 0x50: /* CLCD */
 140         return s->sys_clcd;
 141     case 0x54: /* CLCDSER */
 142         return 0;
 143     case 0x58: /* BOOTCS */
 144         return 0;
 145     case 0x5c: /* 24MHz */
 146         return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
 147     case 0x60: /* MISC */
 148         return 0;
 149     case 0x84: /* PROCID0 */
 150         return s->proc_id;
 151     case 0x88: /* PROCID1 */
 152         return 0xff000000;
 153     case 0x64: /* DMAPSR0 */
 154     case 0x68: /* DMAPSR1 */
 155     case 0x6c: /* DMAPSR2 */
 156     case 0x70: /* IOSEL */
 157     case 0x74: /* PLDCTL */
 158     case 0x80: /* BUSID */
 159     case 0x8c: /* OSCRESET0 */
 160     case 0x90: /* OSCRESET1 */
 161     case 0x94: /* OSCRESET2 */
 162     case 0x98: /* OSCRESET3 */
 163     case 0x9c: /* OSCRESET4 */
 164     case 0xc0: /* SYS_TEST_OSC0 */
 165     case 0xc4: /* SYS_TEST_OSC1 */
 166     case 0xc8: /* SYS_TEST_OSC2 */
 167     case 0xcc: /* SYS_TEST_OSC3 */
 168     case 0xd0: /* SYS_TEST_OSC4 */
 169         return 0;
 170     case 0xa0: /* SYS_CFGDATA */
 171         if (board_id(s) != BOARD_ID_VEXPRESS) {
 172             goto bad_reg;
 173         }
 174         return s->sys_cfgdata;
 175     case 0xa4: /* SYS_CFGCTRL */
 176         if (board_id(s) != BOARD_ID_VEXPRESS) {
 177             goto bad_reg;
 178         }
 179         return s->sys_cfgctrl;
 180     case 0xa8: /* SYS_CFGSTAT */
 181         if (board_id(s) != BOARD_ID_VEXPRESS) {
 182             goto bad_reg;
 183         }
 184         return s->sys_cfgstat;
 185     default:
 186     bad_reg:
 187         qemu_log_mask(LOG_GUEST_ERROR,
 188                       "arm_sysctl_read: Bad register offset 0x%x\n",
 189                       (int)offset);
 190         return 0;
 191     }
 192 }
 193
 194 static void arm_sysctl_write(void *opaque, hwaddr offset,
 195                              uint64_t val, unsigned size)
 196 {
 197     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 198
 199     switch (offset) {
 200     case 0x08: /* LED */
 201         s->leds = val;
 202         break;
 203     case 0x0c: /* OSC0 */
 204     case 0x10: /* OSC1 */
 205     case 0x14: /* OSC2 */
 206     case 0x18: /* OSC3 */
 207     case 0x1c: /* OSC4 */
 208         /* ??? */
 209         break;
 210     case 0x20: /* LOCK */
 211         if (val == LOCK_VALUE)
 212             s->lockval = val;
 213         else
 214             s->lockval = val & 0x7fff;
 215         break;
 216     case 0x28: /* CFGDATA1 */
 217         /* ??? Need to implement this.  */
 218         s->cfgdata1 = val;
 219         break;
 220     case 0x2c: /* CFGDATA2 */
 221         /* ??? Need to implement this.  */
 222         s->cfgdata2 = val;
 223         break;
 224     case 0x30: /* FLAGSSET */
 225         s->flags |= val;
 226         break;
 227     case 0x34: /* FLAGSCLR */
 228         s->flags &= ~val;
 229         break;
 230     case 0x38: /* NVFLAGSSET */
 231         s->nvflags |= val;
 232         break;
 233     case 0x3c: /* NVFLAGSCLR */
 234         s->nvflags &= ~val;
 235         break;
 236     case 0x40: /* RESETCTL */
 237         switch (board_id(s)) {
 238         case BOARD_ID_PB926:
 239             if (s->lockval == LOCK_VALUE) {
 240                 s->resetlevel = val;
 241                 if (val & 0x100) {
 242                     qemu_system_reset_request();
 243                 }
 244             }
 245             break;
 246         case BOARD_ID_PBX:
 247         case BOARD_ID_PBA8:
 248             if (s->lockval == LOCK_VALUE) {
 249                 s->resetlevel = val;
 250                 if (val & 0x04) {
 251                     qemu_system_reset_request();
 252                 }
 253             }
 254             break;
 255         case BOARD_ID_VEXPRESS:
 256         case BOARD_ID_EB:
 257         default:
 258             /* reserved: RAZ/WI */
 259             break;
 260         }
 261         break;
 262     case 0x44: /* PCICTL */
 263         /* nothing to do.  */
 264         break;
 265     case 0x4c: /* FLASH */
 266         break;
 267     case 0x50: /* CLCD */
 268         switch (board_id(s)) {
 269         case BOARD_ID_PB926:
 270             /* On 926 bits 13:8 are R/O, bits 1:0 control
 271              * the mux that defines how to interpret the PL110
 272              * graphics format, and other bits are r/w but we
 273              * don't implement them to do anything.
 274              */
 275             s->sys_clcd &= 0x3f00;
 276             s->sys_clcd |= val & ~0x3f00;
 277             qemu_set_irq(s->pl110_mux_ctrl, val & 3);
 278             break;
 279         case BOARD_ID_EB:
 280             /* The EB is the same except that there is no mux since
 281              * the EB has a PL111.
 282              */
 283             s->sys_clcd &= 0x3f00;
 284             s->sys_clcd |= val & ~0x3f00;
 285             break;
 286         case BOARD_ID_PBA8:
 287         case BOARD_ID_PBX:
 288             /* On PBA8 and PBX bit 7 is r/w and all other bits
 289              * are either r/o or RAZ/WI.
 290              */
 291             s->sys_clcd &= (1 << 7);
 292             s->sys_clcd |= val & ~(1 << 7);
 293             break;
 294         case BOARD_ID_VEXPRESS:
 295         default:
 296             /* On VExpress this register is unimplemented and will RAZ/WI */
 297             break;
 298         }
 299         break;
 300     case 0x54: /* CLCDSER */
 301     case 0x64: /* DMAPSR0 */
 302     case 0x68: /* DMAPSR1 */
 303     case 0x6c: /* DMAPSR2 */
 304     case 0x70: /* IOSEL */
 305     case 0x74: /* PLDCTL */
 306     case 0x80: /* BUSID */
 307     case 0x84: /* PROCID0 */
 308     case 0x88: /* PROCID1 */
 309     case 0x8c: /* OSCRESET0 */
 310     case 0x90: /* OSCRESET1 */
 311     case 0x94: /* OSCRESET2 */
 312     case 0x98: /* OSCRESET3 */
 313     case 0x9c: /* OSCRESET4 */
 314         break;
 315     case 0xa0: /* SYS_CFGDATA */
 316         if (board_id(s) != BOARD_ID_VEXPRESS) {
 317             goto bad_reg;
 318         }
 319         s->sys_cfgdata = val;
 320         return;
 321     case 0xa4: /* SYS_CFGCTRL */
 322         if (board_id(s) != BOARD_ID_VEXPRESS) {
 323             goto bad_reg;
 324         }
 325         s->sys_cfgctrl = val & ~(3 << 18);
 326         s->sys_cfgstat = 1;            /* complete */
 327         switch (s->sys_cfgctrl) {
 328         case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
 329             qemu_system_shutdown_request();
 330             break;
 331         case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
 332             qemu_system_reset_request();
 333             break;
 334         default:
 335             s->sys_cfgstat |= 2;        /* error */
 336         }
 337         return;
 338     case 0xa8: /* SYS_CFGSTAT */
 339         if (board_id(s) != BOARD_ID_VEXPRESS) {
 340             goto bad_reg;
 341         }
 342         s->sys_cfgstat = val & 3;
 343         return;
 344     default:
 345     bad_reg:
 346         qemu_log_mask(LOG_GUEST_ERROR,
 347                       "arm_sysctl_write: Bad register offset 0x%x\n",
 348                       (int)offset);
 349         return;
 350     }
 351 }
 352
 353 static const MemoryRegionOps arm_sysctl_ops = {
 354     .read = arm_sysctl_read,
 355     .write = arm_sysctl_write,
 356     .endianness = DEVICE_NATIVE_ENDIAN,
 357 };
 358
 359 static void arm_sysctl_gpio_set(void *opaque, int line, int level)
 360 {
 361     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 362     switch (line) {
 363     case ARM_SYSCTL_GPIO_MMC_WPROT:
 364     {
 365         /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
 366          * for all later boards it is bit 1.
 367          */
 368         int bit = 2;
 369         if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
 370             bit = 4;
 371         }
 372         s->sys_mci &= ~bit;
 373         if (level) {
 374             s->sys_mci |= bit;
 375         }
 376         break;
 377     }
 378     case ARM_SYSCTL_GPIO_MMC_CARDIN:
 379         s->sys_mci &= ~1;
 380         if (level) {
 381             s->sys_mci |= 1;
 382         }
 383         break;
 384     }
 385 }
 386
 387 static int arm_sysctl_init(SysBusDevice *dev)
 388 {
 389     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
 390
 391     memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
 392     sysbus_init_mmio(dev, &s->iomem);
 393     qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
 394     qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
 395     return 0;
 396 }
 397
 398 static Property arm_sysctl_properties[] = {
 399     DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 400     DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 401     DEFINE_PROP_END_OF_LIST(),
 402 };
 403
 404 static void arm_sysctl_class_init(ObjectClass *klass, void *data)
 405 {
 406     DeviceClass *dc = DEVICE_CLASS(klass);
 407     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 408
 409     k->init = arm_sysctl_init;
 410     dc->reset = arm_sysctl_reset;
 411     dc->vmsd = &vmstate_arm_sysctl;
 412     dc->props = arm_sysctl_properties;
 413 }
 414
 415 static const TypeInfo arm_sysctl_info = {
 416     .name          = "realview_sysctl",
 417     .parent        = TYPE_SYS_BUS_DEVICE,
 418     .instance_size = sizeof(arm_sysctl_state),
 419     .class_init    = arm_sysctl_class_init,
 420 };
 421
 422 static void arm_sysctl_register_types(void)
 423 {
 424     type_register_static(&arm_sysctl_info);
 425 }
 426
 427 type_init(arm_sysctl_register_types)