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target/ppc: cpu_init: Decouple G2 SPR registration from 755
[qemu/rayw.git] / target / ppc / cpu_init.c
blob36d6377a51d258c3931035028ff9ed9340a2fdfb
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_tcg.h"
48 #include "power8-pmu.h"
49
50 /* #define PPC_DEBUG_SPR */
51 /* #define USE_APPLE_GDB */
52
53 static inline void vscr_init(CPUPPCState *env, uint32_t val)
54 {
55 /* Altivec always uses round-to-nearest */
56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
57 ppc_store_vscr(env, val);
58 }
59
60 /**
61 * _spr_register
62 *
63 * Register an SPR with all the callbacks required for tcg,
64 * and the ID number for KVM.
65 *
66 * The reason for the conditional compilation is that the tcg functions
67 * may be compiled out, and the system kvm header may not be available
68 * for supplying the ID numbers. This is ugly, but the best we can do.
69 */
70
71 #ifdef CONFIG_TCG
72 # define USR_ARG(X) X,
73 # ifdef CONFIG_USER_ONLY
74 # define SYS_ARG(X)
75 # else
76 # define SYS_ARG(X) X,
77 # endif
78 #else
79 # define USR_ARG(X)
80 # define SYS_ARG(X)
81 #endif
82 #ifdef CONFIG_KVM
83 # define KVM_ARG(X) X,
84 #else
85 # define KVM_ARG(X)
86 #endif
87
88 typedef void spr_callback(DisasContext *, int, int);
89
90 static void _spr_register(CPUPPCState *env, int num, const char *name,
91 USR_ARG(spr_callback *uea_read)
92 USR_ARG(spr_callback *uea_write)
93 SYS_ARG(spr_callback *oea_read)
94 SYS_ARG(spr_callback *oea_write)
95 SYS_ARG(spr_callback *hea_read)
96 SYS_ARG(spr_callback *hea_write)
97 KVM_ARG(uint64_t one_reg_id)
98 target_ulong initial_value)
99 {
100 ppc_spr_t *spr = &env->spr_cb[num];
101
102 /* No SPR should be registered twice. */
103 assert(spr->name == NULL);
104 assert(name != NULL);
105
106 spr->name = name;
107 spr->default_value = initial_value;
108 env->spr[num] = initial_value;
109
110 #ifdef CONFIG_TCG
111 spr->uea_read = uea_read;
112 spr->uea_write = uea_write;
113 # ifndef CONFIG_USER_ONLY
114 spr->oea_read = oea_read;
115 spr->oea_write = oea_write;
116 spr->hea_read = hea_read;
117 spr->hea_write = hea_write;
118 # endif
119 #endif
120 #ifdef CONFIG_KVM
121 spr->one_reg_id = one_reg_id;
122 #endif
123 }
124
125 /* spr_register_kvm_hv passes all required arguments. */
126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
127 oea_read, oea_write, hea_read, hea_write, \
128 one_reg_id, initial_value) \
129 _spr_register(env, num, name, \
130 USR_ARG(uea_read) USR_ARG(uea_write) \
131 SYS_ARG(oea_read) SYS_ARG(oea_write) \
132 SYS_ARG(hea_read) SYS_ARG(hea_write) \
133 KVM_ARG(one_reg_id) initial_value)
134
135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
137 oea_read, oea_write, one_reg_id, ival) \
138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
139 oea_write, oea_read, oea_write, one_reg_id, ival)
140
141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
142 #define spr_register_hv(env, num, name, uea_read, uea_write, \
143 oea_read, oea_write, hea_read, hea_write, ival) \
144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
145 oea_write, hea_read, hea_write, 0, ival)
146
147 #define spr_register(env, num, name, uea_read, uea_write, \
148 oea_read, oea_write, ival) \
149 spr_register_kvm(env, num, name, uea_read, uea_write, \
150 oea_read, oea_write, 0, ival)
151
152 /* Generic PowerPC SPRs */
153 static void register_generic_sprs(PowerPCCPU *cpu)
154 {
155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
156 CPUPPCState *env = &cpu->env;
157
158 /* Integer processing */
159 spr_register(env, SPR_XER, "XER",
160 &spr_read_xer, &spr_write_xer,
161 &spr_read_xer, &spr_write_xer,
162 0x00000000);
163 /* Branch control */
164 spr_register(env, SPR_LR, "LR",
165 &spr_read_lr, &spr_write_lr,
166 &spr_read_lr, &spr_write_lr,
167 0x00000000);
168 spr_register(env, SPR_CTR, "CTR",
169 &spr_read_ctr, &spr_write_ctr,
170 &spr_read_ctr, &spr_write_ctr,
171 0x00000000);
172 /* Interrupt processing */
173 spr_register(env, SPR_SRR0, "SRR0",
174 SPR_NOACCESS, SPR_NOACCESS,
175 &spr_read_generic, &spr_write_generic,
176 0x00000000);
177 spr_register(env, SPR_SRR1, "SRR1",
178 SPR_NOACCESS, SPR_NOACCESS,
179 &spr_read_generic, &spr_write_generic,
180 0x00000000);
181 /* Processor control */
182 spr_register(env, SPR_SPRG0, "SPRG0",
183 SPR_NOACCESS, SPR_NOACCESS,
184 &spr_read_generic, &spr_write_generic,
185 0x00000000);
186 spr_register(env, SPR_SPRG1, "SPRG1",
187 SPR_NOACCESS, SPR_NOACCESS,
188 &spr_read_generic, &spr_write_generic,
189 0x00000000);
190 spr_register(env, SPR_SPRG2, "SPRG2",
191 SPR_NOACCESS, SPR_NOACCESS,
192 &spr_read_generic, &spr_write_generic,
193 0x00000000);
194 spr_register(env, SPR_SPRG3, "SPRG3",
195 SPR_NOACCESS, SPR_NOACCESS,
196 &spr_read_generic, &spr_write_generic,
197 0x00000000);
198
199 spr_register(env, SPR_PVR, "PVR",
200 /* Linux permits userspace to read PVR */
201 #if defined(CONFIG_LINUX_USER)
202 &spr_read_generic,
203 #else
204 SPR_NOACCESS,
205 #endif
206 SPR_NOACCESS,
207 &spr_read_generic, SPR_NOACCESS,
208 pcc->pvr);
209
210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
211 if (pcc->svr != POWERPC_SVR_NONE) {
212 if (pcc->svr & POWERPC_SVR_E500) {
213 spr_register(env, SPR_E500_SVR, "SVR",
214 SPR_NOACCESS, SPR_NOACCESS,
215 &spr_read_generic, SPR_NOACCESS,
216 pcc->svr & ~POWERPC_SVR_E500);
217 } else {
218 spr_register(env, SPR_SVR, "SVR",
219 SPR_NOACCESS, SPR_NOACCESS,
220 &spr_read_generic, SPR_NOACCESS,
221 pcc->svr);
222 }
223 }
224
225 /* Time base */
226 spr_register(env, SPR_VTBL, "TBL",
227 &spr_read_tbl, SPR_NOACCESS,
228 &spr_read_tbl, SPR_NOACCESS,
229 0x00000000);
230 spr_register(env, SPR_TBL, "TBL",
231 &spr_read_tbl, SPR_NOACCESS,
232 &spr_read_tbl, &spr_write_tbl,
233 0x00000000);
234 spr_register(env, SPR_VTBU, "TBU",
235 &spr_read_tbu, SPR_NOACCESS,
236 &spr_read_tbu, SPR_NOACCESS,
237 0x00000000);
238 spr_register(env, SPR_TBU, "TBU",
239 &spr_read_tbu, SPR_NOACCESS,
240 &spr_read_tbu, &spr_write_tbu,
241 0x00000000);
242 }
243
244 /* SPR common to all non-embedded PowerPC, including 601 */
245 static void register_ne_601_sprs(CPUPPCState *env)
246 {
247 /* Exception processing */
248 spr_register_kvm(env, SPR_DSISR, "DSISR",
249 SPR_NOACCESS, SPR_NOACCESS,
250 &spr_read_generic, &spr_write_generic,
251 KVM_REG_PPC_DSISR, 0x00000000);
252 spr_register_kvm(env, SPR_DAR, "DAR",
253 SPR_NOACCESS, SPR_NOACCESS,
254 &spr_read_generic, &spr_write_generic,
255 KVM_REG_PPC_DAR, 0x00000000);
256 /* Timer */
257 spr_register(env, SPR_DECR, "DECR",
258 SPR_NOACCESS, SPR_NOACCESS,
259 &spr_read_decr, &spr_write_decr,
260 0x00000000);
261 }
262
263 /* Storage Description Register 1 */
264 static void register_sdr1_sprs(CPUPPCState *env)
265 {
266 #ifndef CONFIG_USER_ONLY
267 if (env->has_hv_mode) {
268 /*
269 * SDR1 is a hypervisor resource on CPUs which have a
270 * hypervisor mode
271 */
272 spr_register_hv(env, SPR_SDR1, "SDR1",
273 SPR_NOACCESS, SPR_NOACCESS,
274 SPR_NOACCESS, SPR_NOACCESS,
275 &spr_read_generic, &spr_write_sdr1,
276 0x00000000);
277 } else {
278 spr_register(env, SPR_SDR1, "SDR1",
279 SPR_NOACCESS, SPR_NOACCESS,
280 &spr_read_generic, &spr_write_sdr1,
281 0x00000000);
282 }
283 #endif
284 }
285
286 /* BATs 0-3 */
287 static void register_low_BATs(CPUPPCState *env)
288 {
289 #if !defined(CONFIG_USER_ONLY)
290 spr_register(env, SPR_IBAT0U, "IBAT0U",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_ibat, &spr_write_ibatu,
293 0x00000000);
294 spr_register(env, SPR_IBAT0L, "IBAT0L",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_ibat, &spr_write_ibatl,
297 0x00000000);
298 spr_register(env, SPR_IBAT1U, "IBAT1U",
299 SPR_NOACCESS, SPR_NOACCESS,
300 &spr_read_ibat, &spr_write_ibatu,
301 0x00000000);
302 spr_register(env, SPR_IBAT1L, "IBAT1L",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_ibat, &spr_write_ibatl,
305 0x00000000);
306 spr_register(env, SPR_IBAT2U, "IBAT2U",
307 SPR_NOACCESS, SPR_NOACCESS,
308 &spr_read_ibat, &spr_write_ibatu,
309 0x00000000);
310 spr_register(env, SPR_IBAT2L, "IBAT2L",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_ibat, &spr_write_ibatl,
313 0x00000000);
314 spr_register(env, SPR_IBAT3U, "IBAT3U",
315 SPR_NOACCESS, SPR_NOACCESS,
316 &spr_read_ibat, &spr_write_ibatu,
317 0x00000000);
318 spr_register(env, SPR_IBAT3L, "IBAT3L",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_ibat, &spr_write_ibatl,
321 0x00000000);
322 spr_register(env, SPR_DBAT0U, "DBAT0U",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_dbat, &spr_write_dbatu,
325 0x00000000);
326 spr_register(env, SPR_DBAT0L, "DBAT0L",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_dbat, &spr_write_dbatl,
329 0x00000000);
330 spr_register(env, SPR_DBAT1U, "DBAT1U",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_dbat, &spr_write_dbatu,
333 0x00000000);
334 spr_register(env, SPR_DBAT1L, "DBAT1L",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_dbat, &spr_write_dbatl,
337 0x00000000);
338 spr_register(env, SPR_DBAT2U, "DBAT2U",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_dbat, &spr_write_dbatu,
341 0x00000000);
342 spr_register(env, SPR_DBAT2L, "DBAT2L",
343 SPR_NOACCESS, SPR_NOACCESS,
344 &spr_read_dbat, &spr_write_dbatl,
345 0x00000000);
346 spr_register(env, SPR_DBAT3U, "DBAT3U",
347 SPR_NOACCESS, SPR_NOACCESS,
348 &spr_read_dbat, &spr_write_dbatu,
349 0x00000000);
350 spr_register(env, SPR_DBAT3L, "DBAT3L",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_dbat, &spr_write_dbatl,
353 0x00000000);
354 env->nb_BATs += 4;
355 #endif
356 }
357
358 /* BATs 4-7 */
359 static void register_high_BATs(CPUPPCState *env)
360 {
361 #if !defined(CONFIG_USER_ONLY)
362 spr_register(env, SPR_IBAT4U, "IBAT4U",
363 SPR_NOACCESS, SPR_NOACCESS,
364 &spr_read_ibat_h, &spr_write_ibatu_h,
365 0x00000000);
366 spr_register(env, SPR_IBAT4L, "IBAT4L",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_ibat_h, &spr_write_ibatl_h,
369 0x00000000);
370 spr_register(env, SPR_IBAT5U, "IBAT5U",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_ibat_h, &spr_write_ibatu_h,
373 0x00000000);
374 spr_register(env, SPR_IBAT5L, "IBAT5L",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_ibat_h, &spr_write_ibatl_h,
377 0x00000000);
378 spr_register(env, SPR_IBAT6U, "IBAT6U",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_ibat_h, &spr_write_ibatu_h,
381 0x00000000);
382 spr_register(env, SPR_IBAT6L, "IBAT6L",
383 SPR_NOACCESS, SPR_NOACCESS,
384 &spr_read_ibat_h, &spr_write_ibatl_h,
385 0x00000000);
386 spr_register(env, SPR_IBAT7U, "IBAT7U",
387 SPR_NOACCESS, SPR_NOACCESS,
388 &spr_read_ibat_h, &spr_write_ibatu_h,
389 0x00000000);
390 spr_register(env, SPR_IBAT7L, "IBAT7L",
391 SPR_NOACCESS, SPR_NOACCESS,
392 &spr_read_ibat_h, &spr_write_ibatl_h,
393 0x00000000);
394 spr_register(env, SPR_DBAT4U, "DBAT4U",
395 SPR_NOACCESS, SPR_NOACCESS,
396 &spr_read_dbat_h, &spr_write_dbatu_h,
397 0x00000000);
398 spr_register(env, SPR_DBAT4L, "DBAT4L",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_dbat_h, &spr_write_dbatl_h,
401 0x00000000);
402 spr_register(env, SPR_DBAT5U, "DBAT5U",
403 SPR_NOACCESS, SPR_NOACCESS,
404 &spr_read_dbat_h, &spr_write_dbatu_h,
405 0x00000000);
406 spr_register(env, SPR_DBAT5L, "DBAT5L",
407 SPR_NOACCESS, SPR_NOACCESS,
408 &spr_read_dbat_h, &spr_write_dbatl_h,
409 0x00000000);
410 spr_register(env, SPR_DBAT6U, "DBAT6U",
411 SPR_NOACCESS, SPR_NOACCESS,
412 &spr_read_dbat_h, &spr_write_dbatu_h,
413 0x00000000);
414 spr_register(env, SPR_DBAT6L, "DBAT6L",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_dbat_h, &spr_write_dbatl_h,
417 0x00000000);
418 spr_register(env, SPR_DBAT7U, "DBAT7U",
419 SPR_NOACCESS, SPR_NOACCESS,
420 &spr_read_dbat_h, &spr_write_dbatu_h,
421 0x00000000);
422 spr_register(env, SPR_DBAT7L, "DBAT7L",
423 SPR_NOACCESS, SPR_NOACCESS,
424 &spr_read_dbat_h, &spr_write_dbatl_h,
425 0x00000000);
426 env->nb_BATs += 4;
427 #endif
428 }
429
430 /* Softare table search registers */
431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
432 {
433 #if !defined(CONFIG_USER_ONLY)
434 env->nb_tlb = nb_tlbs;
435 env->nb_ways = nb_ways;
436 env->id_tlbs = 1;
437 env->tlb_type = TLB_6XX;
438 spr_register(env, SPR_DMISS, "DMISS",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, SPR_NOACCESS,
441 0x00000000);
442 spr_register(env, SPR_DCMP, "DCMP",
443 SPR_NOACCESS, SPR_NOACCESS,
444 &spr_read_generic, SPR_NOACCESS,
445 0x00000000);
446 spr_register(env, SPR_HASH1, "HASH1",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, SPR_NOACCESS,
449 0x00000000);
450 spr_register(env, SPR_HASH2, "HASH2",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, SPR_NOACCESS,
453 0x00000000);
454 spr_register(env, SPR_IMISS, "IMISS",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, SPR_NOACCESS,
457 0x00000000);
458 spr_register(env, SPR_ICMP, "ICMP",
459 SPR_NOACCESS, SPR_NOACCESS,
460 &spr_read_generic, SPR_NOACCESS,
461 0x00000000);
462 spr_register(env, SPR_RPA, "RPA",
463 SPR_NOACCESS, SPR_NOACCESS,
464 &spr_read_generic, &spr_write_generic,
465 0x00000000);
466 #endif
467 }
468
469 static void register_755_sprs(CPUPPCState *env)
470 {
471 /* SGPRs */
472 spr_register(env, SPR_SPRG4, "SPRG4",
473 SPR_NOACCESS, SPR_NOACCESS,
474 &spr_read_generic, &spr_write_generic,
475 0x00000000);
476 spr_register(env, SPR_SPRG5, "SPRG5",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 spr_register(env, SPR_SPRG6, "SPRG6",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 spr_register(env, SPR_SPRG7, "SPRG7",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
487 0x00000000);
488 }
489
490 /* SPR common to all 7xx PowerPC implementations */
491 static void register_7xx_sprs(CPUPPCState *env)
492 {
493 /* Breakpoints */
494 spr_register_kvm(env, SPR_DABR, "DABR",
495 SPR_NOACCESS, SPR_NOACCESS,
496 &spr_read_generic, &spr_write_generic,
497 KVM_REG_PPC_DABR, 0x00000000);
498
499 spr_register(env, SPR_IABR, "IABR",
500 SPR_NOACCESS, SPR_NOACCESS,
501 &spr_read_generic, &spr_write_generic,
502 0x00000000);
503 /* Cache management */
504 spr_register(env, SPR_ICTC, "ICTC",
505 SPR_NOACCESS, SPR_NOACCESS,
506 &spr_read_generic, &spr_write_generic,
507 0x00000000);
508 /* Performance monitors */
509 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
510 SPR_NOACCESS, SPR_NOACCESS,
511 &spr_read_generic, &spr_write_generic,
512 0x00000000);
513
514 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518
519 spr_register(env, SPR_7XX_PMC1, "PMC1",
520 SPR_NOACCESS, SPR_NOACCESS,
521 &spr_read_generic, &spr_write_generic,
522 0x00000000);
523
524 spr_register(env, SPR_7XX_PMC2, "PMC2",
525 SPR_NOACCESS, SPR_NOACCESS,
526 &spr_read_generic, &spr_write_generic,
527 0x00000000);
528
529 spr_register(env, SPR_7XX_PMC3, "PMC3",
530 SPR_NOACCESS, SPR_NOACCESS,
531 &spr_read_generic, &spr_write_generic,
532 0x00000000);
533
534 spr_register(env, SPR_7XX_PMC4, "PMC4",
535 SPR_NOACCESS, SPR_NOACCESS,
536 &spr_read_generic, &spr_write_generic,
537 0x00000000);
538
539 spr_register(env, SPR_7XX_SIAR, "SIAR",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_generic, SPR_NOACCESS,
542 0x00000000);
543
544 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
545 &spr_read_ureg, SPR_NOACCESS,
546 &spr_read_ureg, SPR_NOACCESS,
547 0x00000000);
548
549 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
550 &spr_read_ureg, SPR_NOACCESS,
551 &spr_read_ureg, SPR_NOACCESS,
552 0x00000000);
553
554 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
555 &spr_read_ureg, SPR_NOACCESS,
556 &spr_read_ureg, SPR_NOACCESS,
557 0x00000000);
558
559 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
560 &spr_read_ureg, SPR_NOACCESS,
561 &spr_read_ureg, SPR_NOACCESS,
562 0x00000000);
563
564 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
565 &spr_read_ureg, SPR_NOACCESS,
566 &spr_read_ureg, SPR_NOACCESS,
567 0x00000000);
568
569 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
570 &spr_read_ureg, SPR_NOACCESS,
571 &spr_read_ureg, SPR_NOACCESS,
572 0x00000000);
573
574 spr_register(env, SPR_7XX_USIAR, "USIAR",
575 &spr_read_ureg, SPR_NOACCESS,
576 &spr_read_ureg, SPR_NOACCESS,
577 0x00000000);
578 /* External access control */
579 spr_register(env, SPR_EAR, "EAR",
580 SPR_NOACCESS, SPR_NOACCESS,
581 &spr_read_generic, &spr_write_generic,
582 0x00000000);
583 }
584
585 #ifdef TARGET_PPC64
586 static void register_amr_sprs(CPUPPCState *env)
587 {
588 #ifndef CONFIG_USER_ONLY
589 /*
590 * Virtual Page Class Key protection
591 *
592 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
593 * userspace accessible, 29 is privileged. So we only need to set
594 * the kvm ONE_REG id on one of them, we use 29
595 */
596 spr_register(env, SPR_UAMR, "UAMR",
597 &spr_read_generic, &spr_write_amr,
598 &spr_read_generic, &spr_write_amr,
599 0);
600 spr_register_kvm_hv(env, SPR_AMR, "AMR",
601 SPR_NOACCESS, SPR_NOACCESS,
602 &spr_read_generic, &spr_write_amr,
603 &spr_read_generic, &spr_write_generic,
604 KVM_REG_PPC_AMR, 0);
605 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
606 SPR_NOACCESS, SPR_NOACCESS,
607 &spr_read_generic, &spr_write_uamor,
608 &spr_read_generic, &spr_write_generic,
609 KVM_REG_PPC_UAMOR, 0);
610 spr_register_hv(env, SPR_AMOR, "AMOR",
611 SPR_NOACCESS, SPR_NOACCESS,
612 SPR_NOACCESS, SPR_NOACCESS,
613 &spr_read_generic, &spr_write_generic,
614 0);
615 #endif /* !CONFIG_USER_ONLY */
616 }
617
618 static void register_iamr_sprs(CPUPPCState *env)
619 {
620 #ifndef CONFIG_USER_ONLY
621 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
622 SPR_NOACCESS, SPR_NOACCESS,
623 &spr_read_generic, &spr_write_iamr,
624 &spr_read_generic, &spr_write_generic,
625 KVM_REG_PPC_IAMR, 0);
626 #endif /* !CONFIG_USER_ONLY */
627 }
628 #endif /* TARGET_PPC64 */
629
630 static void register_thrm_sprs(CPUPPCState *env)
631 {
632 /* Thermal management */
633 spr_register(env, SPR_THRM1, "THRM1",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_thrm, &spr_write_generic,
636 0x00000000);
637
638 spr_register(env, SPR_THRM2, "THRM2",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_thrm, &spr_write_generic,
641 0x00000000);
642
643 spr_register(env, SPR_THRM3, "THRM3",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_thrm, &spr_write_generic,
646 0x00000000);
647 }
648
649 /* SPR specific to PowerPC 604 implementation */
650 static void register_604_sprs(CPUPPCState *env)
651 {
652 /* Processor identification */
653 spr_register(env, SPR_PIR, "PIR",
654 SPR_NOACCESS, SPR_NOACCESS,
655 &spr_read_generic, &spr_write_pir,
656 0x00000000);
657 /* Breakpoints */
658 spr_register(env, SPR_IABR, "IABR",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_generic, &spr_write_generic,
661 0x00000000);
662
663 spr_register_kvm(env, SPR_DABR, "DABR",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, &spr_write_generic,
666 KVM_REG_PPC_DABR, 0x00000000);
667 /* Performance counters */
668 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672
673 spr_register(env, SPR_7XX_PMC1, "PMC1",
674 SPR_NOACCESS, SPR_NOACCESS,
675 &spr_read_generic, &spr_write_generic,
676 0x00000000);
677
678 spr_register(env, SPR_7XX_PMC2, "PMC2",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_generic, &spr_write_generic,
681 0x00000000);
682
683 spr_register(env, SPR_7XX_SIAR, "SIAR",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_generic, SPR_NOACCESS,
686 0x00000000);
687
688 spr_register(env, SPR_SDA, "SDA",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_generic, SPR_NOACCESS,
691 0x00000000);
692 /* External access control */
693 spr_register(env, SPR_EAR, "EAR",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, &spr_write_generic,
696 0x00000000);
697 }
698
699 /* SPR specific to PowerPC 603 implementation */
700 static void register_603_sprs(CPUPPCState *env)
701 {
702 /* External access control */
703 spr_register(env, SPR_EAR, "EAR",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_generic, &spr_write_generic,
706 0x00000000);
707 /* Breakpoints */
708 spr_register(env, SPR_IABR, "IABR",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_generic, &spr_write_generic,
711 0x00000000);
712
713 }
714
715 /* SPR specific to PowerPC G2 implementation */
716 static void register_G2_sprs(CPUPPCState *env)
717 {
718 /* Memory base address */
719 /* MBAR */
720 spr_register(env, SPR_MBAR, "MBAR",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724 /* Exception processing */
725 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733 /* Breakpoints */
734 spr_register(env, SPR_DABR, "DABR",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738
739 spr_register(env, SPR_DABR2, "DABR2",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_generic, &spr_write_generic,
742 0x00000000);
743
744 spr_register(env, SPR_IABR, "IABR",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748
749 spr_register(env, SPR_IABR2, "IABR2",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_generic, &spr_write_generic,
752 0x00000000);
753
754 spr_register(env, SPR_IBCR, "IBCR",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_generic, &spr_write_generic,
757 0x00000000);
758
759 spr_register(env, SPR_DBCR, "DBCR",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
762 0x00000000);
763
764 /* External access control */
765 spr_register(env, SPR_EAR, "EAR",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_generic,
768 0x00000000);
769 /* Hardware implementation register */
770 spr_register(env, SPR_HID0, "HID0",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
773 0x00000000);
774
775 spr_register(env, SPR_HID1, "HID1",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
778 0x00000000);
779
780 spr_register(env, SPR_HID2, "HID2",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
783 0x00000000);
784
785 /* SGPRs */
786 spr_register(env, SPR_SPRG4, "SPRG4",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_generic,
789 0x00000000);
790 spr_register(env, SPR_SPRG5, "SPRG5",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, &spr_write_generic,
793 0x00000000);
794 spr_register(env, SPR_SPRG6, "SPRG6",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_generic, &spr_write_generic,
797 0x00000000);
798 spr_register(env, SPR_SPRG7, "SPRG7",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_generic, &spr_write_generic,
801 0x00000000);
802 }
803
804 static void register_74xx_sprs(CPUPPCState *env)
805 {
806 /* Processor identification */
807 spr_register(env, SPR_PIR, "PIR",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_pir,
810 0x00000000);
811
812 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816
817 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
818 &spr_read_ureg, SPR_NOACCESS,
819 &spr_read_ureg, SPR_NOACCESS,
820 0x00000000);
821
822 spr_register(env, SPR_BAMR, "BAMR",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826
827 spr_register(env, SPR_MSSCR0, "MSSCR0",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_generic, &spr_write_generic,
830 0x00000000);
831 /* Hardware implementation registers */
832 spr_register(env, SPR_HID0, "HID0",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_generic, &spr_write_generic,
835 0x00000000);
836
837 spr_register(env, SPR_HID1, "HID1",
838 SPR_NOACCESS, SPR_NOACCESS,
839 &spr_read_generic, &spr_write_generic,
840 0x00000000);
841 /* Altivec */
842 spr_register(env, SPR_VRSAVE, "VRSAVE",
843 &spr_read_generic, &spr_write_generic,
844 &spr_read_generic, &spr_write_generic,
845 0x00000000);
846
847 spr_register(env, SPR_L2CR, "L2CR",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, spr_access_nop,
850 0x00000000);
851 }
852
853 static void register_l3_ctrl(CPUPPCState *env)
854 {
855 /* L3CR */
856 spr_register(env, SPR_L3CR, "L3CR",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_generic, &spr_write_generic,
859 0x00000000);
860 /* L3ITCR0 */
861 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_generic, &spr_write_generic,
864 0x00000000);
865 /* L3PM */
866 spr_register(env, SPR_L3PM, "L3PM",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_generic, &spr_write_generic,
869 0x00000000);
870 }
871
872 static void register_usprg3_sprs(CPUPPCState *env)
873 {
874 spr_register(env, SPR_USPRG3, "USPRG3",
875 &spr_read_ureg, SPR_NOACCESS,
876 &spr_read_ureg, SPR_NOACCESS,
877 0x00000000);
878 }
879
880 static void register_usprgh_sprs(CPUPPCState *env)
881 {
882 spr_register(env, SPR_USPRG4, "USPRG4",
883 &spr_read_ureg, SPR_NOACCESS,
884 &spr_read_ureg, SPR_NOACCESS,
885 0x00000000);
886 spr_register(env, SPR_USPRG5, "USPRG5",
887 &spr_read_ureg, SPR_NOACCESS,
888 &spr_read_ureg, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_USPRG6, "USPRG6",
891 &spr_read_ureg, SPR_NOACCESS,
892 &spr_read_ureg, SPR_NOACCESS,
893 0x00000000);
894 spr_register(env, SPR_USPRG7, "USPRG7",
895 &spr_read_ureg, SPR_NOACCESS,
896 &spr_read_ureg, SPR_NOACCESS,
897 0x00000000);
898 }
899
900 /* PowerPC BookE SPR */
901 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
902 {
903 const char *ivor_names[64] = {
904 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
905 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
906 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
907 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
908 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
909 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
910 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
911 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
912 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
913 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
914 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
915 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
916 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
917 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
918 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
919 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
920 };
921 #define SPR_BOOKE_IVORxx (-1)
922 int ivor_sprn[64] = {
923 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
924 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
925 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
926 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
927 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
928 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
929 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
930 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
931 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
932 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
933 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
934 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
935 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
936 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
937 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
938 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
939 };
940 int i;
941
942 /* Interrupt processing */
943 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951 /* Debug */
952 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
956
957 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
961
962 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
963 SPR_NOACCESS, SPR_NOACCESS,
964 &spr_read_generic, &spr_write_generic,
965 0x00000000);
966
967 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, &spr_write_generic,
970 0x00000000);
971
972 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
973 SPR_NOACCESS, SPR_NOACCESS,
974 &spr_read_generic, &spr_write_40x_dbcr0,
975 0x00000000);
976
977 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
978 SPR_NOACCESS, SPR_NOACCESS,
979 &spr_read_generic, &spr_write_generic,
980 0x00000000);
981
982 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, &spr_write_generic,
993 0x00000000);
994
995 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_clear,
998 0x00000000);
999 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003 spr_register(env, SPR_BOOKE_ESR, "ESR",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_excp_prefix,
1010 0x00000000);
1011 /* Exception vectors */
1012 for (i = 0; i < 64; i++) {
1013 if (ivor_mask & (1ULL << i)) {
1014 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1015 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1016 exit(1);
1017 }
1018 spr_register(env, ivor_sprn[i], ivor_names[i],
1019 SPR_NOACCESS, SPR_NOACCESS,
1020 &spr_read_generic, &spr_write_excp_vector,
1021 0x00000000);
1022 }
1023 }
1024 spr_register(env, SPR_BOOKE_PID, "PID",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_booke_pid,
1027 0x00000000);
1028 spr_register(env, SPR_BOOKE_TCR, "TCR",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, &spr_write_booke_tcr,
1031 0x00000000);
1032 spr_register(env, SPR_BOOKE_TSR, "TSR",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, &spr_write_booke_tsr,
1035 0x00000000);
1036 /* Timer */
1037 spr_register(env, SPR_DECR, "DECR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_decr, &spr_write_decr,
1040 0x00000000);
1041 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 SPR_NOACCESS, &spr_write_generic,
1044 0x00000000);
1045 /* SPRGs */
1046 spr_register(env, SPR_USPRG0, "USPRG0",
1047 &spr_read_generic, &spr_write_generic,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 spr_register(env, SPR_SPRG4, "SPRG4",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 spr_register(env, SPR_SPRG5, "SPRG5",
1055 SPR_NOACCESS, SPR_NOACCESS,
1056 &spr_read_generic, &spr_write_generic,
1057 0x00000000);
1058 spr_register(env, SPR_SPRG6, "SPRG6",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 spr_register(env, SPR_SPRG7, "SPRG7",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 0x00000000);
1066 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 &spr_read_generic, &spr_write_generic,
1073 0x00000000);
1074 }
1075
1076 #if !defined(CONFIG_USER_ONLY)
1077 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1078 uint32_t maxsize, uint32_t flags,
1079 uint32_t nentries)
1080 {
1081 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1082 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1083 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1084 flags | nentries;
1085 }
1086 #endif /* !CONFIG_USER_ONLY */
1087
1088 /* BookE 2.06 storage control registers */
1089 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1090 uint32_t *tlbncfg, uint32_t mmucfg)
1091 {
1092 #if !defined(CONFIG_USER_ONLY)
1093 const char *mas_names[8] = {
1094 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1095 };
1096 int mas_sprn[8] = {
1097 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1098 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1099 };
1100 int i;
1101
1102 /* TLB assist registers */
1103 for (i = 0; i < 8; i++) {
1104 if (mas_mask & (1 << i)) {
1105 spr_register(env, mas_sprn[i], mas_names[i],
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic,
1108 (i == 2 && (env->insns_flags & PPC_64B))
1109 ? &spr_write_generic : &spr_write_generic32,
1110 0x00000000);
1111 }
1112 }
1113 if (env->nb_pids > 1) {
1114 spr_register(env, SPR_BOOKE_PID1, "PID1",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_booke_pid,
1117 0x00000000);
1118 }
1119 if (env->nb_pids > 2) {
1120 spr_register(env, SPR_BOOKE_PID2, "PID2",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_booke_pid,
1123 0x00000000);
1124 }
1125
1126 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_eplc,
1129 0x00000000);
1130 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_epsc,
1133 0x00000000);
1134
1135 spr_register(env, SPR_MMUCFG, "MMUCFG",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, SPR_NOACCESS,
1138 mmucfg);
1139 switch (env->nb_ways) {
1140 case 4:
1141 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, SPR_NOACCESS,
1144 tlbncfg[3]);
1145 /* Fallthru */
1146 case 3:
1147 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, SPR_NOACCESS,
1150 tlbncfg[2]);
1151 /* Fallthru */
1152 case 2:
1153 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_generic, SPR_NOACCESS,
1156 tlbncfg[1]);
1157 /* Fallthru */
1158 case 1:
1159 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, SPR_NOACCESS,
1162 tlbncfg[0]);
1163 /* Fallthru */
1164 case 0:
1165 default:
1166 break;
1167 }
1168 #endif
1169 }
1170
1171 /* SPR specific to PowerPC 440 implementation */
1172 static void register_440_sprs(CPUPPCState *env)
1173 {
1174 /* Cache control */
1175 spr_register(env, SPR_440_DNV0, "DNV0",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179
1180 spr_register(env, SPR_440_DNV1, "DNV1",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184
1185 spr_register(env, SPR_440_DNV2, "DNV2",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189
1190 spr_register(env, SPR_440_DNV3, "DNV3",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194
1195 spr_register(env, SPR_440_DTV0, "DTV0",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199
1200 spr_register(env, SPR_440_DTV1, "DTV1",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204
1205 spr_register(env, SPR_440_DTV2, "DTV2",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209
1210 spr_register(env, SPR_440_DTV3, "DTV3",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214
1215 spr_register(env, SPR_440_DVLIM, "DVLIM",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219
1220 spr_register(env, SPR_440_INV0, "INV0",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224
1225 spr_register(env, SPR_440_INV1, "INV1",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_generic, &spr_write_generic,
1228 0x00000000);
1229
1230 spr_register(env, SPR_440_INV2, "INV2",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234
1235 spr_register(env, SPR_440_INV3, "INV3",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239
1240 spr_register(env, SPR_440_ITV0, "ITV0",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244
1245 spr_register(env, SPR_440_ITV1, "ITV1",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_generic, &spr_write_generic,
1248 0x00000000);
1249
1250 spr_register(env, SPR_440_ITV2, "ITV2",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254
1255 spr_register(env, SPR_440_ITV3, "ITV3",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
1259
1260 spr_register(env, SPR_440_IVLIM, "IVLIM",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
1264 /* Cache debug */
1265 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, SPR_NOACCESS,
1268 0x00000000);
1269
1270 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, SPR_NOACCESS,
1273 0x00000000);
1274
1275 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, SPR_NOACCESS,
1278 0x00000000);
1279
1280 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, SPR_NOACCESS,
1283 0x00000000);
1284
1285 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, SPR_NOACCESS,
1288 0x00000000);
1289
1290 spr_register(env, SPR_440_DBDR, "DBDR",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* Processor control */
1295 spr_register(env, SPR_4xx_CCR0, "CCR0",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, SPR_NOACCESS,
1302 0x00000000);
1303 /* Storage control */
1304 spr_register(env, SPR_440_MMUCR, "MMUCR",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 }
1309
1310 /* SPR shared between PowerPC 40x implementations */
1311 static void register_40x_sprs(CPUPPCState *env)
1312 {
1313 /* Cache */
1314 /* not emulated, as QEMU do not emulate caches */
1315 spr_register(env, SPR_40x_DCCR, "DCCR",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* not emulated, as QEMU do not emulate caches */
1320 spr_register(env, SPR_40x_ICCR, "ICCR",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* not emulated, as QEMU do not emulate caches */
1325 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, SPR_NOACCESS,
1328 0x00000000);
1329 /* Exception */
1330 spr_register(env, SPR_40x_DEAR, "DEAR",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 spr_register(env, SPR_40x_ESR, "ESR",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 spr_register(env, SPR_40x_EVPR, "EVPR",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_excp_prefix,
1341 0x00000000);
1342 spr_register(env, SPR_40x_SRR2, "SRR2",
1343 &spr_read_generic, &spr_write_generic,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 spr_register(env, SPR_40x_SRR3, "SRR3",
1347 &spr_read_generic, &spr_write_generic,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* Timers */
1351 spr_register(env, SPR_40x_PIT, "PIT",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_40x_pit, &spr_write_40x_pit,
1354 0x00000000);
1355 spr_register(env, SPR_40x_TCR, "TCR",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_40x_tcr,
1358 0x00000000);
1359 spr_register(env, SPR_40x_TSR, "TSR",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_40x_tsr,
1362 0x00000000);
1363 }
1364
1365 /* SPR specific to PowerPC 405 implementation */
1366 static void register_405_sprs(CPUPPCState *env)
1367 {
1368 /* MMU */
1369 spr_register(env, SPR_40x_PID, "PID",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_40x_pid,
1372 0x00000000);
1373 spr_register(env, SPR_4xx_CCR0, "CCR0",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00700000);
1377 /* Debug interface */
1378 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_40x_dbcr0,
1381 0x00000000);
1382
1383 spr_register(env, SPR_405_DBCR1, "DBCR1",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387
1388 spr_register(env, SPR_40x_DBSR, "DBSR",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_clear,
1391 /* Last reset was system reset */
1392 0x00000300);
1393
1394 spr_register(env, SPR_40x_DAC1, "DAC1",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398 spr_register(env, SPR_40x_DAC2, "DAC2",
1399 SPR_NOACCESS, SPR_NOACCESS,
1400 &spr_read_generic, &spr_write_generic,
1401 0x00000000);
1402
1403 spr_register(env, SPR_405_DVC1, "DVC1",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407
1408 spr_register(env, SPR_405_DVC2, "DVC2",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412
1413 spr_register(env, SPR_40x_IAC1, "IAC1",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 spr_register(env, SPR_40x_IAC2, "IAC2",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421
1422 spr_register(env, SPR_405_IAC3, "IAC3",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_generic,
1425 0x00000000);
1426
1427 spr_register(env, SPR_405_IAC4, "IAC4",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
1431 /* Storage control */
1432 spr_register(env, SPR_405_SLER, "SLER",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, &spr_write_40x_sler,
1435 0x00000000);
1436 spr_register(env, SPR_40x_ZPR, "ZPR",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440
1441 spr_register(env, SPR_405_SU0R, "SU0R",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_generic,
1444 0x00000000);
1445 /* SPRG */
1446 spr_register(env, SPR_USPRG0, "USPRG0",
1447 &spr_read_ureg, SPR_NOACCESS,
1448 &spr_read_ureg, SPR_NOACCESS,
1449 0x00000000);
1450 spr_register(env, SPR_SPRG4, "SPRG4",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1453 0x00000000);
1454 spr_register(env, SPR_SPRG5, "SPRG5",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458 spr_register(env, SPR_SPRG6, "SPRG6",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 spr_register(env, SPR_SPRG7, "SPRG7",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 spr_read_generic, &spr_write_generic,
1465 0x00000000);
1466
1467 /* Bus access control */
1468 /* not emulated, as QEMU never does speculative access */
1469 spr_register(env, SPR_40x_SGR, "SGR",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0xFFFFFFFF);
1473 /* not emulated, as QEMU do not emulate caches */
1474 spr_register(env, SPR_40x_DCWR, "DCWR",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 }
1479
1480
1481 static void register_5xx_8xx_sprs(CPUPPCState *env)
1482 {
1483 /* Exception processing */
1484 spr_register_kvm(env, SPR_DSISR, "DSISR",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 KVM_REG_PPC_DSISR, 0x00000000);
1488 spr_register_kvm(env, SPR_DAR, "DAR",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 KVM_REG_PPC_DAR, 0x00000000);
1492 /* Timer */
1493 spr_register(env, SPR_DECR, "DECR",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_decr, &spr_write_decr,
1496 0x00000000);
1497
1498 spr_register(env, SPR_MPC_EIE, "EIE",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502
1503 spr_register(env, SPR_MPC_EID, "EID",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
1507
1508 spr_register(env, SPR_MPC_NRI, "NRI",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512
1513 spr_register(env, SPR_MPC_CMPA, "CMPA",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517
1518 spr_register(env, SPR_MPC_CMPB, "CMPB",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522
1523 spr_register(env, SPR_MPC_CMPC, "CMPC",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
1527
1528 spr_register(env, SPR_MPC_CMPD, "CMPD",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532
1533 spr_register(env, SPR_MPC_ECR, "ECR",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537
1538 spr_register(env, SPR_MPC_DER, "DER",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542
1543 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547
1548 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552
1553 spr_register(env, SPR_MPC_CMPE, "CMPE",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557
1558 spr_register(env, SPR_MPC_CMPF, "CMPF",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562
1563 spr_register(env, SPR_MPC_CMPG, "CMPG",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567
1568 spr_register(env, SPR_MPC_CMPH, "CMPH",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572
1573 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577
1578 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582
1583 spr_register(env, SPR_MPC_BAR, "BAR",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587
1588 spr_register(env, SPR_MPC_DPDR, "DPDR",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
1592
1593 spr_register(env, SPR_MPC_IMMR, "IMMR",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
1597 }
1598
1599 static void register_5xx_sprs(CPUPPCState *env)
1600 {
1601 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605
1606 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, &spr_write_generic,
1609 0x00000000);
1610
1611 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_generic,
1614 0x00000000);
1615
1616 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_generic,
1619 0x00000000);
1620
1621 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_generic,
1624 0x00000000);
1625
1626 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1627 SPR_NOACCESS, SPR_NOACCESS,
1628 &spr_read_generic, &spr_write_generic,
1629 0x00000000);
1630
1631 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, &spr_write_generic,
1634 0x00000000);
1635
1636 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1637 SPR_NOACCESS, SPR_NOACCESS,
1638 &spr_read_generic, &spr_write_generic,
1639 0x00000000);
1640
1641 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, &spr_write_generic,
1644 0x00000000);
1645
1646 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650
1651 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_generic,
1654 0x00000000);
1655
1656 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_generic,
1659 0x00000000);
1660
1661 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665
1666 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1669 0x00000000);
1670
1671 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675
1676 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680
1681 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685
1686 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
1690
1691 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695
1696 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700
1701 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 }
1706
1707 static void register_8xx_sprs(CPUPPCState *env)
1708 {
1709
1710 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714
1715 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719
1720 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724
1725 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, &spr_write_generic,
1728 0x00000000);
1729
1730 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, &spr_write_generic,
1733 0x00000000);
1734
1735 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
1739
1740 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744
1745 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749
1750 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
1754
1755 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_generic,
1758 0x00000000);
1759
1760 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764
1765 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769
1770 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774
1775 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779
1780 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784
1785 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789
1790 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794
1795 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799
1800 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804
1805 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809
1810 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
1814
1815 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819
1820 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1821 SPR_NOACCESS, SPR_NOACCESS,
1822 &spr_read_generic, &spr_write_generic,
1823 0x00000000);
1824
1825 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829
1830 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 }
1835
1836 /*
1837 * AMR => SPR 29 (Power 2.04)
1838 * CTRL => SPR 136 (Power 2.04)
1839 * CTRL => SPR 152 (Power 2.04)
1840 * SCOMC => SPR 276 (64 bits ?)
1841 * SCOMD => SPR 277 (64 bits ?)
1842 * TBU40 => SPR 286 (Power 2.04 hypv)
1843 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1844 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1845 * HDSISR => SPR 306 (Power 2.04 hypv)
1846 * HDAR => SPR 307 (Power 2.04 hypv)
1847 * PURR => SPR 309 (Power 2.04 hypv)
1848 * HDEC => SPR 310 (Power 2.04 hypv)
1849 * HIOR => SPR 311 (hypv)
1850 * RMOR => SPR 312 (970)
1851 * HRMOR => SPR 313 (Power 2.04 hypv)
1852 * HSRR0 => SPR 314 (Power 2.04 hypv)
1853 * HSRR1 => SPR 315 (Power 2.04 hypv)
1854 * LPIDR => SPR 317 (970)
1855 * EPR => SPR 702 (Power 2.04 emb)
1856 * perf => 768-783 (Power 2.04)
1857 * perf => 784-799 (Power 2.04)
1858 * PPR => SPR 896 (Power 2.04)
1859 * DABRX => 1015 (Power 2.04 hypv)
1860 * FPECR => SPR 1022 (?)
1861 * ... and more (thermal management, performance counters, ...)
1862 */
1863
1864 /*****************************************************************************/
1865 /* Exception vectors models */
1866 static void init_excp_4xx_softmmu(CPUPPCState *env)
1867 {
1868 #if !defined(CONFIG_USER_ONLY)
1869 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1870 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1871 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1872 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1873 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1874 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1875 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1876 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1877 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1878 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1879 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1880 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1881 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1882 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1883 env->ivor_mask = 0x0000FFF0UL;
1884 env->ivpr_mask = 0xFFFF0000UL;
1885 /* Hardware reset vector */
1886 env->hreset_vector = 0xFFFFFFFCUL;
1887 #endif
1888 }
1889
1890 static void init_excp_MPC5xx(CPUPPCState *env)
1891 {
1892 #if !defined(CONFIG_USER_ONLY)
1893 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1894 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1895 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1896 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1897 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1898 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1899 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1900 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1901 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1902 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1903 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1904 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1905 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1906 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1907 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1908 env->ivor_mask = 0x0000FFF0UL;
1909 env->ivpr_mask = 0xFFFF0000UL;
1910 /* Hardware reset vector */
1911 env->hreset_vector = 0x00000100UL;
1912 #endif
1913 }
1914
1915 static void init_excp_MPC8xx(CPUPPCState *env)
1916 {
1917 #if !defined(CONFIG_USER_ONLY)
1918 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1919 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1920 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1921 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1922 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1923 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1924 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1925 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1926 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1927 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1928 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1929 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1930 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1931 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1932 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1933 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1934 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1935 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1936 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1937 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1938 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1939 env->ivor_mask = 0x0000FFF0UL;
1940 env->ivpr_mask = 0xFFFF0000UL;
1941 /* Hardware reset vector */
1942 env->hreset_vector = 0x00000100UL;
1943 #endif
1944 }
1945
1946 static void init_excp_G2(CPUPPCState *env)
1947 {
1948 #if !defined(CONFIG_USER_ONLY)
1949 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1950 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1951 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1952 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1953 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1954 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1955 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1956 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1957 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1958 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1959 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1960 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1961 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1962 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1963 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1964 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1965 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1966 /* Hardware reset vector */
1967 env->hreset_vector = 0x00000100UL;
1968 #endif
1969 }
1970
1971 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1972 {
1973 #if !defined(CONFIG_USER_ONLY)
1974 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1975 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1976 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1977 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1978 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1979 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1980 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1981 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1982 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1983 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1984 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1985 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1986 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1987 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1988 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1989 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1990 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1991 /*
1992 * These two are the same IVOR as POWERPC_EXCP_VPU and
1993 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1994 * powerpc_excp().
1995 */
1996 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1997 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1998
1999 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2000 env->ivor_mask = 0x0000FFF7UL;
2001 env->ivpr_mask = ivpr_mask;
2002 /* Hardware reset vector */
2003 env->hreset_vector = 0xFFFFFFFCUL;
2004 #endif
2005 }
2006
2007 static void init_excp_BookE(CPUPPCState *env)
2008 {
2009 #if !defined(CONFIG_USER_ONLY)
2010 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2011 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2012 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2013 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2014 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2015 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2016 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2017 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2018 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2019 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2020 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2021 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2022 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2023 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2024 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2025 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2026 env->ivor_mask = 0x0000FFF0UL;
2027 env->ivpr_mask = 0xFFFF0000UL;
2028 /* Hardware reset vector */
2029 env->hreset_vector = 0xFFFFFFFCUL;
2030 #endif
2031 }
2032
2033 static void init_excp_603(CPUPPCState *env)
2034 {
2035 #if !defined(CONFIG_USER_ONLY)
2036 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2037 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2038 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2040 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2041 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2042 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2043 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2044 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2047 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2048 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2049 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2050 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2051 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2052 /* Hardware reset vector */
2053 env->hreset_vector = 0x00000100UL;
2054 #endif
2055 }
2056
2057 static void init_excp_604(CPUPPCState *env)
2058 {
2059 #if !defined(CONFIG_USER_ONLY)
2060 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2061 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2062 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2063 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2064 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2065 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2066 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2067 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2068 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2069 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2070 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2071 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2072 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2073 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2074 /* Hardware reset vector */
2075 env->hreset_vector = 0x00000100UL;
2076 #endif
2077 }
2078
2079 static void init_excp_7x0(CPUPPCState *env)
2080 {
2081 #if !defined(CONFIG_USER_ONLY)
2082 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2083 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2084 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2085 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2086 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2087 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2088 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2089 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2090 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2091 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2092 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2093 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2094 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2095 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2096 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2097 /* Hardware reset vector */
2098 env->hreset_vector = 0x00000100UL;
2099 #endif
2100 }
2101
2102 static void init_excp_750cl(CPUPPCState *env)
2103 {
2104 #if !defined(CONFIG_USER_ONLY)
2105 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2106 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2107 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2108 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2109 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2110 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2111 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2112 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2113 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2114 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2115 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2116 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2117 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2118 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2119 /* Hardware reset vector */
2120 env->hreset_vector = 0x00000100UL;
2121 #endif
2122 }
2123
2124 static void init_excp_750cx(CPUPPCState *env)
2125 {
2126 #if !defined(CONFIG_USER_ONLY)
2127 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2128 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2129 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2130 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2131 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2132 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2133 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2134 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2135 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2136 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2137 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2138 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2139 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2140 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2141 /* Hardware reset vector */
2142 env->hreset_vector = 0x00000100UL;
2143 #endif
2144 }
2145
2146 /* XXX: Check if this is correct */
2147 static void init_excp_7x5(CPUPPCState *env)
2148 {
2149 #if !defined(CONFIG_USER_ONLY)
2150 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2151 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2152 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2153 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2154 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2155 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2156 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2157 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2158 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2159 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2160 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2161 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2162 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2163 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2164 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2165 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2166 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2167 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2168 /* Hardware reset vector */
2169 env->hreset_vector = 0x00000100UL;
2170 #endif
2171 }
2172
2173 static void init_excp_7400(CPUPPCState *env)
2174 {
2175 #if !defined(CONFIG_USER_ONLY)
2176 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2177 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2178 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2179 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2180 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2181 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2182 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2183 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2184 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2185 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2186 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2187 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2188 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2189 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2190 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2191 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2192 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2193 /* Hardware reset vector */
2194 env->hreset_vector = 0x00000100UL;
2195 #endif
2196 }
2197
2198 static void init_excp_7450(CPUPPCState *env)
2199 {
2200 #if !defined(CONFIG_USER_ONLY)
2201 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2202 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2203 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2204 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2205 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2206 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2207 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2208 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2209 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2210 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2211 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2212 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2213 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2214 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2215 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2216 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2217 /* Hardware reset vector */
2218 env->hreset_vector = 0x00000100UL;
2219 #endif
2220 }
2221
2222 #if defined(TARGET_PPC64)
2223 static void init_excp_970(CPUPPCState *env)
2224 {
2225 #if !defined(CONFIG_USER_ONLY)
2226 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2227 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2228 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2229 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2230 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2231 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2232 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2233 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2234 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2235 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2236 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2237 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2238 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2239 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2240 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2241 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2242 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2243 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2244 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2245 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2246 /* Hardware reset vector */
2247 env->hreset_vector = 0x0000000000000100ULL;
2248 #endif
2249 }
2250
2251 static void init_excp_POWER7(CPUPPCState *env)
2252 {
2253 #if !defined(CONFIG_USER_ONLY)
2254 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2255 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2256 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2257 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2258 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2259 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2260 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2261 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2262 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2263 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2264 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2265 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2266 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2267 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2268 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2269 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2270 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2271 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2272 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2273 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2274 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2275 /* Hardware reset vector */
2276 env->hreset_vector = 0x0000000000000100ULL;
2277 #endif
2278 }
2279
2280 static void init_excp_POWER8(CPUPPCState *env)
2281 {
2282 init_excp_POWER7(env);
2283
2284 #if !defined(CONFIG_USER_ONLY)
2285 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2286 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2287 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2288 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2289 #endif
2290 }
2291
2292 static void init_excp_POWER9(CPUPPCState *env)
2293 {
2294 init_excp_POWER8(env);
2295
2296 #if !defined(CONFIG_USER_ONLY)
2297 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2298 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2299 #endif
2300 }
2301
2302 static void init_excp_POWER10(CPUPPCState *env)
2303 {
2304 init_excp_POWER9(env);
2305 }
2306
2307 #endif
2308
2309 /*****************************************************************************/
2310 /* Power management enable checks */
2311 static int check_pow_none(CPUPPCState *env)
2312 {
2313 return 0;
2314 }
2315
2316 static int check_pow_nocheck(CPUPPCState *env)
2317 {
2318 return 1;
2319 }
2320
2321 static int check_pow_hid0(CPUPPCState *env)
2322 {
2323 if (env->spr[SPR_HID0] & 0x00E00000) {
2324 return 1;
2325 }
2326
2327 return 0;
2328 }
2329
2330 static int check_pow_hid0_74xx(CPUPPCState *env)
2331 {
2332 if (env->spr[SPR_HID0] & 0x00600000) {
2333 return 1;
2334 }
2335
2336 return 0;
2337 }
2338
2339 /*****************************************************************************/
2340 /* PowerPC implementations definitions */
2341
2342 #define POWERPC_FAMILY(_name) \
2343 static void \
2344 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2345 \
2346 static const TypeInfo \
2347 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2348 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2349 .parent = TYPE_POWERPC_CPU, \
2350 .abstract = true, \
2351 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2352 }; \
2353 \
2354 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2355 { \
2356 type_register_static( \
2357 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2358 } \
2359 \
2360 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2361 \
2362 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2363
2364 static void init_proc_405(CPUPPCState *env)
2365 {
2366 register_40x_sprs(env);
2367 register_405_sprs(env);
2368 register_usprgh_sprs(env);
2369
2370 /* Memory management */
2371 #if !defined(CONFIG_USER_ONLY)
2372 env->nb_tlb = 64;
2373 env->nb_ways = 1;
2374 env->id_tlbs = 0;
2375 env->tlb_type = TLB_EMB;
2376 #endif
2377 init_excp_4xx_softmmu(env);
2378 env->dcache_line_size = 32;
2379 env->icache_line_size = 32;
2380 /* Allocate hardware IRQ controller */
2381 ppc40x_irq_init(env_archcpu(env));
2382
2383 SET_FIT_PERIOD(8, 12, 16, 20);
2384 SET_WDT_PERIOD(16, 20, 24, 28);
2385 }
2386
2387 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2388 {
2389 DeviceClass *dc = DEVICE_CLASS(oc);
2390 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2391
2392 dc->desc = "PowerPC 405";
2393 pcc->init_proc = init_proc_405;
2394 pcc->check_pow = check_pow_nocheck;
2395 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2396 PPC_DCR | PPC_WRTEE |
2397 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2398 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2399 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2400 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2401 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2402 pcc->msr_mask = (1ull << MSR_WE) |
2403 (1ull << MSR_CE) |
2404 (1ull << MSR_EE) |
2405 (1ull << MSR_PR) |
2406 (1ull << MSR_FP) |
2407 (1ull << MSR_ME) |
2408 (1ull << MSR_DWE) |
2409 (1ull << MSR_DE) |
2410 (1ull << MSR_IR) |
2411 (1ull << MSR_DR);
2412 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2413 pcc->excp_model = POWERPC_EXCP_40x;
2414 pcc->bus_model = PPC_FLAGS_INPUT_405;
2415 pcc->bfd_mach = bfd_mach_ppc_403;
2416 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2417 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2418 }
2419
2420 static void init_proc_440EP(CPUPPCState *env)
2421 {
2422 register_BookE_sprs(env, 0x000000000000FFFFULL);
2423 register_440_sprs(env);
2424 register_usprgh_sprs(env);
2425 /* Processor identification */
2426 spr_register(env, SPR_BOOKE_PIR, "PIR",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_pir,
2429 0x00000000);
2430
2431 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435
2436 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440
2441 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445
2446 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450
2451 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2460 SPR_NOACCESS, SPR_NOACCESS,
2461 &spr_read_generic, &spr_write_generic,
2462 0x00000000);
2463
2464 spr_register(env, SPR_440_CCR1, "CCR1",
2465 SPR_NOACCESS, SPR_NOACCESS,
2466 &spr_read_generic, &spr_write_generic,
2467 0x00000000);
2468 /* Memory management */
2469 #if !defined(CONFIG_USER_ONLY)
2470 env->nb_tlb = 64;
2471 env->nb_ways = 1;
2472 env->id_tlbs = 0;
2473 env->tlb_type = TLB_EMB;
2474 #endif
2475 init_excp_BookE(env);
2476 env->dcache_line_size = 32;
2477 env->icache_line_size = 32;
2478 ppc40x_irq_init(env_archcpu(env));
2479
2480 SET_FIT_PERIOD(12, 16, 20, 24);
2481 SET_WDT_PERIOD(20, 24, 28, 32);
2482 }
2483
2484 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2485 {
2486 DeviceClass *dc = DEVICE_CLASS(oc);
2487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2488
2489 dc->desc = "PowerPC 440 EP";
2490 pcc->init_proc = init_proc_440EP;
2491 pcc->check_pow = check_pow_nocheck;
2492 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2493 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2494 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2495 PPC_FLOAT_STFIWX |
2496 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2497 PPC_CACHE | PPC_CACHE_ICBI |
2498 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2499 PPC_MEM_TLBSYNC | PPC_MFTB |
2500 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2501 PPC_440_SPEC;
2502 pcc->msr_mask = (1ull << MSR_POW) |
2503 (1ull << MSR_CE) |
2504 (1ull << MSR_EE) |
2505 (1ull << MSR_PR) |
2506 (1ull << MSR_FP) |
2507 (1ull << MSR_ME) |
2508 (1ull << MSR_FE0) |
2509 (1ull << MSR_DWE) |
2510 (1ull << MSR_DE) |
2511 (1ull << MSR_FE1) |
2512 (1ull << MSR_IR) |
2513 (1ull << MSR_DR);
2514 pcc->mmu_model = POWERPC_MMU_BOOKE;
2515 pcc->excp_model = POWERPC_EXCP_BOOKE;
2516 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2517 pcc->bfd_mach = bfd_mach_ppc_403;
2518 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2519 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2520 }
2521
2522 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2523 {
2524 DeviceClass *dc = DEVICE_CLASS(oc);
2525 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2526
2527 dc->desc = "PowerPC 460 EX";
2528 pcc->init_proc = init_proc_440EP;
2529 pcc->check_pow = check_pow_nocheck;
2530 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2531 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2532 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2533 PPC_FLOAT_STFIWX |
2534 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2535 PPC_CACHE | PPC_CACHE_ICBI |
2536 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2537 PPC_MEM_TLBSYNC | PPC_MFTB |
2538 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2539 PPC_440_SPEC;
2540 pcc->msr_mask = (1ull << MSR_POW) |
2541 (1ull << MSR_CE) |
2542 (1ull << MSR_EE) |
2543 (1ull << MSR_PR) |
2544 (1ull << MSR_FP) |
2545 (1ull << MSR_ME) |
2546 (1ull << MSR_FE0) |
2547 (1ull << MSR_DWE) |
2548 (1ull << MSR_DE) |
2549 (1ull << MSR_FE1) |
2550 (1ull << MSR_IR) |
2551 (1ull << MSR_DR);
2552 pcc->mmu_model = POWERPC_MMU_BOOKE;
2553 pcc->excp_model = POWERPC_EXCP_BOOKE;
2554 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2555 pcc->bfd_mach = bfd_mach_ppc_403;
2556 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2557 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2558 }
2559
2560 static void init_proc_440GP(CPUPPCState *env)
2561 {
2562 register_BookE_sprs(env, 0x000000000000FFFFULL);
2563 register_440_sprs(env);
2564 register_usprgh_sprs(env);
2565 /* Processor identification */
2566 spr_register(env, SPR_BOOKE_PIR, "PIR",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_pir,
2569 0x00000000);
2570
2571 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575
2576 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580
2581 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585
2586 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* Memory management */
2591 #if !defined(CONFIG_USER_ONLY)
2592 env->nb_tlb = 64;
2593 env->nb_ways = 1;
2594 env->id_tlbs = 0;
2595 env->tlb_type = TLB_EMB;
2596 #endif
2597 init_excp_BookE(env);
2598 env->dcache_line_size = 32;
2599 env->icache_line_size = 32;
2600 /* XXX: TODO: allocate internal IRQ controller */
2601
2602 SET_FIT_PERIOD(12, 16, 20, 24);
2603 SET_WDT_PERIOD(20, 24, 28, 32);
2604 }
2605
2606 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2607 {
2608 DeviceClass *dc = DEVICE_CLASS(oc);
2609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2610
2611 dc->desc = "PowerPC 440 GP";
2612 pcc->init_proc = init_proc_440GP;
2613 pcc->check_pow = check_pow_nocheck;
2614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2615 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2616 PPC_CACHE | PPC_CACHE_ICBI |
2617 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2618 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2619 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2620 PPC_440_SPEC;
2621 pcc->msr_mask = (1ull << MSR_POW) |
2622 (1ull << MSR_CE) |
2623 (1ull << MSR_EE) |
2624 (1ull << MSR_PR) |
2625 (1ull << MSR_FP) |
2626 (1ull << MSR_ME) |
2627 (1ull << MSR_FE0) |
2628 (1ull << MSR_DWE) |
2629 (1ull << MSR_DE) |
2630 (1ull << MSR_FE1) |
2631 (1ull << MSR_IR) |
2632 (1ull << MSR_DR);
2633 pcc->mmu_model = POWERPC_MMU_BOOKE;
2634 pcc->excp_model = POWERPC_EXCP_BOOKE;
2635 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2636 pcc->bfd_mach = bfd_mach_ppc_403;
2637 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2638 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2639 }
2640
2641 static void init_proc_440x5(CPUPPCState *env)
2642 {
2643 register_BookE_sprs(env, 0x000000000000FFFFULL);
2644 register_440_sprs(env);
2645 register_usprgh_sprs(env);
2646 /* Processor identification */
2647 spr_register(env, SPR_BOOKE_PIR, "PIR",
2648 SPR_NOACCESS, SPR_NOACCESS,
2649 &spr_read_generic, &spr_write_pir,
2650 0x00000000);
2651
2652 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2653 SPR_NOACCESS, SPR_NOACCESS,
2654 &spr_read_generic, &spr_write_generic,
2655 0x00000000);
2656
2657 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2658 SPR_NOACCESS, SPR_NOACCESS,
2659 &spr_read_generic, &spr_write_generic,
2660 0x00000000);
2661
2662 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2663 SPR_NOACCESS, SPR_NOACCESS,
2664 &spr_read_generic, &spr_write_generic,
2665 0x00000000);
2666
2667 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2668 SPR_NOACCESS, SPR_NOACCESS,
2669 &spr_read_generic, &spr_write_generic,
2670 0x00000000);
2671
2672 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2673 SPR_NOACCESS, SPR_NOACCESS,
2674 &spr_read_generic, &spr_write_generic,
2675 0x00000000);
2676 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2677 SPR_NOACCESS, SPR_NOACCESS,
2678 &spr_read_generic, &spr_write_generic,
2679 0x00000000);
2680 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2681 SPR_NOACCESS, SPR_NOACCESS,
2682 &spr_read_generic, &spr_write_generic,
2683 0x00000000);
2684
2685 spr_register(env, SPR_440_CCR1, "CCR1",
2686 SPR_NOACCESS, SPR_NOACCESS,
2687 &spr_read_generic, &spr_write_generic,
2688 0x00000000);
2689 /* Memory management */
2690 #if !defined(CONFIG_USER_ONLY)
2691 env->nb_tlb = 64;
2692 env->nb_ways = 1;
2693 env->id_tlbs = 0;
2694 env->tlb_type = TLB_EMB;
2695 #endif
2696 init_excp_BookE(env);
2697 env->dcache_line_size = 32;
2698 env->icache_line_size = 32;
2699 ppc40x_irq_init(env_archcpu(env));
2700
2701 SET_FIT_PERIOD(12, 16, 20, 24);
2702 SET_WDT_PERIOD(20, 24, 28, 32);
2703 }
2704
2705 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2706 {
2707 DeviceClass *dc = DEVICE_CLASS(oc);
2708 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2709
2710 dc->desc = "PowerPC 440x5";
2711 pcc->init_proc = init_proc_440x5;
2712 pcc->check_pow = check_pow_nocheck;
2713 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2714 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2715 PPC_CACHE | PPC_CACHE_ICBI |
2716 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2717 PPC_MEM_TLBSYNC | PPC_MFTB |
2718 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2719 PPC_440_SPEC;
2720 pcc->msr_mask = (1ull << MSR_POW) |
2721 (1ull << MSR_CE) |
2722 (1ull << MSR_EE) |
2723 (1ull << MSR_PR) |
2724 (1ull << MSR_FP) |
2725 (1ull << MSR_ME) |
2726 (1ull << MSR_FE0) |
2727 (1ull << MSR_DWE) |
2728 (1ull << MSR_DE) |
2729 (1ull << MSR_FE1) |
2730 (1ull << MSR_IR) |
2731 (1ull << MSR_DR);
2732 pcc->mmu_model = POWERPC_MMU_BOOKE;
2733 pcc->excp_model = POWERPC_EXCP_BOOKE;
2734 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2735 pcc->bfd_mach = bfd_mach_ppc_403;
2736 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2737 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2738 }
2739
2740 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2741 {
2742 DeviceClass *dc = DEVICE_CLASS(oc);
2743 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2744
2745 dc->desc = "PowerPC 440x5 with double precision FPU";
2746 pcc->init_proc = init_proc_440x5;
2747 pcc->check_pow = check_pow_nocheck;
2748 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2749 PPC_FLOAT | PPC_FLOAT_FSQRT |
2750 PPC_FLOAT_STFIWX |
2751 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2752 PPC_CACHE | PPC_CACHE_ICBI |
2753 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2754 PPC_MEM_TLBSYNC | PPC_MFTB |
2755 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2756 PPC_440_SPEC;
2757 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2758 pcc->msr_mask = (1ull << MSR_POW) |
2759 (1ull << MSR_CE) |
2760 (1ull << MSR_EE) |
2761 (1ull << MSR_PR) |
2762 (1ull << MSR_FP) |
2763 (1ull << MSR_ME) |
2764 (1ull << MSR_FE0) |
2765 (1ull << MSR_DWE) |
2766 (1ull << MSR_DE) |
2767 (1ull << MSR_FE1) |
2768 (1ull << MSR_IR) |
2769 (1ull << MSR_DR);
2770 pcc->mmu_model = POWERPC_MMU_BOOKE;
2771 pcc->excp_model = POWERPC_EXCP_BOOKE;
2772 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2773 pcc->bfd_mach = bfd_mach_ppc_403;
2774 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2775 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2776 }
2777
2778 static void init_proc_MPC5xx(CPUPPCState *env)
2779 {
2780 register_5xx_8xx_sprs(env);
2781 register_5xx_sprs(env);
2782 init_excp_MPC5xx(env);
2783 env->dcache_line_size = 32;
2784 env->icache_line_size = 32;
2785 /* XXX: TODO: allocate internal IRQ controller */
2786 }
2787
2788 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2789 {
2790 DeviceClass *dc = DEVICE_CLASS(oc);
2791 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2792
2793 dc->desc = "Freescale 5xx cores (aka RCPU)";
2794 pcc->init_proc = init_proc_MPC5xx;
2795 pcc->check_pow = check_pow_none;
2796 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2797 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2798 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2799 PPC_MFTB;
2800 pcc->msr_mask = (1ull << MSR_ILE) |
2801 (1ull << MSR_EE) |
2802 (1ull << MSR_PR) |
2803 (1ull << MSR_FP) |
2804 (1ull << MSR_ME) |
2805 (1ull << MSR_FE0) |
2806 (1ull << MSR_SE) |
2807 (1ull << MSR_DE) |
2808 (1ull << MSR_FE1) |
2809 (1ull << MSR_EP) |
2810 (1ull << MSR_RI) |
2811 (1ull << MSR_LE);
2812 pcc->mmu_model = POWERPC_MMU_REAL;
2813 pcc->excp_model = POWERPC_EXCP_6xx;
2814 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2815 pcc->bfd_mach = bfd_mach_ppc_505;
2816 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2817 POWERPC_FLAG_BUS_CLK;
2818 }
2819
2820 static void init_proc_MPC8xx(CPUPPCState *env)
2821 {
2822 register_5xx_8xx_sprs(env);
2823 register_8xx_sprs(env);
2824 init_excp_MPC8xx(env);
2825 env->dcache_line_size = 32;
2826 env->icache_line_size = 32;
2827 /* XXX: TODO: allocate internal IRQ controller */
2828 }
2829
2830 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2831 {
2832 DeviceClass *dc = DEVICE_CLASS(oc);
2833 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2834
2835 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2836 pcc->init_proc = init_proc_MPC8xx;
2837 pcc->check_pow = check_pow_none;
2838 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2839 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2840 PPC_CACHE_ICBI | PPC_MFTB;
2841 pcc->msr_mask = (1ull << MSR_ILE) |
2842 (1ull << MSR_EE) |
2843 (1ull << MSR_PR) |
2844 (1ull << MSR_FP) |
2845 (1ull << MSR_ME) |
2846 (1ull << MSR_SE) |
2847 (1ull << MSR_DE) |
2848 (1ull << MSR_EP) |
2849 (1ull << MSR_IR) |
2850 (1ull << MSR_DR) |
2851 (1ull << MSR_RI) |
2852 (1ull << MSR_LE);
2853 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2854 pcc->excp_model = POWERPC_EXCP_6xx;
2855 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2856 pcc->bfd_mach = bfd_mach_ppc_860;
2857 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2858 POWERPC_FLAG_BUS_CLK;
2859 }
2860
2861 /* Freescale 82xx cores (aka PowerQUICC-II) */
2862
2863 static void init_proc_G2(CPUPPCState *env)
2864 {
2865 register_ne_601_sprs(env);
2866 register_sdr1_sprs(env);
2867 register_G2_sprs(env);
2868
2869 /* Memory management */
2870 register_low_BATs(env);
2871 register_high_BATs(env);
2872 register_6xx_7xx_soft_tlb(env, 64, 2);
2873 init_excp_G2(env);
2874 env->dcache_line_size = 32;
2875 env->icache_line_size = 32;
2876 /* Allocate hardware IRQ controller */
2877 ppc6xx_irq_init(env_archcpu(env));
2878 }
2879
2880 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2881 {
2882 DeviceClass *dc = DEVICE_CLASS(oc);
2883 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2884
2885 dc->desc = "PowerPC G2";
2886 pcc->init_proc = init_proc_G2;
2887 pcc->check_pow = check_pow_hid0;
2888 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2890 PPC_FLOAT_STFIWX |
2891 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2892 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2893 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2894 PPC_SEGMENT | PPC_EXTERN;
2895 pcc->msr_mask = (1ull << MSR_POW) |
2896 (1ull << MSR_TGPR) |
2897 (1ull << MSR_EE) |
2898 (1ull << MSR_PR) |
2899 (1ull << MSR_FP) |
2900 (1ull << MSR_ME) |
2901 (1ull << MSR_FE0) |
2902 (1ull << MSR_SE) |
2903 (1ull << MSR_DE) |
2904 (1ull << MSR_FE1) |
2905 (1ull << MSR_AL) |
2906 (1ull << MSR_EP) |
2907 (1ull << MSR_IR) |
2908 (1ull << MSR_DR) |
2909 (1ull << MSR_RI);
2910 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2911 pcc->excp_model = POWERPC_EXCP_6xx;
2912 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2913 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2914 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2915 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2916 }
2917
2918 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2919 {
2920 DeviceClass *dc = DEVICE_CLASS(oc);
2921 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2922
2923 dc->desc = "PowerPC G2LE";
2924 pcc->init_proc = init_proc_G2;
2925 pcc->check_pow = check_pow_hid0;
2926 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2927 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2928 PPC_FLOAT_STFIWX |
2929 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2930 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2931 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2932 PPC_SEGMENT | PPC_EXTERN;
2933 pcc->msr_mask = (1ull << MSR_POW) |
2934 (1ull << MSR_TGPR) |
2935 (1ull << MSR_ILE) |
2936 (1ull << MSR_EE) |
2937 (1ull << MSR_PR) |
2938 (1ull << MSR_FP) |
2939 (1ull << MSR_ME) |
2940 (1ull << MSR_FE0) |
2941 (1ull << MSR_SE) |
2942 (1ull << MSR_DE) |
2943 (1ull << MSR_FE1) |
2944 (1ull << MSR_AL) |
2945 (1ull << MSR_EP) |
2946 (1ull << MSR_IR) |
2947 (1ull << MSR_DR) |
2948 (1ull << MSR_RI) |
2949 (1ull << MSR_LE);
2950 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2951 pcc->excp_model = POWERPC_EXCP_6xx;
2952 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2953 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2954 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2955 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2956 }
2957
2958 static void init_proc_e200(CPUPPCState *env)
2959 {
2960 register_BookE_sprs(env, 0x000000070000FFFFULL);
2961
2962 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2963 &spr_read_spefscr, &spr_write_spefscr,
2964 &spr_read_spefscr, &spr_write_spefscr,
2965 0x00000000);
2966 /* Memory management */
2967 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2968 register_usprgh_sprs(env);
2969
2970 spr_register(env, SPR_HID0, "HID0",
2971 SPR_NOACCESS, SPR_NOACCESS,
2972 &spr_read_generic, &spr_write_generic,
2973 0x00000000);
2974
2975 spr_register(env, SPR_HID1, "HID1",
2976 SPR_NOACCESS, SPR_NOACCESS,
2977 &spr_read_generic, &spr_write_generic,
2978 0x00000000);
2979
2980 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2981 SPR_NOACCESS, SPR_NOACCESS,
2982 &spr_read_generic, &spr_write_generic,
2983 0x00000000);
2984
2985 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2986 SPR_NOACCESS, SPR_NOACCESS,
2987 &spr_read_generic, &spr_write_generic,
2988 0x00000000);
2989
2990 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2991 SPR_NOACCESS, SPR_NOACCESS,
2992 &spr_read_generic, &spr_write_generic,
2993 0x00000000);
2994
2995 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2996 SPR_NOACCESS, SPR_NOACCESS,
2997 &spr_read_generic, &spr_write_generic,
2998 0x00000000);
2999
3000 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3001 SPR_NOACCESS, SPR_NOACCESS,
3002 &spr_read_generic, &spr_write_generic,
3003 0x00000000);
3004
3005 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3006 &spr_read_generic, SPR_NOACCESS,
3007 &spr_read_generic, SPR_NOACCESS,
3008 0x00000000);
3009
3010 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3011 SPR_NOACCESS, SPR_NOACCESS,
3012 &spr_read_generic, &spr_write_generic,
3013 0x00000000);
3014
3015 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3016 SPR_NOACCESS, SPR_NOACCESS,
3017 &spr_read_generic, &spr_write_generic,
3018 0x00000000);
3019
3020 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3021 SPR_NOACCESS, SPR_NOACCESS,
3022 &spr_read_generic, &spr_write_generic,
3023 0x00000000);
3024
3025 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3026 SPR_NOACCESS, SPR_NOACCESS,
3027 &spr_read_generic, &spr_write_generic,
3028 0x00000000);
3029
3030 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3031 SPR_NOACCESS, SPR_NOACCESS,
3032 &spr_read_generic, &spr_write_generic,
3033 0x00000000);
3034
3035 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3036 SPR_NOACCESS, SPR_NOACCESS,
3037 &spr_read_generic, &spr_write_generic,
3038 0x00000000);
3039
3040 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3041 SPR_NOACCESS, SPR_NOACCESS,
3042 &spr_read_generic, &spr_write_generic,
3043 0x00000000); /* TOFIX */
3044 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3045 SPR_NOACCESS, SPR_NOACCESS,
3046 &spr_read_generic, &spr_write_generic,
3047 0x00000000);
3048 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3049 SPR_NOACCESS, SPR_NOACCESS,
3050 &spr_read_generic, &spr_write_generic,
3051 0x00000000);
3052 #if !defined(CONFIG_USER_ONLY)
3053 env->nb_tlb = 64;
3054 env->nb_ways = 1;
3055 env->id_tlbs = 0;
3056 env->tlb_type = TLB_EMB;
3057 #endif
3058 init_excp_e200(env, 0xFFFF0000UL);
3059 env->dcache_line_size = 32;
3060 env->icache_line_size = 32;
3061 /* XXX: TODO: allocate internal IRQ controller */
3062 }
3063
3064 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3065 {
3066 DeviceClass *dc = DEVICE_CLASS(oc);
3067 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3068
3069 dc->desc = "e200 core";
3070 pcc->init_proc = init_proc_e200;
3071 pcc->check_pow = check_pow_hid0;
3072 /*
3073 * XXX: unimplemented instructions:
3074 * dcblc
3075 * dcbtlst
3076 * dcbtstls
3077 * icblc
3078 * icbtls
3079 * tlbivax
3080 * all SPE multiply-accumulate instructions
3081 */
3082 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3083 PPC_SPE | PPC_SPE_SINGLE |
3084 PPC_WRTEE | PPC_RFDI |
3085 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3086 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3087 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3088 PPC_BOOKE;
3089 pcc->msr_mask = (1ull << MSR_UCLE) |
3090 (1ull << MSR_SPE) |
3091 (1ull << MSR_POW) |
3092 (1ull << MSR_CE) |
3093 (1ull << MSR_EE) |
3094 (1ull << MSR_PR) |
3095 (1ull << MSR_FP) |
3096 (1ull << MSR_ME) |
3097 (1ull << MSR_FE0) |
3098 (1ull << MSR_DWE) |
3099 (1ull << MSR_DE) |
3100 (1ull << MSR_FE1) |
3101 (1ull << MSR_IR) |
3102 (1ull << MSR_DR);
3103 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3104 pcc->excp_model = POWERPC_EXCP_BOOKE;
3105 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3106 pcc->bfd_mach = bfd_mach_ppc_860;
3107 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3108 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3109 POWERPC_FLAG_BUS_CLK;
3110 }
3111
3112 static void init_proc_e300(CPUPPCState *env)
3113 {
3114 register_ne_601_sprs(env);
3115 register_sdr1_sprs(env);
3116 register_603_sprs(env);
3117 /* hardware implementation registers */
3118 spr_register(env, SPR_HID0, "HID0",
3119 SPR_NOACCESS, SPR_NOACCESS,
3120 &spr_read_generic, &spr_write_generic,
3121 0x00000000);
3122
3123 spr_register(env, SPR_HID1, "HID1",
3124 SPR_NOACCESS, SPR_NOACCESS,
3125 &spr_read_generic, &spr_write_generic,
3126 0x00000000);
3127
3128 spr_register(env, SPR_HID2, "HID2",
3129 SPR_NOACCESS, SPR_NOACCESS,
3130 &spr_read_generic, &spr_write_generic,
3131 0x00000000);
3132 /* Breakpoints */
3133 spr_register(env, SPR_DABR, "DABR",
3134 SPR_NOACCESS, SPR_NOACCESS,
3135 &spr_read_generic, &spr_write_generic,
3136 0x00000000);
3137
3138 spr_register(env, SPR_DABR2, "DABR2",
3139 SPR_NOACCESS, SPR_NOACCESS,
3140 &spr_read_generic, &spr_write_generic,
3141 0x00000000);
3142
3143 spr_register(env, SPR_IABR2, "IABR2",
3144 SPR_NOACCESS, SPR_NOACCESS,
3145 &spr_read_generic, &spr_write_generic,
3146 0x00000000);
3147
3148 spr_register(env, SPR_IBCR, "IBCR",
3149 SPR_NOACCESS, SPR_NOACCESS,
3150 &spr_read_generic, &spr_write_generic,
3151 0x00000000);
3152
3153 spr_register(env, SPR_DBCR, "DBCR",
3154 SPR_NOACCESS, SPR_NOACCESS,
3155 &spr_read_generic, &spr_write_generic,
3156 0x00000000);
3157 /* Memory management */
3158 register_low_BATs(env);
3159 register_high_BATs(env);
3160 register_6xx_7xx_soft_tlb(env, 64, 2);
3161 init_excp_603(env);
3162 env->dcache_line_size = 32;
3163 env->icache_line_size = 32;
3164 /* Allocate hardware IRQ controller */
3165 ppc6xx_irq_init(env_archcpu(env));
3166 }
3167
3168 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3169 {
3170 DeviceClass *dc = DEVICE_CLASS(oc);
3171 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3172
3173 dc->desc = "e300 core";
3174 pcc->init_proc = init_proc_e300;
3175 pcc->check_pow = check_pow_hid0;
3176 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3177 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3178 PPC_FLOAT_STFIWX |
3179 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3180 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3181 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3182 PPC_SEGMENT | PPC_EXTERN;
3183 pcc->msr_mask = (1ull << MSR_POW) |
3184 (1ull << MSR_TGPR) |
3185 (1ull << MSR_ILE) |
3186 (1ull << MSR_EE) |
3187 (1ull << MSR_PR) |
3188 (1ull << MSR_FP) |
3189 (1ull << MSR_ME) |
3190 (1ull << MSR_FE0) |
3191 (1ull << MSR_SE) |
3192 (1ull << MSR_DE) |
3193 (1ull << MSR_FE1) |
3194 (1ull << MSR_AL) |
3195 (1ull << MSR_EP) |
3196 (1ull << MSR_IR) |
3197 (1ull << MSR_DR) |
3198 (1ull << MSR_RI) |
3199 (1ull << MSR_LE);
3200 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3201 pcc->excp_model = POWERPC_EXCP_6xx;
3202 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3203 pcc->bfd_mach = bfd_mach_ppc_603;
3204 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3205 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3206 }
3207
3208 enum fsl_e500_version {
3209 fsl_e500v1,
3210 fsl_e500v2,
3211 fsl_e500mc,
3212 fsl_e5500,
3213 fsl_e6500,
3214 };
3215
3216 static void init_proc_e500(CPUPPCState *env, int version)
3217 {
3218 uint32_t tlbncfg[2];
3219 uint64_t ivor_mask;
3220 uint64_t ivpr_mask = 0xFFFF0000ULL;
3221 uint32_t l1cfg0 = 0x3800 /* 8 ways */
3222 | 0x0020; /* 32 kb */
3223 uint32_t l1cfg1 = 0x3800 /* 8 ways */
3224 | 0x0020; /* 32 kb */
3225 uint32_t mmucfg = 0;
3226 #if !defined(CONFIG_USER_ONLY)
3227 int i;
3228 #endif
3229
3230 /*
3231 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
3232 * complain when accessing them.
3233 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
3234 */
3235 switch (version) {
3236 case fsl_e500v1:
3237 case fsl_e500v2:
3238 default:
3239 ivor_mask = 0x0000000F0000FFFFULL;
3240 break;
3241 case fsl_e500mc:
3242 case fsl_e5500:
3243 ivor_mask = 0x000003FE0000FFFFULL;
3244 break;
3245 case fsl_e6500:
3246 ivor_mask = 0x000003FF0000FFFFULL;
3247 break;
3248 }
3249 register_BookE_sprs(env, ivor_mask);
3250 register_usprg3_sprs(env);
3251 /* Processor identification */
3252 spr_register(env, SPR_BOOKE_PIR, "PIR",
3253 SPR_NOACCESS, SPR_NOACCESS,
3254 &spr_read_generic, &spr_write_pir,
3255 0x00000000);
3256
3257 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3258 &spr_read_spefscr, &spr_write_spefscr,
3259 &spr_read_spefscr, &spr_write_spefscr,
3260 0x00000000);
3261 #if !defined(CONFIG_USER_ONLY)
3262 /* Memory management */
3263 env->nb_pids = 3;
3264 env->nb_ways = 2;
3265 env->id_tlbs = 0;
3266 switch (version) {
3267 case fsl_e500v1:
3268 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
3269 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3270 break;
3271 case fsl_e500v2:
3272 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3273 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3274 break;
3275 case fsl_e500mc:
3276 case fsl_e5500:
3277 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3278 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
3279 break;
3280 case fsl_e6500:
3281 mmucfg = 0x6510B45;
3282 env->nb_pids = 1;
3283 tlbncfg[0] = 0x08052400;
3284 tlbncfg[1] = 0x40028040;
3285 break;
3286 default:
3287 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3288 env->spr[SPR_PVR]);
3289 }
3290 #endif
3291 /* Cache sizes */
3292 switch (version) {
3293 case fsl_e500v1:
3294 case fsl_e500v2:
3295 env->dcache_line_size = 32;
3296 env->icache_line_size = 32;
3297 break;
3298 case fsl_e500mc:
3299 case fsl_e5500:
3300 env->dcache_line_size = 64;
3301 env->icache_line_size = 64;
3302 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
3303 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
3304 break;
3305 case fsl_e6500:
3306 env->dcache_line_size = 32;
3307 env->icache_line_size = 32;
3308 l1cfg0 |= 0x0F83820;
3309 l1cfg1 |= 0x0B83820;
3310 break;
3311 default:
3312 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3313 env->spr[SPR_PVR]);
3314 }
3315 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
3316 register_usprgh_sprs(env);
3317
3318 spr_register(env, SPR_HID0, "HID0",
3319 SPR_NOACCESS, SPR_NOACCESS,
3320 &spr_read_generic, &spr_write_generic,
3321 0x00000000);
3322
3323 spr_register(env, SPR_HID1, "HID1",
3324 SPR_NOACCESS, SPR_NOACCESS,
3325 &spr_read_generic, &spr_write_generic,
3326 0x00000000);
3327
3328 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
3329 SPR_NOACCESS, SPR_NOACCESS,
3330 &spr_read_generic, &spr_write_generic,
3331 0x00000000);
3332
3333 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
3334 SPR_NOACCESS, SPR_NOACCESS,
3335 &spr_read_generic, &spr_write_generic,
3336 0x00000000);
3337
3338 spr_register(env, SPR_Exxx_MCAR, "MCAR",
3339 SPR_NOACCESS, SPR_NOACCESS,
3340 &spr_read_generic, &spr_write_generic,
3341 0x00000000);
3342
3343 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3344 SPR_NOACCESS, SPR_NOACCESS,
3345 &spr_read_generic, &spr_write_generic,
3346 0x00000000);
3347
3348 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
3349 SPR_NOACCESS, SPR_NOACCESS,
3350 &spr_read_generic, &spr_write_generic,
3351 0x00000000);
3352
3353 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3354 SPR_NOACCESS, SPR_NOACCESS,
3355 &spr_read_generic, &spr_write_generic,
3356 0x00000000);
3357
3358 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3359 &spr_read_generic, SPR_NOACCESS,
3360 &spr_read_generic, SPR_NOACCESS,
3361 l1cfg0);
3362 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
3363 &spr_read_generic, SPR_NOACCESS,
3364 &spr_read_generic, SPR_NOACCESS,
3365 l1cfg1);
3366 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3367 SPR_NOACCESS, SPR_NOACCESS,
3368 &spr_read_generic, &spr_write_e500_l1csr0,
3369 0x00000000);
3370 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
3371 SPR_NOACCESS, SPR_NOACCESS,
3372 &spr_read_generic, &spr_write_e500_l1csr1,
3373 0x00000000);
3374 if (version != fsl_e500v1 && version != fsl_e500v2) {
3375 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
3376 SPR_NOACCESS, SPR_NOACCESS,
3377 &spr_read_generic, &spr_write_e500_l2csr0,
3378 0x00000000);
3379 }
3380 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3381 SPR_NOACCESS, SPR_NOACCESS,
3382 &spr_read_generic, &spr_write_generic,
3383 0x00000000);
3384 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3385 SPR_NOACCESS, SPR_NOACCESS,
3386 &spr_read_generic, &spr_write_generic,
3387 0x00000000);
3388 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3389 SPR_NOACCESS, SPR_NOACCESS,
3390 &spr_read_generic, &spr_write_booke206_mmucsr0,
3391 0x00000000);
3392 spr_register(env, SPR_BOOKE_EPR, "EPR",
3393 SPR_NOACCESS, SPR_NOACCESS,
3394 &spr_read_generic, SPR_NOACCESS,
3395 0x00000000);
3396 /* XXX better abstract into Emb.xxx features */
3397 if ((version == fsl_e5500) || (version == fsl_e6500)) {
3398 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
3399 SPR_NOACCESS, SPR_NOACCESS,
3400 &spr_read_generic, &spr_write_generic,
3401 0x00000000);
3402 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
3403 SPR_NOACCESS, SPR_NOACCESS,
3404 &spr_read_mas73, &spr_write_mas73,
3405 0x00000000);
3406 ivpr_mask = (target_ulong)~0xFFFFULL;
3407 }
3408
3409 if (version == fsl_e6500) {
3410 /* Thread identification */
3411 spr_register(env, SPR_TIR, "TIR",
3412 SPR_NOACCESS, SPR_NOACCESS,
3413 &spr_read_generic, SPR_NOACCESS,
3414 0x00000000);
3415 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3416 SPR_NOACCESS, SPR_NOACCESS,
3417 &spr_read_generic, SPR_NOACCESS,
3418 0x00000004);
3419 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3420 SPR_NOACCESS, SPR_NOACCESS,
3421 &spr_read_generic, SPR_NOACCESS,
3422 0x7FFFFFFC);
3423 }
3424
3425 #if !defined(CONFIG_USER_ONLY)
3426 env->nb_tlb = 0;
3427 env->tlb_type = TLB_MAS;
3428 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3429 env->nb_tlb += booke206_tlb_size(env, i);
3430 }
3431 #endif
3432
3433 init_excp_e200(env, ivpr_mask);
3434 /* Allocate hardware IRQ controller */
3435 ppce500_irq_init(env_archcpu(env));
3436 }
3437
3438 static void init_proc_e500v1(CPUPPCState *env)
3439 {
3440 init_proc_e500(env, fsl_e500v1);
3441 }
3442
3443 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3444 {
3445 DeviceClass *dc = DEVICE_CLASS(oc);
3446 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3447
3448 dc->desc = "e500v1 core";
3449 pcc->init_proc = init_proc_e500v1;
3450 pcc->check_pow = check_pow_hid0;
3451 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3452 PPC_SPE | PPC_SPE_SINGLE |
3453 PPC_WRTEE | PPC_RFDI |
3454 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3455 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3456 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3457 pcc->insns_flags2 = PPC2_BOOKE206;
3458 pcc->msr_mask = (1ull << MSR_UCLE) |
3459 (1ull << MSR_SPE) |
3460 (1ull << MSR_POW) |
3461 (1ull << MSR_CE) |
3462 (1ull << MSR_EE) |
3463 (1ull << MSR_PR) |
3464 (1ull << MSR_FP) |
3465 (1ull << MSR_ME) |
3466 (1ull << MSR_FE0) |
3467 (1ull << MSR_DWE) |
3468 (1ull << MSR_DE) |
3469 (1ull << MSR_FE1) |
3470 (1ull << MSR_IR) |
3471 (1ull << MSR_DR);
3472 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3473 pcc->excp_model = POWERPC_EXCP_BOOKE;
3474 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3475 pcc->bfd_mach = bfd_mach_ppc_860;
3476 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3477 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3478 POWERPC_FLAG_BUS_CLK;
3479 }
3480
3481 static void init_proc_e500v2(CPUPPCState *env)
3482 {
3483 init_proc_e500(env, fsl_e500v2);
3484 }
3485
3486 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3487 {
3488 DeviceClass *dc = DEVICE_CLASS(oc);
3489 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3490
3491 dc->desc = "e500v2 core";
3492 pcc->init_proc = init_proc_e500v2;
3493 pcc->check_pow = check_pow_hid0;
3494 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3495 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3496 PPC_WRTEE | PPC_RFDI |
3497 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3498 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3499 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3500 pcc->insns_flags2 = PPC2_BOOKE206;
3501 pcc->msr_mask = (1ull << MSR_UCLE) |
3502 (1ull << MSR_SPE) |
3503 (1ull << MSR_POW) |
3504 (1ull << MSR_CE) |
3505 (1ull << MSR_EE) |
3506 (1ull << MSR_PR) |
3507 (1ull << MSR_FP) |
3508 (1ull << MSR_ME) |
3509 (1ull << MSR_FE0) |
3510 (1ull << MSR_DWE) |
3511 (1ull << MSR_DE) |
3512 (1ull << MSR_FE1) |
3513 (1ull << MSR_IR) |
3514 (1ull << MSR_DR);
3515 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3516 pcc->excp_model = POWERPC_EXCP_BOOKE;
3517 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3518 pcc->bfd_mach = bfd_mach_ppc_860;
3519 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3520 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3521 POWERPC_FLAG_BUS_CLK;
3522 }
3523
3524 static void init_proc_e500mc(CPUPPCState *env)
3525 {
3526 init_proc_e500(env, fsl_e500mc);
3527 }
3528
3529 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3530 {
3531 DeviceClass *dc = DEVICE_CLASS(oc);
3532 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3533
3534 dc->desc = "e500mc core";
3535 pcc->init_proc = init_proc_e500mc;
3536 pcc->check_pow = check_pow_none;
3537 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3538 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3539 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3540 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3541 PPC_FLOAT | PPC_FLOAT_FRES |
3542 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3543 PPC_FLOAT_STFIWX | PPC_WAIT |
3544 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3545 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3546 pcc->msr_mask = (1ull << MSR_GS) |
3547 (1ull << MSR_UCLE) |
3548 (1ull << MSR_CE) |
3549 (1ull << MSR_EE) |
3550 (1ull << MSR_PR) |
3551 (1ull << MSR_FP) |
3552 (1ull << MSR_ME) |
3553 (1ull << MSR_FE0) |
3554 (1ull << MSR_DE) |
3555 (1ull << MSR_FE1) |
3556 (1ull << MSR_IR) |
3557 (1ull << MSR_DR) |
3558 (1ull << MSR_PX) |
3559 (1ull << MSR_RI);
3560 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3561 pcc->excp_model = POWERPC_EXCP_BOOKE;
3562 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3563 /* FIXME: figure out the correct flag for e500mc */
3564 pcc->bfd_mach = bfd_mach_ppc_e500;
3565 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3566 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3567 }
3568
3569 #ifdef TARGET_PPC64
3570 static void init_proc_e5500(CPUPPCState *env)
3571 {
3572 init_proc_e500(env, fsl_e5500);
3573 }
3574
3575 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3576 {
3577 DeviceClass *dc = DEVICE_CLASS(oc);
3578 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3579
3580 dc->desc = "e5500 core";
3581 pcc->init_proc = init_proc_e5500;
3582 pcc->check_pow = check_pow_none;
3583 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3584 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3585 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3586 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3587 PPC_FLOAT | PPC_FLOAT_FRES |
3588 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3589 PPC_FLOAT_STFIWX | PPC_WAIT |
3590 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3591 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3592 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3593 PPC2_FP_CVT_S64;
3594 pcc->msr_mask = (1ull << MSR_CM) |
3595 (1ull << MSR_GS) |
3596 (1ull << MSR_UCLE) |
3597 (1ull << MSR_CE) |
3598 (1ull << MSR_EE) |
3599 (1ull << MSR_PR) |
3600 (1ull << MSR_FP) |
3601 (1ull << MSR_ME) |
3602 (1ull << MSR_FE0) |
3603 (1ull << MSR_DE) |
3604 (1ull << MSR_FE1) |
3605 (1ull << MSR_IR) |
3606 (1ull << MSR_DR) |
3607 (1ull << MSR_PX) |
3608 (1ull << MSR_RI);
3609 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3610 pcc->excp_model = POWERPC_EXCP_BOOKE;
3611 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3612 /* FIXME: figure out the correct flag for e5500 */
3613 pcc->bfd_mach = bfd_mach_ppc_e500;
3614 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3615 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3616 }
3617
3618 static void init_proc_e6500(CPUPPCState *env)
3619 {
3620 init_proc_e500(env, fsl_e6500);
3621 }
3622
3623 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3624 {
3625 DeviceClass *dc = DEVICE_CLASS(oc);
3626 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3627
3628 dc->desc = "e6500 core";
3629 pcc->init_proc = init_proc_e6500;
3630 pcc->check_pow = check_pow_none;
3631 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3632 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3633 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3634 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3635 PPC_FLOAT | PPC_FLOAT_FRES |
3636 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3637 PPC_FLOAT_STFIWX | PPC_WAIT |
3638 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3639 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3640 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3641 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3642 pcc->msr_mask = (1ull << MSR_CM) |
3643 (1ull << MSR_GS) |
3644 (1ull << MSR_UCLE) |
3645 (1ull << MSR_CE) |
3646 (1ull << MSR_EE) |
3647 (1ull << MSR_PR) |
3648 (1ull << MSR_FP) |
3649 (1ull << MSR_ME) |
3650 (1ull << MSR_FE0) |
3651 (1ull << MSR_DE) |
3652 (1ull << MSR_FE1) |
3653 (1ull << MSR_IS) |
3654 (1ull << MSR_DS) |
3655 (1ull << MSR_PX) |
3656 (1ull << MSR_RI) |
3657 (1ull << MSR_VR);
3658 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3659 pcc->excp_model = POWERPC_EXCP_BOOKE;
3660 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3661 pcc->bfd_mach = bfd_mach_ppc_e500;
3662 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3663 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3664 }
3665
3666 #endif
3667
3668 /* Non-embedded PowerPC */
3669 static void init_proc_603(CPUPPCState *env)
3670 {
3671 register_ne_601_sprs(env);
3672 register_sdr1_sprs(env);
3673 register_603_sprs(env);
3674 /* hardware implementation registers */
3675 spr_register(env, SPR_HID0, "HID0",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679
3680 spr_register(env, SPR_HID1, "HID1",
3681 SPR_NOACCESS, SPR_NOACCESS,
3682 &spr_read_generic, &spr_write_generic,
3683 0x00000000);
3684 /* Memory management */
3685 register_low_BATs(env);
3686 register_6xx_7xx_soft_tlb(env, 64, 2);
3687 init_excp_603(env);
3688 env->dcache_line_size = 32;
3689 env->icache_line_size = 32;
3690 /* Allocate hardware IRQ controller */
3691 ppc6xx_irq_init(env_archcpu(env));
3692 }
3693
3694 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3695 {
3696 DeviceClass *dc = DEVICE_CLASS(oc);
3697 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3698
3699 dc->desc = "PowerPC 603";
3700 pcc->init_proc = init_proc_603;
3701 pcc->check_pow = check_pow_hid0;
3702 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3703 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3704 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3705 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3706 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3707 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3708 PPC_SEGMENT | PPC_EXTERN;
3709 pcc->msr_mask = (1ull << MSR_POW) |
3710 (1ull << MSR_TGPR) |
3711 (1ull << MSR_ILE) |
3712 (1ull << MSR_EE) |
3713 (1ull << MSR_PR) |
3714 (1ull << MSR_FP) |
3715 (1ull << MSR_ME) |
3716 (1ull << MSR_FE0) |
3717 (1ull << MSR_SE) |
3718 (1ull << MSR_DE) |
3719 (1ull << MSR_FE1) |
3720 (1ull << MSR_EP) |
3721 (1ull << MSR_IR) |
3722 (1ull << MSR_DR) |
3723 (1ull << MSR_RI) |
3724 (1ull << MSR_LE);
3725 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3726 pcc->excp_model = POWERPC_EXCP_6xx;
3727 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3728 pcc->bfd_mach = bfd_mach_ppc_603;
3729 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3730 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3731 }
3732
3733 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3734 {
3735 DeviceClass *dc = DEVICE_CLASS(oc);
3736 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3737
3738 dc->desc = "PowerPC 603e";
3739 pcc->init_proc = init_proc_603;
3740 pcc->check_pow = check_pow_hid0;
3741 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3742 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3743 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3744 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3745 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3746 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3747 PPC_SEGMENT | PPC_EXTERN;
3748 pcc->msr_mask = (1ull << MSR_POW) |
3749 (1ull << MSR_TGPR) |
3750 (1ull << MSR_ILE) |
3751 (1ull << MSR_EE) |
3752 (1ull << MSR_PR) |
3753 (1ull << MSR_FP) |
3754 (1ull << MSR_ME) |
3755 (1ull << MSR_FE0) |
3756 (1ull << MSR_SE) |
3757 (1ull << MSR_DE) |
3758 (1ull << MSR_FE1) |
3759 (1ull << MSR_EP) |
3760 (1ull << MSR_IR) |
3761 (1ull << MSR_DR) |
3762 (1ull << MSR_RI) |
3763 (1ull << MSR_LE);
3764 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3765 pcc->excp_model = POWERPC_EXCP_6xx;
3766 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3767 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3768 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3769 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3770 }
3771
3772 static void init_proc_604(CPUPPCState *env)
3773 {
3774 register_ne_601_sprs(env);
3775 register_sdr1_sprs(env);
3776 register_604_sprs(env);
3777 /* Hardware implementation registers */
3778 spr_register(env, SPR_HID0, "HID0",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3781 0x00000000);
3782 /* Memory management */
3783 register_low_BATs(env);
3784 init_excp_604(env);
3785 env->dcache_line_size = 32;
3786 env->icache_line_size = 32;
3787 /* Allocate hardware IRQ controller */
3788 ppc6xx_irq_init(env_archcpu(env));
3789 }
3790
3791 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3792 {
3793 DeviceClass *dc = DEVICE_CLASS(oc);
3794 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3795
3796 dc->desc = "PowerPC 604";
3797 pcc->init_proc = init_proc_604;
3798 pcc->check_pow = check_pow_nocheck;
3799 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3800 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3801 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3802 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3803 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3804 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3805 PPC_SEGMENT | PPC_EXTERN;
3806 pcc->msr_mask = (1ull << MSR_POW) |
3807 (1ull << MSR_ILE) |
3808 (1ull << MSR_EE) |
3809 (1ull << MSR_PR) |
3810 (1ull << MSR_FP) |
3811 (1ull << MSR_ME) |
3812 (1ull << MSR_FE0) |
3813 (1ull << MSR_SE) |
3814 (1ull << MSR_DE) |
3815 (1ull << MSR_FE1) |
3816 (1ull << MSR_EP) |
3817 (1ull << MSR_IR) |
3818 (1ull << MSR_DR) |
3819 (1ull << MSR_PMM) |
3820 (1ull << MSR_RI) |
3821 (1ull << MSR_LE);
3822 pcc->mmu_model = POWERPC_MMU_32B;
3823 pcc->excp_model = POWERPC_EXCP_6xx;
3824 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3825 pcc->bfd_mach = bfd_mach_ppc_604;
3826 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3827 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3828 }
3829
3830 static void init_proc_604E(CPUPPCState *env)
3831 {
3832 register_ne_601_sprs(env);
3833 register_sdr1_sprs(env);
3834 register_604_sprs(env);
3835
3836 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
3837 SPR_NOACCESS, SPR_NOACCESS,
3838 &spr_read_generic, &spr_write_generic,
3839 0x00000000);
3840
3841 spr_register(env, SPR_7XX_PMC3, "PMC3",
3842 SPR_NOACCESS, SPR_NOACCESS,
3843 &spr_read_generic, &spr_write_generic,
3844 0x00000000);
3845
3846 spr_register(env, SPR_7XX_PMC4, "PMC4",
3847 SPR_NOACCESS, SPR_NOACCESS,
3848 &spr_read_generic, &spr_write_generic,
3849 0x00000000);
3850 /* Hardware implementation registers */
3851 spr_register(env, SPR_HID0, "HID0",
3852 SPR_NOACCESS, SPR_NOACCESS,
3853 &spr_read_generic, &spr_write_generic,
3854 0x00000000);
3855
3856 spr_register(env, SPR_HID1, "HID1",
3857 SPR_NOACCESS, SPR_NOACCESS,
3858 &spr_read_generic, &spr_write_generic,
3859 0x00000000);
3860 /* Memory management */
3861 register_low_BATs(env);
3862 init_excp_604(env);
3863 env->dcache_line_size = 32;
3864 env->icache_line_size = 32;
3865 /* Allocate hardware IRQ controller */
3866 ppc6xx_irq_init(env_archcpu(env));
3867 }
3868
3869 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3870 {
3871 DeviceClass *dc = DEVICE_CLASS(oc);
3872 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3873
3874 dc->desc = "PowerPC 604E";
3875 pcc->init_proc = init_proc_604E;
3876 pcc->check_pow = check_pow_nocheck;
3877 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3878 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3879 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3880 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3881 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3882 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3883 PPC_SEGMENT | PPC_EXTERN;
3884 pcc->msr_mask = (1ull << MSR_POW) |
3885 (1ull << MSR_ILE) |
3886 (1ull << MSR_EE) |
3887 (1ull << MSR_PR) |
3888 (1ull << MSR_FP) |
3889 (1ull << MSR_ME) |
3890 (1ull << MSR_FE0) |
3891 (1ull << MSR_SE) |
3892 (1ull << MSR_DE) |
3893 (1ull << MSR_FE1) |
3894 (1ull << MSR_EP) |
3895 (1ull << MSR_IR) |
3896 (1ull << MSR_DR) |
3897 (1ull << MSR_PMM) |
3898 (1ull << MSR_RI) |
3899 (1ull << MSR_LE);
3900 pcc->mmu_model = POWERPC_MMU_32B;
3901 pcc->excp_model = POWERPC_EXCP_6xx;
3902 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3903 pcc->bfd_mach = bfd_mach_ppc_604;
3904 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3905 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3906 }
3907
3908 static void init_proc_740(CPUPPCState *env)
3909 {
3910 register_ne_601_sprs(env);
3911 register_sdr1_sprs(env);
3912 register_7xx_sprs(env);
3913 /* Thermal management */
3914 register_thrm_sprs(env);
3915 /* Hardware implementation registers */
3916 spr_register(env, SPR_HID0, "HID0",
3917 SPR_NOACCESS, SPR_NOACCESS,
3918 &spr_read_generic, &spr_write_generic,
3919 0x00000000);
3920
3921 spr_register(env, SPR_HID1, "HID1",
3922 SPR_NOACCESS, SPR_NOACCESS,
3923 &spr_read_generic, &spr_write_generic,
3924 0x00000000);
3925 /* Memory management */
3926 register_low_BATs(env);
3927 init_excp_7x0(env);
3928 env->dcache_line_size = 32;
3929 env->icache_line_size = 32;
3930 /* Allocate hardware IRQ controller */
3931 ppc6xx_irq_init(env_archcpu(env));
3932 }
3933
3934 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3935 {
3936 DeviceClass *dc = DEVICE_CLASS(oc);
3937 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3938
3939 dc->desc = "PowerPC 740";
3940 pcc->init_proc = init_proc_740;
3941 pcc->check_pow = check_pow_hid0;
3942 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3943 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3944 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3945 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3946 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3947 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3948 PPC_SEGMENT | PPC_EXTERN;
3949 pcc->msr_mask = (1ull << MSR_POW) |
3950 (1ull << MSR_ILE) |
3951 (1ull << MSR_EE) |
3952 (1ull << MSR_PR) |
3953 (1ull << MSR_FP) |
3954 (1ull << MSR_ME) |
3955 (1ull << MSR_FE0) |
3956 (1ull << MSR_SE) |
3957 (1ull << MSR_DE) |
3958 (1ull << MSR_FE1) |
3959 (1ull << MSR_EP) |
3960 (1ull << MSR_IR) |
3961 (1ull << MSR_DR) |
3962 (1ull << MSR_PMM) |
3963 (1ull << MSR_RI) |
3964 (1ull << MSR_LE);
3965 pcc->mmu_model = POWERPC_MMU_32B;
3966 pcc->excp_model = POWERPC_EXCP_7xx;
3967 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3968 pcc->bfd_mach = bfd_mach_ppc_750;
3969 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3970 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3971 }
3972
3973 static void init_proc_750(CPUPPCState *env)
3974 {
3975 register_ne_601_sprs(env);
3976 register_sdr1_sprs(env);
3977 register_7xx_sprs(env);
3978
3979 spr_register(env, SPR_L2CR, "L2CR",
3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, spr_access_nop,
3982 0x00000000);
3983 /* Thermal management */
3984 register_thrm_sprs(env);
3985 /* Hardware implementation registers */
3986 spr_register(env, SPR_HID0, "HID0",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990
3991 spr_register(env, SPR_HID1, "HID1",
3992 SPR_NOACCESS, SPR_NOACCESS,
3993 &spr_read_generic, &spr_write_generic,
3994 0x00000000);
3995 /* Memory management */
3996 register_low_BATs(env);
3997 /*
3998 * XXX: high BATs are also present but are known to be bugged on
3999 * die version 1.x
4000 */
4001 init_excp_7x0(env);
4002 env->dcache_line_size = 32;
4003 env->icache_line_size = 32;
4004 /* Allocate hardware IRQ controller */
4005 ppc6xx_irq_init(env_archcpu(env));
4006 }
4007
4008 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
4009 {
4010 DeviceClass *dc = DEVICE_CLASS(oc);
4011 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4012
4013 dc->desc = "PowerPC 750";
4014 pcc->init_proc = init_proc_750;
4015 pcc->check_pow = check_pow_hid0;
4016 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4017 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4018 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4019 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4020 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4021 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4022 PPC_SEGMENT | PPC_EXTERN;
4023 pcc->msr_mask = (1ull << MSR_POW) |
4024 (1ull << MSR_ILE) |
4025 (1ull << MSR_EE) |
4026 (1ull << MSR_PR) |
4027 (1ull << MSR_FP) |
4028 (1ull << MSR_ME) |
4029 (1ull << MSR_FE0) |
4030 (1ull << MSR_SE) |
4031 (1ull << MSR_DE) |
4032 (1ull << MSR_FE1) |
4033 (1ull << MSR_EP) |
4034 (1ull << MSR_IR) |
4035 (1ull << MSR_DR) |
4036 (1ull << MSR_PMM) |
4037 (1ull << MSR_RI) |
4038 (1ull << MSR_LE);
4039 pcc->mmu_model = POWERPC_MMU_32B;
4040 pcc->excp_model = POWERPC_EXCP_7xx;
4041 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4042 pcc->bfd_mach = bfd_mach_ppc_750;
4043 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4044 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4045 }
4046
4047 static void init_proc_750cl(CPUPPCState *env)
4048 {
4049 register_ne_601_sprs(env);
4050 register_sdr1_sprs(env);
4051 register_7xx_sprs(env);
4052
4053 spr_register(env, SPR_L2CR, "L2CR",
4054 SPR_NOACCESS, SPR_NOACCESS,
4055 &spr_read_generic, spr_access_nop,
4056 0x00000000);
4057 /* Thermal management */
4058 /* Those registers are fake on 750CL */
4059 spr_register(env, SPR_THRM1, "THRM1",
4060 SPR_NOACCESS, SPR_NOACCESS,
4061 &spr_read_generic, &spr_write_generic,
4062 0x00000000);
4063 spr_register(env, SPR_THRM2, "THRM2",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 spr_register(env, SPR_THRM3, "THRM3",
4068 SPR_NOACCESS, SPR_NOACCESS,
4069 &spr_read_generic, &spr_write_generic,
4070 0x00000000);
4071
4072 spr_register(env, SPR_750_TDCL, "TDCL",
4073 SPR_NOACCESS, SPR_NOACCESS,
4074 &spr_read_generic, &spr_write_generic,
4075 0x00000000);
4076 spr_register(env, SPR_750_TDCH, "TDCH",
4077 SPR_NOACCESS, SPR_NOACCESS,
4078 &spr_read_generic, &spr_write_generic,
4079 0x00000000);
4080 /* DMA */
4081 spr_register(env, SPR_750_WPAR, "WPAR",
4082 SPR_NOACCESS, SPR_NOACCESS,
4083 &spr_read_generic, &spr_write_generic,
4084 0x00000000);
4085 spr_register(env, SPR_750_DMAL, "DMAL",
4086 SPR_NOACCESS, SPR_NOACCESS,
4087 &spr_read_generic, &spr_write_generic,
4088 0x00000000);
4089 spr_register(env, SPR_750_DMAU, "DMAU",
4090 SPR_NOACCESS, SPR_NOACCESS,
4091 &spr_read_generic, &spr_write_generic,
4092 0x00000000);
4093 /* Hardware implementation registers */
4094 spr_register(env, SPR_HID0, "HID0",
4095 SPR_NOACCESS, SPR_NOACCESS,
4096 &spr_read_generic, &spr_write_generic,
4097 0x00000000);
4098
4099 spr_register(env, SPR_HID1, "HID1",
4100 SPR_NOACCESS, SPR_NOACCESS,
4101 &spr_read_generic, &spr_write_generic,
4102 0x00000000);
4103
4104 spr_register(env, SPR_750CL_HID2, "HID2",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000);
4108
4109 spr_register(env, SPR_750CL_HID4, "HID4",
4110 SPR_NOACCESS, SPR_NOACCESS,
4111 &spr_read_generic, &spr_write_generic,
4112 0x00000000);
4113 /* Quantization registers */
4114 spr_register(env, SPR_750_GQR0, "GQR0",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, &spr_write_generic,
4117 0x00000000);
4118
4119 spr_register(env, SPR_750_GQR1, "GQR1",
4120 SPR_NOACCESS, SPR_NOACCESS,
4121 &spr_read_generic, &spr_write_generic,
4122 0x00000000);
4123
4124 spr_register(env, SPR_750_GQR2, "GQR2",
4125 SPR_NOACCESS, SPR_NOACCESS,
4126 &spr_read_generic, &spr_write_generic,
4127 0x00000000);
4128
4129 spr_register(env, SPR_750_GQR3, "GQR3",
4130 SPR_NOACCESS, SPR_NOACCESS,
4131 &spr_read_generic, &spr_write_generic,
4132 0x00000000);
4133
4134 spr_register(env, SPR_750_GQR4, "GQR4",
4135 SPR_NOACCESS, SPR_NOACCESS,
4136 &spr_read_generic, &spr_write_generic,
4137 0x00000000);
4138
4139 spr_register(env, SPR_750_GQR5, "GQR5",
4140 SPR_NOACCESS, SPR_NOACCESS,
4141 &spr_read_generic, &spr_write_generic,
4142 0x00000000);
4143
4144 spr_register(env, SPR_750_GQR6, "GQR6",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
4148
4149 spr_register(env, SPR_750_GQR7, "GQR7",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
4153 /* Memory management */
4154 register_low_BATs(env);
4155 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4156 register_high_BATs(env);
4157 init_excp_750cl(env);
4158 env->dcache_line_size = 32;
4159 env->icache_line_size = 32;
4160 /* Allocate hardware IRQ controller */
4161 ppc6xx_irq_init(env_archcpu(env));
4162 }
4163
4164 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
4165 {
4166 DeviceClass *dc = DEVICE_CLASS(oc);
4167 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4168
4169 dc->desc = "PowerPC 750 CL";
4170 pcc->init_proc = init_proc_750cl;
4171 pcc->check_pow = check_pow_hid0;
4172 /*
4173 * XXX: not implemented:
4174 * cache lock instructions:
4175 * dcbz_l
4176 * floating point paired instructions
4177 * psq_lux
4178 * psq_lx
4179 * psq_stux
4180 * psq_stx
4181 * ps_abs
4182 * ps_add
4183 * ps_cmpo0
4184 * ps_cmpo1
4185 * ps_cmpu0
4186 * ps_cmpu1
4187 * ps_div
4188 * ps_madd
4189 * ps_madds0
4190 * ps_madds1
4191 * ps_merge00
4192 * ps_merge01
4193 * ps_merge10
4194 * ps_merge11
4195 * ps_mr
4196 * ps_msub
4197 * ps_mul
4198 * ps_muls0
4199 * ps_muls1
4200 * ps_nabs
4201 * ps_neg
4202 * ps_nmadd
4203 * ps_nmsub
4204 * ps_res
4205 * ps_rsqrte
4206 * ps_sel
4207 * ps_sub
4208 * ps_sum0
4209 * ps_sum1
4210 */
4211 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4212 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4213 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4214 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4215 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4216 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4217 PPC_SEGMENT | PPC_EXTERN;
4218 pcc->msr_mask = (1ull << MSR_POW) |
4219 (1ull << MSR_ILE) |
4220 (1ull << MSR_EE) |
4221 (1ull << MSR_PR) |
4222 (1ull << MSR_FP) |
4223 (1ull << MSR_ME) |
4224 (1ull << MSR_FE0) |
4225 (1ull << MSR_SE) |
4226 (1ull << MSR_DE) |
4227 (1ull << MSR_FE1) |
4228 (1ull << MSR_EP) |
4229 (1ull << MSR_IR) |
4230 (1ull << MSR_DR) |
4231 (1ull << MSR_PMM) |
4232 (1ull << MSR_RI) |
4233 (1ull << MSR_LE);
4234 pcc->mmu_model = POWERPC_MMU_32B;
4235 pcc->excp_model = POWERPC_EXCP_7xx;
4236 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4237 pcc->bfd_mach = bfd_mach_ppc_750;
4238 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4239 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4240 }
4241
4242 static void init_proc_750cx(CPUPPCState *env)
4243 {
4244 register_ne_601_sprs(env);
4245 register_sdr1_sprs(env);
4246 register_7xx_sprs(env);
4247
4248 spr_register(env, SPR_L2CR, "L2CR",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, spr_access_nop,
4251 0x00000000);
4252 /* Thermal management */
4253 register_thrm_sprs(env);
4254
4255 spr_register(env, SPR_SDA, "SDA",
4256 SPR_NOACCESS, SPR_NOACCESS,
4257 &spr_read_generic, &spr_write_generic,
4258 0x00000000);
4259 /* Hardware implementation registers */
4260 spr_register(env, SPR_HID0, "HID0",
4261 SPR_NOACCESS, SPR_NOACCESS,
4262 &spr_read_generic, &spr_write_generic,
4263 0x00000000);
4264
4265 spr_register(env, SPR_HID1, "HID1",
4266 SPR_NOACCESS, SPR_NOACCESS,
4267 &spr_read_generic, &spr_write_generic,
4268 0x00000000);
4269 /* Memory management */
4270 register_low_BATs(env);
4271 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4272 register_high_BATs(env);
4273 init_excp_750cx(env);
4274 env->dcache_line_size = 32;
4275 env->icache_line_size = 32;
4276 /* Allocate hardware IRQ controller */
4277 ppc6xx_irq_init(env_archcpu(env));
4278 }
4279
4280 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
4281 {
4282 DeviceClass *dc = DEVICE_CLASS(oc);
4283 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4284
4285 dc->desc = "PowerPC 750CX";
4286 pcc->init_proc = init_proc_750cx;
4287 pcc->check_pow = check_pow_hid0;
4288 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4289 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4290 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4291 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4292 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4293 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4294 PPC_SEGMENT | PPC_EXTERN;
4295 pcc->msr_mask = (1ull << MSR_POW) |
4296 (1ull << MSR_ILE) |
4297 (1ull << MSR_EE) |
4298 (1ull << MSR_PR) |
4299 (1ull << MSR_FP) |
4300 (1ull << MSR_ME) |
4301 (1ull << MSR_FE0) |
4302 (1ull << MSR_SE) |
4303 (1ull << MSR_DE) |
4304 (1ull << MSR_FE1) |
4305 (1ull << MSR_EP) |
4306 (1ull << MSR_IR) |
4307 (1ull << MSR_DR) |
4308 (1ull << MSR_PMM) |
4309 (1ull << MSR_RI) |
4310 (1ull << MSR_LE);
4311 pcc->mmu_model = POWERPC_MMU_32B;
4312 pcc->excp_model = POWERPC_EXCP_7xx;
4313 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4314 pcc->bfd_mach = bfd_mach_ppc_750;
4315 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4316 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4317 }
4318
4319 static void init_proc_750fx(CPUPPCState *env)
4320 {
4321 register_ne_601_sprs(env);
4322 register_sdr1_sprs(env);
4323 register_7xx_sprs(env);
4324
4325 spr_register(env, SPR_L2CR, "L2CR",
4326 SPR_NOACCESS, SPR_NOACCESS,
4327 &spr_read_generic, spr_access_nop,
4328 0x00000000);
4329 /* Thermal management */
4330 register_thrm_sprs(env);
4331
4332 spr_register(env, SPR_750_THRM4, "THRM4",
4333 SPR_NOACCESS, SPR_NOACCESS,
4334 &spr_read_generic, &spr_write_generic,
4335 0x00000000);
4336 /* Hardware implementation registers */
4337 spr_register(env, SPR_HID0, "HID0",
4338 SPR_NOACCESS, SPR_NOACCESS,
4339 &spr_read_generic, &spr_write_generic,
4340 0x00000000);
4341
4342 spr_register(env, SPR_HID1, "HID1",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, &spr_write_generic,
4345 0x00000000);
4346
4347 spr_register(env, SPR_750FX_HID2, "HID2",
4348 SPR_NOACCESS, SPR_NOACCESS,
4349 &spr_read_generic, &spr_write_generic,
4350 0x00000000);
4351 /* Memory management */
4352 register_low_BATs(env);
4353 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4354 register_high_BATs(env);
4355 init_excp_7x0(env);
4356 env->dcache_line_size = 32;
4357 env->icache_line_size = 32;
4358 /* Allocate hardware IRQ controller */
4359 ppc6xx_irq_init(env_archcpu(env));
4360 }
4361
4362 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
4363 {
4364 DeviceClass *dc = DEVICE_CLASS(oc);
4365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4366
4367 dc->desc = "PowerPC 750FX";
4368 pcc->init_proc = init_proc_750fx;
4369 pcc->check_pow = check_pow_hid0;
4370 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4371 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4372 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4373 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4374 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4375 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4376 PPC_SEGMENT | PPC_EXTERN;
4377 pcc->msr_mask = (1ull << MSR_POW) |
4378 (1ull << MSR_ILE) |
4379 (1ull << MSR_EE) |
4380 (1ull << MSR_PR) |
4381 (1ull << MSR_FP) |
4382 (1ull << MSR_ME) |
4383 (1ull << MSR_FE0) |
4384 (1ull << MSR_SE) |
4385 (1ull << MSR_DE) |
4386 (1ull << MSR_FE1) |
4387 (1ull << MSR_EP) |
4388 (1ull << MSR_IR) |
4389 (1ull << MSR_DR) |
4390 (1ull << MSR_PMM) |
4391 (1ull << MSR_RI) |
4392 (1ull << MSR_LE);
4393 pcc->mmu_model = POWERPC_MMU_32B;
4394 pcc->excp_model = POWERPC_EXCP_7xx;
4395 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4396 pcc->bfd_mach = bfd_mach_ppc_750;
4397 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4398 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4399 }
4400
4401 static void init_proc_750gx(CPUPPCState *env)
4402 {
4403 register_ne_601_sprs(env);
4404 register_sdr1_sprs(env);
4405 register_7xx_sprs(env);
4406
4407 spr_register(env, SPR_L2CR, "L2CR",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, spr_access_nop,
4410 0x00000000);
4411 /* Thermal management */
4412 register_thrm_sprs(env);
4413
4414 spr_register(env, SPR_750_THRM4, "THRM4",
4415 SPR_NOACCESS, SPR_NOACCESS,
4416 &spr_read_generic, &spr_write_generic,
4417 0x00000000);
4418 /* Hardware implementation registers */
4419 spr_register(env, SPR_HID0, "HID0",
4420 SPR_NOACCESS, SPR_NOACCESS,
4421 &spr_read_generic, &spr_write_generic,
4422 0x00000000);
4423
4424 spr_register(env, SPR_HID1, "HID1",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0x00000000);
4428
4429 spr_register(env, SPR_750FX_HID2, "HID2",
4430 SPR_NOACCESS, SPR_NOACCESS,
4431 &spr_read_generic, &spr_write_generic,
4432 0x00000000);
4433 /* Memory management */
4434 register_low_BATs(env);
4435 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4436 register_high_BATs(env);
4437 init_excp_7x0(env);
4438 env->dcache_line_size = 32;
4439 env->icache_line_size = 32;
4440 /* Allocate hardware IRQ controller */
4441 ppc6xx_irq_init(env_archcpu(env));
4442 }
4443
4444 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
4445 {
4446 DeviceClass *dc = DEVICE_CLASS(oc);
4447 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4448
4449 dc->desc = "PowerPC 750GX";
4450 pcc->init_proc = init_proc_750gx;
4451 pcc->check_pow = check_pow_hid0;
4452 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4453 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4454 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4455 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4456 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4457 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4458 PPC_SEGMENT | PPC_EXTERN;
4459 pcc->msr_mask = (1ull << MSR_POW) |
4460 (1ull << MSR_ILE) |
4461 (1ull << MSR_EE) |
4462 (1ull << MSR_PR) |
4463 (1ull << MSR_FP) |
4464 (1ull << MSR_ME) |
4465 (1ull << MSR_FE0) |
4466 (1ull << MSR_SE) |
4467 (1ull << MSR_DE) |
4468 (1ull << MSR_FE1) |
4469 (1ull << MSR_EP) |
4470 (1ull << MSR_IR) |
4471 (1ull << MSR_DR) |
4472 (1ull << MSR_PMM) |
4473 (1ull << MSR_RI) |
4474 (1ull << MSR_LE);
4475 pcc->mmu_model = POWERPC_MMU_32B;
4476 pcc->excp_model = POWERPC_EXCP_7xx;
4477 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4478 pcc->bfd_mach = bfd_mach_ppc_750;
4479 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4480 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4481 }
4482
4483 static void init_proc_745(CPUPPCState *env)
4484 {
4485 register_ne_601_sprs(env);
4486 register_sdr1_sprs(env);
4487 register_7xx_sprs(env);
4488 register_755_sprs(env);
4489 /* Thermal management */
4490 register_thrm_sprs(env);
4491 /* Hardware implementation registers */
4492 spr_register(env, SPR_HID0, "HID0",
4493 SPR_NOACCESS, SPR_NOACCESS,
4494 &spr_read_generic, &spr_write_generic,
4495 0x00000000);
4496
4497 spr_register(env, SPR_HID1, "HID1",
4498 SPR_NOACCESS, SPR_NOACCESS,
4499 &spr_read_generic, &spr_write_generic,
4500 0x00000000);
4501
4502 spr_register(env, SPR_HID2, "HID2",
4503 SPR_NOACCESS, SPR_NOACCESS,
4504 &spr_read_generic, &spr_write_generic,
4505 0x00000000);
4506 /* Memory management */
4507 register_low_BATs(env);
4508 register_high_BATs(env);
4509 register_6xx_7xx_soft_tlb(env, 64, 2);
4510 init_excp_7x5(env);
4511 env->dcache_line_size = 32;
4512 env->icache_line_size = 32;
4513 /* Allocate hardware IRQ controller */
4514 ppc6xx_irq_init(env_archcpu(env));
4515 }
4516
4517 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4518 {
4519 DeviceClass *dc = DEVICE_CLASS(oc);
4520 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4521
4522 dc->desc = "PowerPC 745";
4523 pcc->init_proc = init_proc_745;
4524 pcc->check_pow = check_pow_hid0;
4525 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4526 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4527 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4528 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4529 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4530 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4531 PPC_SEGMENT | PPC_EXTERN;
4532 pcc->msr_mask = (1ull << MSR_POW) |
4533 (1ull << MSR_ILE) |
4534 (1ull << MSR_EE) |
4535 (1ull << MSR_PR) |
4536 (1ull << MSR_FP) |
4537 (1ull << MSR_ME) |
4538 (1ull << MSR_FE0) |
4539 (1ull << MSR_SE) |
4540 (1ull << MSR_DE) |
4541 (1ull << MSR_FE1) |
4542 (1ull << MSR_EP) |
4543 (1ull << MSR_IR) |
4544 (1ull << MSR_DR) |
4545 (1ull << MSR_PMM) |
4546 (1ull << MSR_RI) |
4547 (1ull << MSR_LE);
4548 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4549 pcc->excp_model = POWERPC_EXCP_7xx;
4550 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4551 pcc->bfd_mach = bfd_mach_ppc_750;
4552 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4553 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4554 }
4555
4556 static void init_proc_755(CPUPPCState *env)
4557 {
4558 register_ne_601_sprs(env);
4559 register_sdr1_sprs(env);
4560 register_7xx_sprs(env);
4561 register_755_sprs(env);
4562 /* L2 cache control */
4563 spr_register(env, SPR_L2CR, "L2CR",
4564 SPR_NOACCESS, SPR_NOACCESS,
4565 &spr_read_generic, spr_access_nop,
4566 0x00000000);
4567
4568 spr_register(env, SPR_L2PMCR, "L2PMCR",
4569 SPR_NOACCESS, SPR_NOACCESS,
4570 &spr_read_generic, &spr_write_generic,
4571 0x00000000);
4572 /* Thermal management */
4573 register_thrm_sprs(env);
4574 /* Hardware implementation registers */
4575 spr_register(env, SPR_HID0, "HID0",
4576 SPR_NOACCESS, SPR_NOACCESS,
4577 &spr_read_generic, &spr_write_generic,
4578 0x00000000);
4579
4580 spr_register(env, SPR_HID1, "HID1",
4581 SPR_NOACCESS, SPR_NOACCESS,
4582 &spr_read_generic, &spr_write_generic,
4583 0x00000000);
4584
4585 spr_register(env, SPR_HID2, "HID2",
4586 SPR_NOACCESS, SPR_NOACCESS,
4587 &spr_read_generic, &spr_write_generic,
4588 0x00000000);
4589 /* Memory management */
4590 register_low_BATs(env);
4591 register_high_BATs(env);
4592 register_6xx_7xx_soft_tlb(env, 64, 2);
4593 init_excp_7x5(env);
4594 env->dcache_line_size = 32;
4595 env->icache_line_size = 32;
4596 /* Allocate hardware IRQ controller */
4597 ppc6xx_irq_init(env_archcpu(env));
4598 }
4599
4600 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4601 {
4602 DeviceClass *dc = DEVICE_CLASS(oc);
4603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4604
4605 dc->desc = "PowerPC 755";
4606 pcc->init_proc = init_proc_755;
4607 pcc->check_pow = check_pow_hid0;
4608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4609 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4610 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4611 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4612 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4613 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4614 PPC_SEGMENT | PPC_EXTERN;
4615 pcc->msr_mask = (1ull << MSR_POW) |
4616 (1ull << MSR_ILE) |
4617 (1ull << MSR_EE) |
4618 (1ull << MSR_PR) |
4619 (1ull << MSR_FP) |
4620 (1ull << MSR_ME) |
4621 (1ull << MSR_FE0) |
4622 (1ull << MSR_SE) |
4623 (1ull << MSR_DE) |
4624 (1ull << MSR_FE1) |
4625 (1ull << MSR_EP) |
4626 (1ull << MSR_IR) |
4627 (1ull << MSR_DR) |
4628 (1ull << MSR_PMM) |
4629 (1ull << MSR_RI) |
4630 (1ull << MSR_LE);
4631 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4632 pcc->excp_model = POWERPC_EXCP_7xx;
4633 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4634 pcc->bfd_mach = bfd_mach_ppc_750;
4635 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4636 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4637 }
4638
4639 static void init_proc_7400(CPUPPCState *env)
4640 {
4641 register_ne_601_sprs(env);
4642 register_sdr1_sprs(env);
4643 register_7xx_sprs(env);
4644 /* 74xx specific SPR */
4645 register_74xx_sprs(env);
4646 vscr_init(env, 0x00010000);
4647
4648 spr_register(env, SPR_UBAMR, "UBAMR",
4649 &spr_read_ureg, SPR_NOACCESS,
4650 &spr_read_ureg, SPR_NOACCESS,
4651 0x00000000);
4652
4653 spr_register(env, SPR_MSSCR1, "MSSCR1",
4654 SPR_NOACCESS, SPR_NOACCESS,
4655 &spr_read_generic, &spr_write_generic,
4656 0x00000000);
4657 /* Thermal management */
4658 register_thrm_sprs(env);
4659 /* Memory management */
4660 register_low_BATs(env);
4661 init_excp_7400(env);
4662 env->dcache_line_size = 32;
4663 env->icache_line_size = 32;
4664 /* Allocate hardware IRQ controller */
4665 ppc6xx_irq_init(env_archcpu(env));
4666 }
4667
4668 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4669 {
4670 DeviceClass *dc = DEVICE_CLASS(oc);
4671 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4672
4673 dc->desc = "PowerPC 7400 (aka G4)";
4674 pcc->init_proc = init_proc_7400;
4675 pcc->check_pow = check_pow_hid0;
4676 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4677 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4678 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4679 PPC_FLOAT_STFIWX |
4680 PPC_CACHE | PPC_CACHE_ICBI |
4681 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4682 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4683 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4684 PPC_MEM_TLBIA |
4685 PPC_SEGMENT | PPC_EXTERN |
4686 PPC_ALTIVEC;
4687 pcc->msr_mask = (1ull << MSR_VR) |
4688 (1ull << MSR_POW) |
4689 (1ull << MSR_ILE) |
4690 (1ull << MSR_EE) |
4691 (1ull << MSR_PR) |
4692 (1ull << MSR_FP) |
4693 (1ull << MSR_ME) |
4694 (1ull << MSR_FE0) |
4695 (1ull << MSR_SE) |
4696 (1ull << MSR_DE) |
4697 (1ull << MSR_FE1) |
4698 (1ull << MSR_EP) |
4699 (1ull << MSR_IR) |
4700 (1ull << MSR_DR) |
4701 (1ull << MSR_PMM) |
4702 (1ull << MSR_RI) |
4703 (1ull << MSR_LE);
4704 pcc->mmu_model = POWERPC_MMU_32B;
4705 pcc->excp_model = POWERPC_EXCP_74xx;
4706 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4707 pcc->bfd_mach = bfd_mach_ppc_7400;
4708 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4709 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4710 POWERPC_FLAG_BUS_CLK;
4711 }
4712
4713 static void init_proc_7410(CPUPPCState *env)
4714 {
4715 register_ne_601_sprs(env);
4716 register_sdr1_sprs(env);
4717 register_7xx_sprs(env);
4718 /* 74xx specific SPR */
4719 register_74xx_sprs(env);
4720 vscr_init(env, 0x00010000);
4721
4722 spr_register(env, SPR_UBAMR, "UBAMR",
4723 &spr_read_ureg, SPR_NOACCESS,
4724 &spr_read_ureg, SPR_NOACCESS,
4725 0x00000000);
4726 /* Thermal management */
4727 register_thrm_sprs(env);
4728 /* L2PMCR */
4729
4730 spr_register(env, SPR_L2PMCR, "L2PMCR",
4731 SPR_NOACCESS, SPR_NOACCESS,
4732 &spr_read_generic, &spr_write_generic,
4733 0x00000000);
4734 /* LDSTDB */
4735
4736 spr_register(env, SPR_LDSTDB, "LDSTDB",
4737 SPR_NOACCESS, SPR_NOACCESS,
4738 &spr_read_generic, &spr_write_generic,
4739 0x00000000);
4740 /* Memory management */
4741 register_low_BATs(env);
4742 init_excp_7400(env);
4743 env->dcache_line_size = 32;
4744 env->icache_line_size = 32;
4745 /* Allocate hardware IRQ controller */
4746 ppc6xx_irq_init(env_archcpu(env));
4747 }
4748
4749 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4750 {
4751 DeviceClass *dc = DEVICE_CLASS(oc);
4752 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4753
4754 dc->desc = "PowerPC 7410 (aka G4)";
4755 pcc->init_proc = init_proc_7410;
4756 pcc->check_pow = check_pow_hid0;
4757 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4758 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4759 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4760 PPC_FLOAT_STFIWX |
4761 PPC_CACHE | PPC_CACHE_ICBI |
4762 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4763 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4764 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4765 PPC_MEM_TLBIA |
4766 PPC_SEGMENT | PPC_EXTERN |
4767 PPC_ALTIVEC;
4768 pcc->msr_mask = (1ull << MSR_VR) |
4769 (1ull << MSR_POW) |
4770 (1ull << MSR_ILE) |
4771 (1ull << MSR_EE) |
4772 (1ull << MSR_PR) |
4773 (1ull << MSR_FP) |
4774 (1ull << MSR_ME) |
4775 (1ull << MSR_FE0) |
4776 (1ull << MSR_SE) |
4777 (1ull << MSR_DE) |
4778 (1ull << MSR_FE1) |
4779 (1ull << MSR_EP) |
4780 (1ull << MSR_IR) |
4781 (1ull << MSR_DR) |
4782 (1ull << MSR_PMM) |
4783 (1ull << MSR_RI) |
4784 (1ull << MSR_LE);
4785 pcc->mmu_model = POWERPC_MMU_32B;
4786 pcc->excp_model = POWERPC_EXCP_74xx;
4787 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4788 pcc->bfd_mach = bfd_mach_ppc_7400;
4789 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4790 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4791 POWERPC_FLAG_BUS_CLK;
4792 }
4793
4794 static void init_proc_7440(CPUPPCState *env)
4795 {
4796 register_ne_601_sprs(env);
4797 register_sdr1_sprs(env);
4798 register_7xx_sprs(env);
4799 /* 74xx specific SPR */
4800 register_74xx_sprs(env);
4801 vscr_init(env, 0x00010000);
4802
4803 spr_register(env, SPR_UBAMR, "UBAMR",
4804 &spr_read_ureg, SPR_NOACCESS,
4805 &spr_read_ureg, SPR_NOACCESS,
4806 0x00000000);
4807 /* LDSTCR */
4808 spr_register(env, SPR_LDSTCR, "LDSTCR",
4809 SPR_NOACCESS, SPR_NOACCESS,
4810 &spr_read_generic, &spr_write_generic,
4811 0x00000000);
4812 /* ICTRL */
4813 spr_register(env, SPR_ICTRL, "ICTRL",
4814 SPR_NOACCESS, SPR_NOACCESS,
4815 &spr_read_generic, &spr_write_generic,
4816 0x00000000);
4817 /* MSSSR0 */
4818 spr_register(env, SPR_MSSSR0, "MSSSR0",
4819 SPR_NOACCESS, SPR_NOACCESS,
4820 &spr_read_generic, &spr_write_generic,
4821 0x00000000);
4822 /* PMC */
4823 spr_register(env, SPR_7XX_PMC5, "PMC5",
4824 SPR_NOACCESS, SPR_NOACCESS,
4825 &spr_read_generic, &spr_write_generic,
4826 0x00000000);
4827
4828 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4829 &spr_read_ureg, SPR_NOACCESS,
4830 &spr_read_ureg, SPR_NOACCESS,
4831 0x00000000);
4832
4833 spr_register(env, SPR_7XX_PMC6, "PMC6",
4834 SPR_NOACCESS, SPR_NOACCESS,
4835 &spr_read_generic, &spr_write_generic,
4836 0x00000000);
4837
4838 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4839 &spr_read_ureg, SPR_NOACCESS,
4840 &spr_read_ureg, SPR_NOACCESS,
4841 0x00000000);
4842 /* Memory management */
4843 register_low_BATs(env);
4844 init_excp_7450(env);
4845 env->dcache_line_size = 32;
4846 env->icache_line_size = 32;
4847 /* Allocate hardware IRQ controller */
4848 ppc6xx_irq_init(env_archcpu(env));
4849 }
4850
4851 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4852 {
4853 DeviceClass *dc = DEVICE_CLASS(oc);
4854 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4855
4856 dc->desc = "PowerPC 7440 (aka G4)";
4857 pcc->init_proc = init_proc_7440;
4858 pcc->check_pow = check_pow_hid0_74xx;
4859 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4860 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4861 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4862 PPC_FLOAT_STFIWX |
4863 PPC_CACHE | PPC_CACHE_ICBI |
4864 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4865 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4866 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4867 PPC_MEM_TLBIA |
4868 PPC_SEGMENT | PPC_EXTERN |
4869 PPC_ALTIVEC;
4870 pcc->msr_mask = (1ull << MSR_VR) |
4871 (1ull << MSR_POW) |
4872 (1ull << MSR_ILE) |
4873 (1ull << MSR_EE) |
4874 (1ull << MSR_PR) |
4875 (1ull << MSR_FP) |
4876 (1ull << MSR_ME) |
4877 (1ull << MSR_FE0) |
4878 (1ull << MSR_SE) |
4879 (1ull << MSR_DE) |
4880 (1ull << MSR_FE1) |
4881 (1ull << MSR_EP) |
4882 (1ull << MSR_IR) |
4883 (1ull << MSR_DR) |
4884 (1ull << MSR_PMM) |
4885 (1ull << MSR_RI) |
4886 (1ull << MSR_LE);
4887 pcc->mmu_model = POWERPC_MMU_32B;
4888 pcc->excp_model = POWERPC_EXCP_74xx;
4889 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4890 pcc->bfd_mach = bfd_mach_ppc_7400;
4891 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4892 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4893 POWERPC_FLAG_BUS_CLK;
4894 }
4895
4896 static void init_proc_7450(CPUPPCState *env)
4897 {
4898 register_ne_601_sprs(env);
4899 register_sdr1_sprs(env);
4900 register_7xx_sprs(env);
4901 /* 74xx specific SPR */
4902 register_74xx_sprs(env);
4903 vscr_init(env, 0x00010000);
4904 /* Level 3 cache control */
4905 register_l3_ctrl(env);
4906 /* L3ITCR1 */
4907 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4908 SPR_NOACCESS, SPR_NOACCESS,
4909 &spr_read_generic, &spr_write_generic,
4910 0x00000000);
4911 /* L3ITCR2 */
4912 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* L3ITCR3 */
4917 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921 /* L3OHCR */
4922 spr_register(env, SPR_L3OHCR, "L3OHCR",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926
4927 spr_register(env, SPR_UBAMR, "UBAMR",
4928 &spr_read_ureg, SPR_NOACCESS,
4929 &spr_read_ureg, SPR_NOACCESS,
4930 0x00000000);
4931 /* LDSTCR */
4932 spr_register(env, SPR_LDSTCR, "LDSTCR",
4933 SPR_NOACCESS, SPR_NOACCESS,
4934 &spr_read_generic, &spr_write_generic,
4935 0x00000000);
4936 /* ICTRL */
4937 spr_register(env, SPR_ICTRL, "ICTRL",
4938 SPR_NOACCESS, SPR_NOACCESS,
4939 &spr_read_generic, &spr_write_generic,
4940 0x00000000);
4941 /* MSSSR0 */
4942 spr_register(env, SPR_MSSSR0, "MSSSR0",
4943 SPR_NOACCESS, SPR_NOACCESS,
4944 &spr_read_generic, &spr_write_generic,
4945 0x00000000);
4946 /* PMC */
4947 spr_register(env, SPR_7XX_PMC5, "PMC5",
4948 SPR_NOACCESS, SPR_NOACCESS,
4949 &spr_read_generic, &spr_write_generic,
4950 0x00000000);
4951
4952 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4953 &spr_read_ureg, SPR_NOACCESS,
4954 &spr_read_ureg, SPR_NOACCESS,
4955 0x00000000);
4956
4957 spr_register(env, SPR_7XX_PMC6, "PMC6",
4958 SPR_NOACCESS, SPR_NOACCESS,
4959 &spr_read_generic, &spr_write_generic,
4960 0x00000000);
4961
4962 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4963 &spr_read_ureg, SPR_NOACCESS,
4964 &spr_read_ureg, SPR_NOACCESS,
4965 0x00000000);
4966 /* Memory management */
4967 register_low_BATs(env);
4968 init_excp_7450(env);
4969 env->dcache_line_size = 32;
4970 env->icache_line_size = 32;
4971 /* Allocate hardware IRQ controller */
4972 ppc6xx_irq_init(env_archcpu(env));
4973 }
4974
4975 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4976 {
4977 DeviceClass *dc = DEVICE_CLASS(oc);
4978 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4979
4980 dc->desc = "PowerPC 7450 (aka G4)";
4981 pcc->init_proc = init_proc_7450;
4982 pcc->check_pow = check_pow_hid0_74xx;
4983 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4984 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4985 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4986 PPC_FLOAT_STFIWX |
4987 PPC_CACHE | PPC_CACHE_ICBI |
4988 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4989 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4990 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4991 PPC_MEM_TLBIA |
4992 PPC_SEGMENT | PPC_EXTERN |
4993 PPC_ALTIVEC;
4994 pcc->msr_mask = (1ull << MSR_VR) |
4995 (1ull << MSR_POW) |
4996 (1ull << MSR_ILE) |
4997 (1ull << MSR_EE) |
4998 (1ull << MSR_PR) |
4999 (1ull << MSR_FP) |
5000 (1ull << MSR_ME) |
5001 (1ull << MSR_FE0) |
5002 (1ull << MSR_SE) |
5003 (1ull << MSR_DE) |
5004 (1ull << MSR_FE1) |
5005 (1ull << MSR_EP) |
5006 (1ull << MSR_IR) |
5007 (1ull << MSR_DR) |
5008 (1ull << MSR_PMM) |
5009 (1ull << MSR_RI) |
5010 (1ull << MSR_LE);
5011 pcc->mmu_model = POWERPC_MMU_32B;
5012 pcc->excp_model = POWERPC_EXCP_74xx;
5013 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5014 pcc->bfd_mach = bfd_mach_ppc_7400;
5015 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5016 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5017 POWERPC_FLAG_BUS_CLK;
5018 }
5019
5020 static void init_proc_7445(CPUPPCState *env)
5021 {
5022 register_ne_601_sprs(env);
5023 register_sdr1_sprs(env);
5024 register_7xx_sprs(env);
5025 /* 74xx specific SPR */
5026 register_74xx_sprs(env);
5027 vscr_init(env, 0x00010000);
5028 /* LDSTCR */
5029 spr_register(env, SPR_LDSTCR, "LDSTCR",
5030 SPR_NOACCESS, SPR_NOACCESS,
5031 &spr_read_generic, &spr_write_generic,
5032 0x00000000);
5033 /* ICTRL */
5034 spr_register(env, SPR_ICTRL, "ICTRL",
5035 SPR_NOACCESS, SPR_NOACCESS,
5036 &spr_read_generic, &spr_write_generic,
5037 0x00000000);
5038 /* MSSSR0 */
5039 spr_register(env, SPR_MSSSR0, "MSSSR0",
5040 SPR_NOACCESS, SPR_NOACCESS,
5041 &spr_read_generic, &spr_write_generic,
5042 0x00000000);
5043 /* PMC */
5044 spr_register(env, SPR_7XX_PMC5, "PMC5",
5045 SPR_NOACCESS, SPR_NOACCESS,
5046 &spr_read_generic, &spr_write_generic,
5047 0x00000000);
5048
5049 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5050 &spr_read_ureg, SPR_NOACCESS,
5051 &spr_read_ureg, SPR_NOACCESS,
5052 0x00000000);
5053
5054 spr_register(env, SPR_7XX_PMC6, "PMC6",
5055 SPR_NOACCESS, SPR_NOACCESS,
5056 &spr_read_generic, &spr_write_generic,
5057 0x00000000);
5058
5059 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5060 &spr_read_ureg, SPR_NOACCESS,
5061 &spr_read_ureg, SPR_NOACCESS,
5062 0x00000000);
5063 /* SPRGs */
5064 spr_register(env, SPR_SPRG4, "SPRG4",
5065 SPR_NOACCESS, SPR_NOACCESS,
5066 &spr_read_generic, &spr_write_generic,
5067 0x00000000);
5068 spr_register(env, SPR_USPRG4, "USPRG4",
5069 &spr_read_ureg, SPR_NOACCESS,
5070 &spr_read_ureg, SPR_NOACCESS,
5071 0x00000000);
5072 spr_register(env, SPR_SPRG5, "SPRG5",
5073 SPR_NOACCESS, SPR_NOACCESS,
5074 &spr_read_generic, &spr_write_generic,
5075 0x00000000);
5076 spr_register(env, SPR_USPRG5, "USPRG5",
5077 &spr_read_ureg, SPR_NOACCESS,
5078 &spr_read_ureg, SPR_NOACCESS,
5079 0x00000000);
5080 spr_register(env, SPR_SPRG6, "SPRG6",
5081 SPR_NOACCESS, SPR_NOACCESS,
5082 &spr_read_generic, &spr_write_generic,
5083 0x00000000);
5084 spr_register(env, SPR_USPRG6, "USPRG6",
5085 &spr_read_ureg, SPR_NOACCESS,
5086 &spr_read_ureg, SPR_NOACCESS,
5087 0x00000000);
5088 spr_register(env, SPR_SPRG7, "SPRG7",
5089 SPR_NOACCESS, SPR_NOACCESS,
5090 &spr_read_generic, &spr_write_generic,
5091 0x00000000);
5092 spr_register(env, SPR_USPRG7, "USPRG7",
5093 &spr_read_ureg, SPR_NOACCESS,
5094 &spr_read_ureg, SPR_NOACCESS,
5095 0x00000000);
5096 /* Memory management */
5097 register_low_BATs(env);
5098 register_high_BATs(env);
5099 init_excp_7450(env);
5100 env->dcache_line_size = 32;
5101 env->icache_line_size = 32;
5102 /* Allocate hardware IRQ controller */
5103 ppc6xx_irq_init(env_archcpu(env));
5104 }
5105
5106 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
5107 {
5108 DeviceClass *dc = DEVICE_CLASS(oc);
5109 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5110
5111 dc->desc = "PowerPC 7445 (aka G4)";
5112 pcc->init_proc = init_proc_7445;
5113 pcc->check_pow = check_pow_hid0_74xx;
5114 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5115 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5116 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5117 PPC_FLOAT_STFIWX |
5118 PPC_CACHE | PPC_CACHE_ICBI |
5119 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5120 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5121 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5122 PPC_MEM_TLBIA |
5123 PPC_SEGMENT | PPC_EXTERN |
5124 PPC_ALTIVEC;
5125 pcc->msr_mask = (1ull << MSR_VR) |
5126 (1ull << MSR_POW) |
5127 (1ull << MSR_ILE) |
5128 (1ull << MSR_EE) |
5129 (1ull << MSR_PR) |
5130 (1ull << MSR_FP) |
5131 (1ull << MSR_ME) |
5132 (1ull << MSR_FE0) |
5133 (1ull << MSR_SE) |
5134 (1ull << MSR_DE) |
5135 (1ull << MSR_FE1) |
5136 (1ull << MSR_EP) |
5137 (1ull << MSR_IR) |
5138 (1ull << MSR_DR) |
5139 (1ull << MSR_PMM) |
5140 (1ull << MSR_RI) |
5141 (1ull << MSR_LE);
5142 pcc->mmu_model = POWERPC_MMU_32B;
5143 pcc->excp_model = POWERPC_EXCP_74xx;
5144 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5145 pcc->bfd_mach = bfd_mach_ppc_7400;
5146 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5147 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5148 POWERPC_FLAG_BUS_CLK;
5149 }
5150
5151 static void init_proc_7455(CPUPPCState *env)
5152 {
5153 register_ne_601_sprs(env);
5154 register_sdr1_sprs(env);
5155 register_7xx_sprs(env);
5156 /* 74xx specific SPR */
5157 register_74xx_sprs(env);
5158 vscr_init(env, 0x00010000);
5159 /* Level 3 cache control */
5160 register_l3_ctrl(env);
5161 /* LDSTCR */
5162 spr_register(env, SPR_LDSTCR, "LDSTCR",
5163 SPR_NOACCESS, SPR_NOACCESS,
5164 &spr_read_generic, &spr_write_generic,
5165 0x00000000);
5166 /* ICTRL */
5167 spr_register(env, SPR_ICTRL, "ICTRL",
5168 SPR_NOACCESS, SPR_NOACCESS,
5169 &spr_read_generic, &spr_write_generic,
5170 0x00000000);
5171 /* MSSSR0 */
5172 spr_register(env, SPR_MSSSR0, "MSSSR0",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_generic, &spr_write_generic,
5175 0x00000000);
5176 /* PMC */
5177 spr_register(env, SPR_7XX_PMC5, "PMC5",
5178 SPR_NOACCESS, SPR_NOACCESS,
5179 &spr_read_generic, &spr_write_generic,
5180 0x00000000);
5181
5182 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5183 &spr_read_ureg, SPR_NOACCESS,
5184 &spr_read_ureg, SPR_NOACCESS,
5185 0x00000000);
5186
5187 spr_register(env, SPR_7XX_PMC6, "PMC6",
5188 SPR_NOACCESS, SPR_NOACCESS,
5189 &spr_read_generic, &spr_write_generic,
5190 0x00000000);
5191
5192 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5193 &spr_read_ureg, SPR_NOACCESS,
5194 &spr_read_ureg, SPR_NOACCESS,
5195 0x00000000);
5196 /* SPRGs */
5197 spr_register(env, SPR_SPRG4, "SPRG4",
5198 SPR_NOACCESS, SPR_NOACCESS,
5199 &spr_read_generic, &spr_write_generic,
5200 0x00000000);
5201 spr_register(env, SPR_USPRG4, "USPRG4",
5202 &spr_read_ureg, SPR_NOACCESS,
5203 &spr_read_ureg, SPR_NOACCESS,
5204 0x00000000);
5205 spr_register(env, SPR_SPRG5, "SPRG5",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 spr_register(env, SPR_USPRG5, "USPRG5",
5210 &spr_read_ureg, SPR_NOACCESS,
5211 &spr_read_ureg, SPR_NOACCESS,
5212 0x00000000);
5213 spr_register(env, SPR_SPRG6, "SPRG6",
5214 SPR_NOACCESS, SPR_NOACCESS,
5215 &spr_read_generic, &spr_write_generic,
5216 0x00000000);
5217 spr_register(env, SPR_USPRG6, "USPRG6",
5218 &spr_read_ureg, SPR_NOACCESS,
5219 &spr_read_ureg, SPR_NOACCESS,
5220 0x00000000);
5221 spr_register(env, SPR_SPRG7, "SPRG7",
5222 SPR_NOACCESS, SPR_NOACCESS,
5223 &spr_read_generic, &spr_write_generic,
5224 0x00000000);
5225 spr_register(env, SPR_USPRG7, "USPRG7",
5226 &spr_read_ureg, SPR_NOACCESS,
5227 &spr_read_ureg, SPR_NOACCESS,
5228 0x00000000);
5229 /* Memory management */
5230 register_low_BATs(env);
5231 register_high_BATs(env);
5232 init_excp_7450(env);
5233 env->dcache_line_size = 32;
5234 env->icache_line_size = 32;
5235 /* Allocate hardware IRQ controller */
5236 ppc6xx_irq_init(env_archcpu(env));
5237 }
5238
5239 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
5240 {
5241 DeviceClass *dc = DEVICE_CLASS(oc);
5242 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5243
5244 dc->desc = "PowerPC 7455 (aka G4)";
5245 pcc->init_proc = init_proc_7455;
5246 pcc->check_pow = check_pow_hid0_74xx;
5247 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5248 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5249 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5250 PPC_FLOAT_STFIWX |
5251 PPC_CACHE | PPC_CACHE_ICBI |
5252 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5253 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5254 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5255 PPC_MEM_TLBIA |
5256 PPC_SEGMENT | PPC_EXTERN |
5257 PPC_ALTIVEC;
5258 pcc->msr_mask = (1ull << MSR_VR) |
5259 (1ull << MSR_POW) |
5260 (1ull << MSR_ILE) |
5261 (1ull << MSR_EE) |
5262 (1ull << MSR_PR) |
5263 (1ull << MSR_FP) |
5264 (1ull << MSR_ME) |
5265 (1ull << MSR_FE0) |
5266 (1ull << MSR_SE) |
5267 (1ull << MSR_DE) |
5268 (1ull << MSR_FE1) |
5269 (1ull << MSR_EP) |
5270 (1ull << MSR_IR) |
5271 (1ull << MSR_DR) |
5272 (1ull << MSR_PMM) |
5273 (1ull << MSR_RI) |
5274 (1ull << MSR_LE);
5275 pcc->mmu_model = POWERPC_MMU_32B;
5276 pcc->excp_model = POWERPC_EXCP_74xx;
5277 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5278 pcc->bfd_mach = bfd_mach_ppc_7400;
5279 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5280 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5281 POWERPC_FLAG_BUS_CLK;
5282 }
5283
5284 static void init_proc_7457(CPUPPCState *env)
5285 {
5286 register_ne_601_sprs(env);
5287 register_sdr1_sprs(env);
5288 register_7xx_sprs(env);
5289 /* 74xx specific SPR */
5290 register_74xx_sprs(env);
5291 vscr_init(env, 0x00010000);
5292 /* Level 3 cache control */
5293 register_l3_ctrl(env);
5294 /* L3ITCR1 */
5295 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5296 SPR_NOACCESS, SPR_NOACCESS,
5297 &spr_read_generic, &spr_write_generic,
5298 0x00000000);
5299 /* L3ITCR2 */
5300 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5301 SPR_NOACCESS, SPR_NOACCESS,
5302 &spr_read_generic, &spr_write_generic,
5303 0x00000000);
5304 /* L3ITCR3 */
5305 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5306 SPR_NOACCESS, SPR_NOACCESS,
5307 &spr_read_generic, &spr_write_generic,
5308 0x00000000);
5309 /* L3OHCR */
5310 spr_register(env, SPR_L3OHCR, "L3OHCR",
5311 SPR_NOACCESS, SPR_NOACCESS,
5312 &spr_read_generic, &spr_write_generic,
5313 0x00000000);
5314 /* LDSTCR */
5315 spr_register(env, SPR_LDSTCR, "LDSTCR",
5316 SPR_NOACCESS, SPR_NOACCESS,
5317 &spr_read_generic, &spr_write_generic,
5318 0x00000000);
5319 /* ICTRL */
5320 spr_register(env, SPR_ICTRL, "ICTRL",
5321 SPR_NOACCESS, SPR_NOACCESS,
5322 &spr_read_generic, &spr_write_generic,
5323 0x00000000);
5324 /* MSSSR0 */
5325 spr_register(env, SPR_MSSSR0, "MSSSR0",
5326 SPR_NOACCESS, SPR_NOACCESS,
5327 &spr_read_generic, &spr_write_generic,
5328 0x00000000);
5329 /* PMC */
5330 spr_register(env, SPR_7XX_PMC5, "PMC5",
5331 SPR_NOACCESS, SPR_NOACCESS,
5332 &spr_read_generic, &spr_write_generic,
5333 0x00000000);
5334
5335 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5336 &spr_read_ureg, SPR_NOACCESS,
5337 &spr_read_ureg, SPR_NOACCESS,
5338 0x00000000);
5339
5340 spr_register(env, SPR_7XX_PMC6, "PMC6",
5341 SPR_NOACCESS, SPR_NOACCESS,
5342 &spr_read_generic, &spr_write_generic,
5343 0x00000000);
5344
5345 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5346 &spr_read_ureg, SPR_NOACCESS,
5347 &spr_read_ureg, SPR_NOACCESS,
5348 0x00000000);
5349 /* SPRGs */
5350 spr_register(env, SPR_SPRG4, "SPRG4",
5351 SPR_NOACCESS, SPR_NOACCESS,
5352 &spr_read_generic, &spr_write_generic,
5353 0x00000000);
5354 spr_register(env, SPR_USPRG4, "USPRG4",
5355 &spr_read_ureg, SPR_NOACCESS,
5356 &spr_read_ureg, SPR_NOACCESS,
5357 0x00000000);
5358 spr_register(env, SPR_SPRG5, "SPRG5",
5359 SPR_NOACCESS, SPR_NOACCESS,
5360 &spr_read_generic, &spr_write_generic,
5361 0x00000000);
5362 spr_register(env, SPR_USPRG5, "USPRG5",
5363 &spr_read_ureg, SPR_NOACCESS,
5364 &spr_read_ureg, SPR_NOACCESS,
5365 0x00000000);
5366 spr_register(env, SPR_SPRG6, "SPRG6",
5367 SPR_NOACCESS, SPR_NOACCESS,
5368 &spr_read_generic, &spr_write_generic,
5369 0x00000000);
5370 spr_register(env, SPR_USPRG6, "USPRG6",
5371 &spr_read_ureg, SPR_NOACCESS,
5372 &spr_read_ureg, SPR_NOACCESS,
5373 0x00000000);
5374 spr_register(env, SPR_SPRG7, "SPRG7",
5375 SPR_NOACCESS, SPR_NOACCESS,
5376 &spr_read_generic, &spr_write_generic,
5377 0x00000000);
5378 spr_register(env, SPR_USPRG7, "USPRG7",
5379 &spr_read_ureg, SPR_NOACCESS,
5380 &spr_read_ureg, SPR_NOACCESS,
5381 0x00000000);
5382 /* Memory management */
5383 register_low_BATs(env);
5384 register_high_BATs(env);
5385 init_excp_7450(env);
5386 env->dcache_line_size = 32;
5387 env->icache_line_size = 32;
5388 /* Allocate hardware IRQ controller */
5389 ppc6xx_irq_init(env_archcpu(env));
5390 }
5391
5392 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
5393 {
5394 DeviceClass *dc = DEVICE_CLASS(oc);
5395 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5396
5397 dc->desc = "PowerPC 7457 (aka G4)";
5398 pcc->init_proc = init_proc_7457;
5399 pcc->check_pow = check_pow_hid0_74xx;
5400 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5401 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5402 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5403 PPC_FLOAT_STFIWX |
5404 PPC_CACHE | PPC_CACHE_ICBI |
5405 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5406 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5407 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5408 PPC_MEM_TLBIA |
5409 PPC_SEGMENT | PPC_EXTERN |
5410 PPC_ALTIVEC;
5411 pcc->msr_mask = (1ull << MSR_VR) |
5412 (1ull << MSR_POW) |
5413 (1ull << MSR_ILE) |
5414 (1ull << MSR_EE) |
5415 (1ull << MSR_PR) |
5416 (1ull << MSR_FP) |
5417 (1ull << MSR_ME) |
5418 (1ull << MSR_FE0) |
5419 (1ull << MSR_SE) |
5420 (1ull << MSR_DE) |
5421 (1ull << MSR_FE1) |
5422 (1ull << MSR_EP) |
5423 (1ull << MSR_IR) |
5424 (1ull << MSR_DR) |
5425 (1ull << MSR_PMM) |
5426 (1ull << MSR_RI) |
5427 (1ull << MSR_LE);
5428 pcc->mmu_model = POWERPC_MMU_32B;
5429 pcc->excp_model = POWERPC_EXCP_74xx;
5430 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5431 pcc->bfd_mach = bfd_mach_ppc_7400;
5432 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5433 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5434 POWERPC_FLAG_BUS_CLK;
5435 }
5436
5437 static void init_proc_e600(CPUPPCState *env)
5438 {
5439 register_ne_601_sprs(env);
5440 register_sdr1_sprs(env);
5441 register_7xx_sprs(env);
5442 /* 74xx specific SPR */
5443 register_74xx_sprs(env);
5444 vscr_init(env, 0x00010000);
5445
5446 spr_register(env, SPR_UBAMR, "UBAMR",
5447 &spr_read_ureg, SPR_NOACCESS,
5448 &spr_read_ureg, SPR_NOACCESS,
5449 0x00000000);
5450
5451 spr_register(env, SPR_LDSTCR, "LDSTCR",
5452 SPR_NOACCESS, SPR_NOACCESS,
5453 &spr_read_generic, &spr_write_generic,
5454 0x00000000);
5455
5456 spr_register(env, SPR_ICTRL, "ICTRL",
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 &spr_read_generic, &spr_write_generic,
5459 0x00000000);
5460
5461 spr_register(env, SPR_MSSSR0, "MSSSR0",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465
5466 spr_register(env, SPR_7XX_PMC5, "PMC5",
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 &spr_read_generic, &spr_write_generic,
5469 0x00000000);
5470
5471 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5472 &spr_read_ureg, SPR_NOACCESS,
5473 &spr_read_ureg, SPR_NOACCESS,
5474 0x00000000);
5475
5476 spr_register(env, SPR_7XX_PMC6, "PMC6",
5477 SPR_NOACCESS, SPR_NOACCESS,
5478 &spr_read_generic, &spr_write_generic,
5479 0x00000000);
5480
5481 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5482 &spr_read_ureg, SPR_NOACCESS,
5483 &spr_read_ureg, SPR_NOACCESS,
5484 0x00000000);
5485 /* SPRGs */
5486 spr_register(env, SPR_SPRG4, "SPRG4",
5487 SPR_NOACCESS, SPR_NOACCESS,
5488 &spr_read_generic, &spr_write_generic,
5489 0x00000000);
5490 spr_register(env, SPR_USPRG4, "USPRG4",
5491 &spr_read_ureg, SPR_NOACCESS,
5492 &spr_read_ureg, SPR_NOACCESS,
5493 0x00000000);
5494 spr_register(env, SPR_SPRG5, "SPRG5",
5495 SPR_NOACCESS, SPR_NOACCESS,
5496 &spr_read_generic, &spr_write_generic,
5497 0x00000000);
5498 spr_register(env, SPR_USPRG5, "USPRG5",
5499 &spr_read_ureg, SPR_NOACCESS,
5500 &spr_read_ureg, SPR_NOACCESS,
5501 0x00000000);
5502 spr_register(env, SPR_SPRG6, "SPRG6",
5503 SPR_NOACCESS, SPR_NOACCESS,
5504 &spr_read_generic, &spr_write_generic,
5505 0x00000000);
5506 spr_register(env, SPR_USPRG6, "USPRG6",
5507 &spr_read_ureg, SPR_NOACCESS,
5508 &spr_read_ureg, SPR_NOACCESS,
5509 0x00000000);
5510 spr_register(env, SPR_SPRG7, "SPRG7",
5511 SPR_NOACCESS, SPR_NOACCESS,
5512 &spr_read_generic, &spr_write_generic,
5513 0x00000000);
5514 spr_register(env, SPR_USPRG7, "USPRG7",
5515 &spr_read_ureg, SPR_NOACCESS,
5516 &spr_read_ureg, SPR_NOACCESS,
5517 0x00000000);
5518 /* Memory management */
5519 register_low_BATs(env);
5520 register_high_BATs(env);
5521 init_excp_7450(env);
5522 env->dcache_line_size = 32;
5523 env->icache_line_size = 32;
5524 /* Allocate hardware IRQ controller */
5525 ppc6xx_irq_init(env_archcpu(env));
5526 }
5527
5528 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
5529 {
5530 DeviceClass *dc = DEVICE_CLASS(oc);
5531 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5532
5533 dc->desc = "PowerPC e600";
5534 pcc->init_proc = init_proc_e600;
5535 pcc->check_pow = check_pow_hid0_74xx;
5536 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5537 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5538 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5539 PPC_FLOAT_STFIWX |
5540 PPC_CACHE | PPC_CACHE_ICBI |
5541 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5542 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5543 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5544 PPC_MEM_TLBIA |
5545 PPC_SEGMENT | PPC_EXTERN |
5546 PPC_ALTIVEC;
5547 pcc->insns_flags2 = PPC_NONE;
5548 pcc->msr_mask = (1ull << MSR_VR) |
5549 (1ull << MSR_POW) |
5550 (1ull << MSR_ILE) |
5551 (1ull << MSR_EE) |
5552 (1ull << MSR_PR) |
5553 (1ull << MSR_FP) |
5554 (1ull << MSR_ME) |
5555 (1ull << MSR_FE0) |
5556 (1ull << MSR_SE) |
5557 (1ull << MSR_DE) |
5558 (1ull << MSR_FE1) |
5559 (1ull << MSR_EP) |
5560 (1ull << MSR_IR) |
5561 (1ull << MSR_DR) |
5562 (1ull << MSR_PMM) |
5563 (1ull << MSR_RI) |
5564 (1ull << MSR_LE);
5565 pcc->mmu_model = POWERPC_MMU_32B;
5566 pcc->excp_model = POWERPC_EXCP_74xx;
5567 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5568 pcc->bfd_mach = bfd_mach_ppc_7400;
5569 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5570 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5571 POWERPC_FLAG_BUS_CLK;
5572 }
5573
5574 #if defined(TARGET_PPC64)
5575 #if defined(CONFIG_USER_ONLY)
5576 #define POWERPC970_HID5_INIT 0x00000080
5577 #else
5578 #define POWERPC970_HID5_INIT 0x00000000
5579 #endif
5580
5581 static int check_pow_970(CPUPPCState *env)
5582 {
5583 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5584 return 1;
5585 }
5586
5587 return 0;
5588 }
5589
5590 static void register_970_hid_sprs(CPUPPCState *env)
5591 {
5592 /* Hardware implementation registers */
5593 spr_register(env, SPR_HID0, "HID0",
5594 SPR_NOACCESS, SPR_NOACCESS,
5595 &spr_read_generic, &spr_write_clear,
5596 0x60000000);
5597 spr_register(env, SPR_HID1, "HID1",
5598 SPR_NOACCESS, SPR_NOACCESS,
5599 &spr_read_generic, &spr_write_generic,
5600 0x00000000);
5601 spr_register(env, SPR_970_HID5, "HID5",
5602 SPR_NOACCESS, SPR_NOACCESS,
5603 &spr_read_generic, &spr_write_generic,
5604 POWERPC970_HID5_INIT);
5605 }
5606
5607 static void register_970_hior_sprs(CPUPPCState *env)
5608 {
5609 spr_register(env, SPR_HIOR, "SPR_HIOR",
5610 SPR_NOACCESS, SPR_NOACCESS,
5611 &spr_read_hior, &spr_write_hior,
5612 0x00000000);
5613 }
5614
5615 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5616 {
5617 spr_register(env, SPR_CTRL, "SPR_CTRL",
5618 SPR_NOACCESS, SPR_NOACCESS,
5619 SPR_NOACCESS, &spr_write_CTRL,
5620 0x00000000);
5621 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5622 &spr_read_ureg, SPR_NOACCESS,
5623 &spr_read_ureg, SPR_NOACCESS,
5624 0x00000000);
5625 }
5626
5627 static void register_book3s_altivec_sprs(CPUPPCState *env)
5628 {
5629 if (!(env->insns_flags & PPC_ALTIVEC)) {
5630 return;
5631 }
5632
5633 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5634 &spr_read_generic, &spr_write_generic,
5635 &spr_read_generic, &spr_write_generic,
5636 KVM_REG_PPC_VRSAVE, 0x00000000);
5637
5638 }
5639
5640 static void register_book3s_dbg_sprs(CPUPPCState *env)
5641 {
5642 /*
5643 * TODO: different specs define different scopes for these,
5644 * will have to address this:
5645 * 970: super/write and super/read
5646 * powerisa 2.03..2.04: hypv/write and super/read.
5647 * powerisa 2.05 and newer: hypv/write and hypv/read.
5648 */
5649 spr_register_kvm(env, SPR_DABR, "DABR",
5650 SPR_NOACCESS, SPR_NOACCESS,
5651 &spr_read_generic, &spr_write_generic,
5652 KVM_REG_PPC_DABR, 0x00000000);
5653 spr_register_kvm(env, SPR_DABRX, "DABRX",
5654 SPR_NOACCESS, SPR_NOACCESS,
5655 &spr_read_generic, &spr_write_generic,
5656 KVM_REG_PPC_DABRX, 0x00000000);
5657 }
5658
5659 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5660 {
5661 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5662 SPR_NOACCESS, SPR_NOACCESS,
5663 SPR_NOACCESS, SPR_NOACCESS,
5664 &spr_read_generic, &spr_write_generic,
5665 KVM_REG_PPC_DAWR, 0x00000000);
5666 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 SPR_NOACCESS, SPR_NOACCESS,
5669 &spr_read_generic, &spr_write_generic,
5670 KVM_REG_PPC_DAWRX, 0x00000000);
5671 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5672 SPR_NOACCESS, SPR_NOACCESS,
5673 SPR_NOACCESS, SPR_NOACCESS,
5674 &spr_read_generic, &spr_write_generic,
5675 KVM_REG_PPC_CIABR, 0x00000000);
5676 }
5677
5678 static void register_970_dbg_sprs(CPUPPCState *env)
5679 {
5680 /* Breakpoints */
5681 spr_register(env, SPR_IABR, "IABR",
5682 SPR_NOACCESS, SPR_NOACCESS,
5683 &spr_read_generic, &spr_write_generic,
5684 0x00000000);
5685 }
5686
5687 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5688 {
5689 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 &spr_read_generic, &spr_write_MMCR0,
5692 KVM_REG_PPC_MMCR0, 0x80000000);
5693 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5694 SPR_NOACCESS, SPR_NOACCESS,
5695 &spr_read_generic, &spr_write_MMCR1,
5696 KVM_REG_PPC_MMCR1, 0x00000000);
5697 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5698 SPR_NOACCESS, SPR_NOACCESS,
5699 &spr_read_generic, &spr_write_generic,
5700 KVM_REG_PPC_MMCRA, 0x00000000);
5701 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5702 SPR_NOACCESS, SPR_NOACCESS,
5703 &spr_read_PMC, &spr_write_PMC,
5704 KVM_REG_PPC_PMC1, 0x00000000);
5705 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5706 SPR_NOACCESS, SPR_NOACCESS,
5707 &spr_read_PMC, &spr_write_PMC,
5708 KVM_REG_PPC_PMC2, 0x00000000);
5709 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5710 SPR_NOACCESS, SPR_NOACCESS,
5711 &spr_read_PMC, &spr_write_PMC,
5712 KVM_REG_PPC_PMC3, 0x00000000);
5713 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5714 SPR_NOACCESS, SPR_NOACCESS,
5715 &spr_read_PMC, &spr_write_PMC,
5716 KVM_REG_PPC_PMC4, 0x00000000);
5717 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5718 SPR_NOACCESS, SPR_NOACCESS,
5719 &spr_read_PMC, &spr_write_PMC,
5720 KVM_REG_PPC_PMC5, 0x00000000);
5721 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 &spr_read_PMC, &spr_write_PMC,
5724 KVM_REG_PPC_PMC6, 0x00000000);
5725 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5726 SPR_NOACCESS, SPR_NOACCESS,
5727 &spr_read_generic, &spr_write_generic,
5728 KVM_REG_PPC_SIAR, 0x00000000);
5729 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5730 SPR_NOACCESS, SPR_NOACCESS,
5731 &spr_read_generic, &spr_write_generic,
5732 KVM_REG_PPC_SDAR, 0x00000000);
5733 }
5734
5735 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5736 {
5737 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5738 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5739 &spr_read_ureg, &spr_write_ureg,
5740 0x80000000);
5741 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5742 &spr_read_ureg, SPR_NOACCESS,
5743 &spr_read_ureg, &spr_write_ureg,
5744 0x00000000);
5745 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5746 &spr_read_ureg, SPR_NOACCESS,
5747 &spr_read_ureg, &spr_write_ureg,
5748 0x00000000);
5749 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5750 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5751 &spr_read_ureg, &spr_write_ureg,
5752 0x00000000);
5753 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5754 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5755 &spr_read_ureg, &spr_write_ureg,
5756 0x00000000);
5757 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5758 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5759 &spr_read_ureg, &spr_write_ureg,
5760 0x00000000);
5761 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5762 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5763 &spr_read_ureg, &spr_write_ureg,
5764 0x00000000);
5765 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5766 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5767 &spr_read_ureg, &spr_write_ureg,
5768 0x00000000);
5769 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5770 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5771 &spr_read_ureg, &spr_write_ureg,
5772 0x00000000);
5773 spr_register(env, SPR_POWER_USIAR, "USIAR",
5774 &spr_read_ureg, SPR_NOACCESS,
5775 &spr_read_ureg, &spr_write_ureg,
5776 0x00000000);
5777 spr_register(env, SPR_POWER_USDAR, "USDAR",
5778 &spr_read_ureg, SPR_NOACCESS,
5779 &spr_read_ureg, &spr_write_ureg,
5780 0x00000000);
5781 }
5782
5783 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5784 {
5785 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 KVM_REG_PPC_PMC7, 0x00000000);
5789 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5790 SPR_NOACCESS, SPR_NOACCESS,
5791 &spr_read_generic, &spr_write_generic,
5792 KVM_REG_PPC_PMC8, 0x00000000);
5793 }
5794
5795 static void register_970_pmu_user_sprs(CPUPPCState *env)
5796 {
5797 spr_register(env, SPR_970_UPMC7, "UPMC7",
5798 &spr_read_ureg, SPR_NOACCESS,
5799 &spr_read_ureg, &spr_write_ureg,
5800 0x00000000);
5801 spr_register(env, SPR_970_UPMC8, "UPMC8",
5802 &spr_read_ureg, SPR_NOACCESS,
5803 &spr_read_ureg, &spr_write_ureg,
5804 0x00000000);
5805 }
5806
5807 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5808 {
5809 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5810 SPR_NOACCESS, SPR_NOACCESS,
5811 &spr_read_generic, &spr_write_generic,
5812 KVM_REG_PPC_MMCR2, 0x00000000);
5813 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5814 SPR_NOACCESS, SPR_NOACCESS,
5815 &spr_read_generic, &spr_write_generic,
5816 KVM_REG_PPC_MMCRS, 0x00000000);
5817 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5818 SPR_NOACCESS, SPR_NOACCESS,
5819 &spr_read_generic, &spr_write_generic,
5820 KVM_REG_PPC_SIER, 0x00000000);
5821 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, &spr_write_generic,
5824 KVM_REG_PPC_SPMC1, 0x00000000);
5825 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5826 SPR_NOACCESS, SPR_NOACCESS,
5827 &spr_read_generic, &spr_write_generic,
5828 KVM_REG_PPC_SPMC2, 0x00000000);
5829 spr_register_kvm(env, SPR_TACR, "TACR",
5830 SPR_NOACCESS, SPR_NOACCESS,
5831 &spr_read_generic, &spr_write_generic,
5832 KVM_REG_PPC_TACR, 0x00000000);
5833 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5834 SPR_NOACCESS, SPR_NOACCESS,
5835 &spr_read_generic, &spr_write_generic,
5836 KVM_REG_PPC_TCSCR, 0x00000000);
5837 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5838 SPR_NOACCESS, SPR_NOACCESS,
5839 &spr_read_generic, &spr_write_generic,
5840 KVM_REG_PPC_CSIGR, 0x00000000);
5841 }
5842
5843 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5844 {
5845 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5846 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5847 &spr_read_ureg, &spr_write_ureg,
5848 0x00000000);
5849 spr_register(env, SPR_POWER_USIER, "USIER",
5850 &spr_read_generic, SPR_NOACCESS,
5851 &spr_read_generic, &spr_write_generic,
5852 0x00000000);
5853 }
5854
5855 static void register_power5p_ear_sprs(CPUPPCState *env)
5856 {
5857 /* External access control */
5858 spr_register(env, SPR_EAR, "EAR",
5859 SPR_NOACCESS, SPR_NOACCESS,
5860 &spr_read_generic, &spr_write_generic,
5861 0x00000000);
5862 }
5863
5864 static void register_power5p_tb_sprs(CPUPPCState *env)
5865 {
5866 /* TBU40 (High 40 bits of the Timebase register */
5867 spr_register_hv(env, SPR_TBU40, "TBU40",
5868 SPR_NOACCESS, SPR_NOACCESS,
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 SPR_NOACCESS, &spr_write_tbu40,
5871 0x00000000);
5872 }
5873
5874 static void register_970_lpar_sprs(CPUPPCState *env)
5875 {
5876 #if !defined(CONFIG_USER_ONLY)
5877 /*
5878 * PPC970: HID4 covers things later controlled by the LPCR and
5879 * RMOR in later CPUs, but with a different encoding. We only
5880 * support the 970 in "Apple mode" which has all hypervisor
5881 * facilities disabled by strapping, so we can basically just
5882 * ignore it
5883 */
5884 spr_register(env, SPR_970_HID4, "HID4",
5885 SPR_NOACCESS, SPR_NOACCESS,
5886 &spr_read_generic, &spr_write_generic,
5887 0x00000000);
5888 #endif
5889 }
5890
5891 static void register_power5p_lpar_sprs(CPUPPCState *env)
5892 {
5893 #if !defined(CONFIG_USER_ONLY)
5894 /* Logical partitionning */
5895 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5896 SPR_NOACCESS, SPR_NOACCESS,
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_lpcr,
5899 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5900 spr_register_hv(env, SPR_HDEC, "HDEC",
5901 SPR_NOACCESS, SPR_NOACCESS,
5902 SPR_NOACCESS, SPR_NOACCESS,
5903 &spr_read_hdecr, &spr_write_hdecr, 0);
5904 #endif
5905 }
5906
5907 static void register_book3s_ids_sprs(CPUPPCState *env)
5908 {
5909 /* FIXME: Will need to deal with thread vs core only SPRs */
5910
5911 /* Processor identification */
5912 spr_register_hv(env, SPR_PIR, "PIR",
5913 SPR_NOACCESS, SPR_NOACCESS,
5914 &spr_read_generic, SPR_NOACCESS,
5915 &spr_read_generic, NULL,
5916 0x00000000);
5917 spr_register_hv(env, SPR_HID0, "HID0",
5918 SPR_NOACCESS, SPR_NOACCESS,
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 &spr_read_generic, &spr_write_generic,
5921 0x00000000);
5922 spr_register_hv(env, SPR_TSCR, "TSCR",
5923 SPR_NOACCESS, SPR_NOACCESS,
5924 SPR_NOACCESS, SPR_NOACCESS,
5925 &spr_read_generic, &spr_write_generic,
5926 0x00000000);
5927 spr_register_hv(env, SPR_HMER, "HMER",
5928 SPR_NOACCESS, SPR_NOACCESS,
5929 SPR_NOACCESS, SPR_NOACCESS,
5930 &spr_read_generic, &spr_write_hmer,
5931 0x00000000);
5932 spr_register_hv(env, SPR_HMEER, "HMEER",
5933 SPR_NOACCESS, SPR_NOACCESS,
5934 SPR_NOACCESS, SPR_NOACCESS,
5935 &spr_read_generic, &spr_write_generic,
5936 0x00000000);
5937 spr_register_hv(env, SPR_TFMR, "TFMR",
5938 SPR_NOACCESS, SPR_NOACCESS,
5939 SPR_NOACCESS, SPR_NOACCESS,
5940 &spr_read_generic, &spr_write_generic,
5941 0x00000000);
5942 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5943 SPR_NOACCESS, SPR_NOACCESS,
5944 SPR_NOACCESS, SPR_NOACCESS,
5945 &spr_read_generic, &spr_write_lpidr,
5946 0x00000000);
5947 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5948 SPR_NOACCESS, SPR_NOACCESS,
5949 SPR_NOACCESS, SPR_NOACCESS,
5950 &spr_read_generic, &spr_write_generic,
5951 0x00000000);
5952 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5953 SPR_NOACCESS, SPR_NOACCESS,
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 0x00000000);
5957 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5958 SPR_NOACCESS, SPR_NOACCESS,
5959 SPR_NOACCESS, SPR_NOACCESS,
5960 &spr_read_generic, &spr_write_generic,
5961 0x00000000);
5962 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5963 SPR_NOACCESS, SPR_NOACCESS,
5964 SPR_NOACCESS, SPR_NOACCESS,
5965 &spr_read_generic, &spr_write_generic,
5966 0x00000000);
5967 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5968 SPR_NOACCESS, SPR_NOACCESS,
5969 SPR_NOACCESS, SPR_NOACCESS,
5970 &spr_read_generic, &spr_write_generic,
5971 0x00000000);
5972 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5973 SPR_NOACCESS, SPR_NOACCESS,
5974 SPR_NOACCESS, SPR_NOACCESS,
5975 &spr_read_generic, &spr_write_generic,
5976 0x00000000);
5977 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5978 SPR_NOACCESS, SPR_NOACCESS,
5979 SPR_NOACCESS, SPR_NOACCESS,
5980 &spr_read_generic, &spr_write_generic,
5981 0x00000000);
5982 spr_register_hv(env, SPR_HDAR, "HDAR",
5983 SPR_NOACCESS, SPR_NOACCESS,
5984 SPR_NOACCESS, SPR_NOACCESS,
5985 &spr_read_generic, &spr_write_generic,
5986 0x00000000);
5987 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5988 SPR_NOACCESS, SPR_NOACCESS,
5989 SPR_NOACCESS, SPR_NOACCESS,
5990 &spr_read_generic, &spr_write_generic,
5991 0x00000000);
5992 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5993 SPR_NOACCESS, SPR_NOACCESS,
5994 SPR_NOACCESS, SPR_NOACCESS,
5995 &spr_read_generic, &spr_write_generic,
5996 0x00000000);
5997 }
5998
5999 static void register_rmor_sprs(CPUPPCState *env)
6000 {
6001 spr_register_hv(env, SPR_RMOR, "RMOR",
6002 SPR_NOACCESS, SPR_NOACCESS,
6003 SPR_NOACCESS, SPR_NOACCESS,
6004 &spr_read_generic, &spr_write_generic,
6005 0x00000000);
6006 }
6007
6008 static void register_power8_ids_sprs(CPUPPCState *env)
6009 {
6010 /* Thread identification */
6011 spr_register(env, SPR_TIR, "TIR",
6012 SPR_NOACCESS, SPR_NOACCESS,
6013 &spr_read_generic, SPR_NOACCESS,
6014 0x00000000);
6015 }
6016
6017 static void register_book3s_purr_sprs(CPUPPCState *env)
6018 {
6019 #if !defined(CONFIG_USER_ONLY)
6020 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6021 spr_register_kvm_hv(env, SPR_PURR, "PURR",
6022 &spr_read_purr, SPR_NOACCESS,
6023 &spr_read_purr, SPR_NOACCESS,
6024 &spr_read_purr, &spr_write_purr,
6025 KVM_REG_PPC_PURR, 0x00000000);
6026 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
6027 &spr_read_purr, SPR_NOACCESS,
6028 &spr_read_purr, SPR_NOACCESS,
6029 &spr_read_purr, &spr_write_purr,
6030 KVM_REG_PPC_SPURR, 0x00000000);
6031 #endif
6032 }
6033
6034 static void register_power6_dbg_sprs(CPUPPCState *env)
6035 {
6036 #if !defined(CONFIG_USER_ONLY)
6037 spr_register(env, SPR_CFAR, "SPR_CFAR",
6038 SPR_NOACCESS, SPR_NOACCESS,
6039 &spr_read_cfar, &spr_write_cfar,
6040 0x00000000);
6041 #endif
6042 }
6043
6044 static void register_power5p_common_sprs(CPUPPCState *env)
6045 {
6046 spr_register_kvm(env, SPR_PPR, "PPR",
6047 &spr_read_generic, &spr_write_generic,
6048 &spr_read_generic, &spr_write_generic,
6049 KVM_REG_PPC_PPR, 0x00000000);
6050 }
6051
6052 static void register_power6_common_sprs(CPUPPCState *env)
6053 {
6054 #if !defined(CONFIG_USER_ONLY)
6055 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6056 SPR_NOACCESS, SPR_NOACCESS,
6057 &spr_read_generic, &spr_write_generic,
6058 KVM_REG_PPC_DSCR, 0x00000000);
6059 #endif
6060 /*
6061 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
6062 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
6063 */
6064 spr_register_hv(env, SPR_PCR, "PCR",
6065 SPR_NOACCESS, SPR_NOACCESS,
6066 SPR_NOACCESS, SPR_NOACCESS,
6067 &spr_read_generic, &spr_write_pcr,
6068 0x00000000);
6069 }
6070
6071 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
6072 {
6073 spr_register_kvm(env, SPR_TAR, "TAR",
6074 &spr_read_tar, &spr_write_tar,
6075 &spr_read_generic, &spr_write_generic,
6076 KVM_REG_PPC_TAR, 0x00000000);
6077 }
6078
6079 static void register_power8_tm_sprs(CPUPPCState *env)
6080 {
6081 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
6082 &spr_read_tm, &spr_write_tm,
6083 &spr_read_tm, &spr_write_tm,
6084 KVM_REG_PPC_TFHAR, 0x00000000);
6085 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
6086 &spr_read_tm, &spr_write_tm,
6087 &spr_read_tm, &spr_write_tm,
6088 KVM_REG_PPC_TFIAR, 0x00000000);
6089 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
6090 &spr_read_tm, &spr_write_tm,
6091 &spr_read_tm, &spr_write_tm,
6092 KVM_REG_PPC_TEXASR, 0x00000000);
6093 spr_register(env, SPR_TEXASRU, "TEXASRU",
6094 &spr_read_tm_upper32, &spr_write_tm_upper32,
6095 &spr_read_tm_upper32, &spr_write_tm_upper32,
6096 0x00000000);
6097 }
6098
6099 static void register_power8_ebb_sprs(CPUPPCState *env)
6100 {
6101 spr_register(env, SPR_BESCRS, "BESCRS",
6102 &spr_read_ebb, &spr_write_ebb,
6103 &spr_read_generic, &spr_write_generic,
6104 0x00000000);
6105 spr_register(env, SPR_BESCRSU, "BESCRSU",
6106 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6107 &spr_read_prev_upper32, &spr_write_prev_upper32,
6108 0x00000000);
6109 spr_register(env, SPR_BESCRR, "BESCRR",
6110 &spr_read_ebb, &spr_write_ebb,
6111 &spr_read_generic, &spr_write_generic,
6112 0x00000000);
6113 spr_register(env, SPR_BESCRRU, "BESCRRU",
6114 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6115 &spr_read_prev_upper32, &spr_write_prev_upper32,
6116 0x00000000);
6117 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
6118 &spr_read_ebb, &spr_write_ebb,
6119 &spr_read_generic, &spr_write_generic,
6120 KVM_REG_PPC_EBBHR, 0x00000000);
6121 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
6122 &spr_read_ebb, &spr_write_ebb,
6123 &spr_read_generic, &spr_write_generic,
6124 KVM_REG_PPC_EBBRR, 0x00000000);
6125 spr_register_kvm(env, SPR_BESCR, "BESCR",
6126 &spr_read_ebb, &spr_write_ebb,
6127 &spr_read_generic, &spr_write_generic,
6128 KVM_REG_PPC_BESCR, 0x00000000);
6129 }
6130
6131 /* Virtual Time Base */
6132 static void register_vtb_sprs(CPUPPCState *env)
6133 {
6134 spr_register_kvm_hv(env, SPR_VTB, "VTB",
6135 SPR_NOACCESS, SPR_NOACCESS,
6136 &spr_read_vtb, SPR_NOACCESS,
6137 &spr_read_vtb, &spr_write_vtb,
6138 KVM_REG_PPC_VTB, 0x00000000);
6139 }
6140
6141 static void register_power8_fscr_sprs(CPUPPCState *env)
6142 {
6143 #if defined(CONFIG_USER_ONLY)
6144 target_ulong initval = 1ULL << FSCR_TAR;
6145 #else
6146 target_ulong initval = 0;
6147 #endif
6148 spr_register_kvm(env, SPR_FSCR, "FSCR",
6149 SPR_NOACCESS, SPR_NOACCESS,
6150 &spr_read_generic, &spr_write_generic,
6151 KVM_REG_PPC_FSCR, initval);
6152 }
6153
6154 static void register_power8_pspb_sprs(CPUPPCState *env)
6155 {
6156 spr_register_kvm(env, SPR_PSPB, "PSPB",
6157 SPR_NOACCESS, SPR_NOACCESS,
6158 &spr_read_generic, &spr_write_generic32,
6159 KVM_REG_PPC_PSPB, 0);
6160 }
6161
6162 static void register_power8_dpdes_sprs(CPUPPCState *env)
6163 {
6164 #if !defined(CONFIG_USER_ONLY)
6165 /* Directed Privileged Door-bell Exception State, used for IPI */
6166 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
6167 SPR_NOACCESS, SPR_NOACCESS,
6168 &spr_read_dpdes, SPR_NOACCESS,
6169 &spr_read_dpdes, &spr_write_dpdes,
6170 KVM_REG_PPC_DPDES, 0x00000000);
6171 #endif
6172 }
6173
6174 static void register_power8_ic_sprs(CPUPPCState *env)
6175 {
6176 #if !defined(CONFIG_USER_ONLY)
6177 spr_register_hv(env, SPR_IC, "IC",
6178 SPR_NOACCESS, SPR_NOACCESS,
6179 &spr_read_generic, SPR_NOACCESS,
6180 &spr_read_generic, &spr_write_generic,
6181 0);
6182 #endif
6183 }
6184
6185 static void register_power8_book4_sprs(CPUPPCState *env)
6186 {
6187 /* Add a number of P8 book4 registers */
6188 #if !defined(CONFIG_USER_ONLY)
6189 spr_register_kvm(env, SPR_ACOP, "ACOP",
6190 SPR_NOACCESS, SPR_NOACCESS,
6191 &spr_read_generic, &spr_write_generic,
6192 KVM_REG_PPC_ACOP, 0);
6193 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6194 SPR_NOACCESS, SPR_NOACCESS,
6195 &spr_read_generic, &spr_write_pidr,
6196 KVM_REG_PPC_PID, 0);
6197 spr_register_kvm(env, SPR_WORT, "WORT",
6198 SPR_NOACCESS, SPR_NOACCESS,
6199 &spr_read_generic, &spr_write_generic,
6200 KVM_REG_PPC_WORT, 0);
6201 #endif
6202 }
6203
6204 static void register_power7_book4_sprs(CPUPPCState *env)
6205 {
6206 /* Add a number of P7 book4 registers */
6207 #if !defined(CONFIG_USER_ONLY)
6208 spr_register_kvm(env, SPR_ACOP, "ACOP",
6209 SPR_NOACCESS, SPR_NOACCESS,
6210 &spr_read_generic, &spr_write_generic,
6211 KVM_REG_PPC_ACOP, 0);
6212 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6213 SPR_NOACCESS, SPR_NOACCESS,
6214 &spr_read_generic, &spr_write_generic,
6215 KVM_REG_PPC_PID, 0);
6216 #endif
6217 }
6218
6219 static void register_power8_rpr_sprs(CPUPPCState *env)
6220 {
6221 #if !defined(CONFIG_USER_ONLY)
6222 spr_register_hv(env, SPR_RPR, "RPR",
6223 SPR_NOACCESS, SPR_NOACCESS,
6224 SPR_NOACCESS, SPR_NOACCESS,
6225 &spr_read_generic, &spr_write_generic,
6226 0x00000103070F1F3F);
6227 #endif
6228 }
6229
6230 static void register_power9_mmu_sprs(CPUPPCState *env)
6231 {
6232 #if !defined(CONFIG_USER_ONLY)
6233 /* Partition Table Control */
6234 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
6235 SPR_NOACCESS, SPR_NOACCESS,
6236 SPR_NOACCESS, SPR_NOACCESS,
6237 &spr_read_generic, &spr_write_ptcr,
6238 KVM_REG_PPC_PTCR, 0x00000000);
6239 /* Address Segment Descriptor Register */
6240 spr_register_hv(env, SPR_ASDR, "ASDR",
6241 SPR_NOACCESS, SPR_NOACCESS,
6242 SPR_NOACCESS, SPR_NOACCESS,
6243 &spr_read_generic, &spr_write_generic,
6244 0x0000000000000000);
6245 #endif
6246 }
6247
6248 /*
6249 * Initialize PMU counter overflow timers for Power8 and
6250 * newer Power chips when using TCG.
6251 */
6252 static void init_tcg_pmu_power8(CPUPPCState *env)
6253 {
6254 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
6255 /* Init PMU overflow timers */
6256 if (!kvm_enabled()) {
6257 cpu_ppc_pmu_init(env);
6258 }
6259 #endif
6260 }
6261
6262 static void init_proc_book3s_common(CPUPPCState *env)
6263 {
6264 register_ne_601_sprs(env);
6265 register_usprg3_sprs(env);
6266 register_book3s_altivec_sprs(env);
6267 register_book3s_pmu_sup_sprs(env);
6268 register_book3s_pmu_user_sprs(env);
6269 register_book3s_ctrl_sprs(env);
6270 /*
6271 * Can't find information on what this should be on reset. This
6272 * value is the one used by 74xx processors.
6273 */
6274 vscr_init(env, 0x00010000);
6275 }
6276
6277 static void init_proc_970(CPUPPCState *env)
6278 {
6279 /* Common Registers */
6280 init_proc_book3s_common(env);
6281 register_sdr1_sprs(env);
6282 register_book3s_dbg_sprs(env);
6283
6284 /* 970 Specific Registers */
6285 register_970_hid_sprs(env);
6286 register_970_hior_sprs(env);
6287 register_low_BATs(env);
6288 register_970_pmu_sup_sprs(env);
6289 register_970_pmu_user_sprs(env);
6290 register_970_lpar_sprs(env);
6291 register_970_dbg_sprs(env);
6292
6293 /* env variables */
6294 env->dcache_line_size = 128;
6295 env->icache_line_size = 128;
6296
6297 /* Allocate hardware IRQ controller */
6298 init_excp_970(env);
6299 ppc970_irq_init(env_archcpu(env));
6300 }
6301
6302 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6303 {
6304 DeviceClass *dc = DEVICE_CLASS(oc);
6305 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6306
6307 dc->desc = "PowerPC 970";
6308 pcc->init_proc = init_proc_970;
6309 pcc->check_pow = check_pow_970;
6310 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6311 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6312 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6313 PPC_FLOAT_STFIWX |
6314 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6315 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6317 PPC_64B | PPC_ALTIVEC |
6318 PPC_SEGMENT_64B | PPC_SLBI;
6319 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6320 pcc->msr_mask = (1ull << MSR_SF) |
6321 (1ull << MSR_VR) |
6322 (1ull << MSR_POW) |
6323 (1ull << MSR_EE) |
6324 (1ull << MSR_PR) |
6325 (1ull << MSR_FP) |
6326 (1ull << MSR_ME) |
6327 (1ull << MSR_FE0) |
6328 (1ull << MSR_SE) |
6329 (1ull << MSR_DE) |
6330 (1ull << MSR_FE1) |
6331 (1ull << MSR_IR) |
6332 (1ull << MSR_DR) |
6333 (1ull << MSR_PMM) |
6334 (1ull << MSR_RI);
6335 pcc->mmu_model = POWERPC_MMU_64B;
6336 #if defined(CONFIG_SOFTMMU)
6337 pcc->hash64_opts = &ppc_hash64_opts_basic;
6338 #endif
6339 pcc->excp_model = POWERPC_EXCP_970;
6340 pcc->bus_model = PPC_FLAGS_INPUT_970;
6341 pcc->bfd_mach = bfd_mach_ppc64;
6342 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6343 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6344 POWERPC_FLAG_BUS_CLK;
6345 pcc->l1_dcache_size = 0x8000;
6346 pcc->l1_icache_size = 0x10000;
6347 }
6348
6349 static void init_proc_power5plus(CPUPPCState *env)
6350 {
6351 /* Common Registers */
6352 init_proc_book3s_common(env);
6353 register_sdr1_sprs(env);
6354 register_book3s_dbg_sprs(env);
6355
6356 /* POWER5+ Specific Registers */
6357 register_970_hid_sprs(env);
6358 register_970_hior_sprs(env);
6359 register_low_BATs(env);
6360 register_970_pmu_sup_sprs(env);
6361 register_970_pmu_user_sprs(env);
6362 register_power5p_common_sprs(env);
6363 register_power5p_lpar_sprs(env);
6364 register_power5p_ear_sprs(env);
6365 register_power5p_tb_sprs(env);
6366
6367 /* env variables */
6368 env->dcache_line_size = 128;
6369 env->icache_line_size = 128;
6370
6371 /* Allocate hardware IRQ controller */
6372 init_excp_970(env);
6373 ppc970_irq_init(env_archcpu(env));
6374 }
6375
6376 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6377 {
6378 DeviceClass *dc = DEVICE_CLASS(oc);
6379 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6380
6381 dc->fw_name = "PowerPC,POWER5";
6382 dc->desc = "POWER5+";
6383 pcc->init_proc = init_proc_power5plus;
6384 pcc->check_pow = check_pow_970;
6385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6386 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6387 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6388 PPC_FLOAT_STFIWX |
6389 PPC_FLOAT_EXT |
6390 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6391 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6392 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6393 PPC_64B |
6394 PPC_POPCNTB |
6395 PPC_SEGMENT_64B | PPC_SLBI;
6396 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6397 pcc->msr_mask = (1ull << MSR_SF) |
6398 (1ull << MSR_VR) |
6399 (1ull << MSR_POW) |
6400 (1ull << MSR_EE) |
6401 (1ull << MSR_PR) |
6402 (1ull << MSR_FP) |
6403 (1ull << MSR_ME) |
6404 (1ull << MSR_FE0) |
6405 (1ull << MSR_SE) |
6406 (1ull << MSR_DE) |
6407 (1ull << MSR_FE1) |
6408 (1ull << MSR_IR) |
6409 (1ull << MSR_DR) |
6410 (1ull << MSR_PMM) |
6411 (1ull << MSR_RI);
6412 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6413 LPCR_RMI | LPCR_HDICE;
6414 pcc->mmu_model = POWERPC_MMU_2_03;
6415 #if defined(CONFIG_SOFTMMU)
6416 pcc->hash64_opts = &ppc_hash64_opts_basic;
6417 pcc->lrg_decr_bits = 32;
6418 #endif
6419 pcc->excp_model = POWERPC_EXCP_970;
6420 pcc->bus_model = PPC_FLAGS_INPUT_970;
6421 pcc->bfd_mach = bfd_mach_ppc64;
6422 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6423 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6424 POWERPC_FLAG_BUS_CLK;
6425 pcc->l1_dcache_size = 0x8000;
6426 pcc->l1_icache_size = 0x10000;
6427 }
6428
6429 static void init_proc_POWER7(CPUPPCState *env)
6430 {
6431 /* Common Registers */
6432 init_proc_book3s_common(env);
6433 register_sdr1_sprs(env);
6434 register_book3s_dbg_sprs(env);
6435
6436 /* POWER7 Specific Registers */
6437 register_book3s_ids_sprs(env);
6438 register_rmor_sprs(env);
6439 register_amr_sprs(env);
6440 register_book3s_purr_sprs(env);
6441 register_power5p_common_sprs(env);
6442 register_power5p_lpar_sprs(env);
6443 register_power5p_ear_sprs(env);
6444 register_power5p_tb_sprs(env);
6445 register_power6_common_sprs(env);
6446 register_power6_dbg_sprs(env);
6447 register_power7_book4_sprs(env);
6448
6449 /* env variables */
6450 env->dcache_line_size = 128;
6451 env->icache_line_size = 128;
6452
6453 /* Allocate hardware IRQ controller */
6454 init_excp_POWER7(env);
6455 ppcPOWER7_irq_init(env_archcpu(env));
6456 }
6457
6458 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
6459 {
6460 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
6461 return true;
6462 }
6463 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
6464 return true;
6465 }
6466 return false;
6467 }
6468
6469 static bool cpu_has_work_POWER7(CPUState *cs)
6470 {
6471 PowerPCCPU *cpu = POWERPC_CPU(cs);
6472 CPUPPCState *env = &cpu->env;
6473
6474 if (cs->halted) {
6475 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6476 return false;
6477 }
6478 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6479 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
6480 return true;
6481 }
6482 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6483 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
6484 return true;
6485 }
6486 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6487 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6488 return true;
6489 }
6490 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6491 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6492 return true;
6493 }
6494 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6495 return true;
6496 }
6497 return false;
6498 } else {
6499 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6500 }
6501 }
6502
6503 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6504 {
6505 DeviceClass *dc = DEVICE_CLASS(oc);
6506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6507 CPUClass *cc = CPU_CLASS(oc);
6508
6509 dc->fw_name = "PowerPC,POWER7";
6510 dc->desc = "POWER7";
6511 pcc->pvr_match = ppc_pvr_match_power7;
6512 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6513 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6514 pcc->init_proc = init_proc_POWER7;
6515 pcc->check_pow = check_pow_nocheck;
6516 cc->has_work = cpu_has_work_POWER7;
6517 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6518 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6519 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6520 PPC_FLOAT_FRSQRTES |
6521 PPC_FLOAT_STFIWX |
6522 PPC_FLOAT_EXT |
6523 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6524 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6525 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6526 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6527 PPC_SEGMENT_64B | PPC_SLBI |
6528 PPC_POPCNTB | PPC_POPCNTWD |
6529 PPC_CILDST;
6530 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6531 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6532 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6533 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6534 PPC2_PM_ISA206;
6535 pcc->msr_mask = (1ull << MSR_SF) |
6536 (1ull << MSR_VR) |
6537 (1ull << MSR_VSX) |
6538 (1ull << MSR_EE) |
6539 (1ull << MSR_PR) |
6540 (1ull << MSR_FP) |
6541 (1ull << MSR_ME) |
6542 (1ull << MSR_FE0) |
6543 (1ull << MSR_SE) |
6544 (1ull << MSR_DE) |
6545 (1ull << MSR_FE1) |
6546 (1ull << MSR_IR) |
6547 (1ull << MSR_DR) |
6548 (1ull << MSR_PMM) |
6549 (1ull << MSR_RI) |
6550 (1ull << MSR_LE);
6551 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6552 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6553 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6554 LPCR_MER | LPCR_TC |
6555 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6556 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6557 pcc->mmu_model = POWERPC_MMU_2_06;
6558 #if defined(CONFIG_SOFTMMU)
6559 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6560 pcc->lrg_decr_bits = 32;
6561 #endif
6562 pcc->excp_model = POWERPC_EXCP_POWER7;
6563 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6564 pcc->bfd_mach = bfd_mach_ppc64;
6565 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6566 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6567 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6568 POWERPC_FLAG_VSX;
6569 pcc->l1_dcache_size = 0x8000;
6570 pcc->l1_icache_size = 0x8000;
6571 }
6572
6573 static void init_proc_POWER8(CPUPPCState *env)
6574 {
6575 /* Common Registers */
6576 init_proc_book3s_common(env);
6577 register_sdr1_sprs(env);
6578 register_book3s_207_dbg_sprs(env);
6579
6580 /* Common TCG PMU */
6581 init_tcg_pmu_power8(env);
6582
6583 /* POWER8 Specific Registers */
6584 register_book3s_ids_sprs(env);
6585 register_rmor_sprs(env);
6586 register_amr_sprs(env);
6587 register_iamr_sprs(env);
6588 register_book3s_purr_sprs(env);
6589 register_power5p_common_sprs(env);
6590 register_power5p_lpar_sprs(env);
6591 register_power5p_ear_sprs(env);
6592 register_power5p_tb_sprs(env);
6593 register_power6_common_sprs(env);
6594 register_power6_dbg_sprs(env);
6595 register_power8_tce_address_control_sprs(env);
6596 register_power8_ids_sprs(env);
6597 register_power8_ebb_sprs(env);
6598 register_power8_fscr_sprs(env);
6599 register_power8_pmu_sup_sprs(env);
6600 register_power8_pmu_user_sprs(env);
6601 register_power8_tm_sprs(env);
6602 register_power8_pspb_sprs(env);
6603 register_power8_dpdes_sprs(env);
6604 register_vtb_sprs(env);
6605 register_power8_ic_sprs(env);
6606 register_power8_book4_sprs(env);
6607 register_power8_rpr_sprs(env);
6608
6609 /* env variables */
6610 env->dcache_line_size = 128;
6611 env->icache_line_size = 128;
6612
6613 /* Allocate hardware IRQ controller */
6614 init_excp_POWER8(env);
6615 ppcPOWER7_irq_init(env_archcpu(env));
6616 }
6617
6618 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
6619 {
6620 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
6621 return true;
6622 }
6623 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
6624 return true;
6625 }
6626 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
6627 return true;
6628 }
6629 return false;
6630 }
6631
6632 static bool cpu_has_work_POWER8(CPUState *cs)
6633 {
6634 PowerPCCPU *cpu = POWERPC_CPU(cs);
6635 CPUPPCState *env = &cpu->env;
6636
6637 if (cs->halted) {
6638 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6639 return false;
6640 }
6641 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6642 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6643 return true;
6644 }
6645 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6646 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6647 return true;
6648 }
6649 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6650 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6651 return true;
6652 }
6653 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6654 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6655 return true;
6656 }
6657 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6658 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6659 return true;
6660 }
6661 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6662 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6663 return true;
6664 }
6665 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6666 return true;
6667 }
6668 return false;
6669 } else {
6670 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6671 }
6672 }
6673
6674 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6675 {
6676 DeviceClass *dc = DEVICE_CLASS(oc);
6677 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6678 CPUClass *cc = CPU_CLASS(oc);
6679
6680 dc->fw_name = "PowerPC,POWER8";
6681 dc->desc = "POWER8";
6682 pcc->pvr_match = ppc_pvr_match_power8;
6683 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6684 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6685 pcc->init_proc = init_proc_POWER8;
6686 pcc->check_pow = check_pow_nocheck;
6687 cc->has_work = cpu_has_work_POWER8;
6688 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6689 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6690 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6691 PPC_FLOAT_FRSQRTES |
6692 PPC_FLOAT_STFIWX |
6693 PPC_FLOAT_EXT |
6694 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6695 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6696 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6697 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6698 PPC_SEGMENT_64B | PPC_SLBI |
6699 PPC_POPCNTB | PPC_POPCNTWD |
6700 PPC_CILDST;
6701 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6702 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6703 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6704 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6705 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6706 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6707 PPC2_TM | PPC2_PM_ISA206;
6708 pcc->msr_mask = (1ull << MSR_SF) |
6709 (1ull << MSR_HV) |
6710 (1ull << MSR_TM) |
6711 (1ull << MSR_VR) |
6712 (1ull << MSR_VSX) |
6713 (1ull << MSR_EE) |
6714 (1ull << MSR_PR) |
6715 (1ull << MSR_FP) |
6716 (1ull << MSR_ME) |
6717 (1ull << MSR_FE0) |
6718 (1ull << MSR_SE) |
6719 (1ull << MSR_DE) |
6720 (1ull << MSR_FE1) |
6721 (1ull << MSR_IR) |
6722 (1ull << MSR_DR) |
6723 (1ull << MSR_PMM) |
6724 (1ull << MSR_RI) |
6725 (1ull << MSR_TS0) |
6726 (1ull << MSR_TS1) |
6727 (1ull << MSR_LE);
6728 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6729 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6730 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6731 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6732 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6733 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6734 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6735 pcc->mmu_model = POWERPC_MMU_2_07;
6736 #if defined(CONFIG_SOFTMMU)
6737 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6738 pcc->lrg_decr_bits = 32;
6739 pcc->n_host_threads = 8;
6740 #endif
6741 pcc->excp_model = POWERPC_EXCP_POWER8;
6742 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6743 pcc->bfd_mach = bfd_mach_ppc64;
6744 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6745 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6746 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6747 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6748 pcc->l1_dcache_size = 0x8000;
6749 pcc->l1_icache_size = 0x8000;
6750 }
6751
6752 #ifdef CONFIG_SOFTMMU
6753 /*
6754 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6755 * Encoded as array of int_32s in the form:
6756 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6757 * x -> AP encoding
6758 * y -> radix mode supported page size (encoded as a shift)
6759 */
6760 static struct ppc_radix_page_info POWER9_radix_page_info = {
6761 .count = 4,
6762 .entries = {
6763 0x0000000c, /* 4K - enc: 0x0 */
6764 0xa0000010, /* 64K - enc: 0x5 */
6765 0x20000015, /* 2M - enc: 0x1 */
6766 0x4000001e /* 1G - enc: 0x2 */
6767 }
6768 };
6769 #endif /* CONFIG_SOFTMMU */
6770
6771 static void init_proc_POWER9(CPUPPCState *env)
6772 {
6773 /* Common Registers */
6774 init_proc_book3s_common(env);
6775 register_book3s_207_dbg_sprs(env);
6776
6777 /* Common TCG PMU */
6778 init_tcg_pmu_power8(env);
6779
6780 /* POWER8 Specific Registers */
6781 register_book3s_ids_sprs(env);
6782 register_amr_sprs(env);
6783 register_iamr_sprs(env);
6784 register_book3s_purr_sprs(env);
6785 register_power5p_common_sprs(env);
6786 register_power5p_lpar_sprs(env);
6787 register_power5p_ear_sprs(env);
6788 register_power5p_tb_sprs(env);
6789 register_power6_common_sprs(env);
6790 register_power6_dbg_sprs(env);
6791 register_power8_tce_address_control_sprs(env);
6792 register_power8_ids_sprs(env);
6793 register_power8_ebb_sprs(env);
6794 register_power8_fscr_sprs(env);
6795 register_power8_pmu_sup_sprs(env);
6796 register_power8_pmu_user_sprs(env);
6797 register_power8_tm_sprs(env);
6798 register_power8_pspb_sprs(env);
6799 register_power8_dpdes_sprs(env);
6800 register_vtb_sprs(env);
6801 register_power8_ic_sprs(env);
6802 register_power8_book4_sprs(env);
6803 register_power8_rpr_sprs(env);
6804 register_power9_mmu_sprs(env);
6805
6806 /* POWER9 Specific registers */
6807 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6808 spr_read_generic, spr_write_generic,
6809 KVM_REG_PPC_TIDR, 0);
6810
6811 /* FIXME: Filter fields properly based on privilege level */
6812 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6813 spr_read_generic, spr_write_generic,
6814 KVM_REG_PPC_PSSCR, 0);
6815
6816 /* env variables */
6817 env->dcache_line_size = 128;
6818 env->icache_line_size = 128;
6819
6820 /* Allocate hardware IRQ controller */
6821 init_excp_POWER9(env);
6822 ppcPOWER9_irq_init(env_archcpu(env));
6823 }
6824
6825 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
6826 {
6827 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
6828 return true;
6829 }
6830 return false;
6831 }
6832
6833 static bool cpu_has_work_POWER9(CPUState *cs)
6834 {
6835 PowerPCCPU *cpu = POWERPC_CPU(cs);
6836 CPUPPCState *env = &cpu->env;
6837
6838 if (cs->halted) {
6839 uint64_t psscr = env->spr[SPR_PSSCR];
6840
6841 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6842 return false;
6843 }
6844
6845 /* If EC is clear, just return true on any pending interrupt */
6846 if (!(psscr & PSSCR_EC)) {
6847 return true;
6848 }
6849 /* External Exception */
6850 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6851 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6852 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6853 if (heic == 0 || !msr_hv || msr_pr) {
6854 return true;
6855 }
6856 }
6857 /* Decrementer Exception */
6858 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6859 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6860 return true;
6861 }
6862 /* Machine Check or Hypervisor Maintenance Exception */
6863 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6864 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6865 return true;
6866 }
6867 /* Privileged Doorbell Exception */
6868 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6869 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6870 return true;
6871 }
6872 /* Hypervisor Doorbell Exception */
6873 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6874 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6875 return true;
6876 }
6877 /* Hypervisor virtualization exception */
6878 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6879 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6880 return true;
6881 }
6882 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6883 return true;
6884 }
6885 return false;
6886 } else {
6887 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6888 }
6889 }
6890
6891 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6892 {
6893 DeviceClass *dc = DEVICE_CLASS(oc);
6894 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6895 CPUClass *cc = CPU_CLASS(oc);
6896
6897 dc->fw_name = "PowerPC,POWER9";
6898 dc->desc = "POWER9";
6899 pcc->pvr_match = ppc_pvr_match_power9;
6900 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6901 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6902 PCR_COMPAT_2_05;
6903 pcc->init_proc = init_proc_POWER9;
6904 pcc->check_pow = check_pow_nocheck;
6905 cc->has_work = cpu_has_work_POWER9;
6906 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6907 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6908 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6909 PPC_FLOAT_FRSQRTES |
6910 PPC_FLOAT_STFIWX |
6911 PPC_FLOAT_EXT |
6912 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6913 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6914 PPC_MEM_TLBSYNC |
6915 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6916 PPC_SEGMENT_64B | PPC_SLBI |
6917 PPC_POPCNTB | PPC_POPCNTWD |
6918 PPC_CILDST;
6919 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6920 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6921 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6922 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6923 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6924 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6925 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
6926 pcc->msr_mask = (1ull << MSR_SF) |
6927 (1ull << MSR_HV) |
6928 (1ull << MSR_TM) |
6929 (1ull << MSR_VR) |
6930 (1ull << MSR_VSX) |
6931 (1ull << MSR_EE) |
6932 (1ull << MSR_PR) |
6933 (1ull << MSR_FP) |
6934 (1ull << MSR_ME) |
6935 (1ull << MSR_FE0) |
6936 (1ull << MSR_SE) |
6937 (1ull << MSR_DE) |
6938 (1ull << MSR_FE1) |
6939 (1ull << MSR_IR) |
6940 (1ull << MSR_DR) |
6941 (1ull << MSR_PMM) |
6942 (1ull << MSR_RI) |
6943 (1ull << MSR_LE);
6944 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6945 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6946 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6947 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6948 LPCR_DEE | LPCR_OEE))
6949 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6950 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6951 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6952 pcc->mmu_model = POWERPC_MMU_3_00;
6953 #if defined(CONFIG_SOFTMMU)
6954 /* segment page size remain the same */
6955 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6956 pcc->radix_page_info = &POWER9_radix_page_info;
6957 pcc->lrg_decr_bits = 56;
6958 pcc->n_host_threads = 4;
6959 #endif
6960 pcc->excp_model = POWERPC_EXCP_POWER9;
6961 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6962 pcc->bfd_mach = bfd_mach_ppc64;
6963 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6964 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6965 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6966 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6967 pcc->l1_dcache_size = 0x8000;
6968 pcc->l1_icache_size = 0x8000;
6969 }
6970
6971 #ifdef CONFIG_SOFTMMU
6972 /*
6973 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6974 * Encoded as array of int_32s in the form:
6975 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6976 * x -> AP encoding
6977 * y -> radix mode supported page size (encoded as a shift)
6978 */
6979 static struct ppc_radix_page_info POWER10_radix_page_info = {
6980 .count = 4,
6981 .entries = {
6982 0x0000000c, /* 4K - enc: 0x0 */
6983 0xa0000010, /* 64K - enc: 0x5 */
6984 0x20000015, /* 2M - enc: 0x1 */
6985 0x4000001e /* 1G - enc: 0x2 */
6986 }
6987 };
6988 #endif /* CONFIG_SOFTMMU */
6989
6990 static void init_proc_POWER10(CPUPPCState *env)
6991 {
6992 /* Common Registers */
6993 init_proc_book3s_common(env);
6994 register_book3s_207_dbg_sprs(env);
6995
6996 /* Common TCG PMU */
6997 init_tcg_pmu_power8(env);
6998
6999 /* POWER8 Specific Registers */
7000 register_book3s_ids_sprs(env);
7001 register_amr_sprs(env);
7002 register_iamr_sprs(env);
7003 register_book3s_purr_sprs(env);
7004 register_power5p_common_sprs(env);
7005 register_power5p_lpar_sprs(env);
7006 register_power5p_ear_sprs(env);
7007 register_power6_common_sprs(env);
7008 register_power6_dbg_sprs(env);
7009 register_power8_tce_address_control_sprs(env);
7010 register_power8_ids_sprs(env);
7011 register_power8_ebb_sprs(env);
7012 register_power8_fscr_sprs(env);
7013 register_power8_pmu_sup_sprs(env);
7014 register_power8_pmu_user_sprs(env);
7015 register_power8_tm_sprs(env);
7016 register_power8_pspb_sprs(env);
7017 register_vtb_sprs(env);
7018 register_power8_ic_sprs(env);
7019 register_power8_book4_sprs(env);
7020 register_power8_rpr_sprs(env);
7021 register_power9_mmu_sprs(env);
7022
7023 /* FIXME: Filter fields properly based on privilege level */
7024 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7025 spr_read_generic, spr_write_generic,
7026 KVM_REG_PPC_PSSCR, 0);
7027
7028 /* env variables */
7029 env->dcache_line_size = 128;
7030 env->icache_line_size = 128;
7031
7032 /* Allocate hardware IRQ controller */
7033 init_excp_POWER10(env);
7034 ppcPOWER9_irq_init(env_archcpu(env));
7035 }
7036
7037 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
7038 {
7039 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
7040 return true;
7041 }
7042 return false;
7043 }
7044
7045 static bool cpu_has_work_POWER10(CPUState *cs)
7046 {
7047 PowerPCCPU *cpu = POWERPC_CPU(cs);
7048 CPUPPCState *env = &cpu->env;
7049
7050 if (cs->halted) {
7051 uint64_t psscr = env->spr[SPR_PSSCR];
7052
7053 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7054 return false;
7055 }
7056
7057 /* If EC is clear, just return true on any pending interrupt */
7058 if (!(psscr & PSSCR_EC)) {
7059 return true;
7060 }
7061 /* External Exception */
7062 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7063 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7064 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7065 if (heic == 0 || !msr_hv || msr_pr) {
7066 return true;
7067 }
7068 }
7069 /* Decrementer Exception */
7070 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7071 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7072 return true;
7073 }
7074 /* Machine Check or Hypervisor Maintenance Exception */
7075 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7076 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7077 return true;
7078 }
7079 /* Privileged Doorbell Exception */
7080 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7081 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7082 return true;
7083 }
7084 /* Hypervisor Doorbell Exception */
7085 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7086 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7087 return true;
7088 }
7089 /* Hypervisor virtualization exception */
7090 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7091 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7092 return true;
7093 }
7094 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7095 return true;
7096 }
7097 return false;
7098 } else {
7099 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7100 }
7101 }
7102
7103 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
7104 {
7105 DeviceClass *dc = DEVICE_CLASS(oc);
7106 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7107 CPUClass *cc = CPU_CLASS(oc);
7108
7109 dc->fw_name = "PowerPC,POWER10";
7110 dc->desc = "POWER10";
7111 pcc->pvr_match = ppc_pvr_match_power10;
7112 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
7113 PCR_COMPAT_3_00;
7114 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
7115 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7116 pcc->init_proc = init_proc_POWER10;
7117 pcc->check_pow = check_pow_nocheck;
7118 cc->has_work = cpu_has_work_POWER10;
7119 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7120 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7121 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7122 PPC_FLOAT_FRSQRTES |
7123 PPC_FLOAT_STFIWX |
7124 PPC_FLOAT_EXT |
7125 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7126 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7127 PPC_MEM_TLBSYNC |
7128 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7129 PPC_SEGMENT_64B | PPC_SLBI |
7130 PPC_POPCNTB | PPC_POPCNTWD |
7131 PPC_CILDST;
7132 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7133 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7134 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7135 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7136 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7137 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7138 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
7139 pcc->msr_mask = (1ull << MSR_SF) |
7140 (1ull << MSR_HV) |
7141 (1ull << MSR_TM) |
7142 (1ull << MSR_VR) |
7143 (1ull << MSR_VSX) |
7144 (1ull << MSR_EE) |
7145 (1ull << MSR_PR) |
7146 (1ull << MSR_FP) |
7147 (1ull << MSR_ME) |
7148 (1ull << MSR_FE0) |
7149 (1ull << MSR_SE) |
7150 (1ull << MSR_DE) |
7151 (1ull << MSR_FE1) |
7152 (1ull << MSR_IR) |
7153 (1ull << MSR_DR) |
7154 (1ull << MSR_PMM) |
7155 (1ull << MSR_RI) |
7156 (1ull << MSR_LE);
7157 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7158 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7159 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7160 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7161 LPCR_DEE | LPCR_OEE))
7162 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7163 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7164 /* DD2 adds an extra HAIL bit */
7165 pcc->lpcr_mask |= LPCR_HAIL;
7166
7167 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7168 pcc->mmu_model = POWERPC_MMU_3_00;
7169 #if defined(CONFIG_SOFTMMU)
7170 /* segment page size remain the same */
7171 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7172 pcc->radix_page_info = &POWER10_radix_page_info;
7173 pcc->lrg_decr_bits = 56;
7174 #endif
7175 pcc->excp_model = POWERPC_EXCP_POWER10;
7176 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7177 pcc->bfd_mach = bfd_mach_ppc64;
7178 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7179 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7180 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7181 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7182 pcc->l1_dcache_size = 0x8000;
7183 pcc->l1_icache_size = 0x8000;
7184 }
7185
7186 #if !defined(CONFIG_USER_ONLY)
7187 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
7188 {
7189 CPUPPCState *env = &cpu->env;
7190
7191 cpu->vhyp = vhyp;
7192
7193 /*
7194 * With a virtual hypervisor mode we never allow the CPU to go
7195 * hypervisor mode itself
7196 */
7197 env->msr_mask &= ~MSR_HVB;
7198 }
7199
7200 #endif /* !defined(CONFIG_USER_ONLY) */
7201
7202 #endif /* defined(TARGET_PPC64) */
7203
7204 /*****************************************************************************/
7205 /* Generic CPU instantiation routine */
7206 static void init_ppc_proc(PowerPCCPU *cpu)
7207 {
7208 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7209 CPUPPCState *env = &cpu->env;
7210 #if !defined(CONFIG_USER_ONLY)
7211 int i;
7212
7213 env->irq_inputs = NULL;
7214 /* Set all exception vectors to an invalid address */
7215 for (i = 0; i < POWERPC_EXCP_NB; i++) {
7216 env->excp_vectors[i] = (target_ulong)(-1ULL);
7217 }
7218 env->ivor_mask = 0x00000000;
7219 env->ivpr_mask = 0x00000000;
7220 /* Default MMU definitions */
7221 env->nb_BATs = 0;
7222 env->nb_tlb = 0;
7223 env->nb_ways = 0;
7224 env->tlb_type = TLB_NONE;
7225 #endif
7226 /* Register SPR common to all PowerPC implementations */
7227 register_generic_sprs(cpu);
7228
7229 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7230 (*pcc->init_proc)(env);
7231
7232 #if !defined(CONFIG_USER_ONLY)
7233 ppc_gdb_gen_spr_xml(cpu);
7234 #endif
7235
7236 /* MSR bits & flags consistency checks */
7237 if (env->msr_mask & (1 << 25)) {
7238 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7239 case POWERPC_FLAG_SPE:
7240 case POWERPC_FLAG_VRE:
7241 break;
7242 default:
7243 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7244 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7245 exit(1);
7246 }
7247 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7248 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7249 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7250 exit(1);
7251 }
7252 if (env->msr_mask & (1 << 17)) {
7253 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7254 case POWERPC_FLAG_TGPR:
7255 case POWERPC_FLAG_CE:
7256 break;
7257 default:
7258 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7259 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7260 exit(1);
7261 }
7262 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7263 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7264 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7265 exit(1);
7266 }
7267 if (env->msr_mask & (1 << 10)) {
7268 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7269 POWERPC_FLAG_UBLE)) {
7270 case POWERPC_FLAG_SE:
7271 case POWERPC_FLAG_DWE:
7272 case POWERPC_FLAG_UBLE:
7273 break;
7274 default:
7275 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7276 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7277 "POWERPC_FLAG_UBLE\n");
7278 exit(1);
7279 }
7280 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7281 POWERPC_FLAG_UBLE)) {
7282 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7283 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7284 "POWERPC_FLAG_UBLE\n");
7285 exit(1);
7286 }
7287 if (env->msr_mask & (1 << 9)) {
7288 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7289 case POWERPC_FLAG_BE:
7290 case POWERPC_FLAG_DE:
7291 break;
7292 default:
7293 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7294 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7295 exit(1);
7296 }
7297 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7298 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7299 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7300 exit(1);
7301 }
7302 if (env->msr_mask & (1 << 2)) {
7303 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7304 case POWERPC_FLAG_PX:
7305 case POWERPC_FLAG_PMM:
7306 break;
7307 default:
7308 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7309 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7310 exit(1);
7311 }
7312 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7313 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7314 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7315 exit(1);
7316 }
7317 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
7318 fprintf(stderr, "PowerPC flags inconsistency\n"
7319 "Should define the time-base and decrementer clock source\n");
7320 exit(1);
7321 }
7322 /* Allocate TLBs buffer when needed */
7323 #if !defined(CONFIG_USER_ONLY)
7324 if (env->nb_tlb != 0) {
7325 int nb_tlb = env->nb_tlb;
7326 if (env->id_tlbs != 0) {
7327 nb_tlb *= 2;
7328 }
7329 switch (env->tlb_type) {
7330 case TLB_6XX:
7331 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
7332 break;
7333 case TLB_EMB:
7334 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
7335 break;
7336 case TLB_MAS:
7337 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
7338 break;
7339 }
7340 /* Pre-compute some useful values */
7341 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7342 }
7343 if (env->irq_inputs == NULL) {
7344 warn_report("no internal IRQ controller registered."
7345 " Attempt QEMU to crash very soon !");
7346 }
7347 #endif
7348 if (env->check_pow == NULL) {
7349 warn_report("no power management check handler registered."
7350 " Attempt QEMU to crash very soon !");
7351 }
7352 }
7353
7354
7355 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
7356 {
7357 CPUState *cs = CPU(dev);
7358 PowerPCCPU *cpu = POWERPC_CPU(dev);
7359 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7360 Error *local_err = NULL;
7361
7362 cpu_exec_realizefn(cs, &local_err);
7363 if (local_err != NULL) {
7364 error_propagate(errp, local_err);
7365 return;
7366 }
7367 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
7368 cpu->vcpu_id = cs->cpu_index;
7369 }
7370
7371 if (tcg_enabled()) {
7372 if (ppc_fixup_cpu(cpu) != 0) {
7373 error_setg(errp, "Unable to emulate selected CPU with TCG");
7374 goto unrealize;
7375 }
7376 }
7377
7378 create_ppc_opcodes(cpu, &local_err);
7379 if (local_err != NULL) {
7380 error_propagate(errp, local_err);
7381 goto unrealize;
7382 }
7383 init_ppc_proc(cpu);
7384
7385 ppc_gdb_init(cs, pcc);
7386 qemu_init_vcpu(cs);
7387
7388 pcc->parent_realize(dev, errp);
7389
7390 return;
7391
7392 unrealize:
7393 cpu_exec_unrealizefn(cs);
7394 }
7395
7396 static void ppc_cpu_unrealize(DeviceState *dev)
7397 {
7398 PowerPCCPU *cpu = POWERPC_CPU(dev);
7399 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7400
7401 pcc->parent_unrealize(dev);
7402
7403 cpu_remove_sync(CPU(cpu));
7404
7405 destroy_ppc_opcodes(cpu);
7406 }
7407
7408 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7409 {
7410 ObjectClass *oc = (ObjectClass *)a;
7411 uint32_t pvr = *(uint32_t *)b;
7412 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7413
7414 /* -cpu host does a PVR lookup during construction */
7415 if (unlikely(strcmp(object_class_get_name(oc),
7416 TYPE_HOST_POWERPC_CPU) == 0)) {
7417 return -1;
7418 }
7419
7420 return pcc->pvr == pvr ? 0 : -1;
7421 }
7422
7423 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7424 {
7425 GSList *list, *item;
7426 PowerPCCPUClass *pcc = NULL;
7427
7428 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7429 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7430 if (item != NULL) {
7431 pcc = POWERPC_CPU_CLASS(item->data);
7432 }
7433 g_slist_free(list);
7434
7435 return pcc;
7436 }
7437
7438 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7439 {
7440 ObjectClass *oc = (ObjectClass *)a;
7441 uint32_t pvr = *(uint32_t *)b;
7442 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7443
7444 /* -cpu host does a PVR lookup during construction */
7445 if (unlikely(strcmp(object_class_get_name(oc),
7446 TYPE_HOST_POWERPC_CPU) == 0)) {
7447 return -1;
7448 }
7449
7450 if (pcc->pvr_match(pcc, pvr)) {
7451 return 0;
7452 }
7453
7454 return -1;
7455 }
7456
7457 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
7458 {
7459 GSList *list, *item;
7460 PowerPCCPUClass *pcc = NULL;
7461
7462 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7463 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7464 if (item != NULL) {
7465 pcc = POWERPC_CPU_CLASS(item->data);
7466 }
7467 g_slist_free(list);
7468
7469 return pcc;
7470 }
7471
7472 static const char *ppc_cpu_lookup_alias(const char *alias)
7473 {
7474 int ai;
7475
7476 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7477 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7478 return ppc_cpu_aliases[ai].model;
7479 }
7480 }
7481
7482 return NULL;
7483 }
7484
7485 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7486 {
7487 char *cpu_model, *typename;
7488 ObjectClass *oc;
7489 const char *p;
7490 unsigned long pvr;
7491
7492 /*
7493 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7494 * 0x prefix if present)
7495 */
7496 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7497 int len = p - name;
7498 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7499 if ((len == 8) && (*p == '\0')) {
7500 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7501 }
7502 }
7503
7504 cpu_model = g_ascii_strdown(name, -1);
7505 p = ppc_cpu_lookup_alias(cpu_model);
7506 if (p) {
7507 g_free(cpu_model);
7508 cpu_model = g_strdup(p);
7509 }
7510
7511 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7512 oc = object_class_by_name(typename);
7513 g_free(typename);
7514 g_free(cpu_model);
7515
7516 return oc;
7517 }
7518
7519 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7520 {
7521 ObjectClass *oc = OBJECT_CLASS(pcc);
7522
7523 while (oc && !object_class_is_abstract(oc)) {
7524 oc = object_class_get_parent(oc);
7525 }
7526 assert(oc);
7527
7528 return POWERPC_CPU_CLASS(oc);
7529 }
7530
7531 /* Sort by PVR, ordering special case "host" last. */
7532 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7533 {
7534 ObjectClass *oc_a = (ObjectClass *)a;
7535 ObjectClass *oc_b = (ObjectClass *)b;
7536 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7537 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7538 const char *name_a = object_class_get_name(oc_a);
7539 const char *name_b = object_class_get_name(oc_b);
7540
7541 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7542 return 1;
7543 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7544 return -1;
7545 } else {
7546 /* Avoid an integer overflow during subtraction */
7547 if (pcc_a->pvr < pcc_b->pvr) {
7548 return -1;
7549 } else if (pcc_a->pvr > pcc_b->pvr) {
7550 return 1;
7551 } else {
7552 return 0;
7553 }
7554 }
7555 }
7556
7557 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7558 {
7559 ObjectClass *oc = data;
7560 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7561 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7562 const char *typename = object_class_get_name(oc);
7563 char *name;
7564 int i;
7565
7566 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7567 return;
7568 }
7569
7570 name = g_strndup(typename,
7571 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7572 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7573 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7574 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7575 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7576
7577 if (alias_oc != oc) {
7578 continue;
7579 }
7580 /*
7581 * If running with KVM, we might update the family alias later, so
7582 * avoid printing the wrong alias here and use "preferred" instead
7583 */
7584 if (strcmp(alias->alias, family->desc) == 0) {
7585 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7586 alias->alias, family->desc);
7587 } else {
7588 qemu_printf("PowerPC %-16s (alias for %s)\n",
7589 alias->alias, name);
7590 }
7591 }
7592 g_free(name);
7593 }
7594
7595 void ppc_cpu_list(void)
7596 {
7597 GSList *list;
7598
7599 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7600 list = g_slist_sort(list, ppc_cpu_list_compare);
7601 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7602 g_slist_free(list);
7603
7604 #ifdef CONFIG_KVM
7605 qemu_printf("\n");
7606 qemu_printf("PowerPC %s\n", "host");
7607 #endif
7608 }
7609
7610 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7611 {
7612 ObjectClass *oc = data;
7613 CpuDefinitionInfoList **first = user_data;
7614 const char *typename;
7615 CpuDefinitionInfo *info;
7616
7617 typename = object_class_get_name(oc);
7618 info = g_malloc0(sizeof(*info));
7619 info->name = g_strndup(typename,
7620 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7621
7622 QAPI_LIST_PREPEND(*first, info);
7623 }
7624
7625 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7626 {
7627 CpuDefinitionInfoList *cpu_list = NULL;
7628 GSList *list;
7629 int i;
7630
7631 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7632 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7633 g_slist_free(list);
7634
7635 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7636 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7637 ObjectClass *oc;
7638 CpuDefinitionInfo *info;
7639
7640 oc = ppc_cpu_class_by_name(alias->model);
7641 if (oc == NULL) {
7642 continue;
7643 }
7644
7645 info = g_malloc0(sizeof(*info));
7646 info->name = g_strdup(alias->alias);
7647 info->q_typename = g_strdup(object_class_get_name(oc));
7648
7649 QAPI_LIST_PREPEND(cpu_list, info);
7650 }
7651
7652 return cpu_list;
7653 }
7654
7655 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7656 {
7657 PowerPCCPU *cpu = POWERPC_CPU(cs);
7658
7659 cpu->env.nip = value;
7660 }
7661
7662 static bool ppc_cpu_has_work(CPUState *cs)
7663 {
7664 PowerPCCPU *cpu = POWERPC_CPU(cs);
7665 CPUPPCState *env = &cpu->env;
7666
7667 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7668 }
7669
7670 static void ppc_cpu_reset(DeviceState *dev)
7671 {
7672 CPUState *s = CPU(dev);
7673 PowerPCCPU *cpu = POWERPC_CPU(s);
7674 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7675 CPUPPCState *env = &cpu->env;
7676 target_ulong msr;
7677 int i;
7678
7679 pcc->parent_reset(dev);
7680
7681 msr = (target_ulong)0;
7682 msr |= (target_ulong)MSR_HVB;
7683 msr |= (target_ulong)1 << MSR_EP;
7684 #if defined(DO_SINGLE_STEP) && 0
7685 /* Single step trace mode */
7686 msr |= (target_ulong)1 << MSR_SE;
7687 msr |= (target_ulong)1 << MSR_BE;
7688 #endif
7689 #if defined(CONFIG_USER_ONLY)
7690 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7691 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7692 msr |= (target_ulong)1 << MSR_FE1;
7693 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7694 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7695 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7696 msr |= (target_ulong)1 << MSR_PR;
7697 #if defined(TARGET_PPC64)
7698 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7699 #endif
7700 #if !defined(TARGET_WORDS_BIGENDIAN)
7701 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7702 if (!((env->msr_mask >> MSR_LE) & 1)) {
7703 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7704 exit(1);
7705 }
7706 #endif
7707 #endif
7708
7709 #if defined(TARGET_PPC64)
7710 if (mmu_is_64bit(env->mmu_model)) {
7711 msr |= (1ULL << MSR_SF);
7712 }
7713 #endif
7714
7715 hreg_store_msr(env, msr, 1);
7716
7717 #if !defined(CONFIG_USER_ONLY)
7718 env->nip = env->hreset_vector | env->excp_prefix;
7719 #if defined(CONFIG_TCG)
7720 if (env->mmu_model != POWERPC_MMU_REAL) {
7721 ppc_tlb_invalidate_all(env);
7722 }
7723 #endif /* CONFIG_TCG */
7724 #endif
7725
7726 pmu_update_summaries(env);
7727 hreg_compute_hflags(env);
7728 env->reserve_addr = (target_ulong)-1ULL;
7729 /* Be sure no exception or interrupt is pending */
7730 env->pending_interrupts = 0;
7731 s->exception_index = POWERPC_EXCP_NONE;
7732 env->error_code = 0;
7733 ppc_irq_reset(cpu);
7734
7735 /* tininess for underflow is detected before rounding */
7736 set_float_detect_tininess(float_tininess_before_rounding,
7737 &env->fp_status);
7738
7739 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7740 ppc_spr_t *spr = &env->spr_cb[i];
7741
7742 if (!spr->name) {
7743 continue;
7744 }
7745 env->spr[i] = spr->default_value;
7746 }
7747 }
7748
7749 #ifndef CONFIG_USER_ONLY
7750
7751 static bool ppc_cpu_is_big_endian(CPUState *cs)
7752 {
7753 PowerPCCPU *cpu = POWERPC_CPU(cs);
7754 CPUPPCState *env = &cpu->env;
7755
7756 cpu_synchronize_state(cs);
7757
7758 return !msr_le;
7759 }
7760
7761 #ifdef CONFIG_TCG
7762 static void ppc_cpu_exec_enter(CPUState *cs)
7763 {
7764 PowerPCCPU *cpu = POWERPC_CPU(cs);
7765
7766 if (cpu->vhyp) {
7767 PPCVirtualHypervisorClass *vhc =
7768 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7769 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7770 }
7771 }
7772
7773 static void ppc_cpu_exec_exit(CPUState *cs)
7774 {
7775 PowerPCCPU *cpu = POWERPC_CPU(cs);
7776
7777 if (cpu->vhyp) {
7778 PPCVirtualHypervisorClass *vhc =
7779 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7780 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7781 }
7782 }
7783 #endif /* CONFIG_TCG */
7784
7785 #endif /* !CONFIG_USER_ONLY */
7786
7787 static void ppc_cpu_instance_init(Object *obj)
7788 {
7789 PowerPCCPU *cpu = POWERPC_CPU(obj);
7790 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7791 CPUPPCState *env = &cpu->env;
7792
7793 cpu_set_cpustate_pointers(cpu);
7794 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7795
7796 env->msr_mask = pcc->msr_mask;
7797 env->mmu_model = pcc->mmu_model;
7798 env->excp_model = pcc->excp_model;
7799 env->bus_model = pcc->bus_model;
7800 env->insns_flags = pcc->insns_flags;
7801 env->insns_flags2 = pcc->insns_flags2;
7802 env->flags = pcc->flags;
7803 env->bfd_mach = pcc->bfd_mach;
7804 env->check_pow = pcc->check_pow;
7805
7806 /*
7807 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7808 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7809 * mode support will remain, thus enforcing that we cannot use
7810 * priv. instructions in guest in PAPR mode. For 970 we currently
7811 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7812 * 970. If we ever want to support 970 HV mode, we'll have to add
7813 * a processor attribute of some sort.
7814 */
7815 #if !defined(CONFIG_USER_ONLY)
7816 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7817 #endif
7818
7819 ppc_hash64_init(cpu);
7820 }
7821
7822 static void ppc_cpu_instance_finalize(Object *obj)
7823 {
7824 PowerPCCPU *cpu = POWERPC_CPU(obj);
7825
7826 ppc_hash64_finalize(cpu);
7827 }
7828
7829 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
7830 {
7831 return pcc->pvr == pvr;
7832 }
7833
7834 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7835 {
7836 PowerPCCPU *cpu = POWERPC_CPU(cs);
7837 CPUPPCState *env = &cpu->env;
7838
7839 if ((env->hflags >> MSR_LE) & 1) {
7840 info->endian = BFD_ENDIAN_LITTLE;
7841 }
7842 info->mach = env->bfd_mach;
7843 if (!env->bfd_mach) {
7844 #ifdef TARGET_PPC64
7845 info->mach = bfd_mach_ppc64;
7846 #else
7847 info->mach = bfd_mach_ppc;
7848 #endif
7849 }
7850 info->disassembler_options = (char *)"any";
7851 info->print_insn = print_insn_ppc;
7852
7853 info->cap_arch = CS_ARCH_PPC;
7854 #ifdef TARGET_PPC64
7855 info->cap_mode = CS_MODE_64;
7856 #endif
7857 }
7858
7859 static Property ppc_cpu_properties[] = {
7860 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7861 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7862 false),
7863 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7864 false),
7865 DEFINE_PROP_END_OF_LIST(),
7866 };
7867
7868 #ifndef CONFIG_USER_ONLY
7869 #include "hw/core/sysemu-cpu-ops.h"
7870
7871 static const struct SysemuCPUOps ppc_sysemu_ops = {
7872 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7873 .write_elf32_note = ppc32_cpu_write_elf32_note,
7874 .write_elf64_note = ppc64_cpu_write_elf64_note,
7875 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7876 .legacy_vmsd = &vmstate_ppc_cpu,
7877 };
7878 #endif
7879
7880 #ifdef CONFIG_TCG
7881 #include "hw/core/tcg-cpu-ops.h"
7882
7883 static const struct TCGCPUOps ppc_tcg_ops = {
7884 .initialize = ppc_translate_init,
7885
7886 #ifdef CONFIG_USER_ONLY
7887 .record_sigsegv = ppc_cpu_record_sigsegv,
7888 #else
7889 .tlb_fill = ppc_cpu_tlb_fill,
7890 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7891 .do_interrupt = ppc_cpu_do_interrupt,
7892 .cpu_exec_enter = ppc_cpu_exec_enter,
7893 .cpu_exec_exit = ppc_cpu_exec_exit,
7894 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7895 #endif /* !CONFIG_USER_ONLY */
7896 };
7897 #endif /* CONFIG_TCG */
7898
7899 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7900 {
7901 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7902 CPUClass *cc = CPU_CLASS(oc);
7903 DeviceClass *dc = DEVICE_CLASS(oc);
7904
7905 device_class_set_parent_realize(dc, ppc_cpu_realize,
7906 &pcc->parent_realize);
7907 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7908 &pcc->parent_unrealize);
7909 pcc->pvr_match = ppc_pvr_match_default;
7910 device_class_set_props(dc, ppc_cpu_properties);
7911
7912 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
7913
7914 cc->class_by_name = ppc_cpu_class_by_name;
7915 cc->has_work = ppc_cpu_has_work;
7916 cc->dump_state = ppc_cpu_dump_state;
7917 cc->set_pc = ppc_cpu_set_pc;
7918 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7919 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7920 #ifndef CONFIG_USER_ONLY
7921 cc->sysemu_ops = &ppc_sysemu_ops;
7922 #endif
7923
7924 cc->gdb_num_core_regs = 71;
7925 #ifndef CONFIG_USER_ONLY
7926 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7927 #endif
7928 #ifdef USE_APPLE_GDB
7929 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7930 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7931 cc->gdb_num_core_regs = 71 + 32;
7932 #endif
7933
7934 cc->gdb_arch_name = ppc_gdb_arch_name;
7935 #if defined(TARGET_PPC64)
7936 cc->gdb_core_xml_file = "power64-core.xml";
7937 #else
7938 cc->gdb_core_xml_file = "power-core.xml";
7939 #endif
7940 cc->disas_set_info = ppc_disas_set_info;
7941
7942 dc->fw_name = "PowerPC,UNKNOWN";
7943
7944 #ifdef CONFIG_TCG
7945 cc->tcg_ops = &ppc_tcg_ops;
7946 #endif /* CONFIG_TCG */
7947 }
7948
7949 static const TypeInfo ppc_cpu_type_info = {
7950 .name = TYPE_POWERPC_CPU,
7951 .parent = TYPE_CPU,
7952 .instance_size = sizeof(PowerPCCPU),
7953 .instance_align = __alignof__(PowerPCCPU),
7954 .instance_init = ppc_cpu_instance_init,
7955 .instance_finalize = ppc_cpu_instance_finalize,
7956 .abstract = true,
7957 .class_size = sizeof(PowerPCCPUClass),
7958 .class_init = ppc_cpu_class_init,
7959 };
7960
7961 #ifndef CONFIG_USER_ONLY
7962 static const TypeInfo ppc_vhyp_type_info = {
7963 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7964 .parent = TYPE_INTERFACE,
7965 .class_size = sizeof(PPCVirtualHypervisorClass),
7966 };
7967 #endif
7968
7969 static void ppc_cpu_register_types(void)
7970 {
7971 type_register_static(&ppc_cpu_type_info);
7972 #ifndef CONFIG_USER_ONLY
7973 type_register_static(&ppc_vhyp_type_info);
7974 #endif
7975 }
7976
7977 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7978 {
7979 #define RGPL 4
7980 #define RFPL 4
7981
7982 PowerPCCPU *cpu = POWERPC_CPU(cs);
7983 CPUPPCState *env = &cpu->env;
7984 int i;
7985
7986 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7987 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7988 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7989 cs->cpu_index);
7990 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7991 "%08x iidx %d didx %d\n",
7992 env->msr, env->spr[SPR_HID0], env->hflags,
7993 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
7994 #if !defined(NO_TIMER_DUMP)
7995 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7996 #if !defined(CONFIG_USER_ONLY)
7997 " DECR " TARGET_FMT_lu
7998 #endif
7999 "\n",
8000 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8001 #if !defined(CONFIG_USER_ONLY)
8002 , cpu_ppc_load_decr(env)
8003 #endif
8004 );
8005 #endif
8006 for (i = 0; i < 32; i++) {
8007 if ((i & (RGPL - 1)) == 0) {
8008 qemu_fprintf(f, "GPR%02d", i);
8009 }
8010 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
8011 if ((i & (RGPL - 1)) == (RGPL - 1)) {
8012 qemu_fprintf(f, "\n");
8013 }
8014 }
8015 qemu_fprintf(f, "CR ");
8016 for (i = 0; i < 8; i++)
8017 qemu_fprintf(f, "%01x", env->crf[i]);
8018 qemu_fprintf(f, " [");
8019 for (i = 0; i < 8; i++) {
8020 char a = '-';
8021 if (env->crf[i] & 0x08) {
8022 a = 'L';
8023 } else if (env->crf[i] & 0x04) {
8024 a = 'G';
8025 } else if (env->crf[i] & 0x02) {
8026 a = 'E';
8027 }
8028 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8029 }
8030 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
8031 env->reserve_addr);
8032
8033 if (flags & CPU_DUMP_FPU) {
8034 for (i = 0; i < 32; i++) {
8035 if ((i & (RFPL - 1)) == 0) {
8036 qemu_fprintf(f, "FPR%02d", i);
8037 }
8038 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
8039 if ((i & (RFPL - 1)) == (RFPL - 1)) {
8040 qemu_fprintf(f, "\n");
8041 }
8042 }
8043 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
8044 }
8045
8046 #if !defined(CONFIG_USER_ONLY)
8047 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
8048 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
8049 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
8050 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
8051
8052 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
8053 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
8054 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
8055 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
8056
8057 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
8058 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
8059 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
8060 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
8061
8062 switch (env->excp_model) {
8063 #if defined(TARGET_PPC64)
8064 case POWERPC_EXCP_POWER7:
8065 case POWERPC_EXCP_POWER8:
8066 case POWERPC_EXCP_POWER9:
8067 case POWERPC_EXCP_POWER10:
8068 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
8069 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
8070 break;
8071 #endif
8072 case POWERPC_EXCP_BOOKE:
8073 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
8074 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
8075 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
8076 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
8077
8078 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8079 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8080 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
8081 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
8082
8083 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
8084 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
8085 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
8086 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
8087
8088 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
8089 " EPR " TARGET_FMT_lx "\n",
8090 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
8091 env->spr[SPR_BOOKE_EPR]);
8092
8093 /* FSL-specific */
8094 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
8095 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
8096 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
8097 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
8098
8099 /*
8100 * IVORs are left out as they are large and do not change often --
8101 * they can be read with "p $ivor0", "p $ivor1", etc.
8102 */
8103 break;
8104 case POWERPC_EXCP_40x:
8105 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8106 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8107 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
8108 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
8109
8110 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
8111 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8112 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
8113 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
8114 break;
8115 default:
8116 break;
8117 }
8118
8119 #if defined(TARGET_PPC64)
8120 if (env->flags & POWERPC_FLAG_CFAR) {
8121 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
8122 }
8123 #endif
8124
8125 if (env->spr_cb[SPR_LPCR].name) {
8126 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
8127 }
8128
8129 switch (env->mmu_model) {
8130 case POWERPC_MMU_32B:
8131 case POWERPC_MMU_SOFT_6xx:
8132 #if defined(TARGET_PPC64)
8133 case POWERPC_MMU_64B:
8134 case POWERPC_MMU_2_03:
8135 case POWERPC_MMU_2_06:
8136 case POWERPC_MMU_2_07:
8137 case POWERPC_MMU_3_00:
8138 #endif
8139 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
8140 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
8141 }
8142 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
8143 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
8144 }
8145 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
8146 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
8147 break;
8148 case POWERPC_MMU_BOOKE206:
8149 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
8150 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
8151 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
8152 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
8153
8154 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
8155 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8156 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
8157 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
8158
8159 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
8160 " TLB1CFG " TARGET_FMT_lx "\n",
8161 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
8162 env->spr[SPR_BOOKE_TLB1CFG]);
8163 break;
8164 default:
8165 break;
8166 }
8167 #endif
8168
8169 #undef RGPL
8170 #undef RFPL
8171 }
8172 type_init(ppc_cpu_register_types)
Ray Wang's QEMU Repository