2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
43 #include "multiboot.h"
44 #include "hw/timer/mc146818rtc.h"
45 #include "hw/dma/i8257.h"
46 #include "hw/timer/i8254.h"
47 #include "hw/input/i8042.h"
48 #include "hw/audio/pcspk.h"
49 #include "hw/pci/msi.h"
50 #include "hw/sysbus.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/kvm.h"
54 #include "sysemu/qtest.h"
56 #include "hw/xen/xen.h"
57 #include "hw/xen/start_info.h"
58 #include "ui/qemu-spice.h"
59 #include "exec/memory.h"
60 #include "exec/address-spaces.h"
61 #include "sysemu/arch_init.h"
62 #include "qemu/bitmap.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "qemu/option.h"
66 #include "hw/acpi/acpi.h"
67 #include "hw/acpi/cpu_hotplug.h"
68 #include "hw/boards.h"
69 #include "acpi-build.h"
70 #include "hw/mem/pc-dimm.h"
71 #include "qapi/error.h"
72 #include "qapi/qapi-visit-common.h"
73 #include "qapi/visitor.h"
77 #include "hw/i386/intel_iommu.h"
78 #include "hw/net/ne2000-isa.h"
79 #include "standard-headers/asm-x86/bootparam.h"
81 /* debug PC/ISA interrupts */
85 #define DPRINTF(fmt, ...) \
86 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
88 #define DPRINTF(fmt, ...)
91 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
92 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
93 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
94 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
95 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
97 #define E820_NR_ENTRIES 16
103 } QEMU_PACKED
__attribute((__aligned__(4)));
107 struct e820_entry entry
[E820_NR_ENTRIES
];
108 } QEMU_PACKED
__attribute((__aligned__(4)));
110 static struct e820_table e820_reserve
;
111 static struct e820_entry
*e820_table
;
112 static unsigned e820_entries
;
113 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
115 /* Physical Address of PVH entry point read from kernel ELF NOTE */
116 static size_t pvh_start_addr
;
118 GlobalProperty pc_compat_4_0
[] = {};
119 const size_t pc_compat_4_0_len
= G_N_ELEMENTS(pc_compat_4_0
);
121 GlobalProperty pc_compat_3_1
[] = {
122 { "intel-iommu", "dma-drain", "off" },
123 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "off" },
124 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "off" },
125 { "Opteron_G4" "-" TYPE_X86_CPU
, "npt", "off" },
126 { "Opteron_G4" "-" TYPE_X86_CPU
, "nrip-save", "off" },
127 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "off" },
128 { "Opteron_G5" "-" TYPE_X86_CPU
, "npt", "off" },
129 { "Opteron_G5" "-" TYPE_X86_CPU
, "nrip-save", "off" },
130 { "EPYC" "-" TYPE_X86_CPU
, "npt", "off" },
131 { "EPYC" "-" TYPE_X86_CPU
, "nrip-save", "off" },
132 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "npt", "off" },
133 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "nrip-save", "off" },
134 { "Skylake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
135 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
136 { "Skylake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
137 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
138 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
139 { "Icelake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
140 { "Icelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
141 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "stepping", "5" },
142 { TYPE_X86_CPU
, "x-intel-pt-auto-level", "off" },
144 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
146 GlobalProperty pc_compat_3_0
[] = {
147 { TYPE_X86_CPU
, "x-hv-synic-kvm-only", "on" },
148 { "Skylake-Server" "-" TYPE_X86_CPU
, "pku", "off" },
149 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "pku", "off" },
151 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
153 GlobalProperty pc_compat_2_12
[] = {
154 { TYPE_X86_CPU
, "legacy-cache", "on" },
155 { TYPE_X86_CPU
, "topoext", "off" },
156 { "EPYC-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
157 { "EPYC-IBPB-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
159 const size_t pc_compat_2_12_len
= G_N_ELEMENTS(pc_compat_2_12
);
161 GlobalProperty pc_compat_2_11
[] = {
162 { TYPE_X86_CPU
, "x-migrate-smi-count", "off" },
163 { "Skylake-Server" "-" TYPE_X86_CPU
, "clflushopt", "off" },
165 const size_t pc_compat_2_11_len
= G_N_ELEMENTS(pc_compat_2_11
);
167 GlobalProperty pc_compat_2_10
[] = {
168 { TYPE_X86_CPU
, "x-hv-max-vps", "0x40" },
169 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
170 { "q35-pcihost", "x-pci-hole64-fix", "off" },
172 const size_t pc_compat_2_10_len
= G_N_ELEMENTS(pc_compat_2_10
);
174 GlobalProperty pc_compat_2_9
[] = {
175 { "mch", "extended-tseg-mbytes", "0" },
177 const size_t pc_compat_2_9_len
= G_N_ELEMENTS(pc_compat_2_9
);
179 GlobalProperty pc_compat_2_8
[] = {
180 { TYPE_X86_CPU
, "tcg-cpuid", "off" },
181 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
182 { "ICH9-LPC", "x-smi-broadcast", "off" },
183 { TYPE_X86_CPU
, "vmware-cpuid-freq", "off" },
184 { "Haswell-" TYPE_X86_CPU
, "stepping", "1" },
186 const size_t pc_compat_2_8_len
= G_N_ELEMENTS(pc_compat_2_8
);
188 GlobalProperty pc_compat_2_7
[] = {
189 { TYPE_X86_CPU
, "l3-cache", "off" },
190 { TYPE_X86_CPU
, "full-cpuid-auto-level", "off" },
191 { "Opteron_G3" "-" TYPE_X86_CPU
, "family", "15" },
192 { "Opteron_G3" "-" TYPE_X86_CPU
, "model", "6" },
193 { "Opteron_G3" "-" TYPE_X86_CPU
, "stepping", "1" },
194 { "isa-pcspk", "migrate", "off" },
196 const size_t pc_compat_2_7_len
= G_N_ELEMENTS(pc_compat_2_7
);
198 GlobalProperty pc_compat_2_6
[] = {
199 { TYPE_X86_CPU
, "cpuid-0xb", "off" },
200 { "vmxnet3", "romfile", "" },
201 { TYPE_X86_CPU
, "fill-mtrr-mask", "off" },
202 { "apic-common", "legacy-instance-id", "on", }
204 const size_t pc_compat_2_6_len
= G_N_ELEMENTS(pc_compat_2_6
);
206 GlobalProperty pc_compat_2_5
[] = {};
207 const size_t pc_compat_2_5_len
= G_N_ELEMENTS(pc_compat_2_5
);
209 GlobalProperty pc_compat_2_4
[] = {
210 PC_CPU_MODEL_IDS("2.4.0")
211 { "Haswell-" TYPE_X86_CPU
, "abm", "off" },
212 { "Haswell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
213 { "Broadwell-" TYPE_X86_CPU
, "abm", "off" },
214 { "Broadwell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
215 { "host" "-" TYPE_X86_CPU
, "host-cache-info", "on" },
216 { TYPE_X86_CPU
, "check", "off" },
217 { "qemu64" "-" TYPE_X86_CPU
, "sse4a", "on" },
218 { "qemu64" "-" TYPE_X86_CPU
, "abm", "on" },
219 { "qemu64" "-" TYPE_X86_CPU
, "popcnt", "on" },
220 { "qemu32" "-" TYPE_X86_CPU
, "popcnt", "on" },
221 { "Opteron_G2" "-" TYPE_X86_CPU
, "rdtscp", "on" },
222 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "on" },
223 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "on" },
224 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "on", }
226 const size_t pc_compat_2_4_len
= G_N_ELEMENTS(pc_compat_2_4
);
228 GlobalProperty pc_compat_2_3
[] = {
229 PC_CPU_MODEL_IDS("2.3.0")
230 { TYPE_X86_CPU
, "arat", "off" },
231 { "qemu64" "-" TYPE_X86_CPU
, "min-level", "4" },
232 { "kvm64" "-" TYPE_X86_CPU
, "min-level", "5" },
233 { "pentium3" "-" TYPE_X86_CPU
, "min-level", "2" },
234 { "n270" "-" TYPE_X86_CPU
, "min-level", "5" },
235 { "Conroe" "-" TYPE_X86_CPU
, "min-level", "4" },
236 { "Penryn" "-" TYPE_X86_CPU
, "min-level", "4" },
237 { "Nehalem" "-" TYPE_X86_CPU
, "min-level", "4" },
238 { "n270" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
239 { "Penryn" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
240 { "Conroe" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
241 { "Nehalem" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
242 { "Westmere" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
243 { "SandyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
244 { "IvyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
245 { "Haswell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
246 { "Haswell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
247 { "Broadwell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
248 { "Broadwell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
249 { TYPE_X86_CPU
, "kvm-no-smi-migration", "on" },
251 const size_t pc_compat_2_3_len
= G_N_ELEMENTS(pc_compat_2_3
);
253 GlobalProperty pc_compat_2_2
[] = {
254 PC_CPU_MODEL_IDS("2.2.0")
255 { "kvm64" "-" TYPE_X86_CPU
, "vme", "off" },
256 { "kvm32" "-" TYPE_X86_CPU
, "vme", "off" },
257 { "Conroe" "-" TYPE_X86_CPU
, "vme", "off" },
258 { "Penryn" "-" TYPE_X86_CPU
, "vme", "off" },
259 { "Nehalem" "-" TYPE_X86_CPU
, "vme", "off" },
260 { "Westmere" "-" TYPE_X86_CPU
, "vme", "off" },
261 { "SandyBridge" "-" TYPE_X86_CPU
, "vme", "off" },
262 { "Haswell" "-" TYPE_X86_CPU
, "vme", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU
, "vme", "off" },
264 { "Opteron_G1" "-" TYPE_X86_CPU
, "vme", "off" },
265 { "Opteron_G2" "-" TYPE_X86_CPU
, "vme", "off" },
266 { "Opteron_G3" "-" TYPE_X86_CPU
, "vme", "off" },
267 { "Opteron_G4" "-" TYPE_X86_CPU
, "vme", "off" },
268 { "Opteron_G5" "-" TYPE_X86_CPU
, "vme", "off" },
269 { "Haswell" "-" TYPE_X86_CPU
, "f16c", "off" },
270 { "Haswell" "-" TYPE_X86_CPU
, "rdrand", "off" },
271 { "Broadwell" "-" TYPE_X86_CPU
, "f16c", "off" },
272 { "Broadwell" "-" TYPE_X86_CPU
, "rdrand", "off" },
274 const size_t pc_compat_2_2_len
= G_N_ELEMENTS(pc_compat_2_2
);
276 GlobalProperty pc_compat_2_1
[] = {
277 PC_CPU_MODEL_IDS("2.1.0")
278 { "coreduo" "-" TYPE_X86_CPU
, "vmx", "on" },
279 { "core2duo" "-" TYPE_X86_CPU
, "vmx", "on" },
281 const size_t pc_compat_2_1_len
= G_N_ELEMENTS(pc_compat_2_1
);
283 GlobalProperty pc_compat_2_0
[] = {
284 PC_CPU_MODEL_IDS("2.0.0")
285 { "virtio-scsi-pci", "any_layout", "off" },
286 { "PIIX4_PM", "memory-hotplug-support", "off" },
287 { "apic", "version", "0x11" },
288 { "nec-usb-xhci", "superspeed-ports-first", "off" },
289 { "nec-usb-xhci", "force-pcie-endcap", "on" },
290 { "pci-serial", "prog_if", "0" },
291 { "pci-serial-2x", "prog_if", "0" },
292 { "pci-serial-4x", "prog_if", "0" },
293 { "virtio-net-pci", "guest_announce", "off" },
294 { "ICH9-LPC", "memory-hotplug-support", "off" },
295 { "xio3130-downstream", COMPAT_PROP_PCP
, "off" },
296 { "ioh3420", COMPAT_PROP_PCP
, "off" },
298 const size_t pc_compat_2_0_len
= G_N_ELEMENTS(pc_compat_2_0
);
300 GlobalProperty pc_compat_1_7
[] = {
301 PC_CPU_MODEL_IDS("1.7.0")
302 { TYPE_USB_DEVICE
, "msos-desc", "no" },
303 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
304 { "hpet", HPET_INTCAP
, "4" },
306 const size_t pc_compat_1_7_len
= G_N_ELEMENTS(pc_compat_1_7
);
308 GlobalProperty pc_compat_1_6
[] = {
309 PC_CPU_MODEL_IDS("1.6.0")
310 { "e1000", "mitigation", "off" },
311 { "qemu64-" TYPE_X86_CPU
, "model", "2" },
312 { "qemu32-" TYPE_X86_CPU
, "model", "3" },
313 { "i440FX-pcihost", "short_root_bus", "1" },
314 { "q35-pcihost", "short_root_bus", "1" },
316 const size_t pc_compat_1_6_len
= G_N_ELEMENTS(pc_compat_1_6
);
318 GlobalProperty pc_compat_1_5
[] = {
319 PC_CPU_MODEL_IDS("1.5.0")
320 { "Conroe-" TYPE_X86_CPU
, "model", "2" },
321 { "Conroe-" TYPE_X86_CPU
, "min-level", "2" },
322 { "Penryn-" TYPE_X86_CPU
, "model", "2" },
323 { "Penryn-" TYPE_X86_CPU
, "min-level", "2" },
324 { "Nehalem-" TYPE_X86_CPU
, "model", "2" },
325 { "Nehalem-" TYPE_X86_CPU
, "min-level", "2" },
326 { "virtio-net-pci", "any_layout", "off" },
327 { TYPE_X86_CPU
, "pmu", "on" },
328 { "i440FX-pcihost", "short_root_bus", "0" },
329 { "q35-pcihost", "short_root_bus", "0" },
331 const size_t pc_compat_1_5_len
= G_N_ELEMENTS(pc_compat_1_5
);
333 GlobalProperty pc_compat_1_4
[] = {
334 PC_CPU_MODEL_IDS("1.4.0")
335 { "scsi-hd", "discard_granularity", "0" },
336 { "scsi-cd", "discard_granularity", "0" },
337 { "scsi-disk", "discard_granularity", "0" },
338 { "ide-hd", "discard_granularity", "0" },
339 { "ide-cd", "discard_granularity", "0" },
340 { "ide-drive", "discard_granularity", "0" },
341 { "virtio-blk-pci", "discard_granularity", "0" },
342 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
343 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
344 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
345 { "e1000", "romfile", "pxe-e1000.rom" },
346 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
347 { "pcnet", "romfile", "pxe-pcnet.rom" },
348 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
349 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
350 { "486-" TYPE_X86_CPU
, "model", "0" },
351 { "n270" "-" TYPE_X86_CPU
, "movbe", "off" },
352 { "Westmere" "-" TYPE_X86_CPU
, "pclmulqdq", "off" },
354 const size_t pc_compat_1_4_len
= G_N_ELEMENTS(pc_compat_1_4
);
356 void gsi_handler(void *opaque
, int n
, int level
)
358 GSIState
*s
= opaque
;
360 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
361 if (n
< ISA_NUM_IRQS
) {
362 qemu_set_irq(s
->i8259_irq
[n
], level
);
364 qemu_set_irq(s
->ioapic_irq
[n
], level
);
367 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
372 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
374 return 0xffffffffffffffffULL
;
377 /* MSDOS compatibility mode FPU exception support */
378 static qemu_irq ferr_irq
;
380 void pc_register_ferr_irq(qemu_irq irq
)
385 /* XXX: add IGNNE support */
386 void cpu_set_ferr(CPUX86State
*s
)
388 qemu_irq_raise(ferr_irq
);
391 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
394 qemu_irq_lower(ferr_irq
);
397 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
399 return 0xffffffffffffffffULL
;
403 uint64_t cpu_get_tsc(CPUX86State
*env
)
405 return cpu_get_ticks();
409 int cpu_get_pic_interrupt(CPUX86State
*env
)
411 X86CPU
*cpu
= x86_env_get_cpu(env
);
414 if (!kvm_irqchip_in_kernel()) {
415 intno
= apic_get_interrupt(cpu
->apic_state
);
419 /* read the irq from the PIC */
420 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
425 intno
= pic_read_irq(isa_pic
);
429 static void pic_irq_request(void *opaque
, int irq
, int level
)
431 CPUState
*cs
= first_cpu
;
432 X86CPU
*cpu
= X86_CPU(cs
);
434 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
435 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
438 if (apic_accept_pic_intr(cpu
->apic_state
)) {
439 apic_deliver_pic_intr(cpu
->apic_state
, level
);
444 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
446 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
451 /* PC cmos mappings */
453 #define REG_EQUIPMENT_BYTE 0x14
455 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
460 case FLOPPY_DRIVE_TYPE_144
:
461 /* 1.44 Mb 3"5 drive */
464 case FLOPPY_DRIVE_TYPE_288
:
465 /* 2.88 Mb 3"5 drive */
468 case FLOPPY_DRIVE_TYPE_120
:
469 /* 1.2 Mb 5"5 drive */
472 case FLOPPY_DRIVE_TYPE_NONE
:
480 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
481 int16_t cylinders
, int8_t heads
, int8_t sectors
)
483 rtc_set_memory(s
, type_ofs
, 47);
484 rtc_set_memory(s
, info_ofs
, cylinders
);
485 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
486 rtc_set_memory(s
, info_ofs
+ 2, heads
);
487 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
488 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
489 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
490 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
491 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
492 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
495 /* convert boot_device letter to something recognizable by the bios */
496 static int boot_device2nibble(char boot_device
)
498 switch(boot_device
) {
501 return 0x01; /* floppy boot */
503 return 0x02; /* hard drive boot */
505 return 0x03; /* CD-ROM boot */
507 return 0x04; /* Network boot */
512 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
514 #define PC_MAX_BOOT_DEVICES 3
515 int nbds
, bds
[3] = { 0, };
518 nbds
= strlen(boot_device
);
519 if (nbds
> PC_MAX_BOOT_DEVICES
) {
520 error_setg(errp
, "Too many boot devices for PC");
523 for (i
= 0; i
< nbds
; i
++) {
524 bds
[i
] = boot_device2nibble(boot_device
[i
]);
526 error_setg(errp
, "Invalid boot device for PC: '%c'",
531 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
532 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
535 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
537 set_boot_dev(opaque
, boot_device
, errp
);
540 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
543 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
544 FLOPPY_DRIVE_TYPE_NONE
};
548 for (i
= 0; i
< 2; i
++) {
549 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
552 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
553 cmos_get_fd_drive_type(fd_type
[1]);
554 rtc_set_memory(rtc_state
, 0x10, val
);
556 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
558 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
561 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
568 val
|= 0x01; /* 1 drive, ready for boot */
571 val
|= 0x41; /* 2 drives, ready for boot */
574 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
577 typedef struct pc_cmos_init_late_arg
{
578 ISADevice
*rtc_state
;
580 } pc_cmos_init_late_arg
;
582 typedef struct check_fdc_state
{
587 static int check_fdc(Object
*obj
, void *opaque
)
589 CheckFdcState
*state
= opaque
;
592 Error
*local_err
= NULL
;
594 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
599 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
600 if (local_err
|| iobase
!= 0x3f0) {
601 error_free(local_err
);
606 state
->multiple
= true;
608 state
->floppy
= ISA_DEVICE(obj
);
613 static const char * const fdc_container_path
[] = {
614 "/unattached", "/peripheral", "/peripheral-anon"
618 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
621 ISADevice
*pc_find_fdc0(void)
625 CheckFdcState state
= { 0 };
627 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
628 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
629 object_child_foreach(container
, check_fdc
, &state
);
632 if (state
.multiple
) {
633 warn_report("multiple floppy disk controllers with "
634 "iobase=0x3f0 have been found");
635 error_printf("the one being picked for CMOS setup might not reflect "
642 static void pc_cmos_init_late(void *opaque
)
644 pc_cmos_init_late_arg
*arg
= opaque
;
645 ISADevice
*s
= arg
->rtc_state
;
647 int8_t heads
, sectors
;
652 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
653 &cylinders
, &heads
, §ors
) >= 0) {
654 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
657 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
658 &cylinders
, &heads
, §ors
) >= 0) {
659 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
662 rtc_set_memory(s
, 0x12, val
);
665 for (i
= 0; i
< 4; i
++) {
666 /* NOTE: ide_get_geometry() returns the physical
667 geometry. It is always such that: 1 <= sects <= 63, 1
668 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
669 geometry can be different if a translation is done. */
670 if (arg
->idebus
[i
/ 2] &&
671 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
672 &cylinders
, &heads
, §ors
) >= 0) {
673 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
674 assert((trans
& ~3) == 0);
675 val
|= trans
<< (i
* 2);
678 rtc_set_memory(s
, 0x39, val
);
680 pc_cmos_init_floppy(s
, pc_find_fdc0());
682 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
685 void pc_cmos_init(PCMachineState
*pcms
,
686 BusState
*idebus0
, BusState
*idebus1
,
690 static pc_cmos_init_late_arg arg
;
692 /* various important CMOS locations needed by PC/Bochs bios */
695 /* base memory (first MiB) */
696 val
= MIN(pcms
->below_4g_mem_size
/ KiB
, 640);
697 rtc_set_memory(s
, 0x15, val
);
698 rtc_set_memory(s
, 0x16, val
>> 8);
699 /* extended memory (next 64MiB) */
700 if (pcms
->below_4g_mem_size
> 1 * MiB
) {
701 val
= (pcms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
707 rtc_set_memory(s
, 0x17, val
);
708 rtc_set_memory(s
, 0x18, val
>> 8);
709 rtc_set_memory(s
, 0x30, val
);
710 rtc_set_memory(s
, 0x31, val
>> 8);
711 /* memory between 16MiB and 4GiB */
712 if (pcms
->below_4g_mem_size
> 16 * MiB
) {
713 val
= (pcms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
719 rtc_set_memory(s
, 0x34, val
);
720 rtc_set_memory(s
, 0x35, val
>> 8);
721 /* memory above 4GiB */
722 val
= pcms
->above_4g_mem_size
/ 65536;
723 rtc_set_memory(s
, 0x5b, val
);
724 rtc_set_memory(s
, 0x5c, val
>> 8);
725 rtc_set_memory(s
, 0x5d, val
>> 16);
727 object_property_add_link(OBJECT(pcms
), "rtc_state",
729 (Object
**)&pcms
->rtc
,
730 object_property_allow_set_link
,
731 OBJ_PROP_LINK_STRONG
, &error_abort
);
732 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
733 "rtc_state", &error_abort
);
735 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
738 val
|= 0x02; /* FPU is there */
739 val
|= 0x04; /* PS/2 mouse installed */
740 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
742 /* hard drives and FDC */
744 arg
.idebus
[0] = idebus0
;
745 arg
.idebus
[1] = idebus1
;
746 qemu_register_reset(pc_cmos_init_late
, &arg
);
749 #define TYPE_PORT92 "port92"
750 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
752 /* port 92 stuff: could be split off */
753 typedef struct Port92State
{
754 ISADevice parent_obj
;
761 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
764 Port92State
*s
= opaque
;
765 int oldval
= s
->outport
;
767 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
769 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
770 if ((val
& 1) && !(oldval
& 1)) {
771 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
775 static uint64_t port92_read(void *opaque
, hwaddr addr
,
778 Port92State
*s
= opaque
;
782 DPRINTF("port92: read 0x%02x\n", ret
);
786 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
788 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
791 static const VMStateDescription vmstate_port92_isa
= {
794 .minimum_version_id
= 1,
795 .fields
= (VMStateField
[]) {
796 VMSTATE_UINT8(outport
, Port92State
),
797 VMSTATE_END_OF_LIST()
801 static void port92_reset(DeviceState
*d
)
803 Port92State
*s
= PORT92(d
);
808 static const MemoryRegionOps port92_ops
= {
810 .write
= port92_write
,
812 .min_access_size
= 1,
813 .max_access_size
= 1,
815 .endianness
= DEVICE_LITTLE_ENDIAN
,
818 static void port92_initfn(Object
*obj
)
820 Port92State
*s
= PORT92(obj
);
822 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
826 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
829 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
831 ISADevice
*isadev
= ISA_DEVICE(dev
);
832 Port92State
*s
= PORT92(dev
);
834 isa_register_ioport(isadev
, &s
->io
, 0x92);
837 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
839 DeviceClass
*dc
= DEVICE_CLASS(klass
);
841 dc
->realize
= port92_realizefn
;
842 dc
->reset
= port92_reset
;
843 dc
->vmsd
= &vmstate_port92_isa
;
845 * Reason: unlike ordinary ISA devices, this one needs additional
846 * wiring: its A20 output line needs to be wired up by
849 dc
->user_creatable
= false;
852 static const TypeInfo port92_info
= {
854 .parent
= TYPE_ISA_DEVICE
,
855 .instance_size
= sizeof(Port92State
),
856 .instance_init
= port92_initfn
,
857 .class_init
= port92_class_initfn
,
860 static void port92_register_types(void)
862 type_register_static(&port92_info
);
865 type_init(port92_register_types
)
867 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
869 X86CPU
*cpu
= opaque
;
871 /* XXX: send to all CPUs ? */
872 /* XXX: add logic to handle multiple A20 line sources */
873 x86_cpu_set_a20(cpu
, level
);
876 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
878 int index
= le32_to_cpu(e820_reserve
.count
);
879 struct e820_entry
*entry
;
881 if (type
!= E820_RAM
) {
882 /* old FW_CFG_E820_TABLE entry -- reservations only */
883 if (index
>= E820_NR_ENTRIES
) {
886 entry
= &e820_reserve
.entry
[index
++];
888 entry
->address
= cpu_to_le64(address
);
889 entry
->length
= cpu_to_le64(length
);
890 entry
->type
= cpu_to_le32(type
);
892 e820_reserve
.count
= cpu_to_le32(index
);
895 /* new "etc/e820" file -- include ram too */
896 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
897 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
898 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
899 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
905 int e820_get_num_entries(void)
910 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
912 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
913 *address
= le64_to_cpu(e820_table
[idx
].address
);
914 *length
= le64_to_cpu(e820_table
[idx
].length
);
920 /* Enables contiguous-apic-ID mode, for compatibility */
921 static bool compat_apic_id_mode
;
923 void enable_compat_apic_id_mode(void)
925 compat_apic_id_mode
= true;
928 /* Calculates initial APIC ID for a specific CPU index
930 * Currently we need to be able to calculate the APIC ID from the CPU index
931 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
932 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
933 * all CPUs up to max_cpus.
935 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
940 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
941 if (compat_apic_id_mode
) {
942 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
943 error_report("APIC IDs set in compatibility mode, "
944 "CPU topology won't match the configuration");
953 static void pc_build_smbios(PCMachineState
*pcms
)
955 uint8_t *smbios_tables
, *smbios_anchor
;
956 size_t smbios_tables_len
, smbios_anchor_len
;
957 struct smbios_phys_mem_area
*mem_array
;
958 unsigned i
, array_count
;
959 MachineState
*ms
= MACHINE(pcms
);
960 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
962 /* tell smbios about cpuid version and features */
963 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
965 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
967 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
968 smbios_tables
, smbios_tables_len
);
971 /* build the array of physical mem area from e820 table */
972 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
973 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
976 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
977 mem_array
[array_count
].address
= addr
;
978 mem_array
[array_count
].length
= len
;
982 smbios_get_tables(mem_array
, array_count
,
983 &smbios_tables
, &smbios_tables_len
,
984 &smbios_anchor
, &smbios_anchor_len
);
988 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
989 smbios_tables
, smbios_tables_len
);
990 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
991 smbios_anchor
, smbios_anchor_len
);
995 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
998 uint64_t *numa_fw_cfg
;
1000 const CPUArchIdList
*cpus
;
1001 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1003 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
1004 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1006 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1008 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1009 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1010 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1011 * for CPU hotplug also uses APIC ID and not "CPU index".
1012 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1013 * but the "limit to the APIC ID values SeaBIOS may see".
1015 * So for compatibility reasons with old BIOSes we are stuck with
1016 * "etc/max-cpus" actually being apic_id_limit
1018 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
1019 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1020 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
1021 acpi_tables
, acpi_tables_len
);
1022 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
1024 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
1025 &e820_reserve
, sizeof(e820_reserve
));
1026 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
1027 sizeof(struct e820_entry
) * e820_entries
);
1029 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
1030 /* allocate memory for the NUMA channel: one (64bit) word for the number
1031 * of nodes, one word for each VCPU->node and one word for each node to
1032 * hold the amount of memory.
1034 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
1035 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
1036 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
1037 for (i
= 0; i
< cpus
->len
; i
++) {
1038 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
1039 assert(apic_id
< pcms
->apic_id_limit
);
1040 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
1042 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1043 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
1044 cpu_to_le64(numa_info
[i
].node_mem
);
1046 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
1047 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
1048 sizeof(*numa_fw_cfg
));
1053 static long get_file_size(FILE *f
)
1057 /* XXX: on Unix systems, using fstat() probably makes more sense */
1060 fseek(f
, 0, SEEK_END
);
1062 fseek(f
, where
, SEEK_SET
);
1072 } __attribute__((packed
));
1076 * The entry point into the kernel for PVH boot is different from
1077 * the native entry point. The PVH entry is defined by the x86/HVM
1078 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1080 * This function is passed to load_elf() when it is called from
1081 * load_elfboot() which then additionally checks for an ELF Note of
1082 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1083 * parse the PVH entry address from the ELF Note.
1085 * Due to trickery in elf_opts.h, load_elf() is actually available as
1086 * load_elf32() or load_elf64() and this routine needs to be able
1087 * to deal with being called as 32 or 64 bit.
1089 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1090 * global variable. (although the entry point is 32-bit, the kernel
1091 * binary can be either 32-bit or 64-bit).
1093 static uint64_t read_pvh_start_addr(void *arg1
, void *arg2
, bool is64
)
1095 size_t *elf_note_data_addr
;
1097 /* Check if ELF Note header passed in is valid */
1103 struct elf64_note
*nhdr64
= (struct elf64_note
*)arg1
;
1104 uint64_t nhdr_size64
= sizeof(struct elf64_note
);
1105 uint64_t phdr_align
= *(uint64_t *)arg2
;
1106 uint64_t nhdr_namesz
= nhdr64
->n_namesz
;
1108 elf_note_data_addr
=
1109 ((void *)nhdr64
) + nhdr_size64
+
1110 QEMU_ALIGN_UP(nhdr_namesz
, phdr_align
);
1112 struct elf32_note
*nhdr32
= (struct elf32_note
*)arg1
;
1113 uint32_t nhdr_size32
= sizeof(struct elf32_note
);
1114 uint32_t phdr_align
= *(uint32_t *)arg2
;
1115 uint32_t nhdr_namesz
= nhdr32
->n_namesz
;
1117 elf_note_data_addr
=
1118 ((void *)nhdr32
) + nhdr_size32
+
1119 QEMU_ALIGN_UP(nhdr_namesz
, phdr_align
);
1122 pvh_start_addr
= *elf_note_data_addr
;
1124 return pvh_start_addr
;
1127 static bool load_elfboot(const char *kernel_filename
,
1128 int kernel_file_size
,
1130 size_t pvh_xen_start_addr
,
1134 uint32_t mh_load_addr
= 0;
1135 uint32_t elf_kernel_size
= 0;
1137 uint64_t elf_low
, elf_high
;
1140 if (ldl_p(header
) != 0x464c457f) {
1141 return false; /* no elfboot */
1144 bool elf_is64
= header
[EI_CLASS
] == ELFCLASS64
;
1146 ((Elf64_Ehdr
*)header
)->e_flags
: ((Elf32_Ehdr
*)header
)->e_flags
;
1148 if (flags
& 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1149 error_report("elfboot unsupported flags = %x", flags
);
1153 uint64_t elf_note_type
= XEN_ELFNOTE_PHYS32_ENTRY
;
1154 kernel_size
= load_elf(kernel_filename
, read_pvh_start_addr
,
1155 NULL
, &elf_note_type
, &elf_entry
,
1156 &elf_low
, &elf_high
, 0, I386_ELF_MACHINE
,
1159 if (kernel_size
< 0) {
1160 error_report("Error while loading elf kernel");
1163 mh_load_addr
= elf_low
;
1164 elf_kernel_size
= elf_high
- elf_low
;
1166 if (pvh_start_addr
== 0) {
1167 error_report("Error loading uncompressed kernel without PVH ELF Note");
1170 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ENTRY
, pvh_start_addr
);
1171 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, mh_load_addr
);
1172 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, elf_kernel_size
);
1177 static void load_linux(PCMachineState
*pcms
,
1181 int setup_size
, kernel_size
, cmdline_size
;
1182 int dtb_size
, setup_data_offset
;
1183 uint32_t initrd_max
;
1184 uint8_t header
[8192], *setup
, *kernel
;
1185 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
1188 MachineState
*machine
= MACHINE(pcms
);
1189 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1190 struct setup_data
*setup_data
;
1191 const char *kernel_filename
= machine
->kernel_filename
;
1192 const char *initrd_filename
= machine
->initrd_filename
;
1193 const char *dtb_filename
= machine
->dtb
;
1194 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1196 /* Align to 16 bytes as a paranoia measure */
1197 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
1199 /* load the kernel header */
1200 f
= fopen(kernel_filename
, "rb");
1201 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
1202 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
1203 MIN(ARRAY_SIZE(header
), kernel_size
)) {
1204 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
1205 kernel_filename
, strerror(errno
));
1209 /* kernel protocol version */
1211 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
1213 if (ldl_p(header
+0x202) == 0x53726448) {
1214 protocol
= lduw_p(header
+0x206);
1217 * This could be a multiboot kernel. If it is, let's stop treating it
1218 * like a Linux kernel.
1219 * Note: some multiboot images could be in the ELF format (the same of
1220 * PVH), so we try multiboot first since we check the multiboot magic
1221 * header before to load it.
1223 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
1224 kernel_cmdline
, kernel_size
, header
)) {
1228 * Check if the file is an uncompressed kernel file (ELF) and load it,
1229 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1230 * If load_elfboot() is successful, populate the fw_cfg info.
1232 if (pcmc
->pvh_enabled
&&
1233 load_elfboot(kernel_filename
, kernel_size
,
1234 header
, pvh_start_addr
, fw_cfg
)) {
1237 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1238 strlen(kernel_cmdline
) + 1);
1239 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1241 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, sizeof(header
));
1242 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
,
1243 header
, sizeof(header
));
1246 if (initrd_filename
) {
1249 GError
*gerr
= NULL
;
1251 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1252 &initrd_size
, &gerr
)) {
1253 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1254 initrd_filename
, gerr
->message
);
1258 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
1259 if (initrd_size
>= initrd_max
) {
1260 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1261 "(max: %"PRIu32
", need %"PRId64
")\n",
1262 initrd_max
, (uint64_t)initrd_size
);
1266 initrd_addr
= (initrd_max
- initrd_size
) & ~4095;
1268 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1269 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1270 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
,
1274 option_rom
[nb_option_roms
].bootindex
= 0;
1275 option_rom
[nb_option_roms
].name
= "pvh.bin";
1283 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
1285 real_addr
= 0x90000;
1286 cmdline_addr
= 0x9a000 - cmdline_size
;
1287 prot_addr
= 0x10000;
1288 } else if (protocol
< 0x202) {
1289 /* High but ancient kernel */
1290 real_addr
= 0x90000;
1291 cmdline_addr
= 0x9a000 - cmdline_size
;
1292 prot_addr
= 0x100000;
1294 /* High and recent kernel */
1295 real_addr
= 0x10000;
1296 cmdline_addr
= 0x20000;
1297 prot_addr
= 0x100000;
1302 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
1303 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
1304 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
1310 /* highest address for loading the initrd */
1311 if (protocol
>= 0x20c &&
1312 lduw_p(header
+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G
) {
1314 * Linux has supported initrd up to 4 GB for a very long time (2007,
1315 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1316 * though it only sets initrd_max to 2 GB to "work around bootloader
1317 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1318 * has supported this.
1320 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1321 * be loaded into any address.
1323 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1324 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1327 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1329 initrd_max
= UINT32_MAX
;
1330 } else if (protocol
>= 0x203) {
1331 initrd_max
= ldl_p(header
+0x22c);
1333 initrd_max
= 0x37ffffff;
1336 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
1337 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
1340 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
1341 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
1342 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1344 if (protocol
>= 0x202) {
1345 stl_p(header
+0x228, cmdline_addr
);
1347 stw_p(header
+0x20, 0xA33F);
1348 stw_p(header
+0x22, cmdline_addr
-real_addr
);
1351 /* handle vga= parameter */
1352 vmode
= strstr(kernel_cmdline
, "vga=");
1354 unsigned int video_mode
;
1357 if (!strncmp(vmode
, "normal", 6)) {
1358 video_mode
= 0xffff;
1359 } else if (!strncmp(vmode
, "ext", 3)) {
1360 video_mode
= 0xfffe;
1361 } else if (!strncmp(vmode
, "ask", 3)) {
1362 video_mode
= 0xfffd;
1364 video_mode
= strtol(vmode
, NULL
, 0);
1366 stw_p(header
+0x1fa, video_mode
);
1370 /* High nybble = B reserved for QEMU; low nybble is revision number.
1371 If this code is substantially changed, you may want to consider
1372 incrementing the revision. */
1373 if (protocol
>= 0x200) {
1374 header
[0x210] = 0xB0;
1377 if (protocol
>= 0x201) {
1378 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
1379 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
1383 if (initrd_filename
) {
1386 GError
*gerr
= NULL
;
1388 if (protocol
< 0x200) {
1389 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
1393 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1394 &initrd_size
, &gerr
)) {
1395 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1396 initrd_filename
, gerr
->message
);
1399 if (initrd_size
>= initrd_max
) {
1400 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1401 "(max: %"PRIu32
", need %"PRId64
")\n",
1402 initrd_max
, (uint64_t)initrd_size
);
1406 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
1408 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1409 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1410 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
1412 stl_p(header
+0x218, initrd_addr
);
1413 stl_p(header
+0x21c, initrd_size
);
1416 /* load kernel and setup */
1417 setup_size
= header
[0x1f1];
1418 if (setup_size
== 0) {
1421 setup_size
= (setup_size
+1)*512;
1422 if (setup_size
> kernel_size
) {
1423 fprintf(stderr
, "qemu: invalid kernel header\n");
1426 kernel_size
-= setup_size
;
1428 setup
= g_malloc(setup_size
);
1429 kernel
= g_malloc(kernel_size
);
1430 fseek(f
, 0, SEEK_SET
);
1431 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1432 fprintf(stderr
, "fread() failed\n");
1435 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1436 fprintf(stderr
, "fread() failed\n");
1441 /* append dtb to kernel */
1443 if (protocol
< 0x209) {
1444 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1448 dtb_size
= get_image_size(dtb_filename
);
1449 if (dtb_size
<= 0) {
1450 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1451 dtb_filename
, strerror(errno
));
1455 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1456 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1457 kernel
= g_realloc(kernel
, kernel_size
);
1459 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1461 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1462 setup_data
->next
= 0;
1463 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1464 setup_data
->len
= cpu_to_le32(dtb_size
);
1466 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1469 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1471 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1472 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1473 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1475 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1476 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1477 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1479 option_rom
[nb_option_roms
].bootindex
= 0;
1480 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1481 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1482 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1487 #define NE2000_NB_MAX 6
1489 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1491 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1493 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1495 static int nb_ne2k
= 0;
1497 if (nb_ne2k
== NE2000_NB_MAX
)
1499 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1500 ne2000_irq
[nb_ne2k
], nd
);
1504 DeviceState
*cpu_get_current_apic(void)
1507 X86CPU
*cpu
= X86_CPU(current_cpu
);
1508 return cpu
->apic_state
;
1514 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1516 X86CPU
*cpu
= opaque
;
1519 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1523 static void pc_new_cpu(const char *typename
, int64_t apic_id
, Error
**errp
)
1526 Error
*local_err
= NULL
;
1528 cpu
= object_new(typename
);
1530 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1531 object_property_set_bool(cpu
, true, "realized", &local_err
);
1534 error_propagate(errp
, local_err
);
1537 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
1539 MachineState
*ms
= MACHINE(qdev_get_machine());
1540 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
1541 Error
*local_err
= NULL
;
1544 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1548 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1549 error_setg(errp
, "Unable to add CPU: %" PRIi64
1550 ", resulting APIC ID (%" PRIi64
") is too large",
1555 pc_new_cpu(ms
->cpu_type
, apic_id
, &local_err
);
1557 error_propagate(errp
, local_err
);
1562 void pc_cpus_init(PCMachineState
*pcms
)
1565 const CPUArchIdList
*possible_cpus
;
1566 MachineState
*ms
= MACHINE(pcms
);
1567 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1569 /* Calculates the limit to CPU APIC ID values
1571 * Limit for the APIC ID value, so that all
1572 * CPU APIC IDs are < pcms->apic_id_limit.
1574 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1576 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
1577 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1578 for (i
= 0; i
< smp_cpus
; i
++) {
1579 pc_new_cpu(possible_cpus
->cpus
[i
].type
, possible_cpus
->cpus
[i
].arch_id
,
1584 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1586 MachineState
*ms
= MACHINE(pcms
);
1587 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1588 CPUX86State
*env
= &cpu
->env
;
1589 uint32_t unused
, ecx
, edx
;
1590 uint64_t feature_control_bits
= 0;
1593 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1594 if (ecx
& CPUID_EXT_VMX
) {
1595 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1598 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1599 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1600 (env
->mcg_cap
& MCG_LMCE_P
)) {
1601 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1604 if (!feature_control_bits
) {
1608 val
= g_malloc(sizeof(*val
));
1609 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1610 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1613 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1615 if (cpus_count
> 0xff) {
1616 /* If the number of CPUs can't be represented in 8 bits, the
1617 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1618 * to make old BIOSes fail more predictably.
1620 rtc_set_memory(rtc
, 0x5f, 0);
1622 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1627 void pc_machine_done(Notifier
*notifier
, void *data
)
1629 PCMachineState
*pcms
= container_of(notifier
,
1630 PCMachineState
, machine_done
);
1631 PCIBus
*bus
= pcms
->bus
;
1633 /* set the number of CPUs */
1634 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1637 int extra_hosts
= 0;
1639 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1640 /* look for expander root buses */
1641 if (pci_bus_is_root(bus
)) {
1645 if (extra_hosts
&& pcms
->fw_cfg
) {
1646 uint64_t *val
= g_malloc(sizeof(*val
));
1647 *val
= cpu_to_le64(extra_hosts
);
1648 fw_cfg_add_file(pcms
->fw_cfg
,
1649 "etc/extra-pci-roots", val
, sizeof(*val
));
1655 pc_build_smbios(pcms
);
1656 pc_build_feature_control_file(pcms
);
1657 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1658 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1661 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1662 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1664 if (!iommu
|| !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu
)) ||
1665 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1666 error_report("current -smp configuration requires "
1667 "Extended Interrupt Mode enabled. "
1668 "You can add an IOMMU using: "
1669 "-device intel-iommu,intremap=on,eim=on");
1675 void pc_guest_info_init(PCMachineState
*pcms
)
1679 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1680 pcms
->numa_nodes
= nb_numa_nodes
;
1681 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1682 sizeof *pcms
->node_mem
);
1683 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1684 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1687 pcms
->machine_done
.notify
= pc_machine_done
;
1688 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1691 /* setup pci memory address space mapping into system address space */
1692 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1693 MemoryRegion
*pci_address_space
)
1695 /* Set to lower priority than RAM */
1696 memory_region_add_subregion_overlap(system_memory
, 0x0,
1697 pci_address_space
, -1);
1700 void xen_load_linux(PCMachineState
*pcms
)
1705 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1707 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1708 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1711 load_linux(pcms
, fw_cfg
);
1712 for (i
= 0; i
< nb_option_roms
; i
++) {
1713 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1714 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1715 !strcmp(option_rom
[i
].name
, "pvh.bin") ||
1716 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1717 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1719 pcms
->fw_cfg
= fw_cfg
;
1722 void pc_memory_init(PCMachineState
*pcms
,
1723 MemoryRegion
*system_memory
,
1724 MemoryRegion
*rom_memory
,
1725 MemoryRegion
**ram_memory
)
1728 MemoryRegion
*ram
, *option_rom_mr
;
1729 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1731 MachineState
*machine
= MACHINE(pcms
);
1732 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1734 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
1735 pcms
->above_4g_mem_size
);
1737 linux_boot
= (machine
->kernel_filename
!= NULL
);
1739 /* Allocate RAM. We allocate it as a single memory region and use
1740 * aliases to address portions of it, mostly for backwards compatibility
1741 * with older qemus that used qemu_ram_alloc().
1743 ram
= g_malloc(sizeof(*ram
));
1744 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1747 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1748 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1749 0, pcms
->below_4g_mem_size
);
1750 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1751 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
1752 if (pcms
->above_4g_mem_size
> 0) {
1753 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1754 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1755 pcms
->below_4g_mem_size
,
1756 pcms
->above_4g_mem_size
);
1757 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1759 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
1762 if (!pcmc
->has_reserved_memory
&&
1763 (machine
->ram_slots
||
1764 (machine
->maxram_size
> machine
->ram_size
))) {
1765 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1767 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1772 /* always allocate the device memory information */
1773 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
1775 /* initialize device memory address space */
1776 if (pcmc
->has_reserved_memory
&&
1777 (machine
->ram_size
< machine
->maxram_size
)) {
1778 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
1780 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1781 error_report("unsupported amount of memory slots: %"PRIu64
,
1782 machine
->ram_slots
);
1786 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1787 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1788 error_report("maximum memory size must by aligned to multiple of "
1789 "%d bytes", TARGET_PAGE_SIZE
);
1793 machine
->device_memory
->base
=
1794 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1 * GiB
);
1796 if (pcmc
->enforce_aligned_dimm
) {
1797 /* size device region assuming 1G page max alignment per slot */
1798 device_mem_size
+= (1 * GiB
) * machine
->ram_slots
;
1801 if ((machine
->device_memory
->base
+ device_mem_size
) <
1803 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1804 machine
->maxram_size
);
1808 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
1809 "device-memory", device_mem_size
);
1810 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
1811 &machine
->device_memory
->mr
);
1814 /* Initialize PC system firmware */
1815 pc_system_firmware_init(pcms
, rom_memory
);
1817 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1818 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1820 if (pcmc
->pci_enabled
) {
1821 memory_region_set_readonly(option_rom_mr
, true);
1823 memory_region_add_subregion_overlap(rom_memory
,
1828 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
1832 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
1833 uint64_t *val
= g_malloc(sizeof(*val
));
1834 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1835 uint64_t res_mem_end
= machine
->device_memory
->base
;
1837 if (!pcmc
->broken_reserved_end
) {
1838 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1840 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1841 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1845 load_linux(pcms
, fw_cfg
);
1848 for (i
= 0; i
< nb_option_roms
; i
++) {
1849 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1851 pcms
->fw_cfg
= fw_cfg
;
1853 /* Init default IOAPIC address space */
1854 pcms
->ioapic_as
= &address_space_memory
;
1858 * The 64bit pci hole starts after "above 4G RAM" and
1859 * potentially the space reserved for memory hotplug.
1861 uint64_t pc_pci_hole64_start(void)
1863 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1864 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1865 MachineState
*ms
= MACHINE(pcms
);
1866 uint64_t hole64_start
= 0;
1868 if (pcmc
->has_reserved_memory
&& ms
->device_memory
->base
) {
1869 hole64_start
= ms
->device_memory
->base
;
1870 if (!pcmc
->broken_reserved_end
) {
1871 hole64_start
+= memory_region_size(&ms
->device_memory
->mr
);
1874 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
1877 return ROUND_UP(hole64_start
, 1 * GiB
);
1880 qemu_irq
pc_allocate_cpu_irq(void)
1882 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
1885 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1887 DeviceState
*dev
= NULL
;
1889 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1891 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1892 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1893 } else if (isa_bus
) {
1894 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1895 dev
= isadev
? DEVICE(isadev
) : NULL
;
1897 rom_reset_order_override();
1901 static const MemoryRegionOps ioport80_io_ops
= {
1902 .write
= ioport80_write
,
1903 .read
= ioport80_read
,
1904 .endianness
= DEVICE_NATIVE_ENDIAN
,
1906 .min_access_size
= 1,
1907 .max_access_size
= 1,
1911 static const MemoryRegionOps ioportF0_io_ops
= {
1912 .write
= ioportF0_write
,
1913 .read
= ioportF0_read
,
1914 .endianness
= DEVICE_NATIVE_ENDIAN
,
1916 .min_access_size
= 1,
1917 .max_access_size
= 1,
1921 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
, bool no_vmport
)
1924 DriveInfo
*fd
[MAX_FD
];
1926 ISADevice
*i8042
, *port92
, *vmmouse
;
1928 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1929 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
1931 for (i
= 0; i
< MAX_FD
; i
++) {
1932 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1933 create_fdctrl
|= !!fd
[i
];
1935 if (create_fdctrl
) {
1936 fdctrl_init_isa(isa_bus
, fd
);
1939 i8042
= isa_create_simple(isa_bus
, "i8042");
1941 vmport_init(isa_bus
);
1942 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1947 DeviceState
*dev
= DEVICE(vmmouse
);
1948 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1949 qdev_init_nofail(dev
);
1951 port92
= isa_create_simple(isa_bus
, "port92");
1953 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1954 i8042_setup_a20_line(i8042
, a20_line
[0]);
1955 port92_init(port92
, a20_line
[1]);
1959 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1960 ISADevice
**rtc_state
,
1967 DeviceState
*hpet
= NULL
;
1968 int pit_isa_irq
= 0;
1969 qemu_irq pit_alt_irq
= NULL
;
1970 qemu_irq rtc_irq
= NULL
;
1971 ISADevice
*pit
= NULL
;
1972 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1973 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1975 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1976 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1978 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1979 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1982 * Check if an HPET shall be created.
1984 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1985 * when the HPET wants to take over. Thus we have to disable the latter.
1987 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1988 /* In order to set property, here not using sysbus_try_create_simple */
1989 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1991 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1992 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1995 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
1998 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
2000 qdev_init_nofail(hpet
);
2001 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
2003 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
2004 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
2007 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
2008 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
2011 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
2013 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
2015 if (!xen_enabled() && has_pit
) {
2016 if (kvm_pit_in_kernel()) {
2017 pit
= kvm_pit_init(isa_bus
, 0x40);
2019 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
2022 /* connect PIT to output control line of the HPET */
2023 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
2025 pcspk_init(isa_bus
, pit
);
2028 i8257_dma_init(isa_bus
, 0);
2031 pc_superio_init(isa_bus
, create_fdctrl
, no_vmport
);
2034 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
2038 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
2039 for (i
= 0; i
< nb_nics
; i
++) {
2040 NICInfo
*nd
= &nd_table
[i
];
2041 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
2043 if (g_str_equal(model
, "ne2k_isa")) {
2044 pc_init_ne2k_isa(isa_bus
, nd
);
2046 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
2049 rom_reset_order_override();
2052 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
2058 if (kvm_ioapic_in_kernel()) {
2059 dev
= qdev_create(NULL
, TYPE_KVM_IOAPIC
);
2061 dev
= qdev_create(NULL
, TYPE_IOAPIC
);
2064 object_property_add_child(object_resolve_path(parent_name
, NULL
),
2065 "ioapic", OBJECT(dev
), NULL
);
2067 qdev_init_nofail(dev
);
2068 d
= SYS_BUS_DEVICE(dev
);
2069 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
2071 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
2072 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
2076 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2079 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2080 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2081 const MachineState
*ms
= MACHINE(hotplug_dev
);
2082 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2083 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
2084 Error
*local_err
= NULL
;
2087 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2088 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2089 * addition to cover this case.
2091 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
2093 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2097 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2098 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2102 hotplug_handler_pre_plug(pcms
->acpi_dev
, dev
, &local_err
);
2104 error_propagate(errp
, local_err
);
2108 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
2109 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
2112 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
2113 DeviceState
*dev
, Error
**errp
)
2115 Error
*local_err
= NULL
;
2116 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2117 MachineState
*ms
= MACHINE(hotplug_dev
);
2118 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2120 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
), &local_err
);
2126 nvdimm_plug(ms
->nvdimms_state
);
2129 hotplug_handler_plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
2131 error_propagate(errp
, local_err
);
2134 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
2135 DeviceState
*dev
, Error
**errp
)
2137 Error
*local_err
= NULL
;
2138 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2141 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2142 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2143 * addition to cover this case.
2145 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
2146 error_setg(&local_err
,
2147 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2151 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2152 error_setg(&local_err
,
2153 "nvdimm device hot unplug is not supported yet.");
2157 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
,
2160 error_propagate(errp
, local_err
);
2163 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
2164 DeviceState
*dev
, Error
**errp
)
2166 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2167 Error
*local_err
= NULL
;
2169 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2174 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
2175 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
2177 error_propagate(errp
, local_err
);
2180 static int pc_apic_cmp(const void *a
, const void *b
)
2182 CPUArchId
*apic_a
= (CPUArchId
*)a
;
2183 CPUArchId
*apic_b
= (CPUArchId
*)b
;
2185 return apic_a
->arch_id
- apic_b
->arch_id
;
2188 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2189 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2190 * entry corresponding to CPU's apic_id returns NULL.
2192 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2194 CPUArchId apic_id
, *found_cpu
;
2196 apic_id
.arch_id
= id
;
2197 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
2198 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
2200 if (found_cpu
&& idx
) {
2201 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
2206 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
2207 DeviceState
*dev
, Error
**errp
)
2209 CPUArchId
*found_cpu
;
2210 Error
*local_err
= NULL
;
2211 X86CPU
*cpu
= X86_CPU(dev
);
2212 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2214 if (pcms
->acpi_dev
) {
2215 hotplug_handler_plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2221 /* increment the number of CPUs */
2224 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2227 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2230 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2231 found_cpu
->cpu
= OBJECT(dev
);
2233 error_propagate(errp
, local_err
);
2235 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2236 DeviceState
*dev
, Error
**errp
)
2239 Error
*local_err
= NULL
;
2240 X86CPU
*cpu
= X86_CPU(dev
);
2241 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2243 if (!pcms
->acpi_dev
) {
2244 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
2248 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2251 error_setg(&local_err
, "Boot CPU is unpluggable");
2255 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
,
2262 error_propagate(errp
, local_err
);
2266 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
2267 DeviceState
*dev
, Error
**errp
)
2269 CPUArchId
*found_cpu
;
2270 Error
*local_err
= NULL
;
2271 X86CPU
*cpu
= X86_CPU(dev
);
2272 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2274 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2279 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2280 found_cpu
->cpu
= NULL
;
2281 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
2283 /* decrement the number of CPUs */
2285 /* Update the number of CPUs in CMOS */
2286 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2287 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2289 error_propagate(errp
, local_err
);
2292 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
2293 DeviceState
*dev
, Error
**errp
)
2297 CPUArchId
*cpu_slot
;
2298 X86CPUTopoInfo topo
;
2299 X86CPU
*cpu
= X86_CPU(dev
);
2300 MachineState
*ms
= MACHINE(hotplug_dev
);
2301 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2303 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
2304 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
2309 /* if APIC ID is not set, set it based on socket/core/thread properties */
2310 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
2311 int max_socket
= (max_cpus
- 1) / smp_threads
/ smp_cores
;
2313 if (cpu
->socket_id
< 0) {
2314 error_setg(errp
, "CPU socket-id is not set");
2316 } else if (cpu
->socket_id
> max_socket
) {
2317 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
2318 cpu
->socket_id
, max_socket
);
2321 if (cpu
->core_id
< 0) {
2322 error_setg(errp
, "CPU core-id is not set");
2324 } else if (cpu
->core_id
> (smp_cores
- 1)) {
2325 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
2326 cpu
->core_id
, smp_cores
- 1);
2329 if (cpu
->thread_id
< 0) {
2330 error_setg(errp
, "CPU thread-id is not set");
2332 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
2333 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
2334 cpu
->thread_id
, smp_threads
- 1);
2338 topo
.pkg_id
= cpu
->socket_id
;
2339 topo
.core_id
= cpu
->core_id
;
2340 topo
.smt_id
= cpu
->thread_id
;
2341 cpu
->apic_id
= apicid_from_topo_ids(smp_cores
, smp_threads
, &topo
);
2344 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2346 MachineState
*ms
= MACHINE(pcms
);
2348 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2349 error_setg(errp
, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2350 " APIC ID %" PRIu32
", valid index range 0:%d",
2351 topo
.pkg_id
, topo
.core_id
, topo
.smt_id
, cpu
->apic_id
,
2352 ms
->possible_cpus
->len
- 1);
2356 if (cpu_slot
->cpu
) {
2357 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
2362 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2363 * so that machine_query_hotpluggable_cpus would show correct values
2365 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2366 * once -smp refactoring is complete and there will be CPU private
2367 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2368 x86_topo_ids_from_apicid(cpu
->apic_id
, smp_cores
, smp_threads
, &topo
);
2369 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
2370 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
2371 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
2374 cpu
->socket_id
= topo
.pkg_id
;
2376 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
2377 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
2378 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
2381 cpu
->core_id
= topo
.core_id
;
2383 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
2384 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
2385 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
2388 cpu
->thread_id
= topo
.smt_id
;
2390 if (cpu
->hyperv_vpindex
&& !kvm_hv_vpindex_settable()) {
2391 error_setg(errp
, "kernel doesn't allow setting HyperV VP_INDEX");
2396 cs
->cpu_index
= idx
;
2398 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2401 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2402 DeviceState
*dev
, Error
**errp
)
2404 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2405 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
2406 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2407 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2411 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2412 DeviceState
*dev
, Error
**errp
)
2414 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2415 pc_memory_plug(hotplug_dev
, dev
, errp
);
2416 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2417 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2421 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2422 DeviceState
*dev
, Error
**errp
)
2424 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2425 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
2426 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2427 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2429 error_setg(errp
, "acpi: device unplug request for not supported device"
2430 " type: %s", object_get_typename(OBJECT(dev
)));
2434 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2435 DeviceState
*dev
, Error
**errp
)
2437 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2438 pc_memory_unplug(hotplug_dev
, dev
, errp
);
2439 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2440 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2442 error_setg(errp
, "acpi: device unplug for not supported device"
2443 " type: %s", object_get_typename(OBJECT(dev
)));
2447 static HotplugHandler
*pc_get_hotplug_handler(MachineState
*machine
,
2450 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2451 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2452 return HOTPLUG_HANDLER(machine
);
2459 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
2460 const char *name
, void *opaque
,
2463 MachineState
*ms
= MACHINE(obj
);
2464 int64_t value
= memory_region_size(&ms
->device_memory
->mr
);
2466 visit_type_int(v
, name
, &value
, errp
);
2469 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2470 const char *name
, void *opaque
,
2473 PCMachineState
*pcms
= PC_MACHINE(obj
);
2474 uint64_t value
= pcms
->max_ram_below_4g
;
2476 visit_type_size(v
, name
, &value
, errp
);
2479 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2480 const char *name
, void *opaque
,
2483 PCMachineState
*pcms
= PC_MACHINE(obj
);
2484 Error
*error
= NULL
;
2487 visit_type_size(v
, name
, &value
, &error
);
2489 error_propagate(errp
, error
);
2492 if (value
> 4 * GiB
) {
2494 "Machine option 'max-ram-below-4g=%"PRIu64
2495 "' expects size less than or equal to 4G", value
);
2496 error_propagate(errp
, error
);
2500 if (value
< 1 * MiB
) {
2501 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2502 "BIOS may not work with less than 1MiB", value
);
2505 pcms
->max_ram_below_4g
= value
;
2508 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2509 void *opaque
, Error
**errp
)
2511 PCMachineState
*pcms
= PC_MACHINE(obj
);
2512 OnOffAuto vmport
= pcms
->vmport
;
2514 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2517 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2518 void *opaque
, Error
**errp
)
2520 PCMachineState
*pcms
= PC_MACHINE(obj
);
2522 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2525 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2527 bool smm_available
= false;
2529 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2533 if (tcg_enabled() || qtest_enabled()) {
2534 smm_available
= true;
2535 } else if (kvm_enabled()) {
2536 smm_available
= kvm_has_smm();
2539 if (smm_available
) {
2543 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2544 error_report("System Management Mode not supported by this hypervisor.");
2550 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2551 void *opaque
, Error
**errp
)
2553 PCMachineState
*pcms
= PC_MACHINE(obj
);
2554 OnOffAuto smm
= pcms
->smm
;
2556 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2559 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2560 void *opaque
, Error
**errp
)
2562 PCMachineState
*pcms
= PC_MACHINE(obj
);
2564 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2567 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2569 PCMachineState
*pcms
= PC_MACHINE(obj
);
2571 return pcms
->smbus_enabled
;
2574 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2576 PCMachineState
*pcms
= PC_MACHINE(obj
);
2578 pcms
->smbus_enabled
= value
;
2581 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2583 PCMachineState
*pcms
= PC_MACHINE(obj
);
2585 return pcms
->sata_enabled
;
2588 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2590 PCMachineState
*pcms
= PC_MACHINE(obj
);
2592 pcms
->sata_enabled
= value
;
2595 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2597 PCMachineState
*pcms
= PC_MACHINE(obj
);
2599 return pcms
->pit_enabled
;
2602 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2604 PCMachineState
*pcms
= PC_MACHINE(obj
);
2606 pcms
->pit_enabled
= value
;
2609 static void pc_machine_initfn(Object
*obj
)
2611 PCMachineState
*pcms
= PC_MACHINE(obj
);
2613 pcms
->max_ram_below_4g
= 0; /* use default */
2614 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2615 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2616 /* acpi build is enabled by default if machine supports it */
2617 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2618 pcms
->smbus_enabled
= true;
2619 pcms
->sata_enabled
= true;
2620 pcms
->pit_enabled
= true;
2622 pc_system_flash_create(pcms
);
2625 static void pc_machine_reset(void)
2630 qemu_devices_reset();
2632 /* Reset APIC after devices have been reset to cancel
2633 * any changes that qemu_devices_reset() might have done.
2638 if (cpu
->apic_state
) {
2639 device_reset(cpu
->apic_state
);
2644 static CpuInstanceProperties
2645 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2647 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2648 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2650 assert(cpu_index
< possible_cpus
->len
);
2651 return possible_cpus
->cpus
[cpu_index
].props
;
2654 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2656 X86CPUTopoInfo topo
;
2658 assert(idx
< ms
->possible_cpus
->len
);
2659 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2660 smp_cores
, smp_threads
, &topo
);
2661 return topo
.pkg_id
% nb_numa_nodes
;
2664 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2668 if (ms
->possible_cpus
) {
2670 * make sure that max_cpus hasn't changed since the first use, i.e.
2671 * -smp hasn't been parsed after it
2673 assert(ms
->possible_cpus
->len
== max_cpus
);
2674 return ms
->possible_cpus
;
2677 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2678 sizeof(CPUArchId
) * max_cpus
);
2679 ms
->possible_cpus
->len
= max_cpus
;
2680 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
2681 X86CPUTopoInfo topo
;
2683 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
2684 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
2685 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(i
);
2686 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
2687 smp_cores
, smp_threads
, &topo
);
2688 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
2689 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
2690 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
2691 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
2692 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
2693 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
2695 return ms
->possible_cpus
;
2698 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2700 /* cpu index isn't used */
2704 X86CPU
*cpu
= X86_CPU(cs
);
2706 if (!cpu
->apic_state
) {
2707 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
2709 apic_deliver_nmi(cpu
->apic_state
);
2714 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
2716 MachineClass
*mc
= MACHINE_CLASS(oc
);
2717 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
2718 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2719 NMIClass
*nc
= NMI_CLASS(oc
);
2721 pcmc
->pci_enabled
= true;
2722 pcmc
->has_acpi_build
= true;
2723 pcmc
->rsdp_in_ram
= true;
2724 pcmc
->smbios_defaults
= true;
2725 pcmc
->smbios_uuid_encoded
= true;
2726 pcmc
->gigabyte_align
= true;
2727 pcmc
->has_reserved_memory
= true;
2728 pcmc
->kvmclock_enabled
= true;
2729 pcmc
->enforce_aligned_dimm
= true;
2730 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2731 * to be used at the moment, 32K should be enough for a while. */
2732 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
2733 pcmc
->save_tsc_khz
= true;
2734 pcmc
->linuxboot_dma_enabled
= true;
2735 pcmc
->pvh_enabled
= true;
2736 assert(!mc
->get_hotplug_handler
);
2737 mc
->get_hotplug_handler
= pc_get_hotplug_handler
;
2738 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
2739 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
2740 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
2741 mc
->auto_enable_numa_with_memhp
= true;
2742 mc
->has_hotpluggable_cpus
= true;
2743 mc
->default_boot_order
= "cad";
2744 mc
->hot_add_cpu
= pc_hot_add_cpu
;
2745 mc
->block_default_type
= IF_IDE
;
2747 mc
->reset
= pc_machine_reset
;
2748 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
2749 hc
->plug
= pc_machine_device_plug_cb
;
2750 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
2751 hc
->unplug
= pc_machine_device_unplug_cb
;
2752 nc
->nmi_monitor_handler
= x86_nmi
;
2753 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
2754 mc
->nvdimm_supported
= true;
2756 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
2757 pc_machine_get_device_memory_region_size
, NULL
,
2758 NULL
, NULL
, &error_abort
);
2760 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
2761 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
2762 NULL
, NULL
, &error_abort
);
2764 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
2765 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
2767 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
2768 pc_machine_get_smm
, pc_machine_set_smm
,
2769 NULL
, NULL
, &error_abort
);
2770 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
2771 "Enable SMM (pc & q35)", &error_abort
);
2773 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
2774 pc_machine_get_vmport
, pc_machine_set_vmport
,
2775 NULL
, NULL
, &error_abort
);
2776 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
2777 "Enable vmport (pc & q35)", &error_abort
);
2779 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
2780 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
2782 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
2783 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
2785 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
2786 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
2789 static const TypeInfo pc_machine_info
= {
2790 .name
= TYPE_PC_MACHINE
,
2791 .parent
= TYPE_MACHINE
,
2793 .instance_size
= sizeof(PCMachineState
),
2794 .instance_init
= pc_machine_initfn
,
2795 .class_size
= sizeof(PCMachineClass
),
2796 .class_init
= pc_machine_class_init
,
2797 .interfaces
= (InterfaceInfo
[]) {
2798 { TYPE_HOTPLUG_HANDLER
},
2804 static void pc_machine_register_types(void)
2806 type_register_static(&pc_machine_info
);
2809 type_init(pc_machine_register_types
)