target/arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 #include "exec/translator.h"
   5 #include "internals.h"
   6
   7
   8 /* internal defines */
   9 typedef struct DisasContext {
  10     DisasContextBase base;
  11     const ARMISARegisters *isar;
  12
  13     /* The address of the current instruction being translated. */
  14     target_ulong pc_curr;
  15     target_ulong page_start;
  16     uint32_t insn;
  17     /* Nonzero if this instruction has been conditionally skipped.  */
  18     int condjmp;
  19     /* The label that will be jumped to when the instruction is skipped.  */
  20     TCGLabel *condlabel;
  21     /* Thumb-2 conditional execution bits.  */
  22     int condexec_mask;
  23     int condexec_cond;
  24     /* M-profile ECI/ICI exception-continuable instruction state */
  25     int eci;
  26     /*
  27      * trans_ functions for insns which are continuable should set this true
  28      * after decode (ie after any UNDEF checks)
  29      */
  30     bool eci_handled;
  31     /* TCG op to rewind to if this turns out to be an invalid ECI state */
  32     TCGOp *insn_eci_rewind;
  33     int sctlr_b;
  34     MemOp be_data;
  35 #if !defined(CONFIG_USER_ONLY)
  36     int user;
  37 #endif
  38     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  39     uint8_t tbii;      /* TBI1|TBI0 for insns */
  40     uint8_t tbid;      /* TBI1|TBI0 for data */
  41     uint8_t tcma;      /* TCMA1|TCMA0 for MTE */
  42     bool ns;        /* Use non-secure CPREG bank on access */
  43     int fp_excp_el; /* FP exception EL or 0 if enabled */
  44     int sve_excp_el; /* SVE exception EL or 0 if enabled */
  45     int sme_excp_el; /* SME exception EL or 0 if enabled */
  46     int vl;          /* current vector length in bytes */
  47     int svl;         /* current streaming vector length in bytes */
  48     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  49     int vec_len;
  50     int vec_stride;
  51     bool v7m_handler_mode;
  52     bool v8m_secure; /* true if v8M and we're in Secure mode */
  53     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
  54     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
  55     bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
  56     bool v7m_lspact; /* FPCCR.LSPACT set */
  57     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  58      * so that top level loop can generate correct syndrome information.
  59      */
  60     uint32_t svc_imm;
  61     int current_el;
  62     GHashTable *cp_regs;
  63     uint64_t features; /* CPU features bits */
  64     bool aarch64;
  65     bool thumb;
  66     /* Because unallocated encodings generate different exception syndrome
  67      * information from traps due to FP being disabled, we can't do a single
  68      * "is fp access disabled" check at a high level in the decode tree.
  69      * To help in catching bugs where the access check was forgotten in some
  70      * code path, we set this flag when the access check is done, and assert
  71      * that it is set at the point where we actually touch the FP regs.
  72      */
  73     bool fp_access_checked;
  74     bool sve_access_checked;
  75     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  76      * single-step support).
  77      */
  78     bool ss_active;
  79     bool pstate_ss;
  80     /* True if the insn just emitted was a load-exclusive instruction
  81      * (necessary for syndrome information for single step exceptions),
  82      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  83      */
  84     bool is_ldex;
  85     /* True if AccType_UNPRIV should be used for LDTR et al */
  86     bool unpriv;
  87     /* True if v8.3-PAuth is active.  */
  88     bool pauth_active;
  89     /* True if v8.5-MTE access to tags is enabled.  */
  90     bool ata;
  91     /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv.  */
  92     bool mte_active[2];
  93     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
  94     bool bt;
  95     /* True if any CP15 access is trapped by HSTR_EL2 */
  96     bool hstr_active;
  97     /* True if memory operations require alignment */
  98     bool align_mem;
  99     /* True if PSTATE.IL is set */
 100     bool pstate_il;
 101     /* True if PSTATE.SM is set. */
 102     bool pstate_sm;
 103     /* True if PSTATE.ZA is set. */
 104     bool pstate_za;
 105     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
 106     bool mve_no_pred;
 107     /*
 108      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
 109      *  < 0, set by the current instruction.
 110      */
 111     int8_t btype;
 112     /* A copy of cpu->dcz_blocksize. */
 113     uint8_t dcz_blocksize;
 114     /* True if this page is guarded.  */
 115     bool guarded_page;
 116     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
 117     int c15_cpar;
 118     /* TCG op of the current insn_start.  */
 119     TCGOp *insn_start;
 120 #define TMP_A64_MAX 16
 121     int tmp_a64_count;
 122     TCGv_i64 tmp_a64[TMP_A64_MAX];
 123 } DisasContext;
 124
 125 typedef struct DisasCompare {
 126     TCGCond cond;
 127     TCGv_i32 value;
 128     bool value_global;
 129 } DisasCompare;
 130
 131 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
 132 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
 133 extern TCGv_i64 cpu_exclusive_addr;
 134 extern TCGv_i64 cpu_exclusive_val;
 135
 136 /*
 137  * Constant expanders for the decoders.
 138  */
 139
 140 static inline int negate(DisasContext *s, int x)
 141 {
 142     return -x;
 143 }
 144
 145 static inline int plus_1(DisasContext *s, int x)
 146 {
 147     return x + 1;
 148 }
 149
 150 static inline int plus_2(DisasContext *s, int x)
 151 {
 152     return x + 2;
 153 }
 154
 155 static inline int times_2(DisasContext *s, int x)
 156 {
 157     return x * 2;
 158 }
 159
 160 static inline int times_4(DisasContext *s, int x)
 161 {
 162     return x * 4;
 163 }
 164
 165 static inline int times_2_plus_1(DisasContext *s, int x)
 166 {
 167     return x * 2 + 1;
 168 }
 169
 170 static inline int rsub_64(DisasContext *s, int x)
 171 {
 172     return 64 - x;
 173 }
 174
 175 static inline int rsub_32(DisasContext *s, int x)
 176 {
 177     return 32 - x;
 178 }
 179
 180 static inline int rsub_16(DisasContext *s, int x)
 181 {
 182     return 16 - x;
 183 }
 184
 185 static inline int rsub_8(DisasContext *s, int x)
 186 {
 187     return 8 - x;
 188 }
 189
 190 static inline int neon_3same_fp_size(DisasContext *s, int x)
 191 {
 192     /* Convert 0==fp32, 1==fp16 into a MO_* value */
 193     return MO_32 - x;
 194 }
 195
 196 static inline int arm_dc_feature(DisasContext *dc, int feature)
 197 {
 198     return (dc->features & (1ULL << feature)) != 0;
 199 }
 200
 201 static inline int get_mem_index(DisasContext *s)
 202 {
 203     return arm_to_core_mmu_idx(s->mmu_idx);
 204 }
 205
 206 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 207 {
 208     /* We don't need to save all of the syndrome so we mask and shift
 209      * out unneeded bits to help the sleb128 encoder do a better job.
 210      */
 211     syn &= ARM_INSN_START_WORD2_MASK;
 212     syn >>= ARM_INSN_START_WORD2_SHIFT;
 213
 214     /* We check and clear insn_start_idx to catch multiple updates.  */
 215     assert(s->insn_start != NULL);
 216     tcg_set_insn_start_param(s->insn_start, 2, syn);
 217     s->insn_start = NULL;
 218 }
 219
 220 /* is_jmp field values */
 221 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 222 /* CPU state was modified dynamically; exit to main loop for interrupts. */
 223 #define DISAS_UPDATE_EXIT  DISAS_TARGET_1
 224 /* These instructions trap after executing, so the A32/T32 decoder must
 225  * defer them until after the conditional execution state has been updated.
 226  * WFI also needs special handling when single-stepping.
 227  */
 228 #define DISAS_WFI       DISAS_TARGET_2
 229 #define DISAS_SWI       DISAS_TARGET_3
 230 /* WFE */
 231 #define DISAS_WFE       DISAS_TARGET_4
 232 #define DISAS_HVC       DISAS_TARGET_5
 233 #define DISAS_SMC       DISAS_TARGET_6
 234 #define DISAS_YIELD     DISAS_TARGET_7
 235 /* M profile branch which might be an exception return (and so needs
 236  * custom end-of-TB code)
 237  */
 238 #define DISAS_BX_EXCRET DISAS_TARGET_8
 239 /*
 240  * For instructions which want an immediate exit to the main loop, as opposed
 241  * to attempting to use lookup_and_goto_ptr.  Unlike DISAS_UPDATE_EXIT, this
 242  * doesn't write the PC on exiting the translation loop so you need to ensure
 243  * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
 244  * return from cpu_tb_exec.
 245  */
 246 #define DISAS_EXIT      DISAS_TARGET_9
 247 /* CPU state was modified dynamically; no need to exit, but do not chain. */
 248 #define DISAS_UPDATE_NOCHAIN  DISAS_TARGET_10
 249
 250 #ifdef TARGET_AARCH64
 251 void a64_translate_init(void);
 252 void gen_a64_set_pc_im(uint64_t val);
 253 extern const TranslatorOps aarch64_translator_ops;
 254 #else
 255 static inline void a64_translate_init(void)
 256 {
 257 }
 258
 259 static inline void gen_a64_set_pc_im(uint64_t val)
 260 {
 261 }
 262 #endif
 263
 264 void arm_test_cc(DisasCompare *cmp, int cc);
 265 void arm_free_cc(DisasCompare *cmp);
 266 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 267 void arm_gen_test_cc(int cc, TCGLabel *label);
 268 MemOp pow2_align(unsigned i);
 269 void unallocated_encoding(DisasContext *s);
 270 void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
 271                            uint32_t syn, uint32_t target_el);
 272 void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn);
 273
 274 /* Return state of Alternate Half-precision flag, caller frees result */
 275 static inline TCGv_i32 get_ahp_flag(void)
 276 {
 277     TCGv_i32 ret = tcg_temp_new_i32();
 278
 279     tcg_gen_ld_i32(ret, cpu_env,
 280                    offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
 281     tcg_gen_extract_i32(ret, ret, 26, 1);
 282
 283     return ret;
 284 }
 285
 286 /* Set bits within PSTATE.  */
 287 static inline void set_pstate_bits(uint32_t bits)
 288 {
 289     TCGv_i32 p = tcg_temp_new_i32();
 290
 291     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 292
 293     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 294     tcg_gen_ori_i32(p, p, bits);
 295     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 296     tcg_temp_free_i32(p);
 297 }
 298
 299 /* Clear bits within PSTATE.  */
 300 static inline void clear_pstate_bits(uint32_t bits)
 301 {
 302     TCGv_i32 p = tcg_temp_new_i32();
 303
 304     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 305
 306     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 307     tcg_gen_andi_i32(p, p, ~bits);
 308     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 309     tcg_temp_free_i32(p);
 310 }
 311
 312 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
 313 static inline void gen_ss_advance(DisasContext *s)
 314 {
 315     if (s->ss_active) {
 316         s->pstate_ss = 0;
 317         clear_pstate_bits(PSTATE_SS);
 318     }
 319 }
 320
 321 /* Generate an architectural singlestep exception */
 322 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
 323 {
 324     /* Fill in the same_el field of the syndrome in the helper. */
 325     uint32_t syn = syn_swstep(false, isv, ex);
 326     gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn));
 327 }
 328
 329 /*
 330  * Given a VFP floating point constant encoded into an 8 bit immediate in an
 331  * instruction, expand it to the actual constant value of the specified
 332  * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
 333  */
 334 uint64_t vfp_expand_imm(int size, uint8_t imm8);
 335
 336 /* Vector operations shared between ARM and AArch64.  */
 337 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 338                    uint32_t opr_sz, uint32_t max_sz);
 339 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 340                    uint32_t opr_sz, uint32_t max_sz);
 341 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 342                    uint32_t opr_sz, uint32_t max_sz);
 343 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 344                    uint32_t opr_sz, uint32_t max_sz);
 345 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 346                    uint32_t opr_sz, uint32_t max_sz);
 347
 348 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 349                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 350 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 351                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 352
 353 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 354                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 355 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 356                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 357 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 358                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 359
 360 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 361 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
 362 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
 363 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 364 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 365
 366 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 367                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 368 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 369                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 370 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 371                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 372 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 373                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 374
 375 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 376                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 377 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 378                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 379
 380 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 381                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 382 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 383                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 384 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 385                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 386 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 387                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 388
 389 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 390                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 391 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 392                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 393
 394 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 395                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 396 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 397                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 398
 399 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 400                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 401 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 402                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 403
 404 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 405                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 406 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 407                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 408
 409 /*
 410  * Forward to the isar_feature_* tests given a DisasContext pointer.
 411  */
 412 #define dc_isar_feature(name, ctx) \
 413     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 414
 415 /* Note that the gvec expanders operate on offsets + sizes.  */
 416 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
 417 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
 418                          uint32_t, uint32_t);
 419 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
 420                         uint32_t, uint32_t, uint32_t);
 421 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
 422                         uint32_t, uint32_t, uint32_t);
 423
 424 /* Function prototype for gen_ functions for calling Neon helpers */
 425 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
 426 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
 427 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
 428 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
 429 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
 430                                  TCGv_i32, TCGv_i32);
 431 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
 432 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
 433 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
 434 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
 435 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
 436 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
 437 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
 438 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
 439 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
 440 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
 441 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
 442 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 443 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 444 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 445 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
 446 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 447 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
 448 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
 449
 450 /**
 451  * arm_tbflags_from_tb:
 452  * @tb: the TranslationBlock
 453  *
 454  * Extract the flag values from @tb.
 455  */
 456 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
 457 {
 458     return (CPUARMTBFlags){ tb->flags, tb->cs_base };
 459 }
 460
 461 /*
 462  * Enum for argument to fpstatus_ptr().
 463  */
 464 typedef enum ARMFPStatusFlavour {
 465     FPST_FPCR,
 466     FPST_FPCR_F16,
 467     FPST_STD,
 468     FPST_STD_F16,
 469 } ARMFPStatusFlavour;
 470
 471 /**
 472  * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
 473  *
 474  * We have multiple softfloat float_status fields in the Arm CPU state struct
 475  * (see the comment in cpu.h for details). Return a TCGv_ptr which has
 476  * been set up to point to the requested field in the CPU state struct.
 477  * The options are:
 478  *
 479  * FPST_FPCR
 480  *   for non-FP16 operations controlled by the FPCR
 481  * FPST_FPCR_F16
 482  *   for operations controlled by the FPCR where FPCR.FZ16 is to be used
 483  * FPST_STD
 484  *   for A32/T32 Neon operations using the "standard FPSCR value"
 485  * FPST_STD_F16
 486  *   as FPST_STD, but where FPCR.FZ16 is to be used
 487  */
 488 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
 489 {
 490     TCGv_ptr statusptr = tcg_temp_new_ptr();
 491     int offset;
 492
 493     switch (flavour) {
 494     case FPST_FPCR:
 495         offset = offsetof(CPUARMState, vfp.fp_status);
 496         break;
 497     case FPST_FPCR_F16:
 498         offset = offsetof(CPUARMState, vfp.fp_status_f16);
 499         break;
 500     case FPST_STD:
 501         offset = offsetof(CPUARMState, vfp.standard_fp_status);
 502         break;
 503     case FPST_STD_F16:
 504         offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
 505         break;
 506     default:
 507         g_assert_not_reached();
 508     }
 509     tcg_gen_addi_ptr(statusptr, cpu_env, offset);
 510     return statusptr;
 511 }
 512
 513 /**
 514  * finalize_memop:
 515  * @s: DisasContext
 516  * @opc: size+sign+align of the memory operation
 517  *
 518  * Build the complete MemOp for a memory operation, including alignment
 519  * and endianness.
 520  *
 521  * If (op & MO_AMASK) then the operation already contains the required
 522  * alignment, e.g. for AccType_ATOMIC.  Otherwise, this an optionally
 523  * unaligned operation, e.g. for AccType_NORMAL.
 524  *
 525  * In the latter case, there are configuration bits that require alignment,
 526  * and this is applied here.  Note that there is no way to indicate that
 527  * no alignment should ever be enforced; this must be handled manually.
 528  */
 529 static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
 530 {
 531     if (s->align_mem && !(opc & MO_AMASK)) {
 532         opc |= MO_ALIGN;
 533     }
 534     return opc | s->be_data;
 535 }
 536
 537 /**
 538  * asimd_imm_const: Expand an encoded SIMD constant value
 539  *
 540  * Expand a SIMD constant value. This is essentially the pseudocode
 541  * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
 542  * VMVN and VBIC (when cmode < 14 && op == 1).
 543  *
 544  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
 545  * callers must catch this; we return the 64-bit constant value defined
 546  * for AArch64.
 547  *
 548  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
 549  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 550  * we produce an immediate constant value of 0 in these cases.
 551  */
 552 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
 553
 554 /*
 555  * Helpers for implementing sets of trans_* functions.
 556  * Defer the implementation of NAME to FUNC, with optional extra arguments.
 557  */
 558 #define TRANS(NAME, FUNC, ...) \
 559     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
 560     { return FUNC(s, __VA_ARGS__); }
 561 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
 562     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
 563     { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
 564
 565 #endif /* TARGET_ARM_TRANSLATE_H */