tests: Test IPv6 and ppc64 in the PXE tester
[qemu/rayw.git] / target-lm32 / cpu-qom.h
blobb423d2564b53822b81489775cdadfe3628c74993
1 /*
2 * QEMU LatticeMico32 CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 #ifndef QEMU_LM32_CPU_QOM_H
21 #define QEMU_LM32_CPU_QOM_H
23 #include "qom/cpu.h"
25 #define TYPE_LM32_CPU "lm32-cpu"
27 #define LM32_CPU_CLASS(klass) \
28 OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU)
29 #define LM32_CPU(obj) \
30 OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU)
31 #define LM32_CPU_GET_CLASS(obj) \
32 OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU)
34 /**
35 * LM32CPUClass:
36 * @parent_realize: The parent class' realize handler.
37 * @parent_reset: The parent class' reset handler.
39 * A LatticeMico32 CPU model.
41 typedef struct LM32CPUClass {
42 /*< private >*/
43 CPUClass parent_class;
44 /*< public >*/
46 DeviceRealize parent_realize;
47 void (*parent_reset)(CPUState *cpu);
48 } LM32CPUClass;
50 typedef struct LM32CPU LM32CPU;
52 #endif