hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu/datadir.h"
  27 #include "cpu.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/arm/boot.h"
  30 #include "hw/arm/primecell.h"
  31 #include "hw/net/lan9118.h"
  32 #include "hw/i2c/i2c.h"
  33 #include "net/net.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/boards.h"
  36 #include "hw/loader.h"
  37 #include "hw/block/flash.h"
  38 #include "sysemu/device_tree.h"
  39 #include "qemu/error-report.h"
  40 #include <libfdt.h>
  41 #include "hw/char/pl011.h"
  42 #include "hw/cpu/a9mpcore.h"
  43 #include "hw/cpu/a15mpcore.h"
  44 #include "hw/i2c/arm_sbcon_i2c.h"
  45 #include "hw/sd/sd.h"
  46 #include "qom/object.h"
  47
  48 #define VEXPRESS_BOARD_ID 0x8e0
  49 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  50 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  51
  52 /* Number of virtio transports to create (0..8; limited by
  53  * number of available IRQ lines).
  54  */
  55 #define NUM_VIRTIO_TRANSPORTS 4
  56
  57 /* Address maps for peripherals:
  58  * the Versatile Express motherboard has two possible maps,
  59  * the "legacy" one (used for A9) and the "Cortex-A Series"
  60  * map (used for newer cores).
  61  * Individual daughterboards can also have different maps for
  62  * their peripherals.
  63  */
  64
  65 enum {
  66     VE_SYSREGS,
  67     VE_SP810,
  68     VE_SERIALPCI,
  69     VE_PL041,
  70     VE_MMCI,
  71     VE_KMI0,
  72     VE_KMI1,
  73     VE_UART0,
  74     VE_UART1,
  75     VE_UART2,
  76     VE_UART3,
  77     VE_WDT,
  78     VE_TIMER01,
  79     VE_TIMER23,
  80     VE_SERIALDVI,
  81     VE_RTC,
  82     VE_COMPACTFLASH,
  83     VE_CLCD,
  84     VE_NORFLASH0,
  85     VE_NORFLASH1,
  86     VE_NORFLASHALIAS,
  87     VE_SRAM,
  88     VE_VIDEORAM,
  89     VE_ETHERNET,
  90     VE_USB,
  91     VE_DAPROM,
  92     VE_VIRTIO,
  93 };
  94
  95 static hwaddr motherboard_legacy_map[] = {
  96     [VE_NORFLASHALIAS] = 0,
  97     /* CS7: 0x10000000 .. 0x10020000 */
  98     [VE_SYSREGS] = 0x10000000,
  99     [VE_SP810] = 0x10001000,
 100     [VE_SERIALPCI] = 0x10002000,
 101     [VE_PL041] = 0x10004000,
 102     [VE_MMCI] = 0x10005000,
 103     [VE_KMI0] = 0x10006000,
 104     [VE_KMI1] = 0x10007000,
 105     [VE_UART0] = 0x10009000,
 106     [VE_UART1] = 0x1000a000,
 107     [VE_UART2] = 0x1000b000,
 108     [VE_UART3] = 0x1000c000,
 109     [VE_WDT] = 0x1000f000,
 110     [VE_TIMER01] = 0x10011000,
 111     [VE_TIMER23] = 0x10012000,
 112     [VE_VIRTIO] = 0x10013000,
 113     [VE_SERIALDVI] = 0x10016000,
 114     [VE_RTC] = 0x10017000,
 115     [VE_COMPACTFLASH] = 0x1001a000,
 116     [VE_CLCD] = 0x1001f000,
 117     /* CS0: 0x40000000 .. 0x44000000 */
 118     [VE_NORFLASH0] = 0x40000000,
 119     /* CS1: 0x44000000 .. 0x48000000 */
 120     [VE_NORFLASH1] = 0x44000000,
 121     /* CS2: 0x48000000 .. 0x4a000000 */
 122     [VE_SRAM] = 0x48000000,
 123     /* CS3: 0x4c000000 .. 0x50000000 */
 124     [VE_VIDEORAM] = 0x4c000000,
 125     [VE_ETHERNET] = 0x4e000000,
 126     [VE_USB] = 0x4f000000,
 127 };
 128
 129 static hwaddr motherboard_aseries_map[] = {
 130     [VE_NORFLASHALIAS] = 0,
 131     /* CS0: 0x08000000 .. 0x0c000000 */
 132     [VE_NORFLASH0] = 0x08000000,
 133     /* CS4: 0x0c000000 .. 0x10000000 */
 134     [VE_NORFLASH1] = 0x0c000000,
 135     /* CS5: 0x10000000 .. 0x14000000 */
 136     /* CS1: 0x14000000 .. 0x18000000 */
 137     [VE_SRAM] = 0x14000000,
 138     /* CS2: 0x18000000 .. 0x1c000000 */
 139     [VE_VIDEORAM] = 0x18000000,
 140     [VE_ETHERNET] = 0x1a000000,
 141     [VE_USB] = 0x1b000000,
 142     /* CS3: 0x1c000000 .. 0x20000000 */
 143     [VE_DAPROM] = 0x1c000000,
 144     [VE_SYSREGS] = 0x1c010000,
 145     [VE_SP810] = 0x1c020000,
 146     [VE_SERIALPCI] = 0x1c030000,
 147     [VE_PL041] = 0x1c040000,
 148     [VE_MMCI] = 0x1c050000,
 149     [VE_KMI0] = 0x1c060000,
 150     [VE_KMI1] = 0x1c070000,
 151     [VE_UART0] = 0x1c090000,
 152     [VE_UART1] = 0x1c0a0000,
 153     [VE_UART2] = 0x1c0b0000,
 154     [VE_UART3] = 0x1c0c0000,
 155     [VE_WDT] = 0x1c0f0000,
 156     [VE_TIMER01] = 0x1c110000,
 157     [VE_TIMER23] = 0x1c120000,
 158     [VE_VIRTIO] = 0x1c130000,
 159     [VE_SERIALDVI] = 0x1c160000,
 160     [VE_RTC] = 0x1c170000,
 161     [VE_COMPACTFLASH] = 0x1c1a0000,
 162     [VE_CLCD] = 0x1c1f0000,
 163 };
 164
 165 /* Structure defining the peculiarities of a specific daughterboard */
 166
 167 typedef struct VEDBoardInfo VEDBoardInfo;
 168
 169 struct VexpressMachineClass {
 170     MachineClass parent;
 171     VEDBoardInfo *daughterboard;
 172 };
 173
 174 struct VexpressMachineState {
 175     MachineState parent;
 176     bool secure;
 177     bool virt;
 178 };
 179
 180 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 181 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 182 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 183 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
 184
 185 typedef void DBoardInitFn(const VexpressMachineState *machine,
 186                           ram_addr_t ram_size,
 187                           const char *cpu_type,
 188                           qemu_irq *pic);
 189
 190 struct VEDBoardInfo {
 191     struct arm_boot_info bootinfo;
 192     const hwaddr *motherboard_map;
 193     hwaddr loader_start;
 194     const hwaddr gic_cpu_if_addr;
 195     uint32_t proc_id;
 196     uint32_t num_voltage_sensors;
 197     const uint32_t *voltages;
 198     uint32_t num_clocks;
 199     const uint32_t *clocks;
 200     DBoardInitFn *init;
 201 };
 202
 203 static void init_cpus(MachineState *ms, const char *cpu_type,
 204                       const char *privdev, hwaddr periphbase,
 205                       qemu_irq *pic, bool secure, bool virt)
 206 {
 207     DeviceState *dev;
 208     SysBusDevice *busdev;
 209     int n;
 210     unsigned int smp_cpus = ms->smp.cpus;
 211
 212     /* Create the actual CPUs */
 213     for (n = 0; n < smp_cpus; n++) {
 214         Object *cpuobj = object_new(cpu_type);
 215
 216         if (!secure) {
 217             object_property_set_bool(cpuobj, "has_el3", false, NULL);
 218         }
 219         if (!virt) {
 220             if (object_property_find(cpuobj, "has_el2")) {
 221                 object_property_set_bool(cpuobj, "has_el2", false, NULL);
 222             }
 223         }
 224
 225         if (object_property_find(cpuobj, "reset-cbar")) {
 226             object_property_set_int(cpuobj, "reset-cbar", periphbase,
 227                                     &error_abort);
 228         }
 229         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 230     }
 231
 232     /* Create the private peripheral devices (including the GIC);
 233      * this must happen after the CPUs are created because a15mpcore_priv
 234      * wires itself up to the CPU's generic_timer gpio out lines.
 235      */
 236     dev = qdev_new(privdev);
 237     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 238     busdev = SYS_BUS_DEVICE(dev);
 239     sysbus_realize_and_unref(busdev, &error_fatal);
 240     sysbus_mmio_map(busdev, 0, periphbase);
 241
 242     /* Interrupts [42:0] are from the motherboard;
 243      * [47:43] are reserved; [63:48] are daughterboard
 244      * peripherals. Note that some documentation numbers
 245      * external interrupts starting from 32 (because there
 246      * are internal interrupts 0..31).
 247      */
 248     for (n = 0; n < 64; n++) {
 249         pic[n] = qdev_get_gpio_in(dev, n);
 250     }
 251
 252     /* Connect the CPUs to the GIC */
 253     for (n = 0; n < smp_cpus; n++) {
 254         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 255
 256         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 257         sysbus_connect_irq(busdev, n + smp_cpus,
 258                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 259         sysbus_connect_irq(busdev, n + 2 * smp_cpus,
 260                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 261         sysbus_connect_irq(busdev, n + 3 * smp_cpus,
 262                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 263     }
 264 }
 265
 266 static void a9_daughterboard_init(const VexpressMachineState *vms,
 267                                   ram_addr_t ram_size,
 268                                   const char *cpu_type,
 269                                   qemu_irq *pic)
 270 {
 271     MachineState *machine = MACHINE(vms);
 272     MemoryRegion *sysmem = get_system_memory();
 273     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 274     ram_addr_t low_ram_size;
 275
 276     if (ram_size > 0x40000000) {
 277         /* 1GB is the maximum the address space permits */
 278         error_report("vexpress-a9: cannot model more than 1GB RAM");
 279         exit(1);
 280     }
 281
 282     low_ram_size = ram_size;
 283     if (low_ram_size > 0x4000000) {
 284         low_ram_size = 0x4000000;
 285     }
 286     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 287      * address space should in theory be remappable to various
 288      * things including ROM or RAM; we always map the RAM there.
 289      */
 290     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram,
 291                              0, low_ram_size);
 292     memory_region_add_subregion(sysmem, 0x0, lowram);
 293     memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
 294
 295     /* 0x1e000000 A9MPCore (SCU) private memory region */
 296     init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
 297               vms->secure, vms->virt);
 298
 299     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 300
 301     /* 0x10020000 PL111 CLCD (daughterboard) */
 302     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 303
 304     /* 0x10060000 AXI RAM */
 305     /* 0x100e0000 PL341 Dynamic Memory Controller */
 306     /* 0x100e1000 PL354 Static Memory Controller */
 307     /* 0x100e2000 System Configuration Controller */
 308
 309     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 310     /* 0x100e5000 SP805 Watchdog module */
 311     /* 0x100e6000 BP147 TrustZone Protection Controller */
 312     /* 0x100e9000 PL301 'Fast' AXI matrix */
 313     /* 0x100ea000 PL301 'Slow' AXI matrix */
 314     /* 0x100ec000 TrustZone Address Space Controller */
 315     /* 0x10200000 CoreSight debug APB */
 316     /* 0x1e00a000 PL310 L2 Cache Controller */
 317     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 318 }
 319
 320 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 321  * values are in microvolts.
 322  */
 323 static const uint32_t a9_voltages[] = {
 324     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 325     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 326     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 327     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 328     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 329     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 330 };
 331
 332 /* Reset values for daughterboard oscillators (in Hz) */
 333 static const uint32_t a9_clocks[] = {
 334     45000000, /* AMBA AXI ACLK: 45MHz */
 335     23750000, /* daughterboard CLCD clock: 23.75MHz */
 336     66670000, /* Test chip reference clock: 66.67MHz */
 337 };
 338
 339 static VEDBoardInfo a9_daughterboard = {
 340     .motherboard_map = motherboard_legacy_map,
 341     .loader_start = 0x60000000,
 342     .gic_cpu_if_addr = 0x1e000100,
 343     .proc_id = 0x0c000191,
 344     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 345     .voltages = a9_voltages,
 346     .num_clocks = ARRAY_SIZE(a9_clocks),
 347     .clocks = a9_clocks,
 348     .init = a9_daughterboard_init,
 349 };
 350
 351 static void a15_daughterboard_init(const VexpressMachineState *vms,
 352                                    ram_addr_t ram_size,
 353                                    const char *cpu_type,
 354                                    qemu_irq *pic)
 355 {
 356     MachineState *machine = MACHINE(vms);
 357     MemoryRegion *sysmem = get_system_memory();
 358     MemoryRegion *sram = g_new(MemoryRegion, 1);
 359
 360     {
 361         /* We have to use a separate 64 bit variable here to avoid the gcc
 362          * "comparison is always false due to limited range of data type"
 363          * warning if we are on a host where ram_addr_t is 32 bits.
 364          */
 365         uint64_t rsz = ram_size;
 366         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 367             error_report("vexpress-a15: cannot model more than 30GB RAM");
 368             exit(1);
 369         }
 370     }
 371
 372     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 373     memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
 374
 375     /* 0x2c000000 A15MPCore private memory region (GIC) */
 376     init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
 377               0x2c000000, pic, vms->secure, vms->virt);
 378
 379     /* A15 daughterboard peripherals: */
 380
 381     /* 0x20000000: CoreSight interfaces: not modelled */
 382     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 383     /* 0x2a420000: SCC: not modelled */
 384     /* 0x2a430000: system counter: not modelled */
 385     /* 0x2b000000: HDLCD controller: not modelled */
 386     /* 0x2b060000: SP805 watchdog: not modelled */
 387     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 388     /* 0x2e000000: system SRAM */
 389     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 390                            &error_fatal);
 391     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 392
 393     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 394     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 395 }
 396
 397 static const uint32_t a15_voltages[] = {
 398     900000, /* Vcore: 0.9V : CPU core voltage */
 399 };
 400
 401 static const uint32_t a15_clocks[] = {
 402     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 403     0, /* OSCCLK1: reserved */
 404     0, /* OSCCLK2: reserved */
 405     0, /* OSCCLK3: reserved */
 406     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 407     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 408     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 409     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 410     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 411 };
 412
 413 static VEDBoardInfo a15_daughterboard = {
 414     .motherboard_map = motherboard_aseries_map,
 415     .loader_start = 0x80000000,
 416     .gic_cpu_if_addr = 0x2c002000,
 417     .proc_id = 0x14000237,
 418     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 419     .voltages = a15_voltages,
 420     .num_clocks = ARRAY_SIZE(a15_clocks),
 421     .clocks = a15_clocks,
 422     .init = a15_daughterboard_init,
 423 };
 424
 425 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 426                                 hwaddr addr, hwaddr size, uint32_t intc,
 427                                 int irq)
 428 {
 429     /* Add a virtio_mmio node to the device tree blob:
 430      *   virtio_mmio@ADDRESS {
 431      *       compatible = "virtio,mmio";
 432      *       reg = <ADDRESS, SIZE>;
 433      *       interrupt-parent = <&intc>;
 434      *       interrupts = <0, irq, 1>;
 435      *   }
 436      * (Note that the format of the interrupts property is dependent on the
 437      * interrupt controller that interrupt-parent points to; these are for
 438      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 439      */
 440     int rc;
 441     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 442
 443     rc = qemu_fdt_add_subnode(fdt, nodename);
 444     rc |= qemu_fdt_setprop_string(fdt, nodename,
 445                                   "compatible", "virtio,mmio");
 446     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 447                                        acells, addr, scells, size);
 448     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 449     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 450     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 451     g_free(nodename);
 452     if (rc) {
 453         return -1;
 454     }
 455     return 0;
 456 }
 457
 458 static uint32_t find_int_controller(void *fdt)
 459 {
 460     /* Find the FDT node corresponding to the interrupt controller
 461      * for virtio-mmio devices. We do this by scanning the fdt for
 462      * a node with the right compatibility, since we know there is
 463      * only one GIC on a vexpress board.
 464      * We return the phandle of the node, or 0 if none was found.
 465      */
 466     const char *compat = "arm,cortex-a9-gic";
 467     int offset;
 468
 469     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 470     if (offset >= 0) {
 471         return fdt_get_phandle(fdt, offset);
 472     }
 473     return 0;
 474 }
 475
 476 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 477 {
 478     uint32_t acells, scells, intc;
 479     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 480
 481     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 482                                    NULL, &error_fatal);
 483     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 484                                    NULL, &error_fatal);
 485     intc = find_int_controller(fdt);
 486     if (!intc) {
 487         /* Not fatal, we just won't provide virtio. This will
 488          * happen with older device tree blobs.
 489          */
 490         warn_report("couldn't find interrupt controller in "
 491                     "dtb; will not include virtio-mmio devices in the dtb");
 492     } else {
 493         int i;
 494         const hwaddr *map = daughterboard->motherboard_map;
 495
 496         /* We iterate backwards here because adding nodes
 497          * to the dtb puts them in last-first.
 498          */
 499         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 500             add_virtio_mmio_node(fdt, acells, scells,
 501                                  map[VE_VIRTIO] + 0x200 * i,
 502                                  0x200, intc, 40 + i);
 503         }
 504     }
 505 }
 506
 507
 508 /* Open code a private version of pflash registration since we
 509  * need to set non-default device width for VExpress platform.
 510  */
 511 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
 512                                              DriveInfo *di)
 513 {
 514     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 515
 516     if (di) {
 517         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
 518     }
 519
 520     qdev_prop_set_uint32(dev, "num-blocks",
 521                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 522     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 523     qdev_prop_set_uint8(dev, "width", 4);
 524     qdev_prop_set_uint8(dev, "device-width", 2);
 525     qdev_prop_set_bit(dev, "big-endian", false);
 526     qdev_prop_set_uint16(dev, "id0", 0x89);
 527     qdev_prop_set_uint16(dev, "id1", 0x18);
 528     qdev_prop_set_uint16(dev, "id2", 0x00);
 529     qdev_prop_set_uint16(dev, "id3", 0x00);
 530     qdev_prop_set_string(dev, "name", name);
 531     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 532
 533     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 534     return PFLASH_CFI01(dev);
 535 }
 536
 537 static void vexpress_common_init(MachineState *machine)
 538 {
 539     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 540     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 541     VEDBoardInfo *daughterboard = vmc->daughterboard;
 542     DeviceState *dev, *sysctl, *pl041;
 543     qemu_irq pic[64];
 544     uint32_t sys_id;
 545     DriveInfo *dinfo;
 546     PFlashCFI01 *pflash0;
 547     I2CBus *i2c;
 548     ram_addr_t vram_size, sram_size;
 549     MemoryRegion *sysmem = get_system_memory();
 550     MemoryRegion *vram = g_new(MemoryRegion, 1);
 551     MemoryRegion *sram = g_new(MemoryRegion, 1);
 552     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 553     MemoryRegion *flash0mem;
 554     const hwaddr *map = daughterboard->motherboard_map;
 555     int i;
 556
 557     daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
 558
 559     /*
 560      * If a bios file was provided, attempt to map it into memory
 561      */
 562     if (machine->firmware) {
 563         char *fn;
 564         int image_size;
 565
 566         if (drive_get(IF_PFLASH, 0, 0)) {
 567             error_report("The contents of the first flash device may be "
 568                          "specified with -bios or with -drive if=pflash... "
 569                          "but you cannot use both options at once");
 570             exit(1);
 571         }
 572         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
 573         if (!fn) {
 574             error_report("Could not find ROM image '%s'", machine->firmware);
 575             exit(1);
 576         }
 577         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 578                                          VEXPRESS_FLASH_SIZE);
 579         g_free(fn);
 580         if (image_size < 0) {
 581             error_report("Could not load ROM image '%s'", machine->firmware);
 582             exit(1);
 583         }
 584     }
 585
 586     /* Motherboard peripherals: the wiring is the same but the
 587      * addresses vary between the legacy and A-Series memory maps.
 588      */
 589
 590     sys_id = 0x1190f500;
 591
 592     sysctl = qdev_new("realview_sysctl");
 593     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 594     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 595     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 596                          daughterboard->num_voltage_sensors);
 597     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 598         char *propname = g_strdup_printf("db-voltage[%d]", i);
 599         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 600         g_free(propname);
 601     }
 602     qdev_prop_set_uint32(sysctl, "len-db-clock",
 603                          daughterboard->num_clocks);
 604     for (i = 0; i < daughterboard->num_clocks; i++) {
 605         char *propname = g_strdup_printf("db-clock[%d]", i);
 606         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 607         g_free(propname);
 608     }
 609     sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
 610     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 611
 612     /* VE_SP810: not modelled */
 613     /* VE_SERIALPCI: not modelled */
 614
 615     pl041 = qdev_new("pl041");
 616     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 617     sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
 618     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 619     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 620
 621     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 622     /* Wire up MMC card detect and read-only signals */
 623     qdev_connect_gpio_out_named(dev, "card-read-only", 0,
 624                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 625     qdev_connect_gpio_out_named(dev, "card-inserted", 0,
 626                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 627     dinfo = drive_get(IF_SD, 0, 0);
 628     if (dinfo) {
 629         DeviceState *card;
 630
 631         card = qdev_new(TYPE_SD_CARD);
 632         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 633                                 &error_fatal);
 634         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
 635                                &error_fatal);
 636     }
 637
 638     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 639     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 640
 641     pl011_create(map[VE_UART0], pic[5], serial_hd(0));
 642     pl011_create(map[VE_UART1], pic[6], serial_hd(1));
 643     pl011_create(map[VE_UART2], pic[7], serial_hd(2));
 644     pl011_create(map[VE_UART3], pic[8], serial_hd(3));
 645
 646     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 647     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 648
 649     dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
 650     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 651     i2c_slave_create_simple(i2c, "sii9022", 0x39);
 652
 653     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 654
 655     /* VE_COMPACTFLASH: not modelled */
 656
 657     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 658
 659     dinfo = drive_get(IF_PFLASH, 0, 0);
 660     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 661                                        dinfo);
 662     if (!pflash0) {
 663         error_report("vexpress: error registering flash 0");
 664         exit(1);
 665     }
 666
 667     if (map[VE_NORFLASHALIAS] != -1) {
 668         /* Map flash 0 as an alias into low memory */
 669         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 670         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 671                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 672         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 673     }
 674
 675     dinfo = drive_get(IF_PFLASH, 0, 1);
 676     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 677                                   dinfo)) {
 678         error_report("vexpress: error registering flash 1");
 679         exit(1);
 680     }
 681
 682     sram_size = 0x2000000;
 683     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 684                            &error_fatal);
 685     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 686
 687     vram_size = 0x800000;
 688     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 689                            &error_fatal);
 690     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 691
 692     /* 0x4e000000 LAN9118 Ethernet */
 693     if (nd_table[0].used) {
 694         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 695     }
 696
 697     /* VE_USB: not modelled */
 698
 699     /* VE_DAPROM: not modelled */
 700
 701     /* Create mmio transports, so the user can create virtio backends
 702      * (which will be automatically plugged in to the transports). If
 703      * no backend is created the transport will just sit harmlessly idle.
 704      */
 705     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 706         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 707                              pic[40 + i]);
 708     }
 709
 710     daughterboard->bootinfo.ram_size = machine->ram_size;
 711     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 712     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 713     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 714     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 715     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 716     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 717     /* When booting Linux we should be in secure state if the CPU has one. */
 718     daughterboard->bootinfo.secure_boot = vms->secure;
 719     arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
 720 }
 721
 722 static bool vexpress_get_secure(Object *obj, Error **errp)
 723 {
 724     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 725
 726     return vms->secure;
 727 }
 728
 729 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 730 {
 731     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 732
 733     vms->secure = value;
 734 }
 735
 736 static bool vexpress_get_virt(Object *obj, Error **errp)
 737 {
 738     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 739
 740     return vms->virt;
 741 }
 742
 743 static void vexpress_set_virt(Object *obj, bool value, Error **errp)
 744 {
 745     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 746
 747     vms->virt = value;
 748 }
 749
 750 static void vexpress_instance_init(Object *obj)
 751 {
 752     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 753
 754     /* EL3 is enabled by default on vexpress */
 755     vms->secure = true;
 756 }
 757
 758 static void vexpress_a15_instance_init(Object *obj)
 759 {
 760     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 761
 762     /*
 763      * For the vexpress-a15, EL2 is by default enabled if EL3 is,
 764      * but can also be specifically set to on or off.
 765      */
 766     vms->virt = true;
 767 }
 768
 769 static void vexpress_a9_instance_init(Object *obj)
 770 {
 771     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 772
 773     /* The A9 doesn't have the virt extensions */
 774     vms->virt = false;
 775 }
 776
 777 static void vexpress_class_init(ObjectClass *oc, void *data)
 778 {
 779     MachineClass *mc = MACHINE_CLASS(oc);
 780
 781     mc->desc = "ARM Versatile Express";
 782     mc->init = vexpress_common_init;
 783     mc->max_cpus = 4;
 784     mc->ignore_memory_transaction_failures = true;
 785     mc->default_ram_id = "vexpress.highmem";
 786
 787     object_class_property_add_bool(oc, "secure", vexpress_get_secure,
 788                                    vexpress_set_secure);
 789     object_class_property_set_description(oc, "secure",
 790                                           "Set on/off to enable/disable the ARM "
 791                                           "Security Extensions (TrustZone)");
 792 }
 793
 794 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 795 {
 796     MachineClass *mc = MACHINE_CLASS(oc);
 797     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 798
 799     mc->desc = "ARM Versatile Express for Cortex-A9";
 800     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 801
 802     vmc->daughterboard = &a9_daughterboard;
 803 }
 804
 805 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 806 {
 807     MachineClass *mc = MACHINE_CLASS(oc);
 808     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 809
 810     mc->desc = "ARM Versatile Express for Cortex-A15";
 811     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 812
 813     vmc->daughterboard = &a15_daughterboard;
 814
 815     object_class_property_add_bool(oc, "virtualization", vexpress_get_virt,
 816                                    vexpress_set_virt);
 817     object_class_property_set_description(oc, "virtualization",
 818                                           "Set on/off to enable/disable the ARM "
 819                                           "Virtualization Extensions "
 820                                           "(defaults to same as 'secure')");
 821
 822 }
 823
 824 static const TypeInfo vexpress_info = {
 825     .name = TYPE_VEXPRESS_MACHINE,
 826     .parent = TYPE_MACHINE,
 827     .abstract = true,
 828     .instance_size = sizeof(VexpressMachineState),
 829     .instance_init = vexpress_instance_init,
 830     .class_size = sizeof(VexpressMachineClass),
 831     .class_init = vexpress_class_init,
 832 };
 833
 834 static const TypeInfo vexpress_a9_info = {
 835     .name = TYPE_VEXPRESS_A9_MACHINE,
 836     .parent = TYPE_VEXPRESS_MACHINE,
 837     .class_init = vexpress_a9_class_init,
 838     .instance_init = vexpress_a9_instance_init,
 839 };
 840
 841 static const TypeInfo vexpress_a15_info = {
 842     .name = TYPE_VEXPRESS_A15_MACHINE,
 843     .parent = TYPE_VEXPRESS_MACHINE,
 844     .class_init = vexpress_a15_class_init,
 845     .instance_init = vexpress_a15_instance_init,
 846 };
 847
 848 static void vexpress_machine_init(void)
 849 {
 850     type_register_static(&vexpress_info);
 851     type_register_static(&vexpress_a9_info);
 852     type_register_static(&vexpress_a15_info);
 853 }
 854
 855 type_init(vexpress_machine_init);