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Merge tag 'pull-la-20220704' of https://gitlab.com/rth7680/qemu into staging
[qemu/rayw.git] / hw / arm / aspeed_ast10x0.c
blob33ef331771992b49ab731c400b56e7b319650090
1 /*
2 * ASPEED Ast10x0 SoC
3 *
4 * Copyright (C) 2022 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * Implementation extracted from the AST2600 and adapted for Ast10x0.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "exec/address-spaces.h"
15 #include "sysemu/sysemu.h"
16 #include "hw/qdev-clock.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19
20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
21
22 static const hwaddr aspeed_soc_ast1030_memmap[] = {
23 [ASPEED_DEV_SRAM] = 0x00000000,
24 [ASPEED_DEV_SBC] = 0x79000000,
25 [ASPEED_DEV_IOMEM] = 0x7E600000,
26 [ASPEED_DEV_PWM] = 0x7E610000,
27 [ASPEED_DEV_FMC] = 0x7E620000,
28 [ASPEED_DEV_SPI1] = 0x7E630000,
29 [ASPEED_DEV_SPI2] = 0x7E640000,
30 [ASPEED_DEV_SCU] = 0x7E6E2000,
31 [ASPEED_DEV_ADC] = 0x7E6E9000,
32 [ASPEED_DEV_SBC] = 0x7E6F2000,
33 [ASPEED_DEV_GPIO] = 0x7E780000,
34 [ASPEED_DEV_TIMER1] = 0x7E782000,
35 [ASPEED_DEV_UART1] = 0x7E783000,
36 [ASPEED_DEV_UART2] = 0x7E78D000,
37 [ASPEED_DEV_UART3] = 0x7E78E000,
38 [ASPEED_DEV_UART4] = 0x7E78F000,
39 [ASPEED_DEV_UART5] = 0x7E784000,
40 [ASPEED_DEV_UART6] = 0x7E790000,
41 [ASPEED_DEV_UART7] = 0x7E790100,
42 [ASPEED_DEV_UART8] = 0x7E790200,
43 [ASPEED_DEV_UART9] = 0x7E790300,
44 [ASPEED_DEV_UART10] = 0x7E790400,
45 [ASPEED_DEV_UART11] = 0x7E790500,
46 [ASPEED_DEV_UART12] = 0x7E790600,
47 [ASPEED_DEV_UART13] = 0x7E790700,
48 [ASPEED_DEV_WDT] = 0x7E785000,
49 [ASPEED_DEV_LPC] = 0x7E789000,
50 [ASPEED_DEV_PECI] = 0x7E78B000,
51 [ASPEED_DEV_I2C] = 0x7E7B0000,
52 };
53
54 static const int aspeed_soc_ast1030_irqmap[] = {
55 [ASPEED_DEV_UART1] = 47,
56 [ASPEED_DEV_UART2] = 48,
57 [ASPEED_DEV_UART3] = 49,
58 [ASPEED_DEV_UART4] = 50,
59 [ASPEED_DEV_UART5] = 8,
60 [ASPEED_DEV_UART6] = 57,
61 [ASPEED_DEV_UART7] = 58,
62 [ASPEED_DEV_UART8] = 59,
63 [ASPEED_DEV_UART9] = 60,
64 [ASPEED_DEV_UART10] = 61,
65 [ASPEED_DEV_UART11] = 62,
66 [ASPEED_DEV_UART12] = 63,
67 [ASPEED_DEV_UART13] = 64,
68 [ASPEED_DEV_GPIO] = 11,
69 [ASPEED_DEV_TIMER1] = 16,
70 [ASPEED_DEV_TIMER2] = 17,
71 [ASPEED_DEV_TIMER3] = 18,
72 [ASPEED_DEV_TIMER4] = 19,
73 [ASPEED_DEV_TIMER5] = 20,
74 [ASPEED_DEV_TIMER6] = 21,
75 [ASPEED_DEV_TIMER7] = 22,
76 [ASPEED_DEV_TIMER8] = 23,
77 [ASPEED_DEV_WDT] = 24,
78 [ASPEED_DEV_LPC] = 35,
79 [ASPEED_DEV_PECI] = 38,
80 [ASPEED_DEV_FMC] = 39,
81 [ASPEED_DEV_PWM] = 44,
82 [ASPEED_DEV_ADC] = 46,
83 [ASPEED_DEV_SPI1] = 65,
84 [ASPEED_DEV_SPI2] = 66,
85 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
86 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
87 };
88
89 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
90 {
91 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
92
93 return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
94 }
95
96 static void aspeed_soc_ast1030_init(Object *obj)
97 {
98 AspeedSoCState *s = ASPEED_SOC(obj);
99 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
100 char socname[8];
101 char typename[64];
102 int i;
103
104 if (sscanf(sc->name, "%7s", socname) != 1) {
105 g_assert_not_reached();
106 }
107
108 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
109
110 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
111
112 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
113 object_initialize_child(obj, "scu", &s->scu, typename);
114 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
115
116 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
117 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
118
119 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
120 object_initialize_child(obj, "i2c", &s->i2c, typename);
121
122 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
123 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
124
125 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
126 object_initialize_child(obj, "adc", &s->adc, typename);
127
128 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
129 object_initialize_child(obj, "fmc", &s->fmc, typename);
130
131 for (i = 0; i < sc->spis_num; i++) {
132 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
133 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
134 }
135
136 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
137
138 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
139
140 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
141
142 for (i = 0; i < sc->wdts_num; i++) {
143 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
144 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
145 }
146
147 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
148 object_initialize_child(obj, "gpio", &s->gpio, typename);
149
150 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
151 object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
152 TYPE_UNIMPLEMENTED_DEVICE);
153 }
154
155 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
156 {
157 AspeedSoCState *s = ASPEED_SOC(dev_soc);
158 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
159 DeviceState *armv7m;
160 Error *err = NULL;
161 int i;
162
163 if (!clock_has_source(s->sysclk)) {
164 error_setg(errp, "sysclk clock must be wired up by the board code");
165 return;
166 }
167
168 /* General I/O memory space to catch all unimplemented device */
169 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
170 sc->memmap[ASPEED_DEV_IOMEM],
171 ASPEED_SOC_IOMEM_SIZE);
172 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented),
173 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
174 0x40000);
175
176 /* AST1030 CPU Core */
177 armv7m = DEVICE(&s->armv7m);
178 qdev_prop_set_uint32(armv7m, "num-irq", 256);
179 qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
180 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
181 object_property_set_link(OBJECT(&s->armv7m), "memory",
182 OBJECT(s->memory), &error_abort);
183 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
184
185 /* Internal SRAM */
186 memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
187 if (err != NULL) {
188 error_propagate(errp, err);
189 return;
190 }
191 memory_region_add_subregion(s->memory,
192 sc->memmap[ASPEED_DEV_SRAM],
193 &s->sram);
194
195 /* SCU */
196 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
197 return;
198 }
199 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
200
201 /* I2C */
202
203 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
204 &error_abort);
205 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
206 return;
207 }
208 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
209 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
210 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
211 sc->irqmap[ASPEED_DEV_I2C] + i);
212 /* The AST1030 I2C controller has one IRQ per bus. */
213 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
214 }
215
216 /* PECI */
217 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
218 return;
219 }
220 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
221 sc->memmap[ASPEED_DEV_PECI]);
222 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
223 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
224
225 /* LPC */
226 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
227 return;
228 }
229 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
230
231 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
232 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
233 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
234
235 /*
236 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
237 */
238 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
239 qdev_get_gpio_in(DEVICE(&s->armv7m),
240 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
241
242 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
243 qdev_get_gpio_in(DEVICE(&s->armv7m),
244 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
245
246 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
247 qdev_get_gpio_in(DEVICE(&s->armv7m),
248 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
249
250 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
251 qdev_get_gpio_in(DEVICE(&s->armv7m),
252 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
253
254 /* UART */
255 aspeed_soc_uart_init(s);
256
257 /* Timer */
258 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
259 &error_abort);
260 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
261 return;
262 }
263 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
264 sc->memmap[ASPEED_DEV_TIMER1]);
265 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
266 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
267 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
268 }
269
270 /* ADC */
271 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
272 return;
273 }
274 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
275 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
276 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
277
278 /* FMC, The number of CS is set at the board level */
279 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
280 &error_abort);
281 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
282 return;
283 }
284 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
285 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
286 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
287 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
288 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
289
290 /* SPI */
291 for (i = 0; i < sc->spis_num; i++) {
292 object_property_set_link(OBJECT(&s->spi[i]), "dram",
293 OBJECT(&s->sram), &error_abort);
294 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
295 return;
296 }
297 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
298 sc->memmap[ASPEED_DEV_SPI1 + i]);
299 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
300 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
301 }
302
303 /* Secure Boot Controller */
304 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
305 return;
306 }
307 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
308
309 /* Watch dog */
310 for (i = 0; i < sc->wdts_num; i++) {
311 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
312
313 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
314 &error_abort);
315 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
316 return;
317 }
318 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
319 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
320 }
321
322 /* GPIO */
323 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
324 return;
325 }
326 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
327 sc->memmap[ASPEED_DEV_GPIO]);
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
329 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
330 }
331
332 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
333 {
334 DeviceClass *dc = DEVICE_CLASS(klass);
335 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
336
337 dc->realize = aspeed_soc_ast1030_realize;
338
339 sc->name = "ast1030-a1";
340 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
341 sc->silicon_rev = AST1030_A1_SILICON_REV;
342 sc->sram_size = 0xc0000;
343 sc->spis_num = 2;
344 sc->ehcis_num = 0;
345 sc->wdts_num = 4;
346 sc->macs_num = 1;
347 sc->uarts_num = 13;
348 sc->irqmap = aspeed_soc_ast1030_irqmap;
349 sc->memmap = aspeed_soc_ast1030_memmap;
350 sc->num_cpus = 1;
351 sc->get_irq = aspeed_soc_ast1030_get_irq;
352 }
353
354 static const TypeInfo aspeed_soc_ast1030_type_info = {
355 .name = "ast1030-a1",
356 .parent = TYPE_ASPEED_SOC,
357 .instance_size = sizeof(AspeedSoCState),
358 .instance_init = aspeed_soc_ast1030_init,
359 .class_init = aspeed_soc_ast1030_class_init,
360 .class_size = sizeof(AspeedSoCClass),
361 };
362
363 static void aspeed_soc_register_types(void)
364 {
365 type_register_static(&aspeed_soc_ast1030_type_info);
366 }
367
368 type_init(aspeed_soc_register_types)
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