hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msix.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42 #include "blockdev.h"
  43 #include "ui/qemu-spice.h"
  44 #include "memory.h"
  45 #include "exec-memory.h"
  46
  47 /* output Bochs bios info messages */
  48 //#define DEBUG_BIOS
  49
  50 /* debug PC/ISA interrupts */
  51 //#define DEBUG_IRQ
  52
  53 #ifdef DEBUG_IRQ
  54 #define DPRINTF(fmt, ...)                                       \
  55     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  56 #else
  57 #define DPRINTF(fmt, ...)
  58 #endif
  59
  60 #define BIOS_FILENAME "bios.bin"
  61
  62 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  63
  64 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  65 #define ACPI_DATA_SIZE       0x10000
  66 #define BIOS_CFG_IOPORT 0x510
  67 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  68 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  69 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  70 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  71 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  72
  73 #define MSI_ADDR_BASE 0xfee00000
  74
  75 #define E820_NR_ENTRIES         16
  76
  77 struct e820_entry {
  78     uint64_t address;
  79     uint64_t length;
  80     uint32_t type;
  81 } QEMU_PACKED __attribute((__aligned__(4)));
  82
  83 struct e820_table {
  84     uint32_t count;
  85     struct e820_entry entry[E820_NR_ENTRIES];
  86 } QEMU_PACKED __attribute((__aligned__(4)));
  87
  88 static struct e820_table e820_table;
  89 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  90
  91 void gsi_handler(void *opaque, int n, int level)
  92 {
  93     GSIState *s = opaque;
  94
  95     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  96     if (n < ISA_NUM_IRQS) {
  97         qemu_set_irq(s->i8259_irq[n], level);
  98     }
  99     qemu_set_irq(s->ioapic_irq[n], level);
 100 }
 101
 102 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 103 {
 104 }
 105
 106 /* MSDOS compatibility mode FPU exception support */
 107 static qemu_irq ferr_irq;
 108
 109 void pc_register_ferr_irq(qemu_irq irq)
 110 {
 111     ferr_irq = irq;
 112 }
 113
 114 /* XXX: add IGNNE support */
 115 void cpu_set_ferr(CPUX86State *s)
 116 {
 117     qemu_irq_raise(ferr_irq);
 118 }
 119
 120 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 121 {
 122     qemu_irq_lower(ferr_irq);
 123 }
 124
 125 /* TSC handling */
 126 uint64_t cpu_get_tsc(CPUX86State *env)
 127 {
 128     return cpu_get_ticks();
 129 }
 130
 131 /* SMM support */
 132
 133 static cpu_set_smm_t smm_set;
 134 static void *smm_arg;
 135
 136 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 137 {
 138     assert(smm_set == NULL);
 139     assert(smm_arg == NULL);
 140     smm_set = callback;
 141     smm_arg = arg;
 142 }
 143
 144 void cpu_smm_update(CPUState *env)
 145 {
 146     if (smm_set && smm_arg && env == first_cpu)
 147         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 148 }
 149
 150
 151 /* IRQ handling */
 152 int cpu_get_pic_interrupt(CPUState *env)
 153 {
 154     int intno;
 155
 156     intno = apic_get_interrupt(env->apic_state);
 157     if (intno >= 0) {
 158         return intno;
 159     }
 160     /* read the irq from the PIC */
 161     if (!apic_accept_pic_intr(env->apic_state)) {
 162         return -1;
 163     }
 164
 165     intno = pic_read_irq(isa_pic);
 166     return intno;
 167 }
 168
 169 static void pic_irq_request(void *opaque, int irq, int level)
 170 {
 171     CPUState *env = first_cpu;
 172
 173     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 174     if (env->apic_state) {
 175         while (env) {
 176             if (apic_accept_pic_intr(env->apic_state)) {
 177                 apic_deliver_pic_intr(env->apic_state, level);
 178             }
 179             env = env->next_cpu;
 180         }
 181     } else {
 182         if (level)
 183             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 184         else
 185             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 186     }
 187 }
 188
 189 /* PC cmos mappings */
 190
 191 #define REG_EQUIPMENT_BYTE          0x14
 192
 193 static int cmos_get_fd_drive_type(FDriveType fd0)
 194 {
 195     int val;
 196
 197     switch (fd0) {
 198     case FDRIVE_DRV_144:
 199         /* 1.44 Mb 3"5 drive */
 200         val = 4;
 201         break;
 202     case FDRIVE_DRV_288:
 203         /* 2.88 Mb 3"5 drive */
 204         val = 5;
 205         break;
 206     case FDRIVE_DRV_120:
 207         /* 1.2 Mb 5"5 drive */
 208         val = 2;
 209         break;
 210     case FDRIVE_DRV_NONE:
 211     default:
 212         val = 0;
 213         break;
 214     }
 215     return val;
 216 }
 217
 218 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 219                          ISADevice *s)
 220 {
 221     int cylinders, heads, sectors;
 222     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 223     rtc_set_memory(s, type_ofs, 47);
 224     rtc_set_memory(s, info_ofs, cylinders);
 225     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 226     rtc_set_memory(s, info_ofs + 2, heads);
 227     rtc_set_memory(s, info_ofs + 3, 0xff);
 228     rtc_set_memory(s, info_ofs + 4, 0xff);
 229     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 230     rtc_set_memory(s, info_ofs + 6, cylinders);
 231     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 232     rtc_set_memory(s, info_ofs + 8, sectors);
 233 }
 234
 235 /* convert boot_device letter to something recognizable by the bios */
 236 static int boot_device2nibble(char boot_device)
 237 {
 238     switch(boot_device) {
 239     case 'a':
 240     case 'b':
 241         return 0x01; /* floppy boot */
 242     case 'c':
 243         return 0x02; /* hard drive boot */
 244     case 'd':
 245         return 0x03; /* CD-ROM boot */
 246     case 'n':
 247         return 0x04; /* Network boot */
 248     }
 249     return 0;
 250 }
 251
 252 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 253 {
 254 #define PC_MAX_BOOT_DEVICES 3
 255     int nbds, bds[3] = { 0, };
 256     int i;
 257
 258     nbds = strlen(boot_device);
 259     if (nbds > PC_MAX_BOOT_DEVICES) {
 260         error_report("Too many boot devices for PC");
 261         return(1);
 262     }
 263     for (i = 0; i < nbds; i++) {
 264         bds[i] = boot_device2nibble(boot_device[i]);
 265         if (bds[i] == 0) {
 266             error_report("Invalid boot device for PC: '%c'",
 267                          boot_device[i]);
 268             return(1);
 269         }
 270     }
 271     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 272     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 273     return(0);
 274 }
 275
 276 static int pc_boot_set(void *opaque, const char *boot_device)
 277 {
 278     return set_boot_dev(opaque, boot_device, 0);
 279 }
 280
 281 typedef struct pc_cmos_init_late_arg {
 282     ISADevice *rtc_state;
 283     BusState *idebus0, *idebus1;
 284 } pc_cmos_init_late_arg;
 285
 286 static void pc_cmos_init_late(void *opaque)
 287 {
 288     pc_cmos_init_late_arg *arg = opaque;
 289     ISADevice *s = arg->rtc_state;
 290     int val;
 291     BlockDriverState *hd_table[4];
 292     int i;
 293
 294     ide_get_bs(hd_table, arg->idebus0);
 295     ide_get_bs(hd_table + 2, arg->idebus1);
 296
 297     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 298     if (hd_table[0])
 299         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 300     if (hd_table[1])
 301         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 302
 303     val = 0;
 304     for (i = 0; i < 4; i++) {
 305         if (hd_table[i]) {
 306             int cylinders, heads, sectors, translation;
 307             /* NOTE: bdrv_get_geometry_hint() returns the physical
 308                 geometry.  It is always such that: 1 <= sects <= 63, 1
 309                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 310                 geometry can be different if a translation is done. */
 311             translation = bdrv_get_translation_hint(hd_table[i]);
 312             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 313                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 314                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 315                     /* No translation. */
 316                     translation = 0;
 317                 } else {
 318                     /* LBA translation. */
 319                     translation = 1;
 320                 }
 321             } else {
 322                 translation--;
 323             }
 324             val |= translation << (i * 2);
 325         }
 326     }
 327     rtc_set_memory(s, 0x39, val);
 328
 329     qemu_unregister_reset(pc_cmos_init_late, opaque);
 330 }
 331
 332 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 333                   const char *boot_device,
 334                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 335                   ISADevice *s)
 336 {
 337     int val, nb, nb_heads, max_track, last_sect, i;
 338     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 339     BlockDriverState *fd[MAX_FD];
 340     static pc_cmos_init_late_arg arg;
 341
 342     /* various important CMOS locations needed by PC/Bochs bios */
 343
 344     /* memory size */
 345     val = 640; /* base memory in K */
 346     rtc_set_memory(s, 0x15, val);
 347     rtc_set_memory(s, 0x16, val >> 8);
 348
 349     val = (ram_size / 1024) - 1024;
 350     if (val > 65535)
 351         val = 65535;
 352     rtc_set_memory(s, 0x17, val);
 353     rtc_set_memory(s, 0x18, val >> 8);
 354     rtc_set_memory(s, 0x30, val);
 355     rtc_set_memory(s, 0x31, val >> 8);
 356
 357     if (above_4g_mem_size) {
 358         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 359         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 360         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 361     }
 362
 363     if (ram_size > (16 * 1024 * 1024))
 364         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 365     else
 366         val = 0;
 367     if (val > 65535)
 368         val = 65535;
 369     rtc_set_memory(s, 0x34, val);
 370     rtc_set_memory(s, 0x35, val >> 8);
 371
 372     /* set the number of CPU */
 373     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 374
 375     /* set boot devices, and disable floppy signature check if requested */
 376     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 377         exit(1);
 378     }
 379
 380     /* floppy type */
 381     if (floppy) {
 382         fdc_get_bs(fd, floppy);
 383         for (i = 0; i < 2; i++) {
 384             if (fd[i] && bdrv_is_inserted(fd[i])) {
 385                 bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
 386                                               &last_sect, FDRIVE_DRV_NONE,
 387                                               &fd_type[i]);
 388             }
 389         }
 390     }
 391     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 392         cmos_get_fd_drive_type(fd_type[1]);
 393     rtc_set_memory(s, 0x10, val);
 394
 395     val = 0;
 396     nb = 0;
 397     if (fd_type[0] < FDRIVE_DRV_NONE) {
 398         nb++;
 399     }
 400     if (fd_type[1] < FDRIVE_DRV_NONE) {
 401         nb++;
 402     }
 403     switch (nb) {
 404     case 0:
 405         break;
 406     case 1:
 407         val |= 0x01; /* 1 drive, ready for boot */
 408         break;
 409     case 2:
 410         val |= 0x41; /* 2 drives, ready for boot */
 411         break;
 412     }
 413     val |= 0x02; /* FPU is there */
 414     val |= 0x04; /* PS/2 mouse installed */
 415     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 416
 417     /* hard drives */
 418     arg.rtc_state = s;
 419     arg.idebus0 = idebus0;
 420     arg.idebus1 = idebus1;
 421     qemu_register_reset(pc_cmos_init_late, &arg);
 422 }
 423
 424 /* port 92 stuff: could be split off */
 425 typedef struct Port92State {
 426     ISADevice dev;
 427     MemoryRegion io;
 428     uint8_t outport;
 429     qemu_irq *a20_out;
 430 } Port92State;
 431
 432 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 433 {
 434     Port92State *s = opaque;
 435
 436     DPRINTF("port92: write 0x%02x\n", val);
 437     s->outport = val;
 438     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 439     if (val & 1) {
 440         qemu_system_reset_request();
 441     }
 442 }
 443
 444 static uint32_t port92_read(void *opaque, uint32_t addr)
 445 {
 446     Port92State *s = opaque;
 447     uint32_t ret;
 448
 449     ret = s->outport;
 450     DPRINTF("port92: read 0x%02x\n", ret);
 451     return ret;
 452 }
 453
 454 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 455 {
 456     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 457
 458     s->a20_out = a20_out;
 459 }
 460
 461 static const VMStateDescription vmstate_port92_isa = {
 462     .name = "port92",
 463     .version_id = 1,
 464     .minimum_version_id = 1,
 465     .minimum_version_id_old = 1,
 466     .fields      = (VMStateField []) {
 467         VMSTATE_UINT8(outport, Port92State),
 468         VMSTATE_END_OF_LIST()
 469     }
 470 };
 471
 472 static void port92_reset(DeviceState *d)
 473 {
 474     Port92State *s = container_of(d, Port92State, dev.qdev);
 475
 476     s->outport &= ~1;
 477 }
 478
 479 static const MemoryRegionPortio port92_portio[] = {
 480     { 0, 1, 1, .read = port92_read, .write = port92_write },
 481     PORTIO_END_OF_LIST(),
 482 };
 483
 484 static const MemoryRegionOps port92_ops = {
 485     .old_portio = port92_portio
 486 };
 487
 488 static int port92_initfn(ISADevice *dev)
 489 {
 490     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 491
 492     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 493     isa_register_ioport(dev, &s->io, 0x92);
 494
 495     s->outport = 0;
 496     return 0;
 497 }
 498
 499 static ISADeviceInfo port92_info = {
 500     .qdev.name     = "port92",
 501     .qdev.size     = sizeof(Port92State),
 502     .qdev.vmsd     = &vmstate_port92_isa,
 503     .qdev.no_user  = 1,
 504     .qdev.reset    = port92_reset,
 505     .init          = port92_initfn,
 506 };
 507
 508 static void port92_register(void)
 509 {
 510     isa_qdev_register(&port92_info);
 511 }
 512 device_init(port92_register)
 513
 514 static void handle_a20_line_change(void *opaque, int irq, int level)
 515 {
 516     CPUState *cpu = opaque;
 517
 518     /* XXX: send to all CPUs ? */
 519     /* XXX: add logic to handle multiple A20 line sources */
 520     cpu_x86_set_a20(cpu, level);
 521 }
 522
 523 /***********************************************************/
 524 /* Bochs BIOS debug ports */
 525
 526 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 527 {
 528     static const char shutdown_str[8] = "Shutdown";
 529     static int shutdown_index = 0;
 530
 531     switch(addr) {
 532         /* Bochs BIOS messages */
 533     case 0x400:
 534     case 0x401:
 535         /* used to be panic, now unused */
 536         break;
 537     case 0x402:
 538     case 0x403:
 539 #ifdef DEBUG_BIOS
 540         fprintf(stderr, "%c", val);
 541 #endif
 542         break;
 543     case 0x8900:
 544         /* same as Bochs power off */
 545         if (val == shutdown_str[shutdown_index]) {
 546             shutdown_index++;
 547             if (shutdown_index == 8) {
 548                 shutdown_index = 0;
 549                 qemu_system_shutdown_request();
 550             }
 551         } else {
 552             shutdown_index = 0;
 553         }
 554         break;
 555
 556         /* LGPL'ed VGA BIOS messages */
 557     case 0x501:
 558     case 0x502:
 559         exit((val << 1) | 1);
 560     case 0x500:
 561     case 0x503:
 562 #ifdef DEBUG_BIOS
 563         fprintf(stderr, "%c", val);
 564 #endif
 565         break;
 566     }
 567 }
 568
 569 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 570 {
 571     int index = le32_to_cpu(e820_table.count);
 572     struct e820_entry *entry;
 573
 574     if (index >= E820_NR_ENTRIES)
 575         return -EBUSY;
 576     entry = &e820_table.entry[index++];
 577
 578     entry->address = cpu_to_le64(address);
 579     entry->length = cpu_to_le64(length);
 580     entry->type = cpu_to_le32(type);
 581
 582     e820_table.count = cpu_to_le32(index);
 583     return index;
 584 }
 585
 586 static void *bochs_bios_init(void)
 587 {
 588     void *fw_cfg;
 589     uint8_t *smbios_table;
 590     size_t smbios_len;
 591     uint64_t *numa_fw_cfg;
 592     int i, j;
 593
 594     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 595     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 596     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 597     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 598     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 599
 600     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 601     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 602     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 603     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 604     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 605
 606     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 607
 608     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 609     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 610     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 611                      acpi_tables_len);
 612     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 613
 614     smbios_table = smbios_get_table(&smbios_len);
 615     if (smbios_table)
 616         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 617                          smbios_table, smbios_len);
 618     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 619                      sizeof(struct e820_table));
 620
 621     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 622                      sizeof(struct hpet_fw_config));
 623     /* allocate memory for the NUMA channel: one (64bit) word for the number
 624      * of nodes, one word for each VCPU->node and one word for each node to
 625      * hold the amount of memory.
 626      */
 627     numa_fw_cfg = g_malloc0((1 + smp_cpus + nb_numa_nodes) * 8);
 628     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 629     for (i = 0; i < smp_cpus; i++) {
 630         for (j = 0; j < nb_numa_nodes; j++) {
 631             if (node_cpumask[j] & (1 << i)) {
 632                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 633                 break;
 634             }
 635         }
 636     }
 637     for (i = 0; i < nb_numa_nodes; i++) {
 638         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 639     }
 640     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 641                      (1 + smp_cpus + nb_numa_nodes) * 8);
 642
 643     return fw_cfg;
 644 }
 645
 646 static long get_file_size(FILE *f)
 647 {
 648     long where, size;
 649
 650     /* XXX: on Unix systems, using fstat() probably makes more sense */
 651
 652     where = ftell(f);
 653     fseek(f, 0, SEEK_END);
 654     size = ftell(f);
 655     fseek(f, where, SEEK_SET);
 656
 657     return size;
 658 }
 659
 660 static void load_linux(void *fw_cfg,
 661                        const char *kernel_filename,
 662                        const char *initrd_filename,
 663                        const char *kernel_cmdline,
 664                        target_phys_addr_t max_ram_size)
 665 {
 666     uint16_t protocol;
 667     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 668     uint32_t initrd_max;
 669     uint8_t header[8192], *setup, *kernel, *initrd_data;
 670     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 671     FILE *f;
 672     char *vmode;
 673
 674     /* Align to 16 bytes as a paranoia measure */
 675     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 676
 677     /* load the kernel header */
 678     f = fopen(kernel_filename, "rb");
 679     if (!f || !(kernel_size = get_file_size(f)) ||
 680         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 681         MIN(ARRAY_SIZE(header), kernel_size)) {
 682         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 683                 kernel_filename, strerror(errno));
 684         exit(1);
 685     }
 686
 687     /* kernel protocol version */
 688 #if 0
 689     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 690 #endif
 691     if (ldl_p(header+0x202) == 0x53726448)
 692         protocol = lduw_p(header+0x206);
 693     else {
 694         /* This looks like a multiboot kernel. If it is, let's stop
 695            treating it like a Linux kernel. */
 696         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 697                            kernel_cmdline, kernel_size, header))
 698             return;
 699         protocol = 0;
 700     }
 701
 702     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 703         /* Low kernel */
 704         real_addr    = 0x90000;
 705         cmdline_addr = 0x9a000 - cmdline_size;
 706         prot_addr    = 0x10000;
 707     } else if (protocol < 0x202) {
 708         /* High but ancient kernel */
 709         real_addr    = 0x90000;
 710         cmdline_addr = 0x9a000 - cmdline_size;
 711         prot_addr    = 0x100000;
 712     } else {
 713         /* High and recent kernel */
 714         real_addr    = 0x10000;
 715         cmdline_addr = 0x20000;
 716         prot_addr    = 0x100000;
 717     }
 718
 719 #if 0
 720     fprintf(stderr,
 721             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 722             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 723             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 724             real_addr,
 725             cmdline_addr,
 726             prot_addr);
 727 #endif
 728
 729     /* highest address for loading the initrd */
 730     if (protocol >= 0x203)
 731         initrd_max = ldl_p(header+0x22c);
 732     else
 733         initrd_max = 0x37ffffff;
 734
 735     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 736         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 737
 738     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 739     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 740     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 741                      (uint8_t*)strdup(kernel_cmdline),
 742                      strlen(kernel_cmdline)+1);
 743
 744     if (protocol >= 0x202) {
 745         stl_p(header+0x228, cmdline_addr);
 746     } else {
 747         stw_p(header+0x20, 0xA33F);
 748         stw_p(header+0x22, cmdline_addr-real_addr);
 749     }
 750
 751     /* handle vga= parameter */
 752     vmode = strstr(kernel_cmdline, "vga=");
 753     if (vmode) {
 754         unsigned int video_mode;
 755         /* skip "vga=" */
 756         vmode += 4;
 757         if (!strncmp(vmode, "normal", 6)) {
 758             video_mode = 0xffff;
 759         } else if (!strncmp(vmode, "ext", 3)) {
 760             video_mode = 0xfffe;
 761         } else if (!strncmp(vmode, "ask", 3)) {
 762             video_mode = 0xfffd;
 763         } else {
 764             video_mode = strtol(vmode, NULL, 0);
 765         }
 766         stw_p(header+0x1fa, video_mode);
 767     }
 768
 769     /* loader type */
 770     /* High nybble = B reserved for Qemu; low nybble is revision number.
 771        If this code is substantially changed, you may want to consider
 772        incrementing the revision. */
 773     if (protocol >= 0x200)
 774         header[0x210] = 0xB0;
 775
 776     /* heap */
 777     if (protocol >= 0x201) {
 778         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 779         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 780     }
 781
 782     /* load initrd */
 783     if (initrd_filename) {
 784         if (protocol < 0x200) {
 785             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 786             exit(1);
 787         }
 788
 789         initrd_size = get_image_size(initrd_filename);
 790         if (initrd_size < 0) {
 791             fprintf(stderr, "qemu: error reading initrd %s\n",
 792                     initrd_filename);
 793             exit(1);
 794         }
 795
 796         initrd_addr = (initrd_max-initrd_size) & ~4095;
 797
 798         initrd_data = g_malloc(initrd_size);
 799         load_image(initrd_filename, initrd_data);
 800
 801         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 802         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 803         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 804
 805         stl_p(header+0x218, initrd_addr);
 806         stl_p(header+0x21c, initrd_size);
 807     }
 808
 809     /* load kernel and setup */
 810     setup_size = header[0x1f1];
 811     if (setup_size == 0)
 812         setup_size = 4;
 813     setup_size = (setup_size+1)*512;
 814     kernel_size -= setup_size;
 815
 816     setup  = g_malloc(setup_size);
 817     kernel = g_malloc(kernel_size);
 818     fseek(f, 0, SEEK_SET);
 819     if (fread(setup, 1, setup_size, f) != setup_size) {
 820         fprintf(stderr, "fread() failed\n");
 821         exit(1);
 822     }
 823     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 824         fprintf(stderr, "fread() failed\n");
 825         exit(1);
 826     }
 827     fclose(f);
 828     memcpy(setup, header, MIN(sizeof(header), setup_size));
 829
 830     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 831     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 832     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 833
 834     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 835     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 836     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 837
 838     option_rom[nb_option_roms].name = "linuxboot.bin";
 839     option_rom[nb_option_roms].bootindex = 0;
 840     nb_option_roms++;
 841 }
 842
 843 #define NE2000_NB_MAX 6
 844
 845 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 846                                               0x280, 0x380 };
 847 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 848
 849 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 850 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 851
 852 void pc_init_ne2k_isa(NICInfo *nd)
 853 {
 854     static int nb_ne2k = 0;
 855
 856     if (nb_ne2k == NE2000_NB_MAX)
 857         return;
 858     isa_ne2000_init(ne2000_io[nb_ne2k],
 859                     ne2000_irq[nb_ne2k], nd);
 860     nb_ne2k++;
 861 }
 862
 863 int cpu_is_bsp(CPUState *env)
 864 {
 865     /* We hard-wire the BSP to the first CPU. */
 866     return env->cpu_index == 0;
 867 }
 868
 869 DeviceState *cpu_get_current_apic(void)
 870 {
 871     if (cpu_single_env) {
 872         return cpu_single_env->apic_state;
 873     } else {
 874         return NULL;
 875     }
 876 }
 877
 878 static DeviceState *apic_init(void *env, uint8_t apic_id)
 879 {
 880     DeviceState *dev;
 881     SysBusDevice *d;
 882     static int apic_mapped;
 883
 884     dev = qdev_create(NULL, "apic");
 885     qdev_prop_set_uint8(dev, "id", apic_id);
 886     qdev_prop_set_ptr(dev, "cpu_env", env);
 887     qdev_init_nofail(dev);
 888     d = sysbus_from_qdev(dev);
 889
 890     /* XXX: mapping more APICs at the same memory location */
 891     if (apic_mapped == 0) {
 892         /* NOTE: the APIC is directly connected to the CPU - it is not
 893            on the global memory bus. */
 894         /* XXX: what if the base changes? */
 895         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 896         apic_mapped = 1;
 897     }
 898
 899     msix_supported = 1;
 900
 901     return dev;
 902 }
 903
 904 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 905    BIOS will read it and start S3 resume at POST Entry */
 906 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 907 {
 908     ISADevice *s = opaque;
 909
 910     if (level) {
 911         rtc_set_memory(s, 0xF, 0xFE);
 912     }
 913 }
 914
 915 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 916 {
 917     CPUState *s = opaque;
 918
 919     if (level) {
 920         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 921     }
 922 }
 923
 924 static void pc_cpu_reset(void *opaque)
 925 {
 926     CPUState *env = opaque;
 927
 928     cpu_reset(env);
 929     env->halted = !cpu_is_bsp(env);
 930 }
 931
 932 static CPUState *pc_new_cpu(const char *cpu_model)
 933 {
 934     CPUState *env;
 935
 936     env = cpu_init(cpu_model);
 937     if (!env) {
 938         fprintf(stderr, "Unable to find x86 CPU definition\n");
 939         exit(1);
 940     }
 941     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 942         env->apic_state = apic_init(env, env->cpuid_apic_id);
 943     }
 944     qemu_register_reset(pc_cpu_reset, env);
 945     pc_cpu_reset(env);
 946     return env;
 947 }
 948
 949 void pc_cpus_init(const char *cpu_model)
 950 {
 951     int i;
 952
 953     /* init CPUs */
 954     if (cpu_model == NULL) {
 955 #ifdef TARGET_X86_64
 956         cpu_model = "qemu64";
 957 #else
 958         cpu_model = "qemu32";
 959 #endif
 960     }
 961
 962     for(i = 0; i < smp_cpus; i++) {
 963         pc_new_cpu(cpu_model);
 964     }
 965 }
 966
 967 void pc_memory_init(MemoryRegion *system_memory,
 968                     const char *kernel_filename,
 969                     const char *kernel_cmdline,
 970                     const char *initrd_filename,
 971                     ram_addr_t below_4g_mem_size,
 972                     ram_addr_t above_4g_mem_size,
 973                     MemoryRegion *rom_memory,
 974                     MemoryRegion **ram_memory)
 975 {
 976     char *filename;
 977     int ret, linux_boot, i;
 978     MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr;
 979     MemoryRegion *ram_below_4g, *ram_above_4g;
 980     int bios_size, isa_bios_size;
 981     void *fw_cfg;
 982
 983     linux_boot = (kernel_filename != NULL);
 984
 985     /* Allocate RAM.  We allocate it as a single memory region and use
 986      * aliases to address portions of it, mostly for backwards compatibility
 987      * with older qemus that used qemu_ram_alloc().
 988      */
 989     ram = g_malloc(sizeof(*ram));
 990     memory_region_init_ram(ram, NULL, "pc.ram",
 991                            below_4g_mem_size + above_4g_mem_size);
 992     *ram_memory = ram;
 993     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 994     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 995                              0, below_4g_mem_size);
 996     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 997     if (above_4g_mem_size > 0) {
 998         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 999         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1000                                  below_4g_mem_size, above_4g_mem_size);
1001         memory_region_add_subregion(system_memory, 0x100000000ULL,
1002                                     ram_above_4g);
1003     }
1004
1005     /* BIOS load */
1006     if (bios_name == NULL)
1007         bios_name = BIOS_FILENAME;
1008     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1009     if (filename) {
1010         bios_size = get_image_size(filename);
1011     } else {
1012         bios_size = -1;
1013     }
1014     if (bios_size <= 0 ||
1015         (bios_size % 65536) != 0) {
1016         goto bios_error;
1017     }
1018     bios = g_malloc(sizeof(*bios));
1019     memory_region_init_ram(bios, NULL, "pc.bios", bios_size);
1020     memory_region_set_readonly(bios, true);
1021     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1022     if (ret != 0) {
1023     bios_error:
1024         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1025         exit(1);
1026     }
1027     if (filename) {
1028         g_free(filename);
1029     }
1030     /* map the last 128KB of the BIOS in ISA space */
1031     isa_bios_size = bios_size;
1032     if (isa_bios_size > (128 * 1024))
1033         isa_bios_size = 128 * 1024;
1034     isa_bios = g_malloc(sizeof(*isa_bios));
1035     memory_region_init_alias(isa_bios, "isa-bios", bios,
1036                              bios_size - isa_bios_size, isa_bios_size);
1037     memory_region_add_subregion_overlap(rom_memory,
1038                                         0x100000 - isa_bios_size,
1039                                         isa_bios,
1040                                         1);
1041     memory_region_set_readonly(isa_bios, true);
1042
1043     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1044     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1045     memory_region_add_subregion_overlap(rom_memory,
1046                                         PC_ROM_MIN_VGA,
1047                                         option_rom_mr,
1048                                         1);
1049
1050     /* map all the bios at the top of memory */
1051     memory_region_add_subregion(rom_memory,
1052                                 (uint32_t)(-bios_size),
1053                                 bios);
1054
1055     fw_cfg = bochs_bios_init();
1056     rom_set_fw(fw_cfg);
1057
1058     if (linux_boot) {
1059         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1060     }
1061
1062     for (i = 0; i < nb_option_roms; i++) {
1063         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1064     }
1065 }
1066
1067 qemu_irq *pc_allocate_cpu_irq(void)
1068 {
1069     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1070 }
1071
1072 DeviceState *pc_vga_init(PCIBus *pci_bus)
1073 {
1074     DeviceState *dev = NULL;
1075
1076     if (cirrus_vga_enabled) {
1077         if (pci_bus) {
1078             dev = pci_cirrus_vga_init(pci_bus);
1079         } else {
1080             dev = isa_cirrus_vga_init(get_system_memory());
1081         }
1082     } else if (vmsvga_enabled) {
1083         if (pci_bus) {
1084             dev = pci_vmsvga_init(pci_bus);
1085             if (!dev) {
1086                 fprintf(stderr, "Warning: vmware_vga not available,"
1087                         " using standard VGA instead\n");
1088                 dev = pci_vga_init(pci_bus);
1089             }
1090         } else {
1091             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1092         }
1093 #ifdef CONFIG_SPICE
1094     } else if (qxl_enabled) {
1095         if (pci_bus) {
1096             dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
1097         } else {
1098             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1099         }
1100 #endif
1101     } else if (std_vga_enabled) {
1102         if (pci_bus) {
1103             dev = pci_vga_init(pci_bus);
1104         } else {
1105             dev = isa_vga_init();
1106         }
1107     }
1108
1109     return dev;
1110 }
1111
1112 static void cpu_request_exit(void *opaque, int irq, int level)
1113 {
1114     CPUState *env = cpu_single_env;
1115
1116     if (env && level) {
1117         cpu_exit(env);
1118     }
1119 }
1120
1121 void pc_basic_device_init(qemu_irq *gsi,
1122                           ISADevice **rtc_state,
1123                           ISADevice **floppy,
1124                           bool no_vmport)
1125 {
1126     int i;
1127     DriveInfo *fd[MAX_FD];
1128     qemu_irq rtc_irq = NULL;
1129     qemu_irq *a20_line;
1130     ISADevice *i8042, *port92, *vmmouse, *pit;
1131     qemu_irq *cpu_exit_irq;
1132
1133     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1134
1135     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1136
1137     if (!no_hpet) {
1138         DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1139
1140         if (hpet) {
1141             for (i = 0; i < GSI_NUM_PINS; i++) {
1142                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1143             }
1144             rtc_irq = qdev_get_gpio_in(hpet, 0);
1145         }
1146     }
1147     *rtc_state = rtc_init(2000, rtc_irq);
1148
1149     qemu_register_boot_set(pc_boot_set, *rtc_state);
1150
1151     pit = pit_init(0x40, 0);
1152     pcspk_init(pit);
1153
1154     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1155         if (serial_hds[i]) {
1156             serial_isa_init(i, serial_hds[i]);
1157         }
1158     }
1159
1160     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1161         if (parallel_hds[i]) {
1162             parallel_init(i, parallel_hds[i]);
1163         }
1164     }
1165
1166     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1167     i8042 = isa_create_simple("i8042");
1168     i8042_setup_a20_line(i8042, &a20_line[0]);
1169     if (!no_vmport) {
1170         vmport_init();
1171         vmmouse = isa_try_create("vmmouse");
1172     } else {
1173         vmmouse = NULL;
1174     }
1175     if (vmmouse) {
1176         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1177         qdev_init_nofail(&vmmouse->qdev);
1178     }
1179     port92 = isa_create_simple("port92");
1180     port92_init(port92, &a20_line[1]);
1181
1182     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1183     DMA_init(0, cpu_exit_irq);
1184
1185     for(i = 0; i < MAX_FD; i++) {
1186         fd[i] = drive_get(IF_FLOPPY, 0, i);
1187     }
1188     *floppy = fdctrl_init_isa(fd);
1189 }
1190
1191 void pc_pci_device_init(PCIBus *pci_bus)
1192 {
1193     int max_bus;
1194     int bus;
1195
1196     max_bus = drive_get_max_bus(IF_SCSI);
1197     for (bus = 0; bus <= max_bus; bus++) {
1198         pci_create_simple(pci_bus, -1, "lsi53c895a");
1199     }
1200 }