target/arm: Support PSCI 1.1 and SMCCC 1.0
[qemu/rayw.git] / cpu.c
blob3ea38aea70775b4dadb06661a97d1e26b289f0e4
1 /*
2 * Target-specific parts of the CPU object
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
24 #include "exec/target_page.h"
25 #include "hw/qdev-core.h"
26 #include "hw/qdev-properties.h"
27 #include "qemu/error-report.h"
28 #include "migration/vmstate.h"
29 #ifdef CONFIG_USER_ONLY
30 #include "qemu.h"
31 #else
32 #include "hw/core/sysemu-cpu-ops.h"
33 #include "exec/address-spaces.h"
34 #endif
35 #include "sysemu/tcg.h"
36 #include "sysemu/kvm.h"
37 #include "sysemu/replay.h"
38 #include "exec/translate-all.h"
39 #include "exec/log.h"
40 #include "hw/core/accel-cpu.h"
41 #include "trace/trace-root.h"
43 uintptr_t qemu_host_page_size;
44 intptr_t qemu_host_page_mask;
46 #ifndef CONFIG_USER_ONLY
47 static int cpu_common_post_load(void *opaque, int version_id)
49 CPUState *cpu = opaque;
51 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
52 version_id is increased. */
53 cpu->interrupt_request &= ~0x01;
54 tlb_flush(cpu);
56 /* loadvm has just updated the content of RAM, bypassing the
57 * usual mechanisms that ensure we flush TBs for writes to
58 * memory we've translated code from. So we must flush all TBs,
59 * which will now be stale.
61 tb_flush(cpu);
63 return 0;
66 static int cpu_common_pre_load(void *opaque)
68 CPUState *cpu = opaque;
70 cpu->exception_index = -1;
72 return 0;
75 static bool cpu_common_exception_index_needed(void *opaque)
77 CPUState *cpu = opaque;
79 return tcg_enabled() && cpu->exception_index != -1;
82 static const VMStateDescription vmstate_cpu_common_exception_index = {
83 .name = "cpu_common/exception_index",
84 .version_id = 1,
85 .minimum_version_id = 1,
86 .needed = cpu_common_exception_index_needed,
87 .fields = (VMStateField[]) {
88 VMSTATE_INT32(exception_index, CPUState),
89 VMSTATE_END_OF_LIST()
93 static bool cpu_common_crash_occurred_needed(void *opaque)
95 CPUState *cpu = opaque;
97 return cpu->crash_occurred;
100 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
101 .name = "cpu_common/crash_occurred",
102 .version_id = 1,
103 .minimum_version_id = 1,
104 .needed = cpu_common_crash_occurred_needed,
105 .fields = (VMStateField[]) {
106 VMSTATE_BOOL(crash_occurred, CPUState),
107 VMSTATE_END_OF_LIST()
111 const VMStateDescription vmstate_cpu_common = {
112 .name = "cpu_common",
113 .version_id = 1,
114 .minimum_version_id = 1,
115 .pre_load = cpu_common_pre_load,
116 .post_load = cpu_common_post_load,
117 .fields = (VMStateField[]) {
118 VMSTATE_UINT32(halted, CPUState),
119 VMSTATE_UINT32(interrupt_request, CPUState),
120 VMSTATE_END_OF_LIST()
122 .subsections = (const VMStateDescription*[]) {
123 &vmstate_cpu_common_exception_index,
124 &vmstate_cpu_common_crash_occurred,
125 NULL
128 #endif
130 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
132 #ifndef CONFIG_USER_ONLY
133 CPUClass *cc = CPU_GET_CLASS(cpu);
134 #endif
136 cpu_list_add(cpu);
137 if (!accel_cpu_realizefn(cpu, errp)) {
138 return;
140 /* NB: errp parameter is unused currently */
141 if (tcg_enabled()) {
142 tcg_exec_realizefn(cpu, errp);
145 #ifdef CONFIG_USER_ONLY
146 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
147 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
148 #else
149 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
150 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
152 if (cc->sysemu_ops->legacy_vmsd != NULL) {
153 vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
155 #endif /* CONFIG_USER_ONLY */
158 void cpu_exec_unrealizefn(CPUState *cpu)
160 #ifndef CONFIG_USER_ONLY
161 CPUClass *cc = CPU_GET_CLASS(cpu);
163 if (cc->sysemu_ops->legacy_vmsd != NULL) {
164 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
166 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
167 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
169 #endif
170 if (tcg_enabled()) {
171 tcg_exec_unrealizefn(cpu);
174 cpu_list_remove(cpu);
178 * This can't go in hw/core/cpu.c because that file is compiled only
179 * once for both user-mode and system builds.
181 static Property cpu_common_props[] = {
182 #ifdef CONFIG_USER_ONLY
184 * Create a property for the user-only object, so users can
185 * adjust prctl(PR_SET_UNALIGN) from the command-line.
186 * Has no effect if the target does not support the feature.
188 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
189 prctl_unalign_sigbus, false),
190 #else
192 * Create a memory property for softmmu CPU object, so users can
193 * wire up its memory. The default if no link is set up is to use
194 * the system address space.
196 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
197 MemoryRegion *),
198 #endif
199 DEFINE_PROP_END_OF_LIST(),
202 static bool cpu_get_start_powered_off(Object *obj, Error **errp)
204 CPUState *cpu = CPU(obj);
205 return cpu->start_powered_off;
208 static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
210 CPUState *cpu = CPU(obj);
211 cpu->start_powered_off = value;
214 void cpu_class_init_props(DeviceClass *dc)
216 ObjectClass *oc = OBJECT_CLASS(dc);
218 device_class_set_props(dc, cpu_common_props);
220 * We can't use DEFINE_PROP_BOOL in the Property array for this
221 * property, because we want this to be settable after realize.
223 object_class_property_add_bool(oc, "start-powered-off",
224 cpu_get_start_powered_off,
225 cpu_set_start_powered_off);
228 void cpu_exec_initfn(CPUState *cpu)
230 cpu->as = NULL;
231 cpu->num_ases = 0;
233 #ifndef CONFIG_USER_ONLY
234 cpu->thread_id = qemu_get_thread_id();
235 cpu->memory = get_system_memory();
236 object_ref(OBJECT(cpu->memory));
237 #endif
240 const char *parse_cpu_option(const char *cpu_option)
242 ObjectClass *oc;
243 CPUClass *cc;
244 gchar **model_pieces;
245 const char *cpu_type;
247 model_pieces = g_strsplit(cpu_option, ",", 2);
248 if (!model_pieces[0]) {
249 error_report("-cpu option cannot be empty");
250 exit(1);
253 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
254 if (oc == NULL) {
255 error_report("unable to find CPU model '%s'", model_pieces[0]);
256 g_strfreev(model_pieces);
257 exit(EXIT_FAILURE);
260 cpu_type = object_class_get_name(oc);
261 cc = CPU_CLASS(oc);
262 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
263 g_strfreev(model_pieces);
264 return cpu_type;
267 #if defined(CONFIG_USER_ONLY)
268 void tb_invalidate_phys_addr(target_ulong addr)
270 mmap_lock();
271 tb_invalidate_phys_page_range(addr, addr + 1);
272 mmap_unlock();
274 #else
275 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
277 ram_addr_t ram_addr;
278 MemoryRegion *mr;
279 hwaddr l = 1;
281 if (!tcg_enabled()) {
282 return;
285 RCU_READ_LOCK_GUARD();
286 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
287 if (!(memory_region_is_ram(mr)
288 || memory_region_is_romd(mr))) {
289 return;
291 ram_addr = memory_region_get_ram_addr(mr) + addr;
292 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
294 #endif
296 /* Add a breakpoint. */
297 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
298 CPUBreakpoint **breakpoint)
300 CPUClass *cc = CPU_GET_CLASS(cpu);
301 CPUBreakpoint *bp;
303 if (cc->gdb_adjust_breakpoint) {
304 pc = cc->gdb_adjust_breakpoint(cpu, pc);
307 bp = g_malloc(sizeof(*bp));
309 bp->pc = pc;
310 bp->flags = flags;
312 /* keep all GDB-injected breakpoints in front */
313 if (flags & BP_GDB) {
314 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
315 } else {
316 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
319 if (breakpoint) {
320 *breakpoint = bp;
323 trace_breakpoint_insert(cpu->cpu_index, pc, flags);
324 return 0;
327 /* Remove a specific breakpoint. */
328 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
330 CPUClass *cc = CPU_GET_CLASS(cpu);
331 CPUBreakpoint *bp;
333 if (cc->gdb_adjust_breakpoint) {
334 pc = cc->gdb_adjust_breakpoint(cpu, pc);
337 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
338 if (bp->pc == pc && bp->flags == flags) {
339 cpu_breakpoint_remove_by_ref(cpu, bp);
340 return 0;
343 return -ENOENT;
346 /* Remove a specific breakpoint by reference. */
347 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
349 QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
351 trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
352 g_free(bp);
355 /* Remove all matching breakpoints. */
356 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
358 CPUBreakpoint *bp, *next;
360 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
361 if (bp->flags & mask) {
362 cpu_breakpoint_remove_by_ref(cpu, bp);
367 /* enable or disable single step mode. EXCP_DEBUG is returned by the
368 CPU loop after each instruction */
369 void cpu_single_step(CPUState *cpu, int enabled)
371 if (cpu->singlestep_enabled != enabled) {
372 cpu->singlestep_enabled = enabled;
373 if (kvm_enabled()) {
374 kvm_update_guest_debug(cpu, 0);
376 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
380 void cpu_abort(CPUState *cpu, const char *fmt, ...)
382 va_list ap;
383 va_list ap2;
385 va_start(ap, fmt);
386 va_copy(ap2, ap);
387 fprintf(stderr, "qemu: fatal: ");
388 vfprintf(stderr, fmt, ap);
389 fprintf(stderr, "\n");
390 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
391 if (qemu_log_separate()) {
392 FILE *logfile = qemu_log_lock();
393 qemu_log("qemu: fatal: ");
394 qemu_log_vprintf(fmt, ap2);
395 qemu_log("\n");
396 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
397 qemu_log_flush();
398 qemu_log_unlock(logfile);
399 qemu_log_close();
401 va_end(ap2);
402 va_end(ap);
403 replay_finish();
404 #if defined(CONFIG_USER_ONLY)
406 struct sigaction act;
407 sigfillset(&act.sa_mask);
408 act.sa_handler = SIG_DFL;
409 act.sa_flags = 0;
410 sigaction(SIGABRT, &act, NULL);
412 #endif
413 abort();
416 /* physical memory access (slow version, mainly for debug) */
417 #if defined(CONFIG_USER_ONLY)
418 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
419 void *ptr, target_ulong len, bool is_write)
421 int flags;
422 target_ulong l, page;
423 void * p;
424 uint8_t *buf = ptr;
426 while (len > 0) {
427 page = addr & TARGET_PAGE_MASK;
428 l = (page + TARGET_PAGE_SIZE) - addr;
429 if (l > len)
430 l = len;
431 flags = page_get_flags(page);
432 if (!(flags & PAGE_VALID))
433 return -1;
434 if (is_write) {
435 if (!(flags & PAGE_WRITE))
436 return -1;
437 /* XXX: this code should not depend on lock_user */
438 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
439 return -1;
440 memcpy(p, buf, l);
441 unlock_user(p, addr, l);
442 } else {
443 if (!(flags & PAGE_READ))
444 return -1;
445 /* XXX: this code should not depend on lock_user */
446 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
447 return -1;
448 memcpy(buf, p, l);
449 unlock_user(p, addr, 0);
451 len -= l;
452 buf += l;
453 addr += l;
455 return 0;
457 #endif
459 bool target_words_bigendian(void)
461 #if defined(TARGET_WORDS_BIGENDIAN)
462 return true;
463 #else
464 return false;
465 #endif
468 void page_size_init(void)
470 /* NOTE: we can always suppose that qemu_host_page_size >=
471 TARGET_PAGE_SIZE */
472 if (qemu_host_page_size == 0) {
473 qemu_host_page_size = qemu_real_host_page_size;
475 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
476 qemu_host_page_size = TARGET_PAGE_SIZE;
478 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;