2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qapi/visitor.h"
32 #include "hw/qdev-properties.h"
34 //#define PPC_DUMP_CPU
35 //#define PPC_DEBUG_SPR
36 //#define PPC_DUMP_SPR_ACCESSES
37 /* #define USE_APPLE_GDB */
39 /* For user-mode emulation, we don't emulate any IRQ controller */
40 #if defined(CONFIG_USER_ONLY)
41 #define PPC_IRQ_INIT_FN(name) \
42 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
46 #define PPC_IRQ_INIT_FN(name) \
47 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
53 PPC_IRQ_INIT_FN(POWER7
);
54 PPC_IRQ_INIT_FN(e500
);
57 * do nothing but store/retrieve spr value
59 static void spr_load_dump_spr(int sprn
)
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0
= tcg_const_i32(sprn
);
63 gen_helper_load_dump_spr(cpu_env
, t0
);
64 tcg_temp_free_i32(t0
);
68 static void spr_read_generic (void *opaque
, int gprn
, int sprn
)
70 gen_load_spr(cpu_gpr
[gprn
], sprn
);
71 spr_load_dump_spr(sprn
);
74 static void spr_store_dump_spr(int sprn
)
76 #ifdef PPC_DUMP_SPR_ACCESSES
77 TCGv_i32 t0
= tcg_const_i32(sprn
);
78 gen_helper_store_dump_spr(cpu_env
, t0
);
79 tcg_temp_free_i32(t0
);
83 static void spr_write_generic (void *opaque
, int sprn
, int gprn
)
85 gen_store_spr(sprn
, cpu_gpr
[gprn
]);
86 spr_store_dump_spr(sprn
);
89 #if !defined(CONFIG_USER_ONLY)
90 static void spr_write_generic32(void *opaque
, int sprn
, int gprn
)
93 TCGv t0
= tcg_temp_new();
94 tcg_gen_ext32u_tl(t0
, cpu_gpr
[gprn
]);
95 gen_store_spr(sprn
, t0
);
97 spr_store_dump_spr(sprn
);
99 spr_write_generic(opaque
, sprn
, gprn
);
103 static void spr_write_clear (void *opaque
, int sprn
, int gprn
)
105 TCGv t0
= tcg_temp_new();
106 TCGv t1
= tcg_temp_new();
107 gen_load_spr(t0
, sprn
);
108 tcg_gen_neg_tl(t1
, cpu_gpr
[gprn
]);
109 tcg_gen_and_tl(t0
, t0
, t1
);
110 gen_store_spr(sprn
, t0
);
115 static void spr_access_nop(void *opaque
, int sprn
, int gprn
)
121 /* SPR common to all PowerPC */
123 static void spr_read_xer (void *opaque
, int gprn
, int sprn
)
125 gen_read_xer(cpu_gpr
[gprn
]);
128 static void spr_write_xer (void *opaque
, int sprn
, int gprn
)
130 gen_write_xer(cpu_gpr
[gprn
]);
134 static void spr_read_lr (void *opaque
, int gprn
, int sprn
)
136 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_lr
);
139 static void spr_write_lr (void *opaque
, int sprn
, int gprn
)
141 tcg_gen_mov_tl(cpu_lr
, cpu_gpr
[gprn
]);
145 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
146 static void spr_read_cfar (void *opaque
, int gprn
, int sprn
)
148 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_cfar
);
151 static void spr_write_cfar (void *opaque
, int sprn
, int gprn
)
153 tcg_gen_mov_tl(cpu_cfar
, cpu_gpr
[gprn
]);
155 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
158 static void spr_read_ctr (void *opaque
, int gprn
, int sprn
)
160 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_ctr
);
163 static void spr_write_ctr (void *opaque
, int sprn
, int gprn
)
165 tcg_gen_mov_tl(cpu_ctr
, cpu_gpr
[gprn
]);
168 /* User read access to SPR */
174 static void spr_read_ureg (void *opaque
, int gprn
, int sprn
)
176 gen_load_spr(cpu_gpr
[gprn
], sprn
+ 0x10);
179 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
180 static void spr_write_ureg(void *opaque
, int sprn
, int gprn
)
182 gen_store_spr(sprn
+ 0x10, cpu_gpr
[gprn
]);
186 /* SPR common to all non-embedded PowerPC */
188 #if !defined(CONFIG_USER_ONLY)
189 static void spr_read_decr (void *opaque
, int gprn
, int sprn
)
194 gen_helper_load_decr(cpu_gpr
[gprn
], cpu_env
);
197 gen_stop_exception(opaque
);
201 static void spr_write_decr (void *opaque
, int sprn
, int gprn
)
206 gen_helper_store_decr(cpu_env
, cpu_gpr
[gprn
]);
209 gen_stop_exception(opaque
);
214 /* SPR common to all non-embedded PowerPC, except 601 */
216 static void spr_read_tbl (void *opaque
, int gprn
, int sprn
)
221 gen_helper_load_tbl(cpu_gpr
[gprn
], cpu_env
);
224 gen_stop_exception(opaque
);
228 static void spr_read_tbu (void *opaque
, int gprn
, int sprn
)
233 gen_helper_load_tbu(cpu_gpr
[gprn
], cpu_env
);
236 gen_stop_exception(opaque
);
240 __attribute__ (( unused
))
241 static void spr_read_atbl (void *opaque
, int gprn
, int sprn
)
243 gen_helper_load_atbl(cpu_gpr
[gprn
], cpu_env
);
246 __attribute__ (( unused
))
247 static void spr_read_atbu (void *opaque
, int gprn
, int sprn
)
249 gen_helper_load_atbu(cpu_gpr
[gprn
], cpu_env
);
252 #if !defined(CONFIG_USER_ONLY)
253 static void spr_write_tbl (void *opaque
, int sprn
, int gprn
)
258 gen_helper_store_tbl(cpu_env
, cpu_gpr
[gprn
]);
261 gen_stop_exception(opaque
);
265 static void spr_write_tbu (void *opaque
, int sprn
, int gprn
)
270 gen_helper_store_tbu(cpu_env
, cpu_gpr
[gprn
]);
273 gen_stop_exception(opaque
);
277 __attribute__ (( unused
))
278 static void spr_write_atbl (void *opaque
, int sprn
, int gprn
)
280 gen_helper_store_atbl(cpu_env
, cpu_gpr
[gprn
]);
283 __attribute__ (( unused
))
284 static void spr_write_atbu (void *opaque
, int sprn
, int gprn
)
286 gen_helper_store_atbu(cpu_env
, cpu_gpr
[gprn
]);
289 #if defined(TARGET_PPC64)
290 __attribute__ (( unused
))
291 static void spr_read_purr (void *opaque
, int gprn
, int sprn
)
293 gen_helper_load_purr(cpu_gpr
[gprn
], cpu_env
);
298 #if !defined(CONFIG_USER_ONLY)
299 /* IBAT0U...IBAT0U */
300 /* IBAT0L...IBAT7L */
301 static void spr_read_ibat (void *opaque
, int gprn
, int sprn
)
303 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
306 static void spr_read_ibat_h (void *opaque
, int gprn
, int sprn
)
308 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT4U
) / 2]));
311 static void spr_write_ibatu (void *opaque
, int sprn
, int gprn
)
313 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
314 gen_helper_store_ibatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
315 tcg_temp_free_i32(t0
);
318 static void spr_write_ibatu_h (void *opaque
, int sprn
, int gprn
)
320 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_IBAT4U
) / 2) + 4);
321 gen_helper_store_ibatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
322 tcg_temp_free_i32(t0
);
325 static void spr_write_ibatl (void *opaque
, int sprn
, int gprn
)
327 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0L
) / 2);
328 gen_helper_store_ibatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
329 tcg_temp_free_i32(t0
);
332 static void spr_write_ibatl_h (void *opaque
, int sprn
, int gprn
)
334 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_IBAT4L
) / 2) + 4);
335 gen_helper_store_ibatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
336 tcg_temp_free_i32(t0
);
339 /* DBAT0U...DBAT7U */
340 /* DBAT0L...DBAT7L */
341 static void spr_read_dbat (void *opaque
, int gprn
, int sprn
)
343 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, DBAT
[sprn
& 1][(sprn
- SPR_DBAT0U
) / 2]));
346 static void spr_read_dbat_h (void *opaque
, int gprn
, int sprn
)
348 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, DBAT
[sprn
& 1][((sprn
- SPR_DBAT4U
) / 2) + 4]));
351 static void spr_write_dbatu (void *opaque
, int sprn
, int gprn
)
353 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0U
) / 2);
354 gen_helper_store_dbatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
355 tcg_temp_free_i32(t0
);
358 static void spr_write_dbatu_h (void *opaque
, int sprn
, int gprn
)
360 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4U
) / 2) + 4);
361 gen_helper_store_dbatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
362 tcg_temp_free_i32(t0
);
365 static void spr_write_dbatl (void *opaque
, int sprn
, int gprn
)
367 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0L
) / 2);
368 gen_helper_store_dbatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
369 tcg_temp_free_i32(t0
);
372 static void spr_write_dbatl_h (void *opaque
, int sprn
, int gprn
)
374 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4L
) / 2) + 4);
375 gen_helper_store_dbatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
376 tcg_temp_free_i32(t0
);
380 static void spr_write_sdr1 (void *opaque
, int sprn
, int gprn
)
382 gen_helper_store_sdr1(cpu_env
, cpu_gpr
[gprn
]);
385 /* 64 bits PowerPC specific SPRs */
386 #if defined(TARGET_PPC64)
387 static void spr_read_hior (void *opaque
, int gprn
, int sprn
)
389 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, excp_prefix
));
392 static void spr_write_hior (void *opaque
, int sprn
, int gprn
)
394 TCGv t0
= tcg_temp_new();
395 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], 0x3FFFFF00000ULL
);
396 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, excp_prefix
));
402 /* PowerPC 601 specific registers */
404 static void spr_read_601_rtcl (void *opaque
, int gprn
, int sprn
)
406 gen_helper_load_601_rtcl(cpu_gpr
[gprn
], cpu_env
);
409 static void spr_read_601_rtcu (void *opaque
, int gprn
, int sprn
)
411 gen_helper_load_601_rtcu(cpu_gpr
[gprn
], cpu_env
);
414 #if !defined(CONFIG_USER_ONLY)
415 static void spr_write_601_rtcu (void *opaque
, int sprn
, int gprn
)
417 gen_helper_store_601_rtcu(cpu_env
, cpu_gpr
[gprn
]);
420 static void spr_write_601_rtcl (void *opaque
, int sprn
, int gprn
)
422 gen_helper_store_601_rtcl(cpu_env
, cpu_gpr
[gprn
]);
425 static void spr_write_hid0_601 (void *opaque
, int sprn
, int gprn
)
427 DisasContext
*ctx
= opaque
;
429 gen_helper_store_hid0_601(cpu_env
, cpu_gpr
[gprn
]);
430 /* Must stop the translation as endianness may have changed */
431 gen_stop_exception(ctx
);
436 #if !defined(CONFIG_USER_ONLY)
437 static void spr_read_601_ubat (void *opaque
, int gprn
, int sprn
)
439 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
442 static void spr_write_601_ubatu (void *opaque
, int sprn
, int gprn
)
444 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
445 gen_helper_store_601_batl(cpu_env
, t0
, cpu_gpr
[gprn
]);
446 tcg_temp_free_i32(t0
);
449 static void spr_write_601_ubatl (void *opaque
, int sprn
, int gprn
)
451 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
452 gen_helper_store_601_batu(cpu_env
, t0
, cpu_gpr
[gprn
]);
453 tcg_temp_free_i32(t0
);
457 /* PowerPC 40x specific registers */
458 #if !defined(CONFIG_USER_ONLY)
459 static void spr_read_40x_pit (void *opaque
, int gprn
, int sprn
)
461 gen_helper_load_40x_pit(cpu_gpr
[gprn
], cpu_env
);
464 static void spr_write_40x_pit (void *opaque
, int sprn
, int gprn
)
466 gen_helper_store_40x_pit(cpu_env
, cpu_gpr
[gprn
]);
469 static void spr_write_40x_dbcr0 (void *opaque
, int sprn
, int gprn
)
471 DisasContext
*ctx
= opaque
;
473 gen_helper_store_40x_dbcr0(cpu_env
, cpu_gpr
[gprn
]);
474 /* We must stop translation as we may have rebooted */
475 gen_stop_exception(ctx
);
478 static void spr_write_40x_sler (void *opaque
, int sprn
, int gprn
)
480 gen_helper_store_40x_sler(cpu_env
, cpu_gpr
[gprn
]);
483 static void spr_write_booke_tcr (void *opaque
, int sprn
, int gprn
)
485 gen_helper_store_booke_tcr(cpu_env
, cpu_gpr
[gprn
]);
488 static void spr_write_booke_tsr (void *opaque
, int sprn
, int gprn
)
490 gen_helper_store_booke_tsr(cpu_env
, cpu_gpr
[gprn
]);
494 /* PowerPC 403 specific registers */
495 /* PBL1 / PBU1 / PBL2 / PBU2 */
496 #if !defined(CONFIG_USER_ONLY)
497 static void spr_read_403_pbr (void *opaque
, int gprn
, int sprn
)
499 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, pb
[sprn
- SPR_403_PBL1
]));
502 static void spr_write_403_pbr (void *opaque
, int sprn
, int gprn
)
504 TCGv_i32 t0
= tcg_const_i32(sprn
- SPR_403_PBL1
);
505 gen_helper_store_403_pbr(cpu_env
, t0
, cpu_gpr
[gprn
]);
506 tcg_temp_free_i32(t0
);
509 static void spr_write_pir (void *opaque
, int sprn
, int gprn
)
511 TCGv t0
= tcg_temp_new();
512 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], 0xF);
513 gen_store_spr(SPR_PIR
, t0
);
518 /* SPE specific registers */
519 static void spr_read_spefscr (void *opaque
, int gprn
, int sprn
)
521 TCGv_i32 t0
= tcg_temp_new_i32();
522 tcg_gen_ld_i32(t0
, cpu_env
, offsetof(CPUPPCState
, spe_fscr
));
523 tcg_gen_extu_i32_tl(cpu_gpr
[gprn
], t0
);
524 tcg_temp_free_i32(t0
);
527 static void spr_write_spefscr (void *opaque
, int sprn
, int gprn
)
529 TCGv_i32 t0
= tcg_temp_new_i32();
530 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[gprn
]);
531 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUPPCState
, spe_fscr
));
532 tcg_temp_free_i32(t0
);
535 #if !defined(CONFIG_USER_ONLY)
536 /* Callback used to write the exception vector base */
537 static void spr_write_excp_prefix (void *opaque
, int sprn
, int gprn
)
539 TCGv t0
= tcg_temp_new();
540 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUPPCState
, ivpr_mask
));
541 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
542 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, excp_prefix
));
543 gen_store_spr(sprn
, t0
);
547 static void spr_write_excp_vector (void *opaque
, int sprn
, int gprn
)
549 DisasContext
*ctx
= opaque
;
552 if (sprn
>= SPR_BOOKE_IVOR0
&& sprn
<= SPR_BOOKE_IVOR15
) {
553 sprn_offs
= sprn
- SPR_BOOKE_IVOR0
;
554 } else if (sprn
>= SPR_BOOKE_IVOR32
&& sprn
<= SPR_BOOKE_IVOR37
) {
555 sprn_offs
= sprn
- SPR_BOOKE_IVOR32
+ 32;
556 } else if (sprn
>= SPR_BOOKE_IVOR38
&& sprn
<= SPR_BOOKE_IVOR42
) {
557 sprn_offs
= sprn
- SPR_BOOKE_IVOR38
+ 38;
559 printf("Trying to write an unknown exception vector %d %03x\n",
561 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
565 TCGv t0
= tcg_temp_new();
566 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUPPCState
, ivor_mask
));
567 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
568 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, excp_vectors
[sprn_offs
]));
569 gen_store_spr(sprn
, t0
);
574 static inline void vscr_init (CPUPPCState
*env
, uint32_t val
)
577 /* Altivec always uses round-to-nearest */
578 set_float_rounding_mode(float_round_nearest_even
, &env
->vec_status
);
579 set_flush_to_zero(vscr_nj
, &env
->vec_status
);
582 #ifdef CONFIG_USER_ONLY
583 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, initial_value)
587 #if !defined(CONFIG_KVM)
588 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
589 oea_read, oea_write, one_reg_id, initial_value) \
590 _spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, initial_value)
593 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
594 oea_read, oea_write, one_reg_id, initial_value) \
595 _spr_register(env, num, name, uea_read, uea_write, \
596 oea_read, oea_write, one_reg_id, initial_value)
600 #define spr_register(env, num, name, uea_read, uea_write, \
601 oea_read, oea_write, initial_value) \
602 spr_register_kvm(env, num, name, uea_read, uea_write, \
603 oea_read, oea_write, 0, initial_value)
605 static inline void _spr_register(CPUPPCState
*env
, int num
,
607 void (*uea_read
)(void *opaque
, int gprn
, int sprn
),
608 void (*uea_write
)(void *opaque
, int sprn
, int gprn
),
609 #if !defined(CONFIG_USER_ONLY)
611 void (*oea_read
)(void *opaque
, int gprn
, int sprn
),
612 void (*oea_write
)(void *opaque
, int sprn
, int gprn
),
614 #if defined(CONFIG_KVM)
617 target_ulong initial_value
)
621 spr
= &env
->spr_cb
[num
];
622 if (spr
->name
!= NULL
||env
-> spr
[num
] != 0x00000000 ||
623 #if !defined(CONFIG_USER_ONLY)
624 spr
->oea_read
!= NULL
|| spr
->oea_write
!= NULL
||
626 spr
->uea_read
!= NULL
|| spr
->uea_write
!= NULL
) {
627 printf("Error: Trying to register SPR %d (%03x) twice !\n", num
, num
);
630 #if defined(PPC_DEBUG_SPR)
631 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx
"\n", num
, num
,
632 name
, initial_value
);
635 spr
->uea_read
= uea_read
;
636 spr
->uea_write
= uea_write
;
637 #if !defined(CONFIG_USER_ONLY)
638 spr
->oea_read
= oea_read
;
639 spr
->oea_write
= oea_write
;
641 #if defined(CONFIG_KVM)
642 spr
->one_reg_id
= one_reg_id
,
644 env
->spr
[num
] = spr
->default_value
= initial_value
;
647 /* Generic PowerPC SPRs */
648 static void gen_spr_generic (CPUPPCState
*env
)
650 /* Integer processing */
651 spr_register(env
, SPR_XER
, "XER",
652 &spr_read_xer
, &spr_write_xer
,
653 &spr_read_xer
, &spr_write_xer
,
656 spr_register(env
, SPR_LR
, "LR",
657 &spr_read_lr
, &spr_write_lr
,
658 &spr_read_lr
, &spr_write_lr
,
660 spr_register(env
, SPR_CTR
, "CTR",
661 &spr_read_ctr
, &spr_write_ctr
,
662 &spr_read_ctr
, &spr_write_ctr
,
664 /* Interrupt processing */
665 spr_register(env
, SPR_SRR0
, "SRR0",
666 SPR_NOACCESS
, SPR_NOACCESS
,
667 &spr_read_generic
, &spr_write_generic
,
669 spr_register(env
, SPR_SRR1
, "SRR1",
670 SPR_NOACCESS
, SPR_NOACCESS
,
671 &spr_read_generic
, &spr_write_generic
,
673 /* Processor control */
674 spr_register(env
, SPR_SPRG0
, "SPRG0",
675 SPR_NOACCESS
, SPR_NOACCESS
,
676 &spr_read_generic
, &spr_write_generic
,
678 spr_register(env
, SPR_SPRG1
, "SPRG1",
679 SPR_NOACCESS
, SPR_NOACCESS
,
680 &spr_read_generic
, &spr_write_generic
,
682 spr_register(env
, SPR_SPRG2
, "SPRG2",
683 SPR_NOACCESS
, SPR_NOACCESS
,
684 &spr_read_generic
, &spr_write_generic
,
686 spr_register(env
, SPR_SPRG3
, "SPRG3",
687 SPR_NOACCESS
, SPR_NOACCESS
,
688 &spr_read_generic
, &spr_write_generic
,
692 /* SPR common to all non-embedded PowerPC, including 601 */
693 static void gen_spr_ne_601 (CPUPPCState
*env
)
695 /* Exception processing */
696 spr_register_kvm(env
, SPR_DSISR
, "DSISR",
697 SPR_NOACCESS
, SPR_NOACCESS
,
698 &spr_read_generic
, &spr_write_generic
,
699 KVM_REG_PPC_DSISR
, 0x00000000);
700 spr_register_kvm(env
, SPR_DAR
, "DAR",
701 SPR_NOACCESS
, SPR_NOACCESS
,
702 &spr_read_generic
, &spr_write_generic
,
703 KVM_REG_PPC_DAR
, 0x00000000);
705 spr_register(env
, SPR_DECR
, "DECR",
706 SPR_NOACCESS
, SPR_NOACCESS
,
707 &spr_read_decr
, &spr_write_decr
,
709 /* Memory management */
710 spr_register(env
, SPR_SDR1
, "SDR1",
711 SPR_NOACCESS
, SPR_NOACCESS
,
712 &spr_read_generic
, &spr_write_sdr1
,
717 static void gen_low_BATs (CPUPPCState
*env
)
719 #if !defined(CONFIG_USER_ONLY)
720 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
721 SPR_NOACCESS
, SPR_NOACCESS
,
722 &spr_read_ibat
, &spr_write_ibatu
,
724 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
725 SPR_NOACCESS
, SPR_NOACCESS
,
726 &spr_read_ibat
, &spr_write_ibatl
,
728 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
729 SPR_NOACCESS
, SPR_NOACCESS
,
730 &spr_read_ibat
, &spr_write_ibatu
,
732 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
733 SPR_NOACCESS
, SPR_NOACCESS
,
734 &spr_read_ibat
, &spr_write_ibatl
,
736 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
737 SPR_NOACCESS
, SPR_NOACCESS
,
738 &spr_read_ibat
, &spr_write_ibatu
,
740 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
741 SPR_NOACCESS
, SPR_NOACCESS
,
742 &spr_read_ibat
, &spr_write_ibatl
,
744 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
745 SPR_NOACCESS
, SPR_NOACCESS
,
746 &spr_read_ibat
, &spr_write_ibatu
,
748 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
749 SPR_NOACCESS
, SPR_NOACCESS
,
750 &spr_read_ibat
, &spr_write_ibatl
,
752 spr_register(env
, SPR_DBAT0U
, "DBAT0U",
753 SPR_NOACCESS
, SPR_NOACCESS
,
754 &spr_read_dbat
, &spr_write_dbatu
,
756 spr_register(env
, SPR_DBAT0L
, "DBAT0L",
757 SPR_NOACCESS
, SPR_NOACCESS
,
758 &spr_read_dbat
, &spr_write_dbatl
,
760 spr_register(env
, SPR_DBAT1U
, "DBAT1U",
761 SPR_NOACCESS
, SPR_NOACCESS
,
762 &spr_read_dbat
, &spr_write_dbatu
,
764 spr_register(env
, SPR_DBAT1L
, "DBAT1L",
765 SPR_NOACCESS
, SPR_NOACCESS
,
766 &spr_read_dbat
, &spr_write_dbatl
,
768 spr_register(env
, SPR_DBAT2U
, "DBAT2U",
769 SPR_NOACCESS
, SPR_NOACCESS
,
770 &spr_read_dbat
, &spr_write_dbatu
,
772 spr_register(env
, SPR_DBAT2L
, "DBAT2L",
773 SPR_NOACCESS
, SPR_NOACCESS
,
774 &spr_read_dbat
, &spr_write_dbatl
,
776 spr_register(env
, SPR_DBAT3U
, "DBAT3U",
777 SPR_NOACCESS
, SPR_NOACCESS
,
778 &spr_read_dbat
, &spr_write_dbatu
,
780 spr_register(env
, SPR_DBAT3L
, "DBAT3L",
781 SPR_NOACCESS
, SPR_NOACCESS
,
782 &spr_read_dbat
, &spr_write_dbatl
,
789 static void gen_high_BATs (CPUPPCState
*env
)
791 #if !defined(CONFIG_USER_ONLY)
792 spr_register(env
, SPR_IBAT4U
, "IBAT4U",
793 SPR_NOACCESS
, SPR_NOACCESS
,
794 &spr_read_ibat_h
, &spr_write_ibatu_h
,
796 spr_register(env
, SPR_IBAT4L
, "IBAT4L",
797 SPR_NOACCESS
, SPR_NOACCESS
,
798 &spr_read_ibat_h
, &spr_write_ibatl_h
,
800 spr_register(env
, SPR_IBAT5U
, "IBAT5U",
801 SPR_NOACCESS
, SPR_NOACCESS
,
802 &spr_read_ibat_h
, &spr_write_ibatu_h
,
804 spr_register(env
, SPR_IBAT5L
, "IBAT5L",
805 SPR_NOACCESS
, SPR_NOACCESS
,
806 &spr_read_ibat_h
, &spr_write_ibatl_h
,
808 spr_register(env
, SPR_IBAT6U
, "IBAT6U",
809 SPR_NOACCESS
, SPR_NOACCESS
,
810 &spr_read_ibat_h
, &spr_write_ibatu_h
,
812 spr_register(env
, SPR_IBAT6L
, "IBAT6L",
813 SPR_NOACCESS
, SPR_NOACCESS
,
814 &spr_read_ibat_h
, &spr_write_ibatl_h
,
816 spr_register(env
, SPR_IBAT7U
, "IBAT7U",
817 SPR_NOACCESS
, SPR_NOACCESS
,
818 &spr_read_ibat_h
, &spr_write_ibatu_h
,
820 spr_register(env
, SPR_IBAT7L
, "IBAT7L",
821 SPR_NOACCESS
, SPR_NOACCESS
,
822 &spr_read_ibat_h
, &spr_write_ibatl_h
,
824 spr_register(env
, SPR_DBAT4U
, "DBAT4U",
825 SPR_NOACCESS
, SPR_NOACCESS
,
826 &spr_read_dbat_h
, &spr_write_dbatu_h
,
828 spr_register(env
, SPR_DBAT4L
, "DBAT4L",
829 SPR_NOACCESS
, SPR_NOACCESS
,
830 &spr_read_dbat_h
, &spr_write_dbatl_h
,
832 spr_register(env
, SPR_DBAT5U
, "DBAT5U",
833 SPR_NOACCESS
, SPR_NOACCESS
,
834 &spr_read_dbat_h
, &spr_write_dbatu_h
,
836 spr_register(env
, SPR_DBAT5L
, "DBAT5L",
837 SPR_NOACCESS
, SPR_NOACCESS
,
838 &spr_read_dbat_h
, &spr_write_dbatl_h
,
840 spr_register(env
, SPR_DBAT6U
, "DBAT6U",
841 SPR_NOACCESS
, SPR_NOACCESS
,
842 &spr_read_dbat_h
, &spr_write_dbatu_h
,
844 spr_register(env
, SPR_DBAT6L
, "DBAT6L",
845 SPR_NOACCESS
, SPR_NOACCESS
,
846 &spr_read_dbat_h
, &spr_write_dbatl_h
,
848 spr_register(env
, SPR_DBAT7U
, "DBAT7U",
849 SPR_NOACCESS
, SPR_NOACCESS
,
850 &spr_read_dbat_h
, &spr_write_dbatu_h
,
852 spr_register(env
, SPR_DBAT7L
, "DBAT7L",
853 SPR_NOACCESS
, SPR_NOACCESS
,
854 &spr_read_dbat_h
, &spr_write_dbatl_h
,
860 /* Generic PowerPC time base */
861 static void gen_tbl (CPUPPCState
*env
)
863 spr_register(env
, SPR_VTBL
, "TBL",
864 &spr_read_tbl
, SPR_NOACCESS
,
865 &spr_read_tbl
, SPR_NOACCESS
,
867 spr_register(env
, SPR_TBL
, "TBL",
868 &spr_read_tbl
, SPR_NOACCESS
,
869 &spr_read_tbl
, &spr_write_tbl
,
871 spr_register(env
, SPR_VTBU
, "TBU",
872 &spr_read_tbu
, SPR_NOACCESS
,
873 &spr_read_tbu
, SPR_NOACCESS
,
875 spr_register(env
, SPR_TBU
, "TBU",
876 &spr_read_tbu
, SPR_NOACCESS
,
877 &spr_read_tbu
, &spr_write_tbu
,
881 /* Softare table search registers */
882 static void gen_6xx_7xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
884 #if !defined(CONFIG_USER_ONLY)
885 env
->nb_tlb
= nb_tlbs
;
886 env
->nb_ways
= nb_ways
;
888 env
->tlb_type
= TLB_6XX
;
889 spr_register(env
, SPR_DMISS
, "DMISS",
890 SPR_NOACCESS
, SPR_NOACCESS
,
891 &spr_read_generic
, SPR_NOACCESS
,
893 spr_register(env
, SPR_DCMP
, "DCMP",
894 SPR_NOACCESS
, SPR_NOACCESS
,
895 &spr_read_generic
, SPR_NOACCESS
,
897 spr_register(env
, SPR_HASH1
, "HASH1",
898 SPR_NOACCESS
, SPR_NOACCESS
,
899 &spr_read_generic
, SPR_NOACCESS
,
901 spr_register(env
, SPR_HASH2
, "HASH2",
902 SPR_NOACCESS
, SPR_NOACCESS
,
903 &spr_read_generic
, SPR_NOACCESS
,
905 spr_register(env
, SPR_IMISS
, "IMISS",
906 SPR_NOACCESS
, SPR_NOACCESS
,
907 &spr_read_generic
, SPR_NOACCESS
,
909 spr_register(env
, SPR_ICMP
, "ICMP",
910 SPR_NOACCESS
, SPR_NOACCESS
,
911 &spr_read_generic
, SPR_NOACCESS
,
913 spr_register(env
, SPR_RPA
, "RPA",
914 SPR_NOACCESS
, SPR_NOACCESS
,
915 &spr_read_generic
, &spr_write_generic
,
920 /* SPR common to MPC755 and G2 */
921 static void gen_spr_G2_755 (CPUPPCState
*env
)
924 spr_register(env
, SPR_SPRG4
, "SPRG4",
925 SPR_NOACCESS
, SPR_NOACCESS
,
926 &spr_read_generic
, &spr_write_generic
,
928 spr_register(env
, SPR_SPRG5
, "SPRG5",
929 SPR_NOACCESS
, SPR_NOACCESS
,
930 &spr_read_generic
, &spr_write_generic
,
932 spr_register(env
, SPR_SPRG6
, "SPRG6",
933 SPR_NOACCESS
, SPR_NOACCESS
,
934 &spr_read_generic
, &spr_write_generic
,
936 spr_register(env
, SPR_SPRG7
, "SPRG7",
937 SPR_NOACCESS
, SPR_NOACCESS
,
938 &spr_read_generic
, &spr_write_generic
,
942 /* SPR common to all 7xx PowerPC implementations */
943 static void gen_spr_7xx (CPUPPCState
*env
)
946 /* XXX : not implemented */
947 spr_register_kvm(env
, SPR_DABR
, "DABR",
948 SPR_NOACCESS
, SPR_NOACCESS
,
949 &spr_read_generic
, &spr_write_generic
,
950 KVM_REG_PPC_DABR
, 0x00000000);
951 /* XXX : not implemented */
952 spr_register(env
, SPR_IABR
, "IABR",
953 SPR_NOACCESS
, SPR_NOACCESS
,
954 &spr_read_generic
, &spr_write_generic
,
956 /* Cache management */
957 /* XXX : not implemented */
958 spr_register(env
, SPR_ICTC
, "ICTC",
959 SPR_NOACCESS
, SPR_NOACCESS
,
960 &spr_read_generic
, &spr_write_generic
,
962 /* Performance monitors */
963 /* XXX : not implemented */
964 spr_register(env
, SPR_7XX_MMCR0
, "MMCR0",
965 SPR_NOACCESS
, SPR_NOACCESS
,
966 &spr_read_generic
, &spr_write_generic
,
968 /* XXX : not implemented */
969 spr_register(env
, SPR_7XX_MMCR1
, "MMCR1",
970 SPR_NOACCESS
, SPR_NOACCESS
,
971 &spr_read_generic
, &spr_write_generic
,
973 /* XXX : not implemented */
974 spr_register(env
, SPR_7XX_PMC1
, "PMC1",
975 SPR_NOACCESS
, SPR_NOACCESS
,
976 &spr_read_generic
, &spr_write_generic
,
978 /* XXX : not implemented */
979 spr_register(env
, SPR_7XX_PMC2
, "PMC2",
980 SPR_NOACCESS
, SPR_NOACCESS
,
981 &spr_read_generic
, &spr_write_generic
,
983 /* XXX : not implemented */
984 spr_register(env
, SPR_7XX_PMC3
, "PMC3",
985 SPR_NOACCESS
, SPR_NOACCESS
,
986 &spr_read_generic
, &spr_write_generic
,
988 /* XXX : not implemented */
989 spr_register(env
, SPR_7XX_PMC4
, "PMC4",
990 SPR_NOACCESS
, SPR_NOACCESS
,
991 &spr_read_generic
, &spr_write_generic
,
993 /* XXX : not implemented */
994 spr_register(env
, SPR_7XX_SIAR
, "SIAR",
995 SPR_NOACCESS
, SPR_NOACCESS
,
996 &spr_read_generic
, SPR_NOACCESS
,
998 /* XXX : not implemented */
999 spr_register(env
, SPR_7XX_UMMCR0
, "UMMCR0",
1000 &spr_read_ureg
, SPR_NOACCESS
,
1001 &spr_read_ureg
, SPR_NOACCESS
,
1003 /* XXX : not implemented */
1004 spr_register(env
, SPR_7XX_UMMCR1
, "UMMCR1",
1005 &spr_read_ureg
, SPR_NOACCESS
,
1006 &spr_read_ureg
, SPR_NOACCESS
,
1008 /* XXX : not implemented */
1009 spr_register(env
, SPR_7XX_UPMC1
, "UPMC1",
1010 &spr_read_ureg
, SPR_NOACCESS
,
1011 &spr_read_ureg
, SPR_NOACCESS
,
1013 /* XXX : not implemented */
1014 spr_register(env
, SPR_7XX_UPMC2
, "UPMC2",
1015 &spr_read_ureg
, SPR_NOACCESS
,
1016 &spr_read_ureg
, SPR_NOACCESS
,
1018 /* XXX : not implemented */
1019 spr_register(env
, SPR_7XX_UPMC3
, "UPMC3",
1020 &spr_read_ureg
, SPR_NOACCESS
,
1021 &spr_read_ureg
, SPR_NOACCESS
,
1023 /* XXX : not implemented */
1024 spr_register(env
, SPR_7XX_UPMC4
, "UPMC4",
1025 &spr_read_ureg
, SPR_NOACCESS
,
1026 &spr_read_ureg
, SPR_NOACCESS
,
1028 /* XXX : not implemented */
1029 spr_register(env
, SPR_7XX_USIAR
, "USIAR",
1030 &spr_read_ureg
, SPR_NOACCESS
,
1031 &spr_read_ureg
, SPR_NOACCESS
,
1033 /* External access control */
1034 /* XXX : not implemented */
1035 spr_register(env
, SPR_EAR
, "EAR",
1036 SPR_NOACCESS
, SPR_NOACCESS
,
1037 &spr_read_generic
, &spr_write_generic
,
1042 #ifndef CONFIG_USER_ONLY
1043 static void spr_read_uamr (void *opaque
, int gprn
, int sprn
)
1045 gen_load_spr(cpu_gpr
[gprn
], SPR_AMR
);
1046 spr_load_dump_spr(SPR_AMR
);
1049 static void spr_write_uamr (void *opaque
, int sprn
, int gprn
)
1051 gen_store_spr(SPR_AMR
, cpu_gpr
[gprn
]);
1052 spr_store_dump_spr(SPR_AMR
);
1055 static void spr_write_uamr_pr (void *opaque
, int sprn
, int gprn
)
1057 TCGv t0
= tcg_temp_new();
1059 gen_load_spr(t0
, SPR_UAMOR
);
1060 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
1061 gen_store_spr(SPR_AMR
, t0
);
1062 spr_store_dump_spr(SPR_AMR
);
1064 #endif /* CONFIG_USER_ONLY */
1066 static void gen_spr_amr (CPUPPCState
*env
)
1068 #ifndef CONFIG_USER_ONLY
1069 /* Virtual Page Class Key protection */
1070 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1071 * userspace accessible, 29 is privileged. So we only need to set
1072 * the kvm ONE_REG id on one of them, we use 29 */
1073 spr_register(env
, SPR_UAMR
, "UAMR",
1074 &spr_read_uamr
, &spr_write_uamr_pr
,
1075 &spr_read_uamr
, &spr_write_uamr
,
1077 spr_register_kvm(env
, SPR_AMR
, "AMR",
1078 SPR_NOACCESS
, SPR_NOACCESS
,
1079 &spr_read_generic
, &spr_write_generic
,
1080 KVM_REG_PPC_AMR
, 0);
1081 spr_register_kvm(env
, SPR_UAMOR
, "UAMOR",
1082 SPR_NOACCESS
, SPR_NOACCESS
,
1083 &spr_read_generic
, &spr_write_generic
,
1084 KVM_REG_PPC_UAMOR
, 0);
1085 #endif /* !CONFIG_USER_ONLY */
1087 #endif /* TARGET_PPC64 */
1089 static void gen_spr_thrm (CPUPPCState
*env
)
1091 /* Thermal management */
1092 /* XXX : not implemented */
1093 spr_register(env
, SPR_THRM1
, "THRM1",
1094 SPR_NOACCESS
, SPR_NOACCESS
,
1095 &spr_read_generic
, &spr_write_generic
,
1097 /* XXX : not implemented */
1098 spr_register(env
, SPR_THRM2
, "THRM2",
1099 SPR_NOACCESS
, SPR_NOACCESS
,
1100 &spr_read_generic
, &spr_write_generic
,
1102 /* XXX : not implemented */
1103 spr_register(env
, SPR_THRM3
, "THRM3",
1104 SPR_NOACCESS
, SPR_NOACCESS
,
1105 &spr_read_generic
, &spr_write_generic
,
1109 /* SPR specific to PowerPC 604 implementation */
1110 static void gen_spr_604 (CPUPPCState
*env
)
1112 /* Processor identification */
1113 spr_register(env
, SPR_PIR
, "PIR",
1114 SPR_NOACCESS
, SPR_NOACCESS
,
1115 &spr_read_generic
, &spr_write_pir
,
1118 /* XXX : not implemented */
1119 spr_register(env
, SPR_IABR
, "IABR",
1120 SPR_NOACCESS
, SPR_NOACCESS
,
1121 &spr_read_generic
, &spr_write_generic
,
1123 /* XXX : not implemented */
1124 spr_register_kvm(env
, SPR_DABR
, "DABR",
1125 SPR_NOACCESS
, SPR_NOACCESS
,
1126 &spr_read_generic
, &spr_write_generic
,
1127 KVM_REG_PPC_DABR
, 0x00000000);
1128 /* Performance counters */
1129 /* XXX : not implemented */
1130 spr_register(env
, SPR_7XX_MMCR0
, "MMCR0",
1131 SPR_NOACCESS
, SPR_NOACCESS
,
1132 &spr_read_generic
, &spr_write_generic
,
1134 /* XXX : not implemented */
1135 spr_register(env
, SPR_7XX_PMC1
, "PMC1",
1136 SPR_NOACCESS
, SPR_NOACCESS
,
1137 &spr_read_generic
, &spr_write_generic
,
1139 /* XXX : not implemented */
1140 spr_register(env
, SPR_7XX_PMC2
, "PMC2",
1141 SPR_NOACCESS
, SPR_NOACCESS
,
1142 &spr_read_generic
, &spr_write_generic
,
1144 /* XXX : not implemented */
1145 spr_register(env
, SPR_7XX_SIAR
, "SIAR",
1146 SPR_NOACCESS
, SPR_NOACCESS
,
1147 &spr_read_generic
, SPR_NOACCESS
,
1149 /* XXX : not implemented */
1150 spr_register(env
, SPR_SDA
, "SDA",
1151 SPR_NOACCESS
, SPR_NOACCESS
,
1152 &spr_read_generic
, SPR_NOACCESS
,
1154 /* External access control */
1155 /* XXX : not implemented */
1156 spr_register(env
, SPR_EAR
, "EAR",
1157 SPR_NOACCESS
, SPR_NOACCESS
,
1158 &spr_read_generic
, &spr_write_generic
,
1162 /* SPR specific to PowerPC 603 implementation */
1163 static void gen_spr_603 (CPUPPCState
*env
)
1165 /* External access control */
1166 /* XXX : not implemented */
1167 spr_register(env
, SPR_EAR
, "EAR",
1168 SPR_NOACCESS
, SPR_NOACCESS
,
1169 &spr_read_generic
, &spr_write_generic
,
1172 /* XXX : not implemented */
1173 spr_register(env
, SPR_IABR
, "IABR",
1174 SPR_NOACCESS
, SPR_NOACCESS
,
1175 &spr_read_generic
, &spr_write_generic
,
1180 /* SPR specific to PowerPC G2 implementation */
1181 static void gen_spr_G2 (CPUPPCState
*env
)
1183 /* Memory base address */
1185 /* XXX : not implemented */
1186 spr_register(env
, SPR_MBAR
, "MBAR",
1187 SPR_NOACCESS
, SPR_NOACCESS
,
1188 &spr_read_generic
, &spr_write_generic
,
1190 /* Exception processing */
1191 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1192 SPR_NOACCESS
, SPR_NOACCESS
,
1193 &spr_read_generic
, &spr_write_generic
,
1195 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1196 SPR_NOACCESS
, SPR_NOACCESS
,
1197 &spr_read_generic
, &spr_write_generic
,
1200 /* XXX : not implemented */
1201 spr_register(env
, SPR_DABR
, "DABR",
1202 SPR_NOACCESS
, SPR_NOACCESS
,
1203 &spr_read_generic
, &spr_write_generic
,
1205 /* XXX : not implemented */
1206 spr_register(env
, SPR_DABR2
, "DABR2",
1207 SPR_NOACCESS
, SPR_NOACCESS
,
1208 &spr_read_generic
, &spr_write_generic
,
1210 /* XXX : not implemented */
1211 spr_register(env
, SPR_IABR
, "IABR",
1212 SPR_NOACCESS
, SPR_NOACCESS
,
1213 &spr_read_generic
, &spr_write_generic
,
1215 /* XXX : not implemented */
1216 spr_register(env
, SPR_IABR2
, "IABR2",
1217 SPR_NOACCESS
, SPR_NOACCESS
,
1218 &spr_read_generic
, &spr_write_generic
,
1220 /* XXX : not implemented */
1221 spr_register(env
, SPR_IBCR
, "IBCR",
1222 SPR_NOACCESS
, SPR_NOACCESS
,
1223 &spr_read_generic
, &spr_write_generic
,
1225 /* XXX : not implemented */
1226 spr_register(env
, SPR_DBCR
, "DBCR",
1227 SPR_NOACCESS
, SPR_NOACCESS
,
1228 &spr_read_generic
, &spr_write_generic
,
1232 /* SPR specific to PowerPC 602 implementation */
1233 static void gen_spr_602 (CPUPPCState
*env
)
1236 /* XXX : not implemented */
1237 spr_register(env
, SPR_SER
, "SER",
1238 SPR_NOACCESS
, SPR_NOACCESS
,
1239 &spr_read_generic
, &spr_write_generic
,
1241 /* XXX : not implemented */
1242 spr_register(env
, SPR_SEBR
, "SEBR",
1243 SPR_NOACCESS
, SPR_NOACCESS
,
1244 &spr_read_generic
, &spr_write_generic
,
1246 /* XXX : not implemented */
1247 spr_register(env
, SPR_ESASRR
, "ESASRR",
1248 SPR_NOACCESS
, SPR_NOACCESS
,
1249 &spr_read_generic
, &spr_write_generic
,
1251 /* Floating point status */
1252 /* XXX : not implemented */
1253 spr_register(env
, SPR_SP
, "SP",
1254 SPR_NOACCESS
, SPR_NOACCESS
,
1255 &spr_read_generic
, &spr_write_generic
,
1257 /* XXX : not implemented */
1258 spr_register(env
, SPR_LT
, "LT",
1259 SPR_NOACCESS
, SPR_NOACCESS
,
1260 &spr_read_generic
, &spr_write_generic
,
1262 /* Watchdog timer */
1263 /* XXX : not implemented */
1264 spr_register(env
, SPR_TCR
, "TCR",
1265 SPR_NOACCESS
, SPR_NOACCESS
,
1266 &spr_read_generic
, &spr_write_generic
,
1268 /* Interrupt base */
1269 spr_register(env
, SPR_IBR
, "IBR",
1270 SPR_NOACCESS
, SPR_NOACCESS
,
1271 &spr_read_generic
, &spr_write_generic
,
1273 /* XXX : not implemented */
1274 spr_register(env
, SPR_IABR
, "IABR",
1275 SPR_NOACCESS
, SPR_NOACCESS
,
1276 &spr_read_generic
, &spr_write_generic
,
1280 /* SPR specific to PowerPC 601 implementation */
1281 static void gen_spr_601 (CPUPPCState
*env
)
1283 /* Multiplication/division register */
1285 spr_register(env
, SPR_MQ
, "MQ",
1286 &spr_read_generic
, &spr_write_generic
,
1287 &spr_read_generic
, &spr_write_generic
,
1290 spr_register(env
, SPR_601_RTCU
, "RTCU",
1291 SPR_NOACCESS
, SPR_NOACCESS
,
1292 SPR_NOACCESS
, &spr_write_601_rtcu
,
1294 spr_register(env
, SPR_601_VRTCU
, "RTCU",
1295 &spr_read_601_rtcu
, SPR_NOACCESS
,
1296 &spr_read_601_rtcu
, SPR_NOACCESS
,
1298 spr_register(env
, SPR_601_RTCL
, "RTCL",
1299 SPR_NOACCESS
, SPR_NOACCESS
,
1300 SPR_NOACCESS
, &spr_write_601_rtcl
,
1302 spr_register(env
, SPR_601_VRTCL
, "RTCL",
1303 &spr_read_601_rtcl
, SPR_NOACCESS
,
1304 &spr_read_601_rtcl
, SPR_NOACCESS
,
1308 spr_register(env
, SPR_601_UDECR
, "UDECR",
1309 &spr_read_decr
, SPR_NOACCESS
,
1310 &spr_read_decr
, SPR_NOACCESS
,
1313 /* External access control */
1314 /* XXX : not implemented */
1315 spr_register(env
, SPR_EAR
, "EAR",
1316 SPR_NOACCESS
, SPR_NOACCESS
,
1317 &spr_read_generic
, &spr_write_generic
,
1319 /* Memory management */
1320 #if !defined(CONFIG_USER_ONLY)
1321 spr_register(env
, SPR_IBAT0U
, "IBAT0U",
1322 SPR_NOACCESS
, SPR_NOACCESS
,
1323 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1325 spr_register(env
, SPR_IBAT0L
, "IBAT0L",
1326 SPR_NOACCESS
, SPR_NOACCESS
,
1327 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1329 spr_register(env
, SPR_IBAT1U
, "IBAT1U",
1330 SPR_NOACCESS
, SPR_NOACCESS
,
1331 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1333 spr_register(env
, SPR_IBAT1L
, "IBAT1L",
1334 SPR_NOACCESS
, SPR_NOACCESS
,
1335 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1337 spr_register(env
, SPR_IBAT2U
, "IBAT2U",
1338 SPR_NOACCESS
, SPR_NOACCESS
,
1339 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1341 spr_register(env
, SPR_IBAT2L
, "IBAT2L",
1342 SPR_NOACCESS
, SPR_NOACCESS
,
1343 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1345 spr_register(env
, SPR_IBAT3U
, "IBAT3U",
1346 SPR_NOACCESS
, SPR_NOACCESS
,
1347 &spr_read_601_ubat
, &spr_write_601_ubatu
,
1349 spr_register(env
, SPR_IBAT3L
, "IBAT3L",
1350 SPR_NOACCESS
, SPR_NOACCESS
,
1351 &spr_read_601_ubat
, &spr_write_601_ubatl
,
1357 static void gen_spr_74xx (CPUPPCState
*env
)
1359 /* Processor identification */
1360 spr_register(env
, SPR_PIR
, "PIR",
1361 SPR_NOACCESS
, SPR_NOACCESS
,
1362 &spr_read_generic
, &spr_write_pir
,
1364 /* XXX : not implemented */
1365 spr_register(env
, SPR_74XX_MMCR2
, "MMCR2",
1366 SPR_NOACCESS
, SPR_NOACCESS
,
1367 &spr_read_generic
, &spr_write_generic
,
1369 /* XXX : not implemented */
1370 spr_register(env
, SPR_74XX_UMMCR2
, "UMMCR2",
1371 &spr_read_ureg
, SPR_NOACCESS
,
1372 &spr_read_ureg
, SPR_NOACCESS
,
1374 /* XXX: not implemented */
1375 spr_register(env
, SPR_BAMR
, "BAMR",
1376 SPR_NOACCESS
, SPR_NOACCESS
,
1377 &spr_read_generic
, &spr_write_generic
,
1379 /* XXX : not implemented */
1380 spr_register(env
, SPR_MSSCR0
, "MSSCR0",
1381 SPR_NOACCESS
, SPR_NOACCESS
,
1382 &spr_read_generic
, &spr_write_generic
,
1384 /* Hardware implementation registers */
1385 /* XXX : not implemented */
1386 spr_register(env
, SPR_HID0
, "HID0",
1387 SPR_NOACCESS
, SPR_NOACCESS
,
1388 &spr_read_generic
, &spr_write_generic
,
1390 /* XXX : not implemented */
1391 spr_register(env
, SPR_HID1
, "HID1",
1392 SPR_NOACCESS
, SPR_NOACCESS
,
1393 &spr_read_generic
, &spr_write_generic
,
1396 spr_register(env
, SPR_VRSAVE
, "VRSAVE",
1397 &spr_read_generic
, &spr_write_generic
,
1398 &spr_read_generic
, &spr_write_generic
,
1400 /* XXX : not implemented */
1401 spr_register(env
, SPR_L2CR
, "L2CR",
1402 SPR_NOACCESS
, SPR_NOACCESS
,
1403 &spr_read_generic
, spr_access_nop
,
1405 /* Not strictly an SPR */
1406 vscr_init(env
, 0x00010000);
1409 static void gen_l3_ctrl (CPUPPCState
*env
)
1412 /* XXX : not implemented */
1413 spr_register(env
, SPR_L3CR
, "L3CR",
1414 SPR_NOACCESS
, SPR_NOACCESS
,
1415 &spr_read_generic
, &spr_write_generic
,
1418 /* XXX : not implemented */
1419 spr_register(env
, SPR_L3ITCR0
, "L3ITCR0",
1420 SPR_NOACCESS
, SPR_NOACCESS
,
1421 &spr_read_generic
, &spr_write_generic
,
1424 /* XXX : not implemented */
1425 spr_register(env
, SPR_L3PM
, "L3PM",
1426 SPR_NOACCESS
, SPR_NOACCESS
,
1427 &spr_read_generic
, &spr_write_generic
,
1431 static void gen_74xx_soft_tlb (CPUPPCState
*env
, int nb_tlbs
, int nb_ways
)
1433 #if !defined(CONFIG_USER_ONLY)
1434 env
->nb_tlb
= nb_tlbs
;
1435 env
->nb_ways
= nb_ways
;
1437 env
->tlb_type
= TLB_6XX
;
1438 /* XXX : not implemented */
1439 spr_register(env
, SPR_PTEHI
, "PTEHI",
1440 SPR_NOACCESS
, SPR_NOACCESS
,
1441 &spr_read_generic
, &spr_write_generic
,
1443 /* XXX : not implemented */
1444 spr_register(env
, SPR_PTELO
, "PTELO",
1445 SPR_NOACCESS
, SPR_NOACCESS
,
1446 &spr_read_generic
, &spr_write_generic
,
1448 /* XXX : not implemented */
1449 spr_register(env
, SPR_TLBMISS
, "TLBMISS",
1450 SPR_NOACCESS
, SPR_NOACCESS
,
1451 &spr_read_generic
, &spr_write_generic
,
1456 #if !defined(CONFIG_USER_ONLY)
1457 static void spr_write_e500_l1csr0 (void *opaque
, int sprn
, int gprn
)
1459 TCGv t0
= tcg_temp_new();
1461 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], L1CSR0_DCE
| L1CSR0_CPE
);
1462 gen_store_spr(sprn
, t0
);
1466 static void spr_write_e500_l1csr1(void *opaque
, int sprn
, int gprn
)
1468 TCGv t0
= tcg_temp_new();
1470 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], L1CSR1_ICE
| L1CSR1_CPE
);
1471 gen_store_spr(sprn
, t0
);
1475 static void spr_write_booke206_mmucsr0 (void *opaque
, int sprn
, int gprn
)
1477 gen_helper_booke206_tlbflush(cpu_env
, cpu_gpr
[gprn
]);
1480 static void spr_write_booke_pid (void *opaque
, int sprn
, int gprn
)
1482 TCGv_i32 t0
= tcg_const_i32(sprn
);
1483 gen_helper_booke_setpid(cpu_env
, t0
, cpu_gpr
[gprn
]);
1484 tcg_temp_free_i32(t0
);
1488 static void gen_spr_usprgh (CPUPPCState
*env
)
1490 spr_register(env
, SPR_USPRG4
, "USPRG4",
1491 &spr_read_ureg
, SPR_NOACCESS
,
1492 &spr_read_ureg
, SPR_NOACCESS
,
1494 spr_register(env
, SPR_USPRG5
, "USPRG5",
1495 &spr_read_ureg
, SPR_NOACCESS
,
1496 &spr_read_ureg
, SPR_NOACCESS
,
1498 spr_register(env
, SPR_USPRG6
, "USPRG6",
1499 &spr_read_ureg
, SPR_NOACCESS
,
1500 &spr_read_ureg
, SPR_NOACCESS
,
1502 spr_register(env
, SPR_USPRG7
, "USPRG7",
1503 &spr_read_ureg
, SPR_NOACCESS
,
1504 &spr_read_ureg
, SPR_NOACCESS
,
1508 /* PowerPC BookE SPR */
1509 static void gen_spr_BookE (CPUPPCState
*env
, uint64_t ivor_mask
)
1511 const char *ivor_names
[64] = {
1512 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1513 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1514 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1515 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1516 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1517 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1518 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1519 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1520 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1521 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1522 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1523 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1524 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1525 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1526 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1527 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1529 #define SPR_BOOKE_IVORxx (-1)
1530 int ivor_sprn
[64] = {
1531 SPR_BOOKE_IVOR0
, SPR_BOOKE_IVOR1
, SPR_BOOKE_IVOR2
, SPR_BOOKE_IVOR3
,
1532 SPR_BOOKE_IVOR4
, SPR_BOOKE_IVOR5
, SPR_BOOKE_IVOR6
, SPR_BOOKE_IVOR7
,
1533 SPR_BOOKE_IVOR8
, SPR_BOOKE_IVOR9
, SPR_BOOKE_IVOR10
, SPR_BOOKE_IVOR11
,
1534 SPR_BOOKE_IVOR12
, SPR_BOOKE_IVOR13
, SPR_BOOKE_IVOR14
, SPR_BOOKE_IVOR15
,
1535 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1536 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1537 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1538 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1539 SPR_BOOKE_IVOR32
, SPR_BOOKE_IVOR33
, SPR_BOOKE_IVOR34
, SPR_BOOKE_IVOR35
,
1540 SPR_BOOKE_IVOR36
, SPR_BOOKE_IVOR37
, SPR_BOOKE_IVOR38
, SPR_BOOKE_IVOR39
,
1541 SPR_BOOKE_IVOR40
, SPR_BOOKE_IVOR41
, SPR_BOOKE_IVOR42
, SPR_BOOKE_IVORxx
,
1542 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1543 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1544 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1545 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1546 SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
, SPR_BOOKE_IVORxx
,
1550 /* Interrupt processing */
1551 spr_register(env
, SPR_BOOKE_CSRR0
, "CSRR0",
1552 SPR_NOACCESS
, SPR_NOACCESS
,
1553 &spr_read_generic
, &spr_write_generic
,
1555 spr_register(env
, SPR_BOOKE_CSRR1
, "CSRR1",
1556 SPR_NOACCESS
, SPR_NOACCESS
,
1557 &spr_read_generic
, &spr_write_generic
,
1560 /* XXX : not implemented */
1561 spr_register(env
, SPR_BOOKE_IAC1
, "IAC1",
1562 SPR_NOACCESS
, SPR_NOACCESS
,
1563 &spr_read_generic
, &spr_write_generic
,
1565 /* XXX : not implemented */
1566 spr_register(env
, SPR_BOOKE_IAC2
, "IAC2",
1567 SPR_NOACCESS
, SPR_NOACCESS
,
1568 &spr_read_generic
, &spr_write_generic
,
1570 /* XXX : not implemented */
1571 spr_register(env
, SPR_BOOKE_DAC1
, "DAC1",
1572 SPR_NOACCESS
, SPR_NOACCESS
,
1573 &spr_read_generic
, &spr_write_generic
,
1575 /* XXX : not implemented */
1576 spr_register(env
, SPR_BOOKE_DAC2
, "DAC2",
1577 SPR_NOACCESS
, SPR_NOACCESS
,
1578 &spr_read_generic
, &spr_write_generic
,
1580 /* XXX : not implemented */
1581 spr_register(env
, SPR_BOOKE_DBCR0
, "DBCR0",
1582 SPR_NOACCESS
, SPR_NOACCESS
,
1583 &spr_read_generic
, &spr_write_40x_dbcr0
,
1585 /* XXX : not implemented */
1586 spr_register(env
, SPR_BOOKE_DBCR1
, "DBCR1",
1587 SPR_NOACCESS
, SPR_NOACCESS
,
1588 &spr_read_generic
, &spr_write_generic
,
1590 /* XXX : not implemented */
1591 spr_register(env
, SPR_BOOKE_DBCR2
, "DBCR2",
1592 SPR_NOACCESS
, SPR_NOACCESS
,
1593 &spr_read_generic
, &spr_write_generic
,
1595 /* XXX : not implemented */
1596 spr_register(env
, SPR_BOOKE_DBSR
, "DBSR",
1597 SPR_NOACCESS
, SPR_NOACCESS
,
1598 &spr_read_generic
, &spr_write_clear
,
1600 spr_register(env
, SPR_BOOKE_DEAR
, "DEAR",
1601 SPR_NOACCESS
, SPR_NOACCESS
,
1602 &spr_read_generic
, &spr_write_generic
,
1604 spr_register(env
, SPR_BOOKE_ESR
, "ESR",
1605 SPR_NOACCESS
, SPR_NOACCESS
,
1606 &spr_read_generic
, &spr_write_generic
,
1608 spr_register(env
, SPR_BOOKE_IVPR
, "IVPR",
1609 SPR_NOACCESS
, SPR_NOACCESS
,
1610 &spr_read_generic
, &spr_write_excp_prefix
,
1612 /* Exception vectors */
1613 for (i
= 0; i
< 64; i
++) {
1614 if (ivor_mask
& (1ULL << i
)) {
1615 if (ivor_sprn
[i
] == SPR_BOOKE_IVORxx
) {
1616 fprintf(stderr
, "ERROR: IVOR %d SPR is not defined\n", i
);
1619 spr_register(env
, ivor_sprn
[i
], ivor_names
[i
],
1620 SPR_NOACCESS
, SPR_NOACCESS
,
1621 &spr_read_generic
, &spr_write_excp_vector
,
1625 spr_register(env
, SPR_BOOKE_PID
, "PID",
1626 SPR_NOACCESS
, SPR_NOACCESS
,
1627 &spr_read_generic
, &spr_write_booke_pid
,
1629 spr_register(env
, SPR_BOOKE_TCR
, "TCR",
1630 SPR_NOACCESS
, SPR_NOACCESS
,
1631 &spr_read_generic
, &spr_write_booke_tcr
,
1633 spr_register(env
, SPR_BOOKE_TSR
, "TSR",
1634 SPR_NOACCESS
, SPR_NOACCESS
,
1635 &spr_read_generic
, &spr_write_booke_tsr
,
1638 spr_register(env
, SPR_DECR
, "DECR",
1639 SPR_NOACCESS
, SPR_NOACCESS
,
1640 &spr_read_decr
, &spr_write_decr
,
1642 spr_register(env
, SPR_BOOKE_DECAR
, "DECAR",
1643 SPR_NOACCESS
, SPR_NOACCESS
,
1644 SPR_NOACCESS
, &spr_write_generic
,
1647 spr_register(env
, SPR_USPRG0
, "USPRG0",
1648 &spr_read_generic
, &spr_write_generic
,
1649 &spr_read_generic
, &spr_write_generic
,
1651 spr_register(env
, SPR_SPRG4
, "SPRG4",
1652 SPR_NOACCESS
, SPR_NOACCESS
,
1653 &spr_read_generic
, &spr_write_generic
,
1655 spr_register(env
, SPR_SPRG5
, "SPRG5",
1656 SPR_NOACCESS
, SPR_NOACCESS
,
1657 &spr_read_generic
, &spr_write_generic
,
1659 spr_register(env
, SPR_SPRG6
, "SPRG6",
1660 SPR_NOACCESS
, SPR_NOACCESS
,
1661 &spr_read_generic
, &spr_write_generic
,
1663 spr_register(env
, SPR_SPRG7
, "SPRG7",
1664 SPR_NOACCESS
, SPR_NOACCESS
,
1665 &spr_read_generic
, &spr_write_generic
,
1669 static inline uint32_t gen_tlbncfg(uint32_t assoc
, uint32_t minsize
,
1670 uint32_t maxsize
, uint32_t flags
,
1673 return (assoc
<< TLBnCFG_ASSOC_SHIFT
) |
1674 (minsize
<< TLBnCFG_MINSIZE_SHIFT
) |
1675 (maxsize
<< TLBnCFG_MAXSIZE_SHIFT
) |
1679 /* BookE 2.06 storage control registers */
1680 static void gen_spr_BookE206(CPUPPCState
*env
, uint32_t mas_mask
,
1683 #if !defined(CONFIG_USER_ONLY)
1684 const char *mas_names
[8] = {
1685 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1688 SPR_BOOKE_MAS0
, SPR_BOOKE_MAS1
, SPR_BOOKE_MAS2
, SPR_BOOKE_MAS3
,
1689 SPR_BOOKE_MAS4
, SPR_BOOKE_MAS5
, SPR_BOOKE_MAS6
, SPR_BOOKE_MAS7
,
1693 /* TLB assist registers */
1694 /* XXX : not implemented */
1695 for (i
= 0; i
< 8; i
++) {
1696 void (*uea_write
)(void *o
, int sprn
, int gprn
) = &spr_write_generic32
;
1697 if (i
== 2 && (mas_mask
& (1 << i
)) && (env
->insns_flags
& PPC_64B
)) {
1698 uea_write
= &spr_write_generic
;
1700 if (mas_mask
& (1 << i
)) {
1701 spr_register(env
, mas_sprn
[i
], mas_names
[i
],
1702 SPR_NOACCESS
, SPR_NOACCESS
,
1703 &spr_read_generic
, uea_write
,
1707 if (env
->nb_pids
> 1) {
1708 /* XXX : not implemented */
1709 spr_register(env
, SPR_BOOKE_PID1
, "PID1",
1710 SPR_NOACCESS
, SPR_NOACCESS
,
1711 &spr_read_generic
, &spr_write_booke_pid
,
1714 if (env
->nb_pids
> 2) {
1715 /* XXX : not implemented */
1716 spr_register(env
, SPR_BOOKE_PID2
, "PID2",
1717 SPR_NOACCESS
, SPR_NOACCESS
,
1718 &spr_read_generic
, &spr_write_booke_pid
,
1721 /* XXX : not implemented */
1722 spr_register(env
, SPR_MMUCFG
, "MMUCFG",
1723 SPR_NOACCESS
, SPR_NOACCESS
,
1724 &spr_read_generic
, SPR_NOACCESS
,
1725 0x00000000); /* TOFIX */
1726 switch (env
->nb_ways
) {
1728 spr_register(env
, SPR_BOOKE_TLB3CFG
, "TLB3CFG",
1729 SPR_NOACCESS
, SPR_NOACCESS
,
1730 &spr_read_generic
, SPR_NOACCESS
,
1734 spr_register(env
, SPR_BOOKE_TLB2CFG
, "TLB2CFG",
1735 SPR_NOACCESS
, SPR_NOACCESS
,
1736 &spr_read_generic
, SPR_NOACCESS
,
1740 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
1741 SPR_NOACCESS
, SPR_NOACCESS
,
1742 &spr_read_generic
, SPR_NOACCESS
,
1746 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
1747 SPR_NOACCESS
, SPR_NOACCESS
,
1748 &spr_read_generic
, SPR_NOACCESS
,
1757 gen_spr_usprgh(env
);
1760 /* SPR specific to PowerPC 440 implementation */
1761 static void gen_spr_440 (CPUPPCState
*env
)
1764 /* XXX : not implemented */
1765 spr_register(env
, SPR_440_DNV0
, "DNV0",
1766 SPR_NOACCESS
, SPR_NOACCESS
,
1767 &spr_read_generic
, &spr_write_generic
,
1769 /* XXX : not implemented */
1770 spr_register(env
, SPR_440_DNV1
, "DNV1",
1771 SPR_NOACCESS
, SPR_NOACCESS
,
1772 &spr_read_generic
, &spr_write_generic
,
1774 /* XXX : not implemented */
1775 spr_register(env
, SPR_440_DNV2
, "DNV2",
1776 SPR_NOACCESS
, SPR_NOACCESS
,
1777 &spr_read_generic
, &spr_write_generic
,
1779 /* XXX : not implemented */
1780 spr_register(env
, SPR_440_DNV3
, "DNV3",
1781 SPR_NOACCESS
, SPR_NOACCESS
,
1782 &spr_read_generic
, &spr_write_generic
,
1784 /* XXX : not implemented */
1785 spr_register(env
, SPR_440_DTV0
, "DTV0",
1786 SPR_NOACCESS
, SPR_NOACCESS
,
1787 &spr_read_generic
, &spr_write_generic
,
1789 /* XXX : not implemented */
1790 spr_register(env
, SPR_440_DTV1
, "DTV1",
1791 SPR_NOACCESS
, SPR_NOACCESS
,
1792 &spr_read_generic
, &spr_write_generic
,
1794 /* XXX : not implemented */
1795 spr_register(env
, SPR_440_DTV2
, "DTV2",
1796 SPR_NOACCESS
, SPR_NOACCESS
,
1797 &spr_read_generic
, &spr_write_generic
,
1799 /* XXX : not implemented */
1800 spr_register(env
, SPR_440_DTV3
, "DTV3",
1801 SPR_NOACCESS
, SPR_NOACCESS
,
1802 &spr_read_generic
, &spr_write_generic
,
1804 /* XXX : not implemented */
1805 spr_register(env
, SPR_440_DVLIM
, "DVLIM",
1806 SPR_NOACCESS
, SPR_NOACCESS
,
1807 &spr_read_generic
, &spr_write_generic
,
1809 /* XXX : not implemented */
1810 spr_register(env
, SPR_440_INV0
, "INV0",
1811 SPR_NOACCESS
, SPR_NOACCESS
,
1812 &spr_read_generic
, &spr_write_generic
,
1814 /* XXX : not implemented */
1815 spr_register(env
, SPR_440_INV1
, "INV1",
1816 SPR_NOACCESS
, SPR_NOACCESS
,
1817 &spr_read_generic
, &spr_write_generic
,
1819 /* XXX : not implemented */
1820 spr_register(env
, SPR_440_INV2
, "INV2",
1821 SPR_NOACCESS
, SPR_NOACCESS
,
1822 &spr_read_generic
, &spr_write_generic
,
1824 /* XXX : not implemented */
1825 spr_register(env
, SPR_440_INV3
, "INV3",
1826 SPR_NOACCESS
, SPR_NOACCESS
,
1827 &spr_read_generic
, &spr_write_generic
,
1829 /* XXX : not implemented */
1830 spr_register(env
, SPR_440_ITV0
, "ITV0",
1831 SPR_NOACCESS
, SPR_NOACCESS
,
1832 &spr_read_generic
, &spr_write_generic
,
1834 /* XXX : not implemented */
1835 spr_register(env
, SPR_440_ITV1
, "ITV1",
1836 SPR_NOACCESS
, SPR_NOACCESS
,
1837 &spr_read_generic
, &spr_write_generic
,
1839 /* XXX : not implemented */
1840 spr_register(env
, SPR_440_ITV2
, "ITV2",
1841 SPR_NOACCESS
, SPR_NOACCESS
,
1842 &spr_read_generic
, &spr_write_generic
,
1844 /* XXX : not implemented */
1845 spr_register(env
, SPR_440_ITV3
, "ITV3",
1846 SPR_NOACCESS
, SPR_NOACCESS
,
1847 &spr_read_generic
, &spr_write_generic
,
1849 /* XXX : not implemented */
1850 spr_register(env
, SPR_440_IVLIM
, "IVLIM",
1851 SPR_NOACCESS
, SPR_NOACCESS
,
1852 &spr_read_generic
, &spr_write_generic
,
1855 /* XXX : not implemented */
1856 spr_register(env
, SPR_BOOKE_DCDBTRH
, "DCDBTRH",
1857 SPR_NOACCESS
, SPR_NOACCESS
,
1858 &spr_read_generic
, SPR_NOACCESS
,
1860 /* XXX : not implemented */
1861 spr_register(env
, SPR_BOOKE_DCDBTRL
, "DCDBTRL",
1862 SPR_NOACCESS
, SPR_NOACCESS
,
1863 &spr_read_generic
, SPR_NOACCESS
,
1865 /* XXX : not implemented */
1866 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1867 SPR_NOACCESS
, SPR_NOACCESS
,
1868 &spr_read_generic
, SPR_NOACCESS
,
1870 /* XXX : not implemented */
1871 spr_register(env
, SPR_BOOKE_ICDBTRH
, "ICDBTRH",
1872 SPR_NOACCESS
, SPR_NOACCESS
,
1873 &spr_read_generic
, SPR_NOACCESS
,
1875 /* XXX : not implemented */
1876 spr_register(env
, SPR_BOOKE_ICDBTRL
, "ICDBTRL",
1877 SPR_NOACCESS
, SPR_NOACCESS
,
1878 &spr_read_generic
, SPR_NOACCESS
,
1880 /* XXX : not implemented */
1881 spr_register(env
, SPR_440_DBDR
, "DBDR",
1882 SPR_NOACCESS
, SPR_NOACCESS
,
1883 &spr_read_generic
, &spr_write_generic
,
1885 /* Processor control */
1886 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1887 SPR_NOACCESS
, SPR_NOACCESS
,
1888 &spr_read_generic
, &spr_write_generic
,
1890 spr_register(env
, SPR_440_RSTCFG
, "RSTCFG",
1891 SPR_NOACCESS
, SPR_NOACCESS
,
1892 &spr_read_generic
, SPR_NOACCESS
,
1894 /* Storage control */
1895 spr_register(env
, SPR_440_MMUCR
, "MMUCR",
1896 SPR_NOACCESS
, SPR_NOACCESS
,
1897 &spr_read_generic
, &spr_write_generic
,
1901 /* SPR shared between PowerPC 40x implementations */
1902 static void gen_spr_40x (CPUPPCState
*env
)
1905 /* not emulated, as QEMU do not emulate caches */
1906 spr_register(env
, SPR_40x_DCCR
, "DCCR",
1907 SPR_NOACCESS
, SPR_NOACCESS
,
1908 &spr_read_generic
, &spr_write_generic
,
1910 /* not emulated, as QEMU do not emulate caches */
1911 spr_register(env
, SPR_40x_ICCR
, "ICCR",
1912 SPR_NOACCESS
, SPR_NOACCESS
,
1913 &spr_read_generic
, &spr_write_generic
,
1915 /* not emulated, as QEMU do not emulate caches */
1916 spr_register(env
, SPR_BOOKE_ICDBDR
, "ICDBDR",
1917 SPR_NOACCESS
, SPR_NOACCESS
,
1918 &spr_read_generic
, SPR_NOACCESS
,
1921 spr_register(env
, SPR_40x_DEAR
, "DEAR",
1922 SPR_NOACCESS
, SPR_NOACCESS
,
1923 &spr_read_generic
, &spr_write_generic
,
1925 spr_register(env
, SPR_40x_ESR
, "ESR",
1926 SPR_NOACCESS
, SPR_NOACCESS
,
1927 &spr_read_generic
, &spr_write_generic
,
1929 spr_register(env
, SPR_40x_EVPR
, "EVPR",
1930 SPR_NOACCESS
, SPR_NOACCESS
,
1931 &spr_read_generic
, &spr_write_excp_prefix
,
1933 spr_register(env
, SPR_40x_SRR2
, "SRR2",
1934 &spr_read_generic
, &spr_write_generic
,
1935 &spr_read_generic
, &spr_write_generic
,
1937 spr_register(env
, SPR_40x_SRR3
, "SRR3",
1938 &spr_read_generic
, &spr_write_generic
,
1939 &spr_read_generic
, &spr_write_generic
,
1942 spr_register(env
, SPR_40x_PIT
, "PIT",
1943 SPR_NOACCESS
, SPR_NOACCESS
,
1944 &spr_read_40x_pit
, &spr_write_40x_pit
,
1946 spr_register(env
, SPR_40x_TCR
, "TCR",
1947 SPR_NOACCESS
, SPR_NOACCESS
,
1948 &spr_read_generic
, &spr_write_booke_tcr
,
1950 spr_register(env
, SPR_40x_TSR
, "TSR",
1951 SPR_NOACCESS
, SPR_NOACCESS
,
1952 &spr_read_generic
, &spr_write_booke_tsr
,
1956 /* SPR specific to PowerPC 405 implementation */
1957 static void gen_spr_405 (CPUPPCState
*env
)
1960 spr_register(env
, SPR_40x_PID
, "PID",
1961 SPR_NOACCESS
, SPR_NOACCESS
,
1962 &spr_read_generic
, &spr_write_generic
,
1964 spr_register(env
, SPR_4xx_CCR0
, "CCR0",
1965 SPR_NOACCESS
, SPR_NOACCESS
,
1966 &spr_read_generic
, &spr_write_generic
,
1968 /* Debug interface */
1969 /* XXX : not implemented */
1970 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
1971 SPR_NOACCESS
, SPR_NOACCESS
,
1972 &spr_read_generic
, &spr_write_40x_dbcr0
,
1974 /* XXX : not implemented */
1975 spr_register(env
, SPR_405_DBCR1
, "DBCR1",
1976 SPR_NOACCESS
, SPR_NOACCESS
,
1977 &spr_read_generic
, &spr_write_generic
,
1979 /* XXX : not implemented */
1980 spr_register(env
, SPR_40x_DBSR
, "DBSR",
1981 SPR_NOACCESS
, SPR_NOACCESS
,
1982 &spr_read_generic
, &spr_write_clear
,
1983 /* Last reset was system reset */
1985 /* XXX : not implemented */
1986 spr_register(env
, SPR_40x_DAC1
, "DAC1",
1987 SPR_NOACCESS
, SPR_NOACCESS
,
1988 &spr_read_generic
, &spr_write_generic
,
1990 spr_register(env
, SPR_40x_DAC2
, "DAC2",
1991 SPR_NOACCESS
, SPR_NOACCESS
,
1992 &spr_read_generic
, &spr_write_generic
,
1994 /* XXX : not implemented */
1995 spr_register(env
, SPR_405_DVC1
, "DVC1",
1996 SPR_NOACCESS
, SPR_NOACCESS
,
1997 &spr_read_generic
, &spr_write_generic
,
1999 /* XXX : not implemented */
2000 spr_register(env
, SPR_405_DVC2
, "DVC2",
2001 SPR_NOACCESS
, SPR_NOACCESS
,
2002 &spr_read_generic
, &spr_write_generic
,
2004 /* XXX : not implemented */
2005 spr_register(env
, SPR_40x_IAC1
, "IAC1",
2006 SPR_NOACCESS
, SPR_NOACCESS
,
2007 &spr_read_generic
, &spr_write_generic
,
2009 spr_register(env
, SPR_40x_IAC2
, "IAC2",
2010 SPR_NOACCESS
, SPR_NOACCESS
,
2011 &spr_read_generic
, &spr_write_generic
,
2013 /* XXX : not implemented */
2014 spr_register(env
, SPR_405_IAC3
, "IAC3",
2015 SPR_NOACCESS
, SPR_NOACCESS
,
2016 &spr_read_generic
, &spr_write_generic
,
2018 /* XXX : not implemented */
2019 spr_register(env
, SPR_405_IAC4
, "IAC4",
2020 SPR_NOACCESS
, SPR_NOACCESS
,
2021 &spr_read_generic
, &spr_write_generic
,
2023 /* Storage control */
2024 /* XXX: TODO: not implemented */
2025 spr_register(env
, SPR_405_SLER
, "SLER",
2026 SPR_NOACCESS
, SPR_NOACCESS
,
2027 &spr_read_generic
, &spr_write_40x_sler
,
2029 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2030 SPR_NOACCESS
, SPR_NOACCESS
,
2031 &spr_read_generic
, &spr_write_generic
,
2033 /* XXX : not implemented */
2034 spr_register(env
, SPR_405_SU0R
, "SU0R",
2035 SPR_NOACCESS
, SPR_NOACCESS
,
2036 &spr_read_generic
, &spr_write_generic
,
2039 spr_register(env
, SPR_USPRG0
, "USPRG0",
2040 &spr_read_ureg
, SPR_NOACCESS
,
2041 &spr_read_ureg
, SPR_NOACCESS
,
2043 spr_register(env
, SPR_SPRG4
, "SPRG4",
2044 SPR_NOACCESS
, SPR_NOACCESS
,
2045 &spr_read_generic
, &spr_write_generic
,
2047 spr_register(env
, SPR_SPRG5
, "SPRG5",
2048 SPR_NOACCESS
, SPR_NOACCESS
,
2049 spr_read_generic
, &spr_write_generic
,
2051 spr_register(env
, SPR_SPRG6
, "SPRG6",
2052 SPR_NOACCESS
, SPR_NOACCESS
,
2053 spr_read_generic
, &spr_write_generic
,
2055 spr_register(env
, SPR_SPRG7
, "SPRG7",
2056 SPR_NOACCESS
, SPR_NOACCESS
,
2057 spr_read_generic
, &spr_write_generic
,
2059 gen_spr_usprgh(env
);
2062 /* SPR shared between PowerPC 401 & 403 implementations */
2063 static void gen_spr_401_403 (CPUPPCState
*env
)
2066 spr_register(env
, SPR_403_VTBL
, "TBL",
2067 &spr_read_tbl
, SPR_NOACCESS
,
2068 &spr_read_tbl
, SPR_NOACCESS
,
2070 spr_register(env
, SPR_403_TBL
, "TBL",
2071 SPR_NOACCESS
, SPR_NOACCESS
,
2072 SPR_NOACCESS
, &spr_write_tbl
,
2074 spr_register(env
, SPR_403_VTBU
, "TBU",
2075 &spr_read_tbu
, SPR_NOACCESS
,
2076 &spr_read_tbu
, SPR_NOACCESS
,
2078 spr_register(env
, SPR_403_TBU
, "TBU",
2079 SPR_NOACCESS
, SPR_NOACCESS
,
2080 SPR_NOACCESS
, &spr_write_tbu
,
2083 /* not emulated, as QEMU do not emulate caches */
2084 spr_register(env
, SPR_403_CDBCR
, "CDBCR",
2085 SPR_NOACCESS
, SPR_NOACCESS
,
2086 &spr_read_generic
, &spr_write_generic
,
2090 /* SPR specific to PowerPC 401 implementation */
2091 static void gen_spr_401 (CPUPPCState
*env
)
2093 /* Debug interface */
2094 /* XXX : not implemented */
2095 spr_register(env
, SPR_40x_DBCR0
, "DBCR",
2096 SPR_NOACCESS
, SPR_NOACCESS
,
2097 &spr_read_generic
, &spr_write_40x_dbcr0
,
2099 /* XXX : not implemented */
2100 spr_register(env
, SPR_40x_DBSR
, "DBSR",
2101 SPR_NOACCESS
, SPR_NOACCESS
,
2102 &spr_read_generic
, &spr_write_clear
,
2103 /* Last reset was system reset */
2105 /* XXX : not implemented */
2106 spr_register(env
, SPR_40x_DAC1
, "DAC",
2107 SPR_NOACCESS
, SPR_NOACCESS
,
2108 &spr_read_generic
, &spr_write_generic
,
2110 /* XXX : not implemented */
2111 spr_register(env
, SPR_40x_IAC1
, "IAC",
2112 SPR_NOACCESS
, SPR_NOACCESS
,
2113 &spr_read_generic
, &spr_write_generic
,
2115 /* Storage control */
2116 /* XXX: TODO: not implemented */
2117 spr_register(env
, SPR_405_SLER
, "SLER",
2118 SPR_NOACCESS
, SPR_NOACCESS
,
2119 &spr_read_generic
, &spr_write_40x_sler
,
2121 /* not emulated, as QEMU never does speculative access */
2122 spr_register(env
, SPR_40x_SGR
, "SGR",
2123 SPR_NOACCESS
, SPR_NOACCESS
,
2124 &spr_read_generic
, &spr_write_generic
,
2126 /* not emulated, as QEMU do not emulate caches */
2127 spr_register(env
, SPR_40x_DCWR
, "DCWR",
2128 SPR_NOACCESS
, SPR_NOACCESS
,
2129 &spr_read_generic
, &spr_write_generic
,
2133 static void gen_spr_401x2 (CPUPPCState
*env
)
2136 spr_register(env
, SPR_40x_PID
, "PID",
2137 SPR_NOACCESS
, SPR_NOACCESS
,
2138 &spr_read_generic
, &spr_write_generic
,
2140 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2141 SPR_NOACCESS
, SPR_NOACCESS
,
2142 &spr_read_generic
, &spr_write_generic
,
2146 /* SPR specific to PowerPC 403 implementation */
2147 static void gen_spr_403 (CPUPPCState
*env
)
2149 /* Debug interface */
2150 /* XXX : not implemented */
2151 spr_register(env
, SPR_40x_DBCR0
, "DBCR0",
2152 SPR_NOACCESS
, SPR_NOACCESS
,
2153 &spr_read_generic
, &spr_write_40x_dbcr0
,
2155 /* XXX : not implemented */
2156 spr_register(env
, SPR_40x_DBSR
, "DBSR",
2157 SPR_NOACCESS
, SPR_NOACCESS
,
2158 &spr_read_generic
, &spr_write_clear
,
2159 /* Last reset was system reset */
2161 /* XXX : not implemented */
2162 spr_register(env
, SPR_40x_DAC1
, "DAC1",
2163 SPR_NOACCESS
, SPR_NOACCESS
,
2164 &spr_read_generic
, &spr_write_generic
,
2166 /* XXX : not implemented */
2167 spr_register(env
, SPR_40x_DAC2
, "DAC2",
2168 SPR_NOACCESS
, SPR_NOACCESS
,
2169 &spr_read_generic
, &spr_write_generic
,
2171 /* XXX : not implemented */
2172 spr_register(env
, SPR_40x_IAC1
, "IAC1",
2173 SPR_NOACCESS
, SPR_NOACCESS
,
2174 &spr_read_generic
, &spr_write_generic
,
2176 /* XXX : not implemented */
2177 spr_register(env
, SPR_40x_IAC2
, "IAC2",
2178 SPR_NOACCESS
, SPR_NOACCESS
,
2179 &spr_read_generic
, &spr_write_generic
,
2183 static void gen_spr_403_real (CPUPPCState
*env
)
2185 spr_register(env
, SPR_403_PBL1
, "PBL1",
2186 SPR_NOACCESS
, SPR_NOACCESS
,
2187 &spr_read_403_pbr
, &spr_write_403_pbr
,
2189 spr_register(env
, SPR_403_PBU1
, "PBU1",
2190 SPR_NOACCESS
, SPR_NOACCESS
,
2191 &spr_read_403_pbr
, &spr_write_403_pbr
,
2193 spr_register(env
, SPR_403_PBL2
, "PBL2",
2194 SPR_NOACCESS
, SPR_NOACCESS
,
2195 &spr_read_403_pbr
, &spr_write_403_pbr
,
2197 spr_register(env
, SPR_403_PBU2
, "PBU2",
2198 SPR_NOACCESS
, SPR_NOACCESS
,
2199 &spr_read_403_pbr
, &spr_write_403_pbr
,
2203 static void gen_spr_403_mmu (CPUPPCState
*env
)
2206 spr_register(env
, SPR_40x_PID
, "PID",
2207 SPR_NOACCESS
, SPR_NOACCESS
,
2208 &spr_read_generic
, &spr_write_generic
,
2210 spr_register(env
, SPR_40x_ZPR
, "ZPR",
2211 SPR_NOACCESS
, SPR_NOACCESS
,
2212 &spr_read_generic
, &spr_write_generic
,
2216 /* SPR specific to PowerPC compression coprocessor extension */
2217 static void gen_spr_compress (CPUPPCState
*env
)
2219 /* XXX : not implemented */
2220 spr_register(env
, SPR_401_SKR
, "SKR",
2221 SPR_NOACCESS
, SPR_NOACCESS
,
2222 &spr_read_generic
, &spr_write_generic
,
2226 static void gen_spr_5xx_8xx (CPUPPCState
*env
)
2228 /* Exception processing */
2229 spr_register_kvm(env
, SPR_DSISR
, "DSISR",
2230 SPR_NOACCESS
, SPR_NOACCESS
,
2231 &spr_read_generic
, &spr_write_generic
,
2232 KVM_REG_PPC_DSISR
, 0x00000000);
2233 spr_register_kvm(env
, SPR_DAR
, "DAR",
2234 SPR_NOACCESS
, SPR_NOACCESS
,
2235 &spr_read_generic
, &spr_write_generic
,
2236 KVM_REG_PPC_DAR
, 0x00000000);
2238 spr_register(env
, SPR_DECR
, "DECR",
2239 SPR_NOACCESS
, SPR_NOACCESS
,
2240 &spr_read_decr
, &spr_write_decr
,
2242 /* XXX : not implemented */
2243 spr_register(env
, SPR_MPC_EIE
, "EIE",
2244 SPR_NOACCESS
, SPR_NOACCESS
,
2245 &spr_read_generic
, &spr_write_generic
,
2247 /* XXX : not implemented */
2248 spr_register(env
, SPR_MPC_EID
, "EID",
2249 SPR_NOACCESS
, SPR_NOACCESS
,
2250 &spr_read_generic
, &spr_write_generic
,
2252 /* XXX : not implemented */
2253 spr_register(env
, SPR_MPC_NRI
, "NRI",
2254 SPR_NOACCESS
, SPR_NOACCESS
,
2255 &spr_read_generic
, &spr_write_generic
,
2257 /* XXX : not implemented */
2258 spr_register(env
, SPR_MPC_CMPA
, "CMPA",
2259 SPR_NOACCESS
, SPR_NOACCESS
,
2260 &spr_read_generic
, &spr_write_generic
,
2262 /* XXX : not implemented */
2263 spr_register(env
, SPR_MPC_CMPB
, "CMPB",
2264 SPR_NOACCESS
, SPR_NOACCESS
,
2265 &spr_read_generic
, &spr_write_generic
,
2267 /* XXX : not implemented */
2268 spr_register(env
, SPR_MPC_CMPC
, "CMPC",
2269 SPR_NOACCESS
, SPR_NOACCESS
,
2270 &spr_read_generic
, &spr_write_generic
,
2272 /* XXX : not implemented */
2273 spr_register(env
, SPR_MPC_CMPD
, "CMPD",
2274 SPR_NOACCESS
, SPR_NOACCESS
,
2275 &spr_read_generic
, &spr_write_generic
,
2277 /* XXX : not implemented */
2278 spr_register(env
, SPR_MPC_ECR
, "ECR",
2279 SPR_NOACCESS
, SPR_NOACCESS
,
2280 &spr_read_generic
, &spr_write_generic
,
2282 /* XXX : not implemented */
2283 spr_register(env
, SPR_MPC_DER
, "DER",
2284 SPR_NOACCESS
, SPR_NOACCESS
,
2285 &spr_read_generic
, &spr_write_generic
,
2287 /* XXX : not implemented */
2288 spr_register(env
, SPR_MPC_COUNTA
, "COUNTA",
2289 SPR_NOACCESS
, SPR_NOACCESS
,
2290 &spr_read_generic
, &spr_write_generic
,
2292 /* XXX : not implemented */
2293 spr_register(env
, SPR_MPC_COUNTB
, "COUNTB",
2294 SPR_NOACCESS
, SPR_NOACCESS
,
2295 &spr_read_generic
, &spr_write_generic
,
2297 /* XXX : not implemented */
2298 spr_register(env
, SPR_MPC_CMPE
, "CMPE",
2299 SPR_NOACCESS
, SPR_NOACCESS
,
2300 &spr_read_generic
, &spr_write_generic
,
2302 /* XXX : not implemented */
2303 spr_register(env
, SPR_MPC_CMPF
, "CMPF",
2304 SPR_NOACCESS
, SPR_NOACCESS
,
2305 &spr_read_generic
, &spr_write_generic
,
2307 /* XXX : not implemented */
2308 spr_register(env
, SPR_MPC_CMPG
, "CMPG",
2309 SPR_NOACCESS
, SPR_NOACCESS
,
2310 &spr_read_generic
, &spr_write_generic
,
2312 /* XXX : not implemented */
2313 spr_register(env
, SPR_MPC_CMPH
, "CMPH",
2314 SPR_NOACCESS
, SPR_NOACCESS
,
2315 &spr_read_generic
, &spr_write_generic
,
2317 /* XXX : not implemented */
2318 spr_register(env
, SPR_MPC_LCTRL1
, "LCTRL1",
2319 SPR_NOACCESS
, SPR_NOACCESS
,
2320 &spr_read_generic
, &spr_write_generic
,
2322 /* XXX : not implemented */
2323 spr_register(env
, SPR_MPC_LCTRL2
, "LCTRL2",
2324 SPR_NOACCESS
, SPR_NOACCESS
,
2325 &spr_read_generic
, &spr_write_generic
,
2327 /* XXX : not implemented */
2328 spr_register(env
, SPR_MPC_BAR
, "BAR",
2329 SPR_NOACCESS
, SPR_NOACCESS
,
2330 &spr_read_generic
, &spr_write_generic
,
2332 /* XXX : not implemented */
2333 spr_register(env
, SPR_MPC_DPDR
, "DPDR",
2334 SPR_NOACCESS
, SPR_NOACCESS
,
2335 &spr_read_generic
, &spr_write_generic
,
2337 /* XXX : not implemented */
2338 spr_register(env
, SPR_MPC_IMMR
, "IMMR",
2339 SPR_NOACCESS
, SPR_NOACCESS
,
2340 &spr_read_generic
, &spr_write_generic
,
2344 static void gen_spr_5xx (CPUPPCState
*env
)
2346 /* XXX : not implemented */
2347 spr_register(env
, SPR_RCPU_MI_GRA
, "MI_GRA",
2348 SPR_NOACCESS
, SPR_NOACCESS
,
2349 &spr_read_generic
, &spr_write_generic
,
2351 /* XXX : not implemented */
2352 spr_register(env
, SPR_RCPU_L2U_GRA
, "L2U_GRA",
2353 SPR_NOACCESS
, SPR_NOACCESS
,
2354 &spr_read_generic
, &spr_write_generic
,
2356 /* XXX : not implemented */
2357 spr_register(env
, SPR_RPCU_BBCMCR
, "L2U_BBCMCR",
2358 SPR_NOACCESS
, SPR_NOACCESS
,
2359 &spr_read_generic
, &spr_write_generic
,
2361 /* XXX : not implemented */
2362 spr_register(env
, SPR_RCPU_L2U_MCR
, "L2U_MCR",
2363 SPR_NOACCESS
, SPR_NOACCESS
,
2364 &spr_read_generic
, &spr_write_generic
,
2366 /* XXX : not implemented */
2367 spr_register(env
, SPR_RCPU_MI_RBA0
, "MI_RBA0",
2368 SPR_NOACCESS
, SPR_NOACCESS
,
2369 &spr_read_generic
, &spr_write_generic
,
2371 /* XXX : not implemented */
2372 spr_register(env
, SPR_RCPU_MI_RBA1
, "MI_RBA1",
2373 SPR_NOACCESS
, SPR_NOACCESS
,
2374 &spr_read_generic
, &spr_write_generic
,
2376 /* XXX : not implemented */
2377 spr_register(env
, SPR_RCPU_MI_RBA2
, "MI_RBA2",
2378 SPR_NOACCESS
, SPR_NOACCESS
,
2379 &spr_read_generic
, &spr_write_generic
,
2381 /* XXX : not implemented */
2382 spr_register(env
, SPR_RCPU_MI_RBA3
, "MI_RBA3",
2383 SPR_NOACCESS
, SPR_NOACCESS
,
2384 &spr_read_generic
, &spr_write_generic
,
2386 /* XXX : not implemented */
2387 spr_register(env
, SPR_RCPU_L2U_RBA0
, "L2U_RBA0",
2388 SPR_NOACCESS
, SPR_NOACCESS
,
2389 &spr_read_generic
, &spr_write_generic
,
2391 /* XXX : not implemented */
2392 spr_register(env
, SPR_RCPU_L2U_RBA1
, "L2U_RBA1",
2393 SPR_NOACCESS
, SPR_NOACCESS
,
2394 &spr_read_generic
, &spr_write_generic
,
2396 /* XXX : not implemented */
2397 spr_register(env
, SPR_RCPU_L2U_RBA2
, "L2U_RBA2",
2398 SPR_NOACCESS
, SPR_NOACCESS
,
2399 &spr_read_generic
, &spr_write_generic
,
2401 /* XXX : not implemented */
2402 spr_register(env
, SPR_RCPU_L2U_RBA3
, "L2U_RBA3",
2403 SPR_NOACCESS
, SPR_NOACCESS
,
2404 &spr_read_generic
, &spr_write_generic
,
2406 /* XXX : not implemented */
2407 spr_register(env
, SPR_RCPU_MI_RA0
, "MI_RA0",
2408 SPR_NOACCESS
, SPR_NOACCESS
,
2409 &spr_read_generic
, &spr_write_generic
,
2411 /* XXX : not implemented */
2412 spr_register(env
, SPR_RCPU_MI_RA1
, "MI_RA1",
2413 SPR_NOACCESS
, SPR_NOACCESS
,
2414 &spr_read_generic
, &spr_write_generic
,
2416 /* XXX : not implemented */
2417 spr_register(env
, SPR_RCPU_MI_RA2
, "MI_RA2",
2418 SPR_NOACCESS
, SPR_NOACCESS
,
2419 &spr_read_generic
, &spr_write_generic
,
2421 /* XXX : not implemented */
2422 spr_register(env
, SPR_RCPU_MI_RA3
, "MI_RA3",
2423 SPR_NOACCESS
, SPR_NOACCESS
,
2424 &spr_read_generic
, &spr_write_generic
,
2426 /* XXX : not implemented */
2427 spr_register(env
, SPR_RCPU_L2U_RA0
, "L2U_RA0",
2428 SPR_NOACCESS
, SPR_NOACCESS
,
2429 &spr_read_generic
, &spr_write_generic
,
2431 /* XXX : not implemented */
2432 spr_register(env
, SPR_RCPU_L2U_RA1
, "L2U_RA1",
2433 SPR_NOACCESS
, SPR_NOACCESS
,
2434 &spr_read_generic
, &spr_write_generic
,
2436 /* XXX : not implemented */
2437 spr_register(env
, SPR_RCPU_L2U_RA2
, "L2U_RA2",
2438 SPR_NOACCESS
, SPR_NOACCESS
,
2439 &spr_read_generic
, &spr_write_generic
,
2441 /* XXX : not implemented */
2442 spr_register(env
, SPR_RCPU_L2U_RA3
, "L2U_RA3",
2443 SPR_NOACCESS
, SPR_NOACCESS
,
2444 &spr_read_generic
, &spr_write_generic
,
2446 /* XXX : not implemented */
2447 spr_register(env
, SPR_RCPU_FPECR
, "FPECR",
2448 SPR_NOACCESS
, SPR_NOACCESS
,
2449 &spr_read_generic
, &spr_write_generic
,
2453 static void gen_spr_8xx (CPUPPCState
*env
)
2455 /* XXX : not implemented */
2456 spr_register(env
, SPR_MPC_IC_CST
, "IC_CST",
2457 SPR_NOACCESS
, SPR_NOACCESS
,
2458 &spr_read_generic
, &spr_write_generic
,
2460 /* XXX : not implemented */
2461 spr_register(env
, SPR_MPC_IC_ADR
, "IC_ADR",
2462 SPR_NOACCESS
, SPR_NOACCESS
,
2463 &spr_read_generic
, &spr_write_generic
,
2465 /* XXX : not implemented */
2466 spr_register(env
, SPR_MPC_IC_DAT
, "IC_DAT",
2467 SPR_NOACCESS
, SPR_NOACCESS
,
2468 &spr_read_generic
, &spr_write_generic
,
2470 /* XXX : not implemented */
2471 spr_register(env
, SPR_MPC_DC_CST
, "DC_CST",
2472 SPR_NOACCESS
, SPR_NOACCESS
,
2473 &spr_read_generic
, &spr_write_generic
,
2475 /* XXX : not implemented */
2476 spr_register(env
, SPR_MPC_DC_ADR
, "DC_ADR",
2477 SPR_NOACCESS
, SPR_NOACCESS
,
2478 &spr_read_generic
, &spr_write_generic
,
2480 /* XXX : not implemented */
2481 spr_register(env
, SPR_MPC_DC_DAT
, "DC_DAT",
2482 SPR_NOACCESS
, SPR_NOACCESS
,
2483 &spr_read_generic
, &spr_write_generic
,
2485 /* XXX : not implemented */
2486 spr_register(env
, SPR_MPC_MI_CTR
, "MI_CTR",
2487 SPR_NOACCESS
, SPR_NOACCESS
,
2488 &spr_read_generic
, &spr_write_generic
,
2490 /* XXX : not implemented */
2491 spr_register(env
, SPR_MPC_MI_AP
, "MI_AP",
2492 SPR_NOACCESS
, SPR_NOACCESS
,
2493 &spr_read_generic
, &spr_write_generic
,
2495 /* XXX : not implemented */
2496 spr_register(env
, SPR_MPC_MI_EPN
, "MI_EPN",
2497 SPR_NOACCESS
, SPR_NOACCESS
,
2498 &spr_read_generic
, &spr_write_generic
,
2500 /* XXX : not implemented */
2501 spr_register(env
, SPR_MPC_MI_TWC
, "MI_TWC",
2502 SPR_NOACCESS
, SPR_NOACCESS
,
2503 &spr_read_generic
, &spr_write_generic
,
2505 /* XXX : not implemented */
2506 spr_register(env
, SPR_MPC_MI_RPN
, "MI_RPN",
2507 SPR_NOACCESS
, SPR_NOACCESS
,
2508 &spr_read_generic
, &spr_write_generic
,
2510 /* XXX : not implemented */
2511 spr_register(env
, SPR_MPC_MI_DBCAM
, "MI_DBCAM",
2512 SPR_NOACCESS
, SPR_NOACCESS
,
2513 &spr_read_generic
, &spr_write_generic
,
2515 /* XXX : not implemented */
2516 spr_register(env
, SPR_MPC_MI_DBRAM0
, "MI_DBRAM0",
2517 SPR_NOACCESS
, SPR_NOACCESS
,
2518 &spr_read_generic
, &spr_write_generic
,
2520 /* XXX : not implemented */
2521 spr_register(env
, SPR_MPC_MI_DBRAM1
, "MI_DBRAM1",
2522 SPR_NOACCESS
, SPR_NOACCESS
,
2523 &spr_read_generic
, &spr_write_generic
,
2525 /* XXX : not implemented */
2526 spr_register(env
, SPR_MPC_MD_CTR
, "MD_CTR",
2527 SPR_NOACCESS
, SPR_NOACCESS
,
2528 &spr_read_generic
, &spr_write_generic
,
2530 /* XXX : not implemented */
2531 spr_register(env
, SPR_MPC_MD_CASID
, "MD_CASID",
2532 SPR_NOACCESS
, SPR_NOACCESS
,
2533 &spr_read_generic
, &spr_write_generic
,
2535 /* XXX : not implemented */
2536 spr_register(env
, SPR_MPC_MD_AP
, "MD_AP",
2537 SPR_NOACCESS
, SPR_NOACCESS
,
2538 &spr_read_generic
, &spr_write_generic
,
2540 /* XXX : not implemented */
2541 spr_register(env
, SPR_MPC_MD_EPN
, "MD_EPN",
2542 SPR_NOACCESS
, SPR_NOACCESS
,
2543 &spr_read_generic
, &spr_write_generic
,
2545 /* XXX : not implemented */
2546 spr_register(env
, SPR_MPC_MD_TWB
, "MD_TWB",
2547 SPR_NOACCESS
, SPR_NOACCESS
,
2548 &spr_read_generic
, &spr_write_generic
,
2550 /* XXX : not implemented */
2551 spr_register(env
, SPR_MPC_MD_TWC
, "MD_TWC",
2552 SPR_NOACCESS
, SPR_NOACCESS
,
2553 &spr_read_generic
, &spr_write_generic
,
2555 /* XXX : not implemented */
2556 spr_register(env
, SPR_MPC_MD_RPN
, "MD_RPN",
2557 SPR_NOACCESS
, SPR_NOACCESS
,
2558 &spr_read_generic
, &spr_write_generic
,
2560 /* XXX : not implemented */
2561 spr_register(env
, SPR_MPC_MD_TW
, "MD_TW",
2562 SPR_NOACCESS
, SPR_NOACCESS
,
2563 &spr_read_generic
, &spr_write_generic
,
2565 /* XXX : not implemented */
2566 spr_register(env
, SPR_MPC_MD_DBCAM
, "MD_DBCAM",
2567 SPR_NOACCESS
, SPR_NOACCESS
,
2568 &spr_read_generic
, &spr_write_generic
,
2570 /* XXX : not implemented */
2571 spr_register(env
, SPR_MPC_MD_DBRAM0
, "MD_DBRAM0",
2572 SPR_NOACCESS
, SPR_NOACCESS
,
2573 &spr_read_generic
, &spr_write_generic
,
2575 /* XXX : not implemented */
2576 spr_register(env
, SPR_MPC_MD_DBRAM1
, "MD_DBRAM1",
2577 SPR_NOACCESS
, SPR_NOACCESS
,
2578 &spr_read_generic
, &spr_write_generic
,
2584 * AMR => SPR 29 (Power 2.04)
2585 * CTRL => SPR 136 (Power 2.04)
2586 * CTRL => SPR 152 (Power 2.04)
2587 * SCOMC => SPR 276 (64 bits ?)
2588 * SCOMD => SPR 277 (64 bits ?)
2589 * TBU40 => SPR 286 (Power 2.04 hypv)
2590 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2591 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2592 * HDSISR => SPR 306 (Power 2.04 hypv)
2593 * HDAR => SPR 307 (Power 2.04 hypv)
2594 * PURR => SPR 309 (Power 2.04 hypv)
2595 * HDEC => SPR 310 (Power 2.04 hypv)
2596 * HIOR => SPR 311 (hypv)
2597 * RMOR => SPR 312 (970)
2598 * HRMOR => SPR 313 (Power 2.04 hypv)
2599 * HSRR0 => SPR 314 (Power 2.04 hypv)
2600 * HSRR1 => SPR 315 (Power 2.04 hypv)
2601 * LPIDR => SPR 317 (970)
2602 * EPR => SPR 702 (Power 2.04 emb)
2603 * perf => 768-783 (Power 2.04)
2604 * perf => 784-799 (Power 2.04)
2605 * PPR => SPR 896 (Power 2.04)
2606 * EPLC => SPR 947 (Power 2.04 emb)
2607 * EPSC => SPR 948 (Power 2.04 emb)
2608 * DABRX => 1015 (Power 2.04 hypv)
2609 * FPECR => SPR 1022 (?)
2610 * ... and more (thermal management, performance counters, ...)
2613 /*****************************************************************************/
2614 /* Exception vectors models */
2615 static void init_excp_4xx_real (CPUPPCState
*env
)
2617 #if !defined(CONFIG_USER_ONLY)
2618 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2619 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2620 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2621 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2622 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2623 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2624 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2625 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2626 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2627 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2628 env
->ivor_mask
= 0x0000FFF0UL
;
2629 env
->ivpr_mask
= 0xFFFF0000UL
;
2630 /* Hardware reset vector */
2631 env
->hreset_vector
= 0xFFFFFFFCUL
;
2635 static void init_excp_4xx_softmmu (CPUPPCState
*env
)
2637 #if !defined(CONFIG_USER_ONLY)
2638 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000100;
2639 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2640 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2641 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2642 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2643 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2644 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2645 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2646 env
->excp_vectors
[POWERPC_EXCP_PIT
] = 0x00001000;
2647 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00001010;
2648 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001020;
2649 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001100;
2650 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001200;
2651 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00002000;
2652 env
->ivor_mask
= 0x0000FFF0UL
;
2653 env
->ivpr_mask
= 0xFFFF0000UL
;
2654 /* Hardware reset vector */
2655 env
->hreset_vector
= 0xFFFFFFFCUL
;
2659 static void init_excp_MPC5xx (CPUPPCState
*env
)
2661 #if !defined(CONFIG_USER_ONLY)
2662 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2663 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2664 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2665 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2666 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2667 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000900;
2668 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2669 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2670 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2671 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2672 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
2673 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
2674 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
2675 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
2676 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
2677 env
->ivor_mask
= 0x0000FFF0UL
;
2678 env
->ivpr_mask
= 0xFFFF0000UL
;
2679 /* Hardware reset vector */
2680 env
->hreset_vector
= 0x00000100UL
;
2684 static void init_excp_MPC8xx (CPUPPCState
*env
)
2686 #if !defined(CONFIG_USER_ONLY)
2687 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2688 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2689 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2690 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2691 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2692 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2693 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2694 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000900;
2695 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2696 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2697 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2698 env
->excp_vectors
[POWERPC_EXCP_FPA
] = 0x00000E00;
2699 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001000;
2700 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00001100;
2701 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00001200;
2702 env
->excp_vectors
[POWERPC_EXCP_ITLBE
] = 0x00001300;
2703 env
->excp_vectors
[POWERPC_EXCP_DTLBE
] = 0x00001400;
2704 env
->excp_vectors
[POWERPC_EXCP_DABR
] = 0x00001C00;
2705 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001C00;
2706 env
->excp_vectors
[POWERPC_EXCP_MEXTBR
] = 0x00001E00;
2707 env
->excp_vectors
[POWERPC_EXCP_NMEXTBR
] = 0x00001F00;
2708 env
->ivor_mask
= 0x0000FFF0UL
;
2709 env
->ivpr_mask
= 0xFFFF0000UL
;
2710 /* Hardware reset vector */
2711 env
->hreset_vector
= 0x00000100UL
;
2715 static void init_excp_G2 (CPUPPCState
*env
)
2717 #if !defined(CONFIG_USER_ONLY)
2718 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2719 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2720 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2721 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2722 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2723 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2724 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2725 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2726 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2727 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000A00;
2728 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2729 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2730 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2731 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2732 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2733 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2734 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2735 /* Hardware reset vector */
2736 env
->hreset_vector
= 0x00000100UL
;
2740 static void init_excp_e200(CPUPPCState
*env
, target_ulong ivpr_mask
)
2742 #if !defined(CONFIG_USER_ONLY)
2743 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000FFC;
2744 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2745 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2746 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2747 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2748 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2749 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2750 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2751 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2752 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2753 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2754 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2755 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2756 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2757 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2758 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2759 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2760 env
->excp_vectors
[POWERPC_EXCP_SPEU
] = 0x00000000;
2761 env
->excp_vectors
[POWERPC_EXCP_EFPDI
] = 0x00000000;
2762 env
->excp_vectors
[POWERPC_EXCP_EFPRI
] = 0x00000000;
2763 env
->ivor_mask
= 0x0000FFF7UL
;
2764 env
->ivpr_mask
= ivpr_mask
;
2765 /* Hardware reset vector */
2766 env
->hreset_vector
= 0xFFFFFFFCUL
;
2770 static void init_excp_BookE (CPUPPCState
*env
)
2772 #if !defined(CONFIG_USER_ONLY)
2773 env
->excp_vectors
[POWERPC_EXCP_CRITICAL
] = 0x00000000;
2774 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000000;
2775 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000000;
2776 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000000;
2777 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000000;
2778 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000000;
2779 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000000;
2780 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000000;
2781 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000000;
2782 env
->excp_vectors
[POWERPC_EXCP_APU
] = 0x00000000;
2783 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000000;
2784 env
->excp_vectors
[POWERPC_EXCP_FIT
] = 0x00000000;
2785 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00000000;
2786 env
->excp_vectors
[POWERPC_EXCP_DTLB
] = 0x00000000;
2787 env
->excp_vectors
[POWERPC_EXCP_ITLB
] = 0x00000000;
2788 env
->excp_vectors
[POWERPC_EXCP_DEBUG
] = 0x00000000;
2789 env
->ivor_mask
= 0x0000FFE0UL
;
2790 env
->ivpr_mask
= 0xFFFF0000UL
;
2791 /* Hardware reset vector */
2792 env
->hreset_vector
= 0xFFFFFFFCUL
;
2796 static void init_excp_601 (CPUPPCState
*env
)
2798 #if !defined(CONFIG_USER_ONLY)
2799 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2800 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2801 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2802 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2803 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2804 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2805 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2806 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2807 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2808 env
->excp_vectors
[POWERPC_EXCP_IO
] = 0x00000A00;
2809 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2810 env
->excp_vectors
[POWERPC_EXCP_RUNM
] = 0x00002000;
2811 /* Hardware reset vector */
2812 env
->hreset_vector
= 0x00000100UL
;
2816 static void init_excp_602 (CPUPPCState
*env
)
2818 #if !defined(CONFIG_USER_ONLY)
2819 /* XXX: exception prefix has a special behavior on 602 */
2820 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2821 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2822 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2823 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2824 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2825 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2826 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2827 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2828 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2829 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2830 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2831 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2832 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2833 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2834 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2835 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2836 env
->excp_vectors
[POWERPC_EXCP_WDT
] = 0x00001500;
2837 env
->excp_vectors
[POWERPC_EXCP_EMUL
] = 0x00001600;
2838 /* Hardware reset vector */
2839 env
->hreset_vector
= 0x00000100UL
;
2843 static void init_excp_603 (CPUPPCState
*env
)
2845 #if !defined(CONFIG_USER_ONLY)
2846 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2847 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2848 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2849 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2850 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2851 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2852 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2853 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2854 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2855 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2856 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2857 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2858 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2859 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2860 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2861 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2862 /* Hardware reset vector */
2863 env
->hreset_vector
= 0x00000100UL
;
2867 static void init_excp_604 (CPUPPCState
*env
)
2869 #if !defined(CONFIG_USER_ONLY)
2870 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2871 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2872 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2873 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2874 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2875 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2876 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2877 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2878 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2879 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2880 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2881 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2882 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2883 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2884 /* Hardware reset vector */
2885 env
->hreset_vector
= 0x00000100UL
;
2889 static void init_excp_7x0 (CPUPPCState
*env
)
2891 #if !defined(CONFIG_USER_ONLY)
2892 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2893 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2894 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2895 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2896 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2897 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2898 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2899 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2900 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2901 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2902 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2903 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2904 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2905 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2906 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2907 /* Hardware reset vector */
2908 env
->hreset_vector
= 0x00000100UL
;
2912 static void init_excp_750cl (CPUPPCState
*env
)
2914 #if !defined(CONFIG_USER_ONLY)
2915 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2916 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2917 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2918 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2919 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2920 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2921 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2922 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2923 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2924 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2925 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2926 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2927 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2928 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2929 /* Hardware reset vector */
2930 env
->hreset_vector
= 0x00000100UL
;
2934 static void init_excp_750cx (CPUPPCState
*env
)
2936 #if !defined(CONFIG_USER_ONLY)
2937 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2938 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2939 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2940 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2941 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2942 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2943 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2944 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2945 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2946 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2947 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2948 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2949 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2950 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2951 /* Hardware reset vector */
2952 env
->hreset_vector
= 0x00000100UL
;
2956 /* XXX: Check if this is correct */
2957 static void init_excp_7x5 (CPUPPCState
*env
)
2959 #if !defined(CONFIG_USER_ONLY)
2960 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2961 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2962 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2963 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2964 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2965 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2966 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2967 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2968 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2969 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2970 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2971 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2972 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
2973 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
2974 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
2975 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
2976 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
2977 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
2978 /* Hardware reset vector */
2979 env
->hreset_vector
= 0x00000100UL
;
2983 static void init_excp_7400 (CPUPPCState
*env
)
2985 #if !defined(CONFIG_USER_ONLY)
2986 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
2987 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
2988 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
2989 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
2990 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
2991 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
2992 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
2993 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
2994 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
2995 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
2996 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
2997 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
2998 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
2999 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3000 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3001 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
3002 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001700;
3003 /* Hardware reset vector */
3004 env
->hreset_vector
= 0x00000100UL
;
3008 static void init_excp_7450 (CPUPPCState
*env
)
3010 #if !defined(CONFIG_USER_ONLY)
3011 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3012 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3013 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3014 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3015 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3016 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3017 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3018 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3019 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3020 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3021 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3022 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3023 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3024 env
->excp_vectors
[POWERPC_EXCP_IFTLB
] = 0x00001000;
3025 env
->excp_vectors
[POWERPC_EXCP_DLTLB
] = 0x00001100;
3026 env
->excp_vectors
[POWERPC_EXCP_DSTLB
] = 0x00001200;
3027 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3028 env
->excp_vectors
[POWERPC_EXCP_SMI
] = 0x00001400;
3029 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001600;
3030 /* Hardware reset vector */
3031 env
->hreset_vector
= 0x00000100UL
;
3035 #if defined (TARGET_PPC64)
3036 static void init_excp_970 (CPUPPCState
*env
)
3038 #if !defined(CONFIG_USER_ONLY)
3039 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3040 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3041 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3042 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
3043 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3044 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
3045 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3046 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3047 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3048 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3049 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3050 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
3051 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3052 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3053 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3054 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3055 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3056 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
3057 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
3058 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
3059 /* Hardware reset vector */
3060 env
->hreset_vector
= 0x0000000000000100ULL
;
3064 static void init_excp_POWER7 (CPUPPCState
*env
)
3066 #if !defined(CONFIG_USER_ONLY)
3067 env
->excp_vectors
[POWERPC_EXCP_RESET
] = 0x00000100;
3068 env
->excp_vectors
[POWERPC_EXCP_MCHECK
] = 0x00000200;
3069 env
->excp_vectors
[POWERPC_EXCP_DSI
] = 0x00000300;
3070 env
->excp_vectors
[POWERPC_EXCP_DSEG
] = 0x00000380;
3071 env
->excp_vectors
[POWERPC_EXCP_ISI
] = 0x00000400;
3072 env
->excp_vectors
[POWERPC_EXCP_ISEG
] = 0x00000480;
3073 env
->excp_vectors
[POWERPC_EXCP_EXTERNAL
] = 0x00000500;
3074 env
->excp_vectors
[POWERPC_EXCP_ALIGN
] = 0x00000600;
3075 env
->excp_vectors
[POWERPC_EXCP_PROGRAM
] = 0x00000700;
3076 env
->excp_vectors
[POWERPC_EXCP_FPU
] = 0x00000800;
3077 env
->excp_vectors
[POWERPC_EXCP_DECR
] = 0x00000900;
3078 env
->excp_vectors
[POWERPC_EXCP_HDECR
] = 0x00000980;
3079 env
->excp_vectors
[POWERPC_EXCP_SYSCALL
] = 0x00000C00;
3080 env
->excp_vectors
[POWERPC_EXCP_TRACE
] = 0x00000D00;
3081 env
->excp_vectors
[POWERPC_EXCP_PERFM
] = 0x00000F00;
3082 env
->excp_vectors
[POWERPC_EXCP_VPU
] = 0x00000F20;
3083 env
->excp_vectors
[POWERPC_EXCP_VSXU
] = 0x00000F40;
3084 env
->excp_vectors
[POWERPC_EXCP_FU
] = 0x00000F60;
3085 env
->excp_vectors
[POWERPC_EXCP_IABR
] = 0x00001300;
3086 env
->excp_vectors
[POWERPC_EXCP_MAINT
] = 0x00001600;
3087 env
->excp_vectors
[POWERPC_EXCP_VPUA
] = 0x00001700;
3088 env
->excp_vectors
[POWERPC_EXCP_THERM
] = 0x00001800;
3089 /* Hardware reset vector */
3090 env
->hreset_vector
= 0x0000000000000100ULL
;
3095 /*****************************************************************************/
3096 /* Power management enable checks */
3097 static int check_pow_none (CPUPPCState
*env
)
3102 static int check_pow_nocheck (CPUPPCState
*env
)
3107 static int check_pow_hid0 (CPUPPCState
*env
)
3109 if (env
->spr
[SPR_HID0
] & 0x00E00000)
3115 static int check_pow_hid0_74xx (CPUPPCState
*env
)
3117 if (env
->spr
[SPR_HID0
] & 0x00600000)
3123 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU
*cpu
)
3129 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU
*cpu
)
3131 return !(cpu
->env
.spr
[SPR_LPCR
] & LPCR_ILE
);
3135 /*****************************************************************************/
3136 /* PowerPC implementations definitions */
3138 #define POWERPC_FAMILY(_name) \
3140 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3142 static const TypeInfo \
3143 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3144 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3145 .parent = TYPE_POWERPC_CPU, \
3147 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3150 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3152 type_register_static( \
3153 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3156 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3158 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3160 static void init_proc_401 (CPUPPCState
*env
)
3163 gen_spr_401_403(env
);
3165 init_excp_4xx_real(env
);
3166 env
->dcache_line_size
= 32;
3167 env
->icache_line_size
= 32;
3168 /* Allocate hardware IRQ controller */
3169 ppc40x_irq_init(env
);
3171 SET_FIT_PERIOD(12, 16, 20, 24);
3172 SET_WDT_PERIOD(16, 20, 24, 28);
3175 POWERPC_FAMILY(401)(ObjectClass
*oc
, void *data
)
3177 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3178 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3180 dc
->desc
= "PowerPC 401";
3181 pcc
->init_proc
= init_proc_401
;
3182 pcc
->check_pow
= check_pow_nocheck
;
3183 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3184 PPC_WRTEE
| PPC_DCR
|
3185 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
3187 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3188 PPC_4xx_COMMON
| PPC_40x_EXCP
;
3189 pcc
->msr_mask
= (1ull << MSR_KEY
) |
3198 pcc
->mmu_model
= POWERPC_MMU_REAL
;
3199 pcc
->excp_model
= POWERPC_EXCP_40x
;
3200 pcc
->bus_model
= PPC_FLAGS_INPUT_401
;
3201 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3202 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
3203 POWERPC_FLAG_BUS_CLK
;
3206 static void init_proc_401x2 (CPUPPCState
*env
)
3209 gen_spr_401_403(env
);
3211 gen_spr_compress(env
);
3212 /* Memory management */
3213 #if !defined(CONFIG_USER_ONLY)
3217 env
->tlb_type
= TLB_EMB
;
3219 init_excp_4xx_softmmu(env
);
3220 env
->dcache_line_size
= 32;
3221 env
->icache_line_size
= 32;
3222 /* Allocate hardware IRQ controller */
3223 ppc40x_irq_init(env
);
3225 SET_FIT_PERIOD(12, 16, 20, 24);
3226 SET_WDT_PERIOD(16, 20, 24, 28);
3229 POWERPC_FAMILY(401x2
)(ObjectClass
*oc
, void *data
)
3231 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3232 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3234 dc
->desc
= "PowerPC 401x2";
3235 pcc
->init_proc
= init_proc_401x2
;
3236 pcc
->check_pow
= check_pow_nocheck
;
3237 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3238 PPC_DCR
| PPC_WRTEE
|
3239 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
3240 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3241 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3242 PPC_40x_TLB
| PPC_MEM_TLBIA
| PPC_MEM_TLBSYNC
|
3243 PPC_4xx_COMMON
| PPC_40x_EXCP
;
3244 pcc
->msr_mask
= (1ull << 20) |
3256 pcc
->mmu_model
= POWERPC_MMU_SOFT_4xx_Z
;
3257 pcc
->excp_model
= POWERPC_EXCP_40x
;
3258 pcc
->bus_model
= PPC_FLAGS_INPUT_401
;
3259 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3260 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
3261 POWERPC_FLAG_BUS_CLK
;
3264 static void init_proc_401x3 (CPUPPCState
*env
)
3267 gen_spr_401_403(env
);
3270 gen_spr_compress(env
);
3271 init_excp_4xx_softmmu(env
);
3272 env
->dcache_line_size
= 32;
3273 env
->icache_line_size
= 32;
3274 /* Allocate hardware IRQ controller */
3275 ppc40x_irq_init(env
);
3277 SET_FIT_PERIOD(12, 16, 20, 24);
3278 SET_WDT_PERIOD(16, 20, 24, 28);
3281 POWERPC_FAMILY(401x3
)(ObjectClass
*oc
, void *data
)
3283 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3284 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3286 dc
->desc
= "PowerPC 401x3";
3287 pcc
->init_proc
= init_proc_401x3
;
3288 pcc
->check_pow
= check_pow_nocheck
;
3289 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3290 PPC_DCR
| PPC_WRTEE
|
3291 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
3292 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3293 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3294 PPC_40x_TLB
| PPC_MEM_TLBIA
| PPC_MEM_TLBSYNC
|
3295 PPC_4xx_COMMON
| PPC_40x_EXCP
;
3296 pcc
->msr_mask
= (1ull << 20) |
3309 pcc
->mmu_model
= POWERPC_MMU_SOFT_4xx_Z
;
3310 pcc
->excp_model
= POWERPC_EXCP_40x
;
3311 pcc
->bus_model
= PPC_FLAGS_INPUT_401
;
3312 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3313 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
3314 POWERPC_FLAG_BUS_CLK
;
3317 static void init_proc_IOP480 (CPUPPCState
*env
)
3320 gen_spr_401_403(env
);
3322 gen_spr_compress(env
);
3323 /* Memory management */
3324 #if !defined(CONFIG_USER_ONLY)
3328 env
->tlb_type
= TLB_EMB
;
3330 init_excp_4xx_softmmu(env
);
3331 env
->dcache_line_size
= 32;
3332 env
->icache_line_size
= 32;
3333 /* Allocate hardware IRQ controller */
3334 ppc40x_irq_init(env
);
3336 SET_FIT_PERIOD(8, 12, 16, 20);
3337 SET_WDT_PERIOD(16, 20, 24, 28);
3340 POWERPC_FAMILY(IOP480
)(ObjectClass
*oc
, void *data
)
3342 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3343 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3345 dc
->desc
= "IOP480";
3346 pcc
->init_proc
= init_proc_IOP480
;
3347 pcc
->check_pow
= check_pow_nocheck
;
3348 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3349 PPC_DCR
| PPC_WRTEE
|
3350 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
3351 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3352 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3353 PPC_40x_TLB
| PPC_MEM_TLBIA
| PPC_MEM_TLBSYNC
|
3354 PPC_4xx_COMMON
| PPC_40x_EXCP
;
3355 pcc
->msr_mask
= (1ull << 20) |
3367 pcc
->mmu_model
= POWERPC_MMU_SOFT_4xx_Z
;
3368 pcc
->excp_model
= POWERPC_EXCP_40x
;
3369 pcc
->bus_model
= PPC_FLAGS_INPUT_401
;
3370 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3371 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
3372 POWERPC_FLAG_BUS_CLK
;
3375 static void init_proc_403 (CPUPPCState
*env
)
3378 gen_spr_401_403(env
);
3380 gen_spr_403_real(env
);
3381 init_excp_4xx_real(env
);
3382 env
->dcache_line_size
= 32;
3383 env
->icache_line_size
= 32;
3384 /* Allocate hardware IRQ controller */
3385 ppc40x_irq_init(env
);
3387 SET_FIT_PERIOD(8, 12, 16, 20);
3388 SET_WDT_PERIOD(16, 20, 24, 28);
3391 POWERPC_FAMILY(403)(ObjectClass
*oc
, void *data
)
3393 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3394 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3396 dc
->desc
= "PowerPC 403";
3397 pcc
->init_proc
= init_proc_403
;
3398 pcc
->check_pow
= check_pow_nocheck
;
3399 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3400 PPC_DCR
| PPC_WRTEE
|
3401 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
3403 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3404 PPC_4xx_COMMON
| PPC_40x_EXCP
;
3405 pcc
->msr_mask
= (1ull << MSR_POW
) |
3414 pcc
->mmu_model
= POWERPC_MMU_REAL
;
3415 pcc
->excp_model
= POWERPC_EXCP_40x
;
3416 pcc
->bus_model
= PPC_FLAGS_INPUT_401
;
3417 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3418 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_PX
|
3419 POWERPC_FLAG_BUS_CLK
;
3422 static void init_proc_403GCX (CPUPPCState
*env
)
3425 gen_spr_401_403(env
);
3427 gen_spr_403_real(env
);
3428 gen_spr_403_mmu(env
);
3429 /* Bus access control */
3430 /* not emulated, as QEMU never does speculative access */
3431 spr_register(env
, SPR_40x_SGR
, "SGR",
3432 SPR_NOACCESS
, SPR_NOACCESS
,
3433 &spr_read_generic
, &spr_write_generic
,
3435 /* not emulated, as QEMU do not emulate caches */
3436 spr_register(env
, SPR_40x_DCWR
, "DCWR",
3437 SPR_NOACCESS
, SPR_NOACCESS
,
3438 &spr_read_generic
, &spr_write_generic
,
3440 /* Memory management */
3441 #if !defined(CONFIG_USER_ONLY)
3445 env
->tlb_type
= TLB_EMB
;
3447 init_excp_4xx_softmmu(env
);
3448 env
->dcache_line_size
= 32;
3449 env
->icache_line_size
= 32;
3450 /* Allocate hardware IRQ controller */
3451 ppc40x_irq_init(env
);
3453 SET_FIT_PERIOD(8, 12, 16, 20);
3454 SET_WDT_PERIOD(16, 20, 24, 28);
3457 POWERPC_FAMILY(403GCX
)(ObjectClass
*oc
, void *data
)
3459 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3460 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3462 dc
->desc
= "PowerPC 403 GCX";
3463 pcc
->init_proc
= init_proc_403GCX
;
3464 pcc
->check_pow
= check_pow_nocheck
;
3465 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3466 PPC_DCR
| PPC_WRTEE
|
3467 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
3469 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3470 PPC_40x_TLB
| PPC_MEM_TLBIA
| PPC_MEM_TLBSYNC
|
3471 PPC_4xx_COMMON
| PPC_40x_EXCP
;
3472 pcc
->msr_mask
= (1ull << MSR_POW
) |
3481 pcc
->mmu_model
= POWERPC_MMU_SOFT_4xx_Z
;
3482 pcc
->excp_model
= POWERPC_EXCP_40x
;
3483 pcc
->bus_model
= PPC_FLAGS_INPUT_401
;
3484 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3485 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_PX
|
3486 POWERPC_FLAG_BUS_CLK
;
3489 static void init_proc_405 (CPUPPCState
*env
)
3495 /* Bus access control */
3496 /* not emulated, as QEMU never does speculative access */
3497 spr_register(env
, SPR_40x_SGR
, "SGR",
3498 SPR_NOACCESS
, SPR_NOACCESS
,
3499 &spr_read_generic
, &spr_write_generic
,
3501 /* not emulated, as QEMU do not emulate caches */
3502 spr_register(env
, SPR_40x_DCWR
, "DCWR",
3503 SPR_NOACCESS
, SPR_NOACCESS
,
3504 &spr_read_generic
, &spr_write_generic
,
3506 /* Memory management */
3507 #if !defined(CONFIG_USER_ONLY)
3511 env
->tlb_type
= TLB_EMB
;
3513 init_excp_4xx_softmmu(env
);
3514 env
->dcache_line_size
= 32;
3515 env
->icache_line_size
= 32;
3516 /* Allocate hardware IRQ controller */
3517 ppc40x_irq_init(env
);
3519 SET_FIT_PERIOD(8, 12, 16, 20);
3520 SET_WDT_PERIOD(16, 20, 24, 28);
3523 POWERPC_FAMILY(405)(ObjectClass
*oc
, void *data
)
3525 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3526 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3528 dc
->desc
= "PowerPC 405";
3529 pcc
->init_proc
= init_proc_405
;
3530 pcc
->check_pow
= check_pow_nocheck
;
3531 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
3532 PPC_DCR
| PPC_WRTEE
|
3533 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_40x_ICBT
|
3534 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3535 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
3536 PPC_40x_TLB
| PPC_MEM_TLBIA
| PPC_MEM_TLBSYNC
|
3537 PPC_4xx_COMMON
| PPC_405_MAC
| PPC_40x_EXCP
;
3538 pcc
->msr_mask
= (1ull << MSR_POW
) |
3547 pcc
->mmu_model
= POWERPC_MMU_SOFT_4xx
;
3548 pcc
->excp_model
= POWERPC_EXCP_40x
;
3549 pcc
->bus_model
= PPC_FLAGS_INPUT_405
;
3550 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3551 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
3552 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
3555 static void init_proc_440EP (CPUPPCState
*env
)
3559 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3561 gen_spr_usprgh(env
);
3562 /* Processor identification */
3563 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3564 SPR_NOACCESS
, SPR_NOACCESS
,
3565 &spr_read_generic
, &spr_write_pir
,
3567 /* XXX : not implemented */
3568 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3569 SPR_NOACCESS
, SPR_NOACCESS
,
3570 &spr_read_generic
, &spr_write_generic
,
3572 /* XXX : not implemented */
3573 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3574 SPR_NOACCESS
, SPR_NOACCESS
,
3575 &spr_read_generic
, &spr_write_generic
,
3577 /* XXX : not implemented */
3578 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3579 SPR_NOACCESS
, SPR_NOACCESS
,
3580 &spr_read_generic
, &spr_write_generic
,
3582 /* XXX : not implemented */
3583 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3584 SPR_NOACCESS
, SPR_NOACCESS
,
3585 &spr_read_generic
, &spr_write_generic
,
3587 /* XXX : not implemented */
3588 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3589 SPR_NOACCESS
, SPR_NOACCESS
,
3590 &spr_read_generic
, &spr_write_generic
,
3592 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3593 SPR_NOACCESS
, SPR_NOACCESS
,
3594 &spr_read_generic
, &spr_write_generic
,
3596 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3597 SPR_NOACCESS
, SPR_NOACCESS
,
3598 &spr_read_generic
, &spr_write_generic
,
3600 /* XXX : not implemented */
3601 spr_register(env
, SPR_440_CCR1
, "CCR1",
3602 SPR_NOACCESS
, SPR_NOACCESS
,
3603 &spr_read_generic
, &spr_write_generic
,
3605 /* Memory management */
3606 #if !defined(CONFIG_USER_ONLY)
3610 env
->tlb_type
= TLB_EMB
;
3612 init_excp_BookE(env
);
3613 env
->dcache_line_size
= 32;
3614 env
->icache_line_size
= 32;
3615 ppc40x_irq_init(env
);
3617 SET_FIT_PERIOD(12, 16, 20, 24);
3618 SET_WDT_PERIOD(20, 24, 28, 32);
3621 POWERPC_FAMILY(440EP
)(ObjectClass
*oc
, void *data
)
3623 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3624 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3626 dc
->desc
= "PowerPC 440 EP";
3627 pcc
->init_proc
= init_proc_440EP
;
3628 pcc
->check_pow
= check_pow_nocheck
;
3629 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3630 PPC_FLOAT
| PPC_FLOAT_FRES
| PPC_FLOAT_FSEL
|
3631 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
3633 PPC_DCR
| PPC_WRTEE
| PPC_RFMCI
|
3634 PPC_CACHE
| PPC_CACHE_ICBI
|
3635 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3636 PPC_MEM_TLBSYNC
| PPC_MFTB
|
3637 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
3639 pcc
->msr_mask
= (1ull << MSR_POW
) |
3651 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
3652 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3653 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3654 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3655 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
3656 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
3659 static void init_proc_440GP (CPUPPCState
*env
)
3663 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3665 gen_spr_usprgh(env
);
3666 /* Processor identification */
3667 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3668 SPR_NOACCESS
, SPR_NOACCESS
,
3669 &spr_read_generic
, &spr_write_pir
,
3671 /* XXX : not implemented */
3672 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3673 SPR_NOACCESS
, SPR_NOACCESS
,
3674 &spr_read_generic
, &spr_write_generic
,
3676 /* XXX : not implemented */
3677 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3678 SPR_NOACCESS
, SPR_NOACCESS
,
3679 &spr_read_generic
, &spr_write_generic
,
3681 /* XXX : not implemented */
3682 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3683 SPR_NOACCESS
, SPR_NOACCESS
,
3684 &spr_read_generic
, &spr_write_generic
,
3686 /* XXX : not implemented */
3687 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3688 SPR_NOACCESS
, SPR_NOACCESS
,
3689 &spr_read_generic
, &spr_write_generic
,
3691 /* Memory management */
3692 #if !defined(CONFIG_USER_ONLY)
3696 env
->tlb_type
= TLB_EMB
;
3698 init_excp_BookE(env
);
3699 env
->dcache_line_size
= 32;
3700 env
->icache_line_size
= 32;
3701 /* XXX: TODO: allocate internal IRQ controller */
3703 SET_FIT_PERIOD(12, 16, 20, 24);
3704 SET_WDT_PERIOD(20, 24, 28, 32);
3707 POWERPC_FAMILY(440GP
)(ObjectClass
*oc
, void *data
)
3709 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3710 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3712 dc
->desc
= "PowerPC 440 GP";
3713 pcc
->init_proc
= init_proc_440GP
;
3714 pcc
->check_pow
= check_pow_nocheck
;
3715 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3716 PPC_DCR
| PPC_DCRX
| PPC_WRTEE
| PPC_MFAPIDI
|
3717 PPC_CACHE
| PPC_CACHE_ICBI
|
3718 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3719 PPC_MEM_TLBSYNC
| PPC_TLBIVA
| PPC_MFTB
|
3720 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
3722 pcc
->msr_mask
= (1ull << MSR_POW
) |
3734 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
3735 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3736 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3737 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3738 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
3739 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
3742 static void init_proc_440x4 (CPUPPCState
*env
)
3746 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3748 gen_spr_usprgh(env
);
3749 /* Processor identification */
3750 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3751 SPR_NOACCESS
, SPR_NOACCESS
,
3752 &spr_read_generic
, &spr_write_pir
,
3754 /* XXX : not implemented */
3755 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3756 SPR_NOACCESS
, SPR_NOACCESS
,
3757 &spr_read_generic
, &spr_write_generic
,
3759 /* XXX : not implemented */
3760 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3761 SPR_NOACCESS
, SPR_NOACCESS
,
3762 &spr_read_generic
, &spr_write_generic
,
3764 /* XXX : not implemented */
3765 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3766 SPR_NOACCESS
, SPR_NOACCESS
,
3767 &spr_read_generic
, &spr_write_generic
,
3769 /* XXX : not implemented */
3770 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3771 SPR_NOACCESS
, SPR_NOACCESS
,
3772 &spr_read_generic
, &spr_write_generic
,
3774 /* Memory management */
3775 #if !defined(CONFIG_USER_ONLY)
3779 env
->tlb_type
= TLB_EMB
;
3781 init_excp_BookE(env
);
3782 env
->dcache_line_size
= 32;
3783 env
->icache_line_size
= 32;
3784 /* XXX: TODO: allocate internal IRQ controller */
3786 SET_FIT_PERIOD(12, 16, 20, 24);
3787 SET_WDT_PERIOD(20, 24, 28, 32);
3790 POWERPC_FAMILY(440x4
)(ObjectClass
*oc
, void *data
)
3792 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3793 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3795 dc
->desc
= "PowerPC 440x4";
3796 pcc
->init_proc
= init_proc_440x4
;
3797 pcc
->check_pow
= check_pow_nocheck
;
3798 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3799 PPC_DCR
| PPC_WRTEE
|
3800 PPC_CACHE
| PPC_CACHE_ICBI
|
3801 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3802 PPC_MEM_TLBSYNC
| PPC_MFTB
|
3803 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
3805 pcc
->msr_mask
= (1ull << MSR_POW
) |
3817 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
3818 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3819 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3820 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3821 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
3822 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
3825 static void init_proc_440x5 (CPUPPCState
*env
)
3829 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3831 gen_spr_usprgh(env
);
3832 /* Processor identification */
3833 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3834 SPR_NOACCESS
, SPR_NOACCESS
,
3835 &spr_read_generic
, &spr_write_pir
,
3837 /* XXX : not implemented */
3838 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3839 SPR_NOACCESS
, SPR_NOACCESS
,
3840 &spr_read_generic
, &spr_write_generic
,
3842 /* XXX : not implemented */
3843 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3844 SPR_NOACCESS
, SPR_NOACCESS
,
3845 &spr_read_generic
, &spr_write_generic
,
3847 /* XXX : not implemented */
3848 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3849 SPR_NOACCESS
, SPR_NOACCESS
,
3850 &spr_read_generic
, &spr_write_generic
,
3852 /* XXX : not implemented */
3853 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3854 SPR_NOACCESS
, SPR_NOACCESS
,
3855 &spr_read_generic
, &spr_write_generic
,
3857 /* XXX : not implemented */
3858 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3859 SPR_NOACCESS
, SPR_NOACCESS
,
3860 &spr_read_generic
, &spr_write_generic
,
3862 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3863 SPR_NOACCESS
, SPR_NOACCESS
,
3864 &spr_read_generic
, &spr_write_generic
,
3866 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3867 SPR_NOACCESS
, SPR_NOACCESS
,
3868 &spr_read_generic
, &spr_write_generic
,
3870 /* XXX : not implemented */
3871 spr_register(env
, SPR_440_CCR1
, "CCR1",
3872 SPR_NOACCESS
, SPR_NOACCESS
,
3873 &spr_read_generic
, &spr_write_generic
,
3875 /* Memory management */
3876 #if !defined(CONFIG_USER_ONLY)
3880 env
->tlb_type
= TLB_EMB
;
3882 init_excp_BookE(env
);
3883 env
->dcache_line_size
= 32;
3884 env
->icache_line_size
= 32;
3885 ppc40x_irq_init(env
);
3887 SET_FIT_PERIOD(12, 16, 20, 24);
3888 SET_WDT_PERIOD(20, 24, 28, 32);
3891 POWERPC_FAMILY(440x5
)(ObjectClass
*oc
, void *data
)
3893 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3894 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
3896 dc
->desc
= "PowerPC 440x5";
3897 pcc
->init_proc
= init_proc_440x5
;
3898 pcc
->check_pow
= check_pow_nocheck
;
3899 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
3900 PPC_DCR
| PPC_WRTEE
| PPC_RFMCI
|
3901 PPC_CACHE
| PPC_CACHE_ICBI
|
3902 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
3903 PPC_MEM_TLBSYNC
| PPC_MFTB
|
3904 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
3906 pcc
->msr_mask
= (1ull << MSR_POW
) |
3918 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
3919 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
3920 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
3921 pcc
->bfd_mach
= bfd_mach_ppc_403
;
3922 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
3923 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
3926 static void init_proc_460 (CPUPPCState
*env
)
3930 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
3932 gen_spr_usprgh(env
);
3933 /* Processor identification */
3934 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
3935 SPR_NOACCESS
, SPR_NOACCESS
,
3936 &spr_read_generic
, &spr_write_pir
,
3938 /* XXX : not implemented */
3939 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
3940 SPR_NOACCESS
, SPR_NOACCESS
,
3941 &spr_read_generic
, &spr_write_generic
,
3943 /* XXX : not implemented */
3944 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
3945 SPR_NOACCESS
, SPR_NOACCESS
,
3946 &spr_read_generic
, &spr_write_generic
,
3948 /* XXX : not implemented */
3949 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
3950 SPR_NOACCESS
, SPR_NOACCESS
,
3951 &spr_read_generic
, &spr_write_generic
,
3953 /* XXX : not implemented */
3954 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
3955 SPR_NOACCESS
, SPR_NOACCESS
,
3956 &spr_read_generic
, &spr_write_generic
,
3958 /* XXX : not implemented */
3959 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
3960 SPR_NOACCESS
, SPR_NOACCESS
,
3961 &spr_read_generic
, &spr_write_generic
,
3963 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
3964 SPR_NOACCESS
, SPR_NOACCESS
,
3965 &spr_read_generic
, &spr_write_generic
,
3967 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
3968 SPR_NOACCESS
, SPR_NOACCESS
,
3969 &spr_read_generic
, &spr_write_generic
,
3971 /* XXX : not implemented */
3972 spr_register(env
, SPR_440_CCR1
, "CCR1",
3973 SPR_NOACCESS
, SPR_NOACCESS
,
3974 &spr_read_generic
, &spr_write_generic
,
3976 /* XXX : not implemented */
3977 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
3978 &spr_read_generic
, &spr_write_generic
,
3979 &spr_read_generic
, &spr_write_generic
,
3981 /* Memory management */
3982 #if !defined(CONFIG_USER_ONLY)
3986 env
->tlb_type
= TLB_EMB
;
3988 init_excp_BookE(env
);
3989 env
->dcache_line_size
= 32;
3990 env
->icache_line_size
= 32;
3991 /* XXX: TODO: allocate internal IRQ controller */
3993 SET_FIT_PERIOD(12, 16, 20, 24);
3994 SET_WDT_PERIOD(20, 24, 28, 32);
3997 POWERPC_FAMILY(460)(ObjectClass
*oc
, void *data
)
3999 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4000 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4002 dc
->desc
= "PowerPC 460 (guessed)";
4003 pcc
->init_proc
= init_proc_460
;
4004 pcc
->check_pow
= check_pow_nocheck
;
4005 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
4006 PPC_DCR
| PPC_DCRX
| PPC_DCRUX
|
4007 PPC_WRTEE
| PPC_MFAPIDI
| PPC_MFTB
|
4008 PPC_CACHE
| PPC_CACHE_ICBI
|
4009 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
4010 PPC_MEM_TLBSYNC
| PPC_TLBIVA
|
4011 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
4013 pcc
->msr_mask
= (1ull << MSR_POW
) |
4025 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
4026 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
4027 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
4028 pcc
->bfd_mach
= bfd_mach_ppc_403
;
4029 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
4030 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
4033 static void init_proc_460F (CPUPPCState
*env
)
4037 gen_spr_BookE(env
, 0x000000000000FFFFULL
);
4039 gen_spr_usprgh(env
);
4040 /* Processor identification */
4041 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
4042 SPR_NOACCESS
, SPR_NOACCESS
,
4043 &spr_read_generic
, &spr_write_pir
,
4045 /* XXX : not implemented */
4046 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
4047 SPR_NOACCESS
, SPR_NOACCESS
,
4048 &spr_read_generic
, &spr_write_generic
,
4050 /* XXX : not implemented */
4051 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
4052 SPR_NOACCESS
, SPR_NOACCESS
,
4053 &spr_read_generic
, &spr_write_generic
,
4055 /* XXX : not implemented */
4056 spr_register(env
, SPR_BOOKE_DVC1
, "DVC1",
4057 SPR_NOACCESS
, SPR_NOACCESS
,
4058 &spr_read_generic
, &spr_write_generic
,
4060 /* XXX : not implemented */
4061 spr_register(env
, SPR_BOOKE_DVC2
, "DVC2",
4062 SPR_NOACCESS
, SPR_NOACCESS
,
4063 &spr_read_generic
, &spr_write_generic
,
4065 /* XXX : not implemented */
4066 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
4067 SPR_NOACCESS
, SPR_NOACCESS
,
4068 &spr_read_generic
, &spr_write_generic
,
4070 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
4071 SPR_NOACCESS
, SPR_NOACCESS
,
4072 &spr_read_generic
, &spr_write_generic
,
4074 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
4075 SPR_NOACCESS
, SPR_NOACCESS
,
4076 &spr_read_generic
, &spr_write_generic
,
4078 /* XXX : not implemented */
4079 spr_register(env
, SPR_440_CCR1
, "CCR1",
4080 SPR_NOACCESS
, SPR_NOACCESS
,
4081 &spr_read_generic
, &spr_write_generic
,
4083 /* XXX : not implemented */
4084 spr_register(env
, SPR_DCRIPR
, "SPR_DCRIPR",
4085 &spr_read_generic
, &spr_write_generic
,
4086 &spr_read_generic
, &spr_write_generic
,
4088 /* Memory management */
4089 #if !defined(CONFIG_USER_ONLY)
4093 env
->tlb_type
= TLB_EMB
;
4095 init_excp_BookE(env
);
4096 env
->dcache_line_size
= 32;
4097 env
->icache_line_size
= 32;
4098 /* XXX: TODO: allocate internal IRQ controller */
4100 SET_FIT_PERIOD(12, 16, 20, 24);
4101 SET_WDT_PERIOD(20, 24, 28, 32);
4104 POWERPC_FAMILY(460F
)(ObjectClass
*oc
, void *data
)
4106 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4107 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4109 dc
->desc
= "PowerPC 460F (guessed)";
4110 pcc
->init_proc
= init_proc_460F
;
4111 pcc
->check_pow
= check_pow_nocheck
;
4112 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
4113 PPC_FLOAT
| PPC_FLOAT_FRES
| PPC_FLOAT_FSEL
|
4114 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
4115 PPC_FLOAT_STFIWX
| PPC_MFTB
|
4116 PPC_DCR
| PPC_DCRX
| PPC_DCRUX
|
4117 PPC_WRTEE
| PPC_MFAPIDI
|
4118 PPC_CACHE
| PPC_CACHE_ICBI
|
4119 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
4120 PPC_MEM_TLBSYNC
| PPC_TLBIVA
|
4121 PPC_BOOKE
| PPC_4xx_COMMON
| PPC_405_MAC
|
4123 pcc
->msr_mask
= (1ull << MSR_POW
) |
4135 pcc
->mmu_model
= POWERPC_MMU_BOOKE
;
4136 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
4137 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
4138 pcc
->bfd_mach
= bfd_mach_ppc_403
;
4139 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DWE
|
4140 POWERPC_FLAG_DE
| POWERPC_FLAG_BUS_CLK
;
4143 static void init_proc_MPC5xx (CPUPPCState
*env
)
4147 gen_spr_5xx_8xx(env
);
4149 init_excp_MPC5xx(env
);
4150 env
->dcache_line_size
= 32;
4151 env
->icache_line_size
= 32;
4152 /* XXX: TODO: allocate internal IRQ controller */
4155 POWERPC_FAMILY(MPC5xx
)(ObjectClass
*oc
, void *data
)
4157 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4158 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4160 dc
->desc
= "Freescale 5xx cores (aka RCPU)";
4161 pcc
->init_proc
= init_proc_MPC5xx
;
4162 pcc
->check_pow
= check_pow_none
;
4163 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
4164 PPC_MEM_EIEIO
| PPC_MEM_SYNC
|
4165 PPC_CACHE_ICBI
| PPC_FLOAT
| PPC_FLOAT_STFIWX
|
4167 pcc
->msr_mask
= (1ull << MSR_ILE
) |
4179 pcc
->mmu_model
= POWERPC_MMU_REAL
;
4180 pcc
->excp_model
= POWERPC_EXCP_603
;
4181 pcc
->bus_model
= PPC_FLAGS_INPUT_RCPU
;
4182 pcc
->bfd_mach
= bfd_mach_ppc_505
;
4183 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
4184 POWERPC_FLAG_BUS_CLK
;
4187 static void init_proc_MPC8xx (CPUPPCState
*env
)
4191 gen_spr_5xx_8xx(env
);
4193 init_excp_MPC8xx(env
);
4194 env
->dcache_line_size
= 32;
4195 env
->icache_line_size
= 32;
4196 /* XXX: TODO: allocate internal IRQ controller */
4199 POWERPC_FAMILY(MPC8xx
)(ObjectClass
*oc
, void *data
)
4201 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4202 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4204 dc
->desc
= "Freescale 8xx cores (aka PowerQUICC)";
4205 pcc
->init_proc
= init_proc_MPC8xx
;
4206 pcc
->check_pow
= check_pow_none
;
4207 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
|
4208 PPC_MEM_EIEIO
| PPC_MEM_SYNC
|
4209 PPC_CACHE_ICBI
| PPC_MFTB
;
4210 pcc
->msr_mask
= (1ull << MSR_ILE
) |
4222 pcc
->mmu_model
= POWERPC_MMU_MPC8xx
;
4223 pcc
->excp_model
= POWERPC_EXCP_603
;
4224 pcc
->bus_model
= PPC_FLAGS_INPUT_RCPU
;
4225 pcc
->bfd_mach
= bfd_mach_ppc_860
;
4226 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
4227 POWERPC_FLAG_BUS_CLK
;
4230 /* Freescale 82xx cores (aka PowerQUICC-II) */
4232 static void init_proc_G2 (CPUPPCState
*env
)
4234 gen_spr_ne_601(env
);
4235 gen_spr_G2_755(env
);
4239 /* External access control */
4240 /* XXX : not implemented */
4241 spr_register(env
, SPR_EAR
, "EAR",
4242 SPR_NOACCESS
, SPR_NOACCESS
,
4243 &spr_read_generic
, &spr_write_generic
,
4245 /* Hardware implementation register */
4246 /* XXX : not implemented */
4247 spr_register(env
, SPR_HID0
, "HID0",
4248 SPR_NOACCESS
, SPR_NOACCESS
,
4249 &spr_read_generic
, &spr_write_generic
,
4251 /* XXX : not implemented */
4252 spr_register(env
, SPR_HID1
, "HID1",
4253 SPR_NOACCESS
, SPR_NOACCESS
,
4254 &spr_read_generic
, &spr_write_generic
,
4256 /* XXX : not implemented */
4257 spr_register(env
, SPR_HID2
, "HID2",
4258 SPR_NOACCESS
, SPR_NOACCESS
,
4259 &spr_read_generic
, &spr_write_generic
,
4261 /* Memory management */
4264 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4266 env
->dcache_line_size
= 32;
4267 env
->icache_line_size
= 32;
4268 /* Allocate hardware IRQ controller */
4269 ppc6xx_irq_init(env
);
4272 POWERPC_FAMILY(G2
)(ObjectClass
*oc
, void *data
)
4274 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4275 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4277 dc
->desc
= "PowerPC G2";
4278 pcc
->init_proc
= init_proc_G2
;
4279 pcc
->check_pow
= check_pow_hid0
;
4280 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4281 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4283 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
4284 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4285 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
4286 PPC_SEGMENT
| PPC_EXTERN
;
4287 pcc
->msr_mask
= (1ull << MSR_POW
) |
4288 (1ull << MSR_TGPR
) |
4302 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
4303 pcc
->excp_model
= POWERPC_EXCP_G2
;
4304 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4305 pcc
->bfd_mach
= bfd_mach_ppc_ec603e
;
4306 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
4307 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
4310 static void init_proc_G2LE (CPUPPCState
*env
)
4312 gen_spr_ne_601(env
);
4313 gen_spr_G2_755(env
);
4317 /* External access control */
4318 /* XXX : not implemented */
4319 spr_register(env
, SPR_EAR
, "EAR",
4320 SPR_NOACCESS
, SPR_NOACCESS
,
4321 &spr_read_generic
, &spr_write_generic
,
4323 /* Hardware implementation register */
4324 /* XXX : not implemented */
4325 spr_register(env
, SPR_HID0
, "HID0",
4326 SPR_NOACCESS
, SPR_NOACCESS
,
4327 &spr_read_generic
, &spr_write_generic
,
4329 /* XXX : not implemented */
4330 spr_register(env
, SPR_HID1
, "HID1",
4331 SPR_NOACCESS
, SPR_NOACCESS
,
4332 &spr_read_generic
, &spr_write_generic
,
4334 /* XXX : not implemented */
4335 spr_register(env
, SPR_HID2
, "HID2",
4336 SPR_NOACCESS
, SPR_NOACCESS
,
4337 &spr_read_generic
, &spr_write_generic
,
4340 /* XXX : not implemented */
4341 spr_register(env
, SPR_DABR
, "DABR",
4342 SPR_NOACCESS
, SPR_NOACCESS
,
4343 &spr_read_generic
, &spr_write_generic
,
4345 /* XXX : not implemented */
4346 spr_register(env
, SPR_DABR2
, "DABR2",
4347 SPR_NOACCESS
, SPR_NOACCESS
,
4348 &spr_read_generic
, &spr_write_generic
,
4350 /* XXX : not implemented */
4351 spr_register(env
, SPR_IABR2
, "IABR2",
4352 SPR_NOACCESS
, SPR_NOACCESS
,
4353 &spr_read_generic
, &spr_write_generic
,
4355 /* XXX : not implemented */
4356 spr_register(env
, SPR_IBCR
, "IBCR",
4357 SPR_NOACCESS
, SPR_NOACCESS
,
4358 &spr_read_generic
, &spr_write_generic
,
4360 /* XXX : not implemented */
4361 spr_register(env
, SPR_DBCR
, "DBCR",
4362 SPR_NOACCESS
, SPR_NOACCESS
,
4363 &spr_read_generic
, &spr_write_generic
,
4366 /* Memory management */
4369 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4371 env
->dcache_line_size
= 32;
4372 env
->icache_line_size
= 32;
4373 /* Allocate hardware IRQ controller */
4374 ppc6xx_irq_init(env
);
4377 POWERPC_FAMILY(G2LE
)(ObjectClass
*oc
, void *data
)
4379 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4380 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4382 dc
->desc
= "PowerPC G2LE";
4383 pcc
->init_proc
= init_proc_G2LE
;
4384 pcc
->check_pow
= check_pow_hid0
;
4385 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4386 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4388 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
4389 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4390 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
4391 PPC_SEGMENT
| PPC_EXTERN
;
4392 pcc
->msr_mask
= (1ull << MSR_POW
) |
4393 (1ull << MSR_TGPR
) |
4409 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
4410 pcc
->excp_model
= POWERPC_EXCP_G2
;
4411 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4412 pcc
->bfd_mach
= bfd_mach_ppc_ec603e
;
4413 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
4414 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
4417 static void init_proc_e200 (CPUPPCState
*env
)
4421 gen_spr_BookE(env
, 0x000000070000FFFFULL
);
4422 /* XXX : not implemented */
4423 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
4424 &spr_read_spefscr
, &spr_write_spefscr
,
4425 &spr_read_spefscr
, &spr_write_spefscr
,
4427 /* Memory management */
4428 gen_spr_BookE206(env
, 0x0000005D, NULL
);
4429 /* XXX : not implemented */
4430 spr_register(env
, SPR_HID0
, "HID0",
4431 SPR_NOACCESS
, SPR_NOACCESS
,
4432 &spr_read_generic
, &spr_write_generic
,
4434 /* XXX : not implemented */
4435 spr_register(env
, SPR_HID1
, "HID1",
4436 SPR_NOACCESS
, SPR_NOACCESS
,
4437 &spr_read_generic
, &spr_write_generic
,
4439 /* XXX : not implemented */
4440 spr_register(env
, SPR_Exxx_ALTCTXCR
, "ALTCTXCR",
4441 SPR_NOACCESS
, SPR_NOACCESS
,
4442 &spr_read_generic
, &spr_write_generic
,
4444 /* XXX : not implemented */
4445 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
4446 SPR_NOACCESS
, SPR_NOACCESS
,
4447 &spr_read_generic
, &spr_write_generic
,
4449 /* XXX : not implemented */
4450 spr_register(env
, SPR_Exxx_CTXCR
, "CTXCR",
4451 SPR_NOACCESS
, SPR_NOACCESS
,
4452 &spr_read_generic
, &spr_write_generic
,
4454 /* XXX : not implemented */
4455 spr_register(env
, SPR_Exxx_DBCNT
, "DBCNT",
4456 SPR_NOACCESS
, SPR_NOACCESS
,
4457 &spr_read_generic
, &spr_write_generic
,
4459 /* XXX : not implemented */
4460 spr_register(env
, SPR_Exxx_DBCR3
, "DBCR3",
4461 SPR_NOACCESS
, SPR_NOACCESS
,
4462 &spr_read_generic
, &spr_write_generic
,
4464 /* XXX : not implemented */
4465 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
4466 &spr_read_generic
, SPR_NOACCESS
,
4467 &spr_read_generic
, SPR_NOACCESS
,
4469 /* XXX : not implemented */
4470 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
4471 SPR_NOACCESS
, SPR_NOACCESS
,
4472 &spr_read_generic
, &spr_write_generic
,
4474 /* XXX : not implemented */
4475 spr_register(env
, SPR_Exxx_L1FINV0
, "L1FINV0",
4476 SPR_NOACCESS
, SPR_NOACCESS
,
4477 &spr_read_generic
, &spr_write_generic
,
4479 /* XXX : not implemented */
4480 spr_register(env
, SPR_BOOKE_TLB0CFG
, "TLB0CFG",
4481 SPR_NOACCESS
, SPR_NOACCESS
,
4482 &spr_read_generic
, &spr_write_generic
,
4484 /* XXX : not implemented */
4485 spr_register(env
, SPR_BOOKE_TLB1CFG
, "TLB1CFG",
4486 SPR_NOACCESS
, SPR_NOACCESS
,
4487 &spr_read_generic
, &spr_write_generic
,
4489 /* XXX : not implemented */
4490 spr_register(env
, SPR_BOOKE_IAC3
, "IAC3",
4491 SPR_NOACCESS
, SPR_NOACCESS
,
4492 &spr_read_generic
, &spr_write_generic
,
4494 /* XXX : not implemented */
4495 spr_register(env
, SPR_BOOKE_IAC4
, "IAC4",
4496 SPR_NOACCESS
, SPR_NOACCESS
,
4497 &spr_read_generic
, &spr_write_generic
,
4499 /* XXX : not implemented */
4500 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4501 SPR_NOACCESS
, SPR_NOACCESS
,
4502 &spr_read_generic
, &spr_write_generic
,
4503 0x00000000); /* TOFIX */
4504 spr_register(env
, SPR_BOOKE_DSRR0
, "DSRR0",
4505 SPR_NOACCESS
, SPR_NOACCESS
,
4506 &spr_read_generic
, &spr_write_generic
,
4508 spr_register(env
, SPR_BOOKE_DSRR1
, "DSRR1",
4509 SPR_NOACCESS
, SPR_NOACCESS
,
4510 &spr_read_generic
, &spr_write_generic
,
4512 #if !defined(CONFIG_USER_ONLY)
4516 env
->tlb_type
= TLB_EMB
;
4518 init_excp_e200(env
, 0xFFFF0000UL
);
4519 env
->dcache_line_size
= 32;
4520 env
->icache_line_size
= 32;
4521 /* XXX: TODO: allocate internal IRQ controller */
4524 POWERPC_FAMILY(e200
)(ObjectClass
*oc
, void *data
)
4526 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4527 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4529 dc
->desc
= "e200 core";
4530 pcc
->init_proc
= init_proc_e200
;
4531 pcc
->check_pow
= check_pow_hid0
;
4532 /* XXX: unimplemented instructions:
4539 * all SPE multiply-accumulate instructions
4541 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
4542 PPC_SPE
| PPC_SPE_SINGLE
|
4543 PPC_WRTEE
| PPC_RFDI
|
4544 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
4545 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
4546 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
|
4548 pcc
->msr_mask
= (1ull << MSR_UCLE
) |
4562 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
4563 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
4564 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
4565 pcc
->bfd_mach
= bfd_mach_ppc_860
;
4566 pcc
->flags
= POWERPC_FLAG_SPE
| POWERPC_FLAG_CE
|
4567 POWERPC_FLAG_UBLE
| POWERPC_FLAG_DE
|
4568 POWERPC_FLAG_BUS_CLK
;
4571 static void init_proc_e300 (CPUPPCState
*env
)
4573 gen_spr_ne_601(env
);
4577 /* hardware implementation registers */
4578 /* XXX : not implemented */
4579 spr_register(env
, SPR_HID0
, "HID0",
4580 SPR_NOACCESS
, SPR_NOACCESS
,
4581 &spr_read_generic
, &spr_write_generic
,
4583 /* XXX : not implemented */
4584 spr_register(env
, SPR_HID1
, "HID1",
4585 SPR_NOACCESS
, SPR_NOACCESS
,
4586 &spr_read_generic
, &spr_write_generic
,
4588 /* XXX : not implemented */
4589 spr_register(env
, SPR_HID2
, "HID2",
4590 SPR_NOACCESS
, SPR_NOACCESS
,
4591 &spr_read_generic
, &spr_write_generic
,
4593 /* Memory management */
4596 gen_6xx_7xx_soft_tlb(env
, 64, 2);
4598 env
->dcache_line_size
= 32;
4599 env
->icache_line_size
= 32;
4600 /* Allocate hardware IRQ controller */
4601 ppc6xx_irq_init(env
);
4604 POWERPC_FAMILY(e300
)(ObjectClass
*oc
, void *data
)
4606 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4607 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4609 dc
->desc
= "e300 core";
4610 pcc
->init_proc
= init_proc_e300
;
4611 pcc
->check_pow
= check_pow_hid0
;
4612 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
4613 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
4615 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
4616 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
4617 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
4618 PPC_SEGMENT
| PPC_EXTERN
;
4619 pcc
->msr_mask
= (1ull << MSR_POW
) |
4620 (1ull << MSR_TGPR
) |
4636 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
4637 pcc
->excp_model
= POWERPC_EXCP_603
;
4638 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
4639 pcc
->bfd_mach
= bfd_mach_ppc_603
;
4640 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
4641 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
4644 #if !defined(CONFIG_USER_ONLY)
4645 static void spr_write_mas73(void *opaque
, int sprn
, int gprn
)
4647 TCGv val
= tcg_temp_new();
4648 tcg_gen_ext32u_tl(val
, cpu_gpr
[gprn
]);
4649 gen_store_spr(SPR_BOOKE_MAS3
, val
);
4650 tcg_gen_shri_tl(val
, cpu_gpr
[gprn
], 32);
4651 gen_store_spr(SPR_BOOKE_MAS7
, val
);
4655 static void spr_read_mas73(void *opaque
, int gprn
, int sprn
)
4657 TCGv mas7
= tcg_temp_new();
4658 TCGv mas3
= tcg_temp_new();
4659 gen_load_spr(mas7
, SPR_BOOKE_MAS7
);
4660 tcg_gen_shli_tl(mas7
, mas7
, 32);
4661 gen_load_spr(mas3
, SPR_BOOKE_MAS3
);
4662 tcg_gen_or_tl(cpu_gpr
[gprn
], mas3
, mas7
);
4663 tcg_temp_free(mas3
);
4664 tcg_temp_free(mas7
);
4669 enum fsl_e500_version
{
4676 static void init_proc_e500 (CPUPPCState
*env
, int version
)
4678 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
4679 uint32_t tlbncfg
[2];
4681 uint64_t ivpr_mask
= 0xFFFF0000ULL
;
4682 uint32_t l1cfg0
= 0x3800 /* 8 ways */
4683 | 0x0020; /* 32 kb */
4684 uint32_t l1cfg1
= 0x3800 /* 8 ways */
4685 | 0x0020; /* 32 kb */
4686 #if !defined(CONFIG_USER_ONLY)
4693 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4694 * complain when accessing them.
4695 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4701 ivor_mask
= 0x0000000F0000FFFFULL
;
4705 ivor_mask
= 0x000003FE0000FFFFULL
;
4708 gen_spr_BookE(env
, ivor_mask
);
4709 /* Processor identification */
4710 spr_register(env
, SPR_BOOKE_PIR
, "PIR",
4711 SPR_NOACCESS
, SPR_NOACCESS
,
4712 &spr_read_generic
, &spr_write_pir
,
4714 /* XXX : not implemented */
4715 spr_register(env
, SPR_BOOKE_SPEFSCR
, "SPEFSCR",
4716 &spr_read_spefscr
, &spr_write_spefscr
,
4717 &spr_read_spefscr
, &spr_write_spefscr
,
4719 #if !defined(CONFIG_USER_ONLY)
4720 /* Memory management */
4726 tlbncfg
[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4727 tlbncfg
[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 16);
4730 tlbncfg
[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4731 tlbncfg
[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 16);
4735 tlbncfg
[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4736 tlbncfg
[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL
| TLBnCFG_IPROT
, 64);
4739 cpu_abort(CPU(cpu
), "Unknown CPU: " TARGET_FMT_lx
"\n", env
->spr
[SPR_PVR
]);
4746 env
->dcache_line_size
= 32;
4747 env
->icache_line_size
= 32;
4751 env
->dcache_line_size
= 64;
4752 env
->icache_line_size
= 64;
4753 l1cfg0
|= 0x1000000; /* 64 byte cache block size */
4754 l1cfg1
|= 0x1000000; /* 64 byte cache block size */
4757 cpu_abort(CPU(cpu
), "Unknown CPU: " TARGET_FMT_lx
"\n", env
->spr
[SPR_PVR
]);
4759 gen_spr_BookE206(env
, 0x000000DF, tlbncfg
);
4760 /* XXX : not implemented */
4761 spr_register(env
, SPR_HID0
, "HID0",
4762 SPR_NOACCESS
, SPR_NOACCESS
,
4763 &spr_read_generic
, &spr_write_generic
,
4765 /* XXX : not implemented */
4766 spr_register(env
, SPR_HID1
, "HID1",
4767 SPR_NOACCESS
, SPR_NOACCESS
,
4768 &spr_read_generic
, &spr_write_generic
,
4770 /* XXX : not implemented */
4771 spr_register(env
, SPR_Exxx_BBEAR
, "BBEAR",
4772 SPR_NOACCESS
, SPR_NOACCESS
,
4773 &spr_read_generic
, &spr_write_generic
,
4775 /* XXX : not implemented */
4776 spr_register(env
, SPR_Exxx_BBTAR
, "BBTAR",
4777 SPR_NOACCESS
, SPR_NOACCESS
,
4778 &spr_read_generic
, &spr_write_generic
,
4780 /* XXX : not implemented */
4781 spr_register(env
, SPR_Exxx_MCAR
, "MCAR",
4782 SPR_NOACCESS
, SPR_NOACCESS
,
4783 &spr_read_generic
, &spr_write_generic
,
4785 /* XXX : not implemented */
4786 spr_register(env
, SPR_BOOKE_MCSR
, "MCSR",
4787 SPR_NOACCESS
, SPR_NOACCESS
,
4788 &spr_read_generic
, &spr_write_generic
,
4790 /* XXX : not implemented */
4791 spr_register(env
, SPR_Exxx_NPIDR
, "NPIDR",
4792 SPR_NOACCESS
, SPR_NOACCESS
,
4793 &spr_read_generic
, &spr_write_generic
,
4795 /* XXX : not implemented */
4796 spr_register(env
, SPR_Exxx_BUCSR
, "BUCSR",
4797 SPR_NOACCESS
, SPR_NOACCESS
,
4798 &spr_read_generic
, &spr_write_generic
,
4800 /* XXX : not implemented */
4801 spr_register(env
, SPR_Exxx_L1CFG0
, "L1CFG0",
4802 &spr_read_generic
, SPR_NOACCESS
,
4803 &spr_read_generic
, SPR_NOACCESS
,
4805 spr_register(env
, SPR_Exxx_L1CFG1
, "L1CFG1",
4806 &spr_read_generic
, SPR_NOACCESS
,
4807 &spr_read_generic
, SPR_NOACCESS
,
4809 spr_register(env
, SPR_Exxx_L1CSR0
, "L1CSR0",
4810 SPR_NOACCESS
, SPR_NOACCESS
,
4811 &spr_read_generic
, &spr_write_e500_l1csr0
,
4813 spr_register(env
, SPR_Exxx_L1CSR1
, "L1CSR1",
4814 SPR_NOACCESS
, SPR_NOACCESS
,
4815 &spr_read_generic
, &spr_write_e500_l1csr1
,
4817 spr_register(env
, SPR_BOOKE_MCSRR0
, "MCSRR0",
4818 SPR_NOACCESS
, SPR_NOACCESS
,
4819 &spr_read_generic
, &spr_write_generic
,
4821 spr_register(env
, SPR_BOOKE_MCSRR1
, "MCSRR1",
4822 SPR_NOACCESS
, SPR_NOACCESS
,
4823 &spr_read_generic
, &spr_write_generic
,
4825 spr_register(env
, SPR_MMUCSR0
, "MMUCSR0",
4826 SPR_NOACCESS
, SPR_NOACCESS
,
4827 &spr_read_generic
, &spr_write_booke206_mmucsr0
,
4829 spr_register(env
, SPR_BOOKE_EPR
, "EPR",
4830 SPR_NOACCESS
, SPR_NOACCESS
,
4831 &spr_read_generic
, SPR_NOACCESS
,
4833 /* XXX better abstract into Emb.xxx features */
4834 if (version
== fsl_e5500
) {
4835 spr_register(env
, SPR_BOOKE_EPCR
, "EPCR",
4836 SPR_NOACCESS
, SPR_NOACCESS
,
4837 &spr_read_generic
, &spr_write_generic
,
4839 spr_register(env
, SPR_BOOKE_MAS7_MAS3
, "MAS7_MAS3",
4840 SPR_NOACCESS
, SPR_NOACCESS
,
4841 &spr_read_mas73
, &spr_write_mas73
,
4843 ivpr_mask
= (target_ulong
)~0xFFFFULL
;
4846 #if !defined(CONFIG_USER_ONLY)
4848 env
->tlb_type
= TLB_MAS
;
4849 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
4850 env
->nb_tlb
+= booke206_tlb_size(env
, i
);
4854 init_excp_e200(env
, ivpr_mask
);
4855 /* Allocate hardware IRQ controller */
4856 ppce500_irq_init(env
);
4859 static void init_proc_e500v1(CPUPPCState
*env
)
4861 init_proc_e500(env
, fsl_e500v1
);
4864 POWERPC_FAMILY(e500v1
)(ObjectClass
*oc
, void *data
)
4866 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4867 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4869 dc
->desc
= "e500v1 core";
4870 pcc
->init_proc
= init_proc_e500v1
;
4871 pcc
->check_pow
= check_pow_hid0
;
4872 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
4873 PPC_SPE
| PPC_SPE_SINGLE
|
4874 PPC_WRTEE
| PPC_RFDI
|
4875 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
4876 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
4877 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
;
4878 pcc
->insns_flags2
= PPC2_BOOKE206
;
4879 pcc
->msr_mask
= (1ull << MSR_UCLE
) |
4893 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
4894 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
4895 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
4896 pcc
->bfd_mach
= bfd_mach_ppc_860
;
4897 pcc
->flags
= POWERPC_FLAG_SPE
| POWERPC_FLAG_CE
|
4898 POWERPC_FLAG_UBLE
| POWERPC_FLAG_DE
|
4899 POWERPC_FLAG_BUS_CLK
;
4902 static void init_proc_e500v2(CPUPPCState
*env
)
4904 init_proc_e500(env
, fsl_e500v2
);
4907 POWERPC_FAMILY(e500v2
)(ObjectClass
*oc
, void *data
)
4909 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4910 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4912 dc
->desc
= "e500v2 core";
4913 pcc
->init_proc
= init_proc_e500v2
;
4914 pcc
->check_pow
= check_pow_hid0
;
4915 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
4916 PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
|
4917 PPC_WRTEE
| PPC_RFDI
|
4918 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
4919 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
4920 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
;
4921 pcc
->insns_flags2
= PPC2_BOOKE206
;
4922 pcc
->msr_mask
= (1ull << MSR_UCLE
) |
4936 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
4937 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
4938 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
4939 pcc
->bfd_mach
= bfd_mach_ppc_860
;
4940 pcc
->flags
= POWERPC_FLAG_SPE
| POWERPC_FLAG_CE
|
4941 POWERPC_FLAG_UBLE
| POWERPC_FLAG_DE
|
4942 POWERPC_FLAG_BUS_CLK
;
4945 static void init_proc_e500mc(CPUPPCState
*env
)
4947 init_proc_e500(env
, fsl_e500mc
);
4950 POWERPC_FAMILY(e500mc
)(ObjectClass
*oc
, void *data
)
4952 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4953 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
4955 dc
->desc
= "e500mc core";
4956 pcc
->init_proc
= init_proc_e500mc
;
4957 pcc
->check_pow
= check_pow_none
;
4958 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
4959 PPC_WRTEE
| PPC_RFDI
| PPC_RFMCI
|
4960 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
4961 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
4962 PPC_FLOAT
| PPC_FLOAT_FRES
|
4963 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FSEL
|
4964 PPC_FLOAT_STFIWX
| PPC_WAIT
|
4965 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
;
4966 pcc
->insns_flags2
= PPC2_BOOKE206
| PPC2_PRCNTL
;
4967 pcc
->msr_mask
= (1ull << MSR_GS
) |
4968 (1ull << MSR_UCLE
) |
4981 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
4982 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
4983 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
4984 /* FIXME: figure out the correct flag for e500mc */
4985 pcc
->bfd_mach
= bfd_mach_ppc_e500
;
4986 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
4987 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
4991 static void init_proc_e5500(CPUPPCState
*env
)
4993 init_proc_e500(env
, fsl_e5500
);
4996 POWERPC_FAMILY(e5500
)(ObjectClass
*oc
, void *data
)
4998 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4999 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5001 dc
->desc
= "e5500 core";
5002 pcc
->init_proc
= init_proc_e5500
;
5003 pcc
->check_pow
= check_pow_none
;
5004 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
|
5005 PPC_WRTEE
| PPC_RFDI
| PPC_RFMCI
|
5006 PPC_CACHE
| PPC_CACHE_LOCK
| PPC_CACHE_ICBI
|
5007 PPC_CACHE_DCBZ
| PPC_CACHE_DCBA
|
5008 PPC_FLOAT
| PPC_FLOAT_FRES
|
5009 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FSEL
|
5010 PPC_FLOAT_STFIWX
| PPC_WAIT
|
5011 PPC_MEM_TLBSYNC
| PPC_TLBIVAX
| PPC_MEM_SYNC
|
5012 PPC_64B
| PPC_POPCNTB
| PPC_POPCNTWD
;
5013 pcc
->insns_flags2
= PPC2_BOOKE206
| PPC2_PRCNTL
| PPC2_PERM_ISA206
;
5014 pcc
->msr_mask
= (1ull << MSR_CM
) |
5016 (1ull << MSR_UCLE
) |
5029 pcc
->mmu_model
= POWERPC_MMU_BOOKE206
;
5030 pcc
->excp_model
= POWERPC_EXCP_BOOKE
;
5031 pcc
->bus_model
= PPC_FLAGS_INPUT_BookE
;
5032 /* FIXME: figure out the correct flag for e5500 */
5033 pcc
->bfd_mach
= bfd_mach_ppc_e500
;
5034 pcc
->flags
= POWERPC_FLAG_CE
| POWERPC_FLAG_DE
|
5035 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
5039 /* Non-embedded PowerPC */
5041 /* POWER : same as 601, without mfmsr, mfsr */
5042 POWERPC_FAMILY(POWER
)(ObjectClass
*oc
, void *data
)
5044 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5045 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5048 /* pcc->insns_flags = XXX_TODO; */
5049 /* POWER RSC (from RAD6000) */
5050 pcc
->msr_mask
= (1ull << MSR_EE
) |
5063 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5065 static void init_proc_601 (CPUPPCState
*env
)
5067 gen_spr_ne_601(env
);
5069 /* Hardware implementation registers */
5070 /* XXX : not implemented */
5071 spr_register(env
, SPR_HID0
, "HID0",
5072 SPR_NOACCESS
, SPR_NOACCESS
,
5073 &spr_read_generic
, &spr_write_hid0_601
,
5075 /* XXX : not implemented */
5076 spr_register(env
, SPR_HID1
, "HID1",
5077 SPR_NOACCESS
, SPR_NOACCESS
,
5078 &spr_read_generic
, &spr_write_generic
,
5080 /* XXX : not implemented */
5081 spr_register(env
, SPR_601_HID2
, "HID2",
5082 SPR_NOACCESS
, SPR_NOACCESS
,
5083 &spr_read_generic
, &spr_write_generic
,
5085 /* XXX : not implemented */
5086 spr_register(env
, SPR_601_HID5
, "HID5",
5087 SPR_NOACCESS
, SPR_NOACCESS
,
5088 &spr_read_generic
, &spr_write_generic
,
5090 /* Memory management */
5092 /* XXX: beware that dcache line size is 64
5093 * but dcbz uses 32 bytes "sectors"
5094 * XXX: this breaks clcs instruction !
5096 env
->dcache_line_size
= 32;
5097 env
->icache_line_size
= 64;
5098 /* Allocate hardware IRQ controller */
5099 ppc6xx_irq_init(env
);
5102 POWERPC_FAMILY(601)(ObjectClass
*oc
, void *data
)
5104 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5105 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5107 dc
->desc
= "PowerPC 601";
5108 pcc
->init_proc
= init_proc_601
;
5109 pcc
->check_pow
= check_pow_none
;
5110 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_POWER_BR
|
5112 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5113 PPC_MEM_SYNC
| PPC_MEM_EIEIO
| PPC_MEM_TLBIE
|
5114 PPC_SEGMENT
| PPC_EXTERN
;
5115 pcc
->msr_mask
= (1ull << MSR_EE
) |
5125 pcc
->mmu_model
= POWERPC_MMU_601
;
5126 #if defined(CONFIG_SOFTMMU)
5127 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5129 pcc
->excp_model
= POWERPC_EXCP_601
;
5130 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5131 pcc
->bfd_mach
= bfd_mach_ppc_601
;
5132 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_RTC_CLK
;
5135 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5137 static void init_proc_601v (CPUPPCState
*env
)
5140 /* XXX : not implemented */
5141 spr_register(env
, SPR_601_HID15
, "HID15",
5142 SPR_NOACCESS
, SPR_NOACCESS
,
5143 &spr_read_generic
, &spr_write_generic
,
5147 POWERPC_FAMILY(601v
)(ObjectClass
*oc
, void *data
)
5149 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5150 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5152 dc
->desc
= "PowerPC 601v";
5153 pcc
->init_proc
= init_proc_601v
;
5154 pcc
->check_pow
= check_pow_none
;
5155 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_POWER_BR
|
5157 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5158 PPC_MEM_SYNC
| PPC_MEM_EIEIO
| PPC_MEM_TLBIE
|
5159 PPC_SEGMENT
| PPC_EXTERN
;
5160 pcc
->msr_mask
= (1ull << MSR_EE
) |
5170 pcc
->mmu_model
= POWERPC_MMU_601
;
5171 #if defined(CONFIG_SOFTMMU)
5172 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5174 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5175 pcc
->bfd_mach
= bfd_mach_ppc_601
;
5176 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_RTC_CLK
;
5179 static void init_proc_602 (CPUPPCState
*env
)
5181 gen_spr_ne_601(env
);
5185 /* hardware implementation registers */
5186 /* XXX : not implemented */
5187 spr_register(env
, SPR_HID0
, "HID0",
5188 SPR_NOACCESS
, SPR_NOACCESS
,
5189 &spr_read_generic
, &spr_write_generic
,
5191 /* XXX : not implemented */
5192 spr_register(env
, SPR_HID1
, "HID1",
5193 SPR_NOACCESS
, SPR_NOACCESS
,
5194 &spr_read_generic
, &spr_write_generic
,
5196 /* Memory management */
5198 gen_6xx_7xx_soft_tlb(env
, 64, 2);
5200 env
->dcache_line_size
= 32;
5201 env
->icache_line_size
= 32;
5202 /* Allocate hardware IRQ controller */
5203 ppc6xx_irq_init(env
);
5206 POWERPC_FAMILY(602)(ObjectClass
*oc
, void *data
)
5208 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5209 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5211 dc
->desc
= "PowerPC 602";
5212 pcc
->init_proc
= init_proc_602
;
5213 pcc
->check_pow
= check_pow_hid0
;
5214 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5215 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5216 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5217 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5218 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5219 PPC_MEM_TLBIE
| PPC_6xx_TLB
| PPC_MEM_TLBSYNC
|
5220 PPC_SEGMENT
| PPC_602_SPEC
;
5221 pcc
->msr_mask
= (1ull << MSR_VSX
) |
5224 (1ull << MSR_TGPR
) |
5239 /* XXX: 602 MMU is quite specific. Should add a special case */
5240 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
5241 pcc
->excp_model
= POWERPC_EXCP_602
;
5242 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5243 pcc
->bfd_mach
= bfd_mach_ppc_602
;
5244 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
5245 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
5248 static void init_proc_603 (CPUPPCState
*env
)
5250 gen_spr_ne_601(env
);
5254 /* hardware implementation registers */
5255 /* XXX : not implemented */
5256 spr_register(env
, SPR_HID0
, "HID0",
5257 SPR_NOACCESS
, SPR_NOACCESS
,
5258 &spr_read_generic
, &spr_write_generic
,
5260 /* XXX : not implemented */
5261 spr_register(env
, SPR_HID1
, "HID1",
5262 SPR_NOACCESS
, SPR_NOACCESS
,
5263 &spr_read_generic
, &spr_write_generic
,
5265 /* Memory management */
5267 gen_6xx_7xx_soft_tlb(env
, 64, 2);
5269 env
->dcache_line_size
= 32;
5270 env
->icache_line_size
= 32;
5271 /* Allocate hardware IRQ controller */
5272 ppc6xx_irq_init(env
);
5275 POWERPC_FAMILY(603)(ObjectClass
*oc
, void *data
)
5277 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5278 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5280 dc
->desc
= "PowerPC 603";
5281 pcc
->init_proc
= init_proc_603
;
5282 pcc
->check_pow
= check_pow_hid0
;
5283 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5284 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5285 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5286 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5287 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5288 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
5289 PPC_SEGMENT
| PPC_EXTERN
;
5290 pcc
->msr_mask
= (1ull << MSR_POW
) |
5291 (1ull << MSR_TGPR
) |
5306 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
5307 pcc
->excp_model
= POWERPC_EXCP_603
;
5308 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5309 pcc
->bfd_mach
= bfd_mach_ppc_603
;
5310 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
5311 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
5314 static void init_proc_603E (CPUPPCState
*env
)
5316 gen_spr_ne_601(env
);
5320 /* hardware implementation registers */
5321 /* XXX : not implemented */
5322 spr_register(env
, SPR_HID0
, "HID0",
5323 SPR_NOACCESS
, SPR_NOACCESS
,
5324 &spr_read_generic
, &spr_write_generic
,
5326 /* XXX : not implemented */
5327 spr_register(env
, SPR_HID1
, "HID1",
5328 SPR_NOACCESS
, SPR_NOACCESS
,
5329 &spr_read_generic
, &spr_write_generic
,
5331 /* Memory management */
5333 gen_6xx_7xx_soft_tlb(env
, 64, 2);
5335 env
->dcache_line_size
= 32;
5336 env
->icache_line_size
= 32;
5337 /* Allocate hardware IRQ controller */
5338 ppc6xx_irq_init(env
);
5341 POWERPC_FAMILY(603E
)(ObjectClass
*oc
, void *data
)
5343 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5344 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5346 dc
->desc
= "PowerPC 603e";
5347 pcc
->init_proc
= init_proc_603E
;
5348 pcc
->check_pow
= check_pow_hid0
;
5349 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5350 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5351 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5352 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5353 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5354 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
5355 PPC_SEGMENT
| PPC_EXTERN
;
5356 pcc
->msr_mask
= (1ull << MSR_POW
) |
5357 (1ull << MSR_TGPR
) |
5372 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
5373 pcc
->excp_model
= POWERPC_EXCP_603E
;
5374 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5375 pcc
->bfd_mach
= bfd_mach_ppc_ec603e
;
5376 pcc
->flags
= POWERPC_FLAG_TGPR
| POWERPC_FLAG_SE
|
5377 POWERPC_FLAG_BE
| POWERPC_FLAG_BUS_CLK
;
5380 static void init_proc_604 (CPUPPCState
*env
)
5382 gen_spr_ne_601(env
);
5386 /* Hardware implementation registers */
5387 /* XXX : not implemented */
5388 spr_register(env
, SPR_HID0
, "HID0",
5389 SPR_NOACCESS
, SPR_NOACCESS
,
5390 &spr_read_generic
, &spr_write_generic
,
5392 /* Memory management */
5395 env
->dcache_line_size
= 32;
5396 env
->icache_line_size
= 32;
5397 /* Allocate hardware IRQ controller */
5398 ppc6xx_irq_init(env
);
5401 POWERPC_FAMILY(604)(ObjectClass
*oc
, void *data
)
5403 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5404 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5406 dc
->desc
= "PowerPC 604";
5407 pcc
->init_proc
= init_proc_604
;
5408 pcc
->check_pow
= check_pow_nocheck
;
5409 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5410 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5411 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5412 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5413 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5414 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5415 PPC_SEGMENT
| PPC_EXTERN
;
5416 pcc
->msr_mask
= (1ull << MSR_POW
) |
5432 pcc
->mmu_model
= POWERPC_MMU_32B
;
5433 #if defined(CONFIG_SOFTMMU)
5434 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5436 pcc
->excp_model
= POWERPC_EXCP_604
;
5437 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5438 pcc
->bfd_mach
= bfd_mach_ppc_604
;
5439 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
5440 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
5443 static void init_proc_604E (CPUPPCState
*env
)
5445 gen_spr_ne_601(env
);
5447 /* XXX : not implemented */
5448 spr_register(env
, SPR_7XX_MMCR1
, "MMCR1",
5449 SPR_NOACCESS
, SPR_NOACCESS
,
5450 &spr_read_generic
, &spr_write_generic
,
5452 /* XXX : not implemented */
5453 spr_register(env
, SPR_7XX_PMC3
, "PMC3",
5454 SPR_NOACCESS
, SPR_NOACCESS
,
5455 &spr_read_generic
, &spr_write_generic
,
5457 /* XXX : not implemented */
5458 spr_register(env
, SPR_7XX_PMC4
, "PMC4",
5459 SPR_NOACCESS
, SPR_NOACCESS
,
5460 &spr_read_generic
, &spr_write_generic
,
5464 /* Hardware implementation registers */
5465 /* XXX : not implemented */
5466 spr_register(env
, SPR_HID0
, "HID0",
5467 SPR_NOACCESS
, SPR_NOACCESS
,
5468 &spr_read_generic
, &spr_write_generic
,
5470 /* XXX : not implemented */
5471 spr_register(env
, SPR_HID1
, "HID1",
5472 SPR_NOACCESS
, SPR_NOACCESS
,
5473 &spr_read_generic
, &spr_write_generic
,
5475 /* Memory management */
5478 env
->dcache_line_size
= 32;
5479 env
->icache_line_size
= 32;
5480 /* Allocate hardware IRQ controller */
5481 ppc6xx_irq_init(env
);
5484 POWERPC_FAMILY(604E
)(ObjectClass
*oc
, void *data
)
5486 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5487 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5489 dc
->desc
= "PowerPC 604E";
5490 pcc
->init_proc
= init_proc_604E
;
5491 pcc
->check_pow
= check_pow_nocheck
;
5492 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5493 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5494 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5495 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5496 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5497 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5498 PPC_SEGMENT
| PPC_EXTERN
;
5499 pcc
->msr_mask
= (1ull << MSR_POW
) |
5515 pcc
->mmu_model
= POWERPC_MMU_32B
;
5516 #if defined(CONFIG_SOFTMMU)
5517 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5519 pcc
->excp_model
= POWERPC_EXCP_604
;
5520 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5521 pcc
->bfd_mach
= bfd_mach_ppc_604
;
5522 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
5523 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
5526 static void init_proc_740 (CPUPPCState
*env
)
5528 gen_spr_ne_601(env
);
5532 /* Thermal management */
5534 /* Hardware implementation registers */
5535 /* XXX : not implemented */
5536 spr_register(env
, SPR_HID0
, "HID0",
5537 SPR_NOACCESS
, SPR_NOACCESS
,
5538 &spr_read_generic
, &spr_write_generic
,
5540 /* XXX : not implemented */
5541 spr_register(env
, SPR_HID1
, "HID1",
5542 SPR_NOACCESS
, SPR_NOACCESS
,
5543 &spr_read_generic
, &spr_write_generic
,
5545 /* Memory management */
5548 env
->dcache_line_size
= 32;
5549 env
->icache_line_size
= 32;
5550 /* Allocate hardware IRQ controller */
5551 ppc6xx_irq_init(env
);
5554 POWERPC_FAMILY(740)(ObjectClass
*oc
, void *data
)
5556 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5557 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5559 dc
->desc
= "PowerPC 740";
5560 pcc
->init_proc
= init_proc_740
;
5561 pcc
->check_pow
= check_pow_hid0
;
5562 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5563 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5564 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5565 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5566 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5567 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5568 PPC_SEGMENT
| PPC_EXTERN
;
5569 pcc
->msr_mask
= (1ull << MSR_POW
) |
5585 pcc
->mmu_model
= POWERPC_MMU_32B
;
5586 #if defined(CONFIG_SOFTMMU)
5587 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5589 pcc
->excp_model
= POWERPC_EXCP_7x0
;
5590 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5591 pcc
->bfd_mach
= bfd_mach_ppc_750
;
5592 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
5593 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
5596 static void init_proc_750 (CPUPPCState
*env
)
5598 gen_spr_ne_601(env
);
5600 /* XXX : not implemented */
5601 spr_register(env
, SPR_L2CR
, "L2CR",
5602 SPR_NOACCESS
, SPR_NOACCESS
,
5603 &spr_read_generic
, spr_access_nop
,
5607 /* Thermal management */
5609 /* Hardware implementation registers */
5610 /* XXX : not implemented */
5611 spr_register(env
, SPR_HID0
, "HID0",
5612 SPR_NOACCESS
, SPR_NOACCESS
,
5613 &spr_read_generic
, &spr_write_generic
,
5615 /* XXX : not implemented */
5616 spr_register(env
, SPR_HID1
, "HID1",
5617 SPR_NOACCESS
, SPR_NOACCESS
,
5618 &spr_read_generic
, &spr_write_generic
,
5620 /* Memory management */
5622 /* XXX: high BATs are also present but are known to be bugged on
5626 env
->dcache_line_size
= 32;
5627 env
->icache_line_size
= 32;
5628 /* Allocate hardware IRQ controller */
5629 ppc6xx_irq_init(env
);
5632 POWERPC_FAMILY(750)(ObjectClass
*oc
, void *data
)
5634 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5635 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5637 dc
->desc
= "PowerPC 750";
5638 pcc
->init_proc
= init_proc_750
;
5639 pcc
->check_pow
= check_pow_hid0
;
5640 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5641 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5642 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5643 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5644 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5645 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5646 PPC_SEGMENT
| PPC_EXTERN
;
5647 pcc
->msr_mask
= (1ull << MSR_POW
) |
5663 pcc
->mmu_model
= POWERPC_MMU_32B
;
5664 #if defined(CONFIG_SOFTMMU)
5665 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5667 pcc
->excp_model
= POWERPC_EXCP_7x0
;
5668 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5669 pcc
->bfd_mach
= bfd_mach_ppc_750
;
5670 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
5671 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
5674 static void init_proc_750cl (CPUPPCState
*env
)
5676 gen_spr_ne_601(env
);
5678 /* XXX : not implemented */
5679 spr_register(env
, SPR_L2CR
, "L2CR",
5680 SPR_NOACCESS
, SPR_NOACCESS
,
5681 &spr_read_generic
, spr_access_nop
,
5685 /* Thermal management */
5686 /* Those registers are fake on 750CL */
5687 spr_register(env
, SPR_THRM1
, "THRM1",
5688 SPR_NOACCESS
, SPR_NOACCESS
,
5689 &spr_read_generic
, &spr_write_generic
,
5691 spr_register(env
, SPR_THRM2
, "THRM2",
5692 SPR_NOACCESS
, SPR_NOACCESS
,
5693 &spr_read_generic
, &spr_write_generic
,
5695 spr_register(env
, SPR_THRM3
, "THRM3",
5696 SPR_NOACCESS
, SPR_NOACCESS
,
5697 &spr_read_generic
, &spr_write_generic
,
5699 /* XXX: not implemented */
5700 spr_register(env
, SPR_750_TDCL
, "TDCL",
5701 SPR_NOACCESS
, SPR_NOACCESS
,
5702 &spr_read_generic
, &spr_write_generic
,
5704 spr_register(env
, SPR_750_TDCH
, "TDCH",
5705 SPR_NOACCESS
, SPR_NOACCESS
,
5706 &spr_read_generic
, &spr_write_generic
,
5709 /* XXX : not implemented */
5710 spr_register(env
, SPR_750_WPAR
, "WPAR",
5711 SPR_NOACCESS
, SPR_NOACCESS
,
5712 &spr_read_generic
, &spr_write_generic
,
5714 spr_register(env
, SPR_750_DMAL
, "DMAL",
5715 SPR_NOACCESS
, SPR_NOACCESS
,
5716 &spr_read_generic
, &spr_write_generic
,
5718 spr_register(env
, SPR_750_DMAU
, "DMAU",
5719 SPR_NOACCESS
, SPR_NOACCESS
,
5720 &spr_read_generic
, &spr_write_generic
,
5722 /* Hardware implementation registers */
5723 /* XXX : not implemented */
5724 spr_register(env
, SPR_HID0
, "HID0",
5725 SPR_NOACCESS
, SPR_NOACCESS
,
5726 &spr_read_generic
, &spr_write_generic
,
5728 /* XXX : not implemented */
5729 spr_register(env
, SPR_HID1
, "HID1",
5730 SPR_NOACCESS
, SPR_NOACCESS
,
5731 &spr_read_generic
, &spr_write_generic
,
5733 /* XXX : not implemented */
5734 spr_register(env
, SPR_750CL_HID2
, "HID2",
5735 SPR_NOACCESS
, SPR_NOACCESS
,
5736 &spr_read_generic
, &spr_write_generic
,
5738 /* XXX : not implemented */
5739 spr_register(env
, SPR_750CL_HID4
, "HID4",
5740 SPR_NOACCESS
, SPR_NOACCESS
,
5741 &spr_read_generic
, &spr_write_generic
,
5743 /* Quantization registers */
5744 /* XXX : not implemented */
5745 spr_register(env
, SPR_750_GQR0
, "GQR0",
5746 SPR_NOACCESS
, SPR_NOACCESS
,
5747 &spr_read_generic
, &spr_write_generic
,
5749 /* XXX : not implemented */
5750 spr_register(env
, SPR_750_GQR1
, "GQR1",
5751 SPR_NOACCESS
, SPR_NOACCESS
,
5752 &spr_read_generic
, &spr_write_generic
,
5754 /* XXX : not implemented */
5755 spr_register(env
, SPR_750_GQR2
, "GQR2",
5756 SPR_NOACCESS
, SPR_NOACCESS
,
5757 &spr_read_generic
, &spr_write_generic
,
5759 /* XXX : not implemented */
5760 spr_register(env
, SPR_750_GQR3
, "GQR3",
5761 SPR_NOACCESS
, SPR_NOACCESS
,
5762 &spr_read_generic
, &spr_write_generic
,
5764 /* XXX : not implemented */
5765 spr_register(env
, SPR_750_GQR4
, "GQR4",
5766 SPR_NOACCESS
, SPR_NOACCESS
,
5767 &spr_read_generic
, &spr_write_generic
,
5769 /* XXX : not implemented */
5770 spr_register(env
, SPR_750_GQR5
, "GQR5",
5771 SPR_NOACCESS
, SPR_NOACCESS
,
5772 &spr_read_generic
, &spr_write_generic
,
5774 /* XXX : not implemented */
5775 spr_register(env
, SPR_750_GQR6
, "GQR6",
5776 SPR_NOACCESS
, SPR_NOACCESS
,
5777 &spr_read_generic
, &spr_write_generic
,
5779 /* XXX : not implemented */
5780 spr_register(env
, SPR_750_GQR7
, "GQR7",
5781 SPR_NOACCESS
, SPR_NOACCESS
,
5782 &spr_read_generic
, &spr_write_generic
,
5784 /* Memory management */
5786 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5788 init_excp_750cl(env
);
5789 env
->dcache_line_size
= 32;
5790 env
->icache_line_size
= 32;
5791 /* Allocate hardware IRQ controller */
5792 ppc6xx_irq_init(env
);
5795 POWERPC_FAMILY(750cl
)(ObjectClass
*oc
, void *data
)
5797 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5798 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5800 dc
->desc
= "PowerPC 750 CL";
5801 pcc
->init_proc
= init_proc_750cl
;
5802 pcc
->check_pow
= check_pow_hid0
;
5803 /* XXX: not implemented:
5804 * cache lock instructions:
5806 * floating point paired instructions
5841 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5842 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5843 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5844 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5845 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5846 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5847 PPC_SEGMENT
| PPC_EXTERN
;
5848 pcc
->msr_mask
= (1ull << MSR_POW
) |
5864 pcc
->mmu_model
= POWERPC_MMU_32B
;
5865 #if defined(CONFIG_SOFTMMU)
5866 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5868 pcc
->excp_model
= POWERPC_EXCP_7x0
;
5869 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5870 pcc
->bfd_mach
= bfd_mach_ppc_750
;
5871 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
5872 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
5875 static void init_proc_750cx (CPUPPCState
*env
)
5877 gen_spr_ne_601(env
);
5879 /* XXX : not implemented */
5880 spr_register(env
, SPR_L2CR
, "L2CR",
5881 SPR_NOACCESS
, SPR_NOACCESS
,
5882 &spr_read_generic
, spr_access_nop
,
5886 /* Thermal management */
5888 /* This register is not implemented but is present for compatibility */
5889 spr_register(env
, SPR_SDA
, "SDA",
5890 SPR_NOACCESS
, SPR_NOACCESS
,
5891 &spr_read_generic
, &spr_write_generic
,
5893 /* Hardware implementation registers */
5894 /* XXX : not implemented */
5895 spr_register(env
, SPR_HID0
, "HID0",
5896 SPR_NOACCESS
, SPR_NOACCESS
,
5897 &spr_read_generic
, &spr_write_generic
,
5899 /* XXX : not implemented */
5900 spr_register(env
, SPR_HID1
, "HID1",
5901 SPR_NOACCESS
, SPR_NOACCESS
,
5902 &spr_read_generic
, &spr_write_generic
,
5904 /* Memory management */
5906 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5908 init_excp_750cx(env
);
5909 env
->dcache_line_size
= 32;
5910 env
->icache_line_size
= 32;
5911 /* Allocate hardware IRQ controller */
5912 ppc6xx_irq_init(env
);
5915 POWERPC_FAMILY(750cx
)(ObjectClass
*oc
, void *data
)
5917 DeviceClass
*dc
= DEVICE_CLASS(oc
);
5918 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
5920 dc
->desc
= "PowerPC 750CX";
5921 pcc
->init_proc
= init_proc_750cx
;
5922 pcc
->check_pow
= check_pow_hid0
;
5923 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
5924 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
5925 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
5926 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
5927 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
5928 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
5929 PPC_SEGMENT
| PPC_EXTERN
;
5930 pcc
->msr_mask
= (1ull << MSR_POW
) |
5946 pcc
->mmu_model
= POWERPC_MMU_32B
;
5947 #if defined(CONFIG_SOFTMMU)
5948 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
5950 pcc
->excp_model
= POWERPC_EXCP_7x0
;
5951 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
5952 pcc
->bfd_mach
= bfd_mach_ppc_750
;
5953 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
5954 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
5957 static void init_proc_750fx (CPUPPCState
*env
)
5959 gen_spr_ne_601(env
);
5961 /* XXX : not implemented */
5962 spr_register(env
, SPR_L2CR
, "L2CR",
5963 SPR_NOACCESS
, SPR_NOACCESS
,
5964 &spr_read_generic
, spr_access_nop
,
5968 /* Thermal management */
5970 /* XXX : not implemented */
5971 spr_register(env
, SPR_750_THRM4
, "THRM4",
5972 SPR_NOACCESS
, SPR_NOACCESS
,
5973 &spr_read_generic
, &spr_write_generic
,
5975 /* Hardware implementation registers */
5976 /* XXX : not implemented */
5977 spr_register(env
, SPR_HID0
, "HID0",
5978 SPR_NOACCESS
, SPR_NOACCESS
,
5979 &spr_read_generic
, &spr_write_generic
,
5981 /* XXX : not implemented */
5982 spr_register(env
, SPR_HID1
, "HID1",
5983 SPR_NOACCESS
, SPR_NOACCESS
,
5984 &spr_read_generic
, &spr_write_generic
,
5986 /* XXX : not implemented */
5987 spr_register(env
, SPR_750FX_HID2
, "HID2",
5988 SPR_NOACCESS
, SPR_NOACCESS
,
5989 &spr_read_generic
, &spr_write_generic
,
5991 /* Memory management */
5993 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5996 env
->dcache_line_size
= 32;
5997 env
->icache_line_size
= 32;
5998 /* Allocate hardware IRQ controller */
5999 ppc6xx_irq_init(env
);
6002 POWERPC_FAMILY(750fx
)(ObjectClass
*oc
, void *data
)
6004 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6005 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6007 dc
->desc
= "PowerPC 750FX";
6008 pcc
->init_proc
= init_proc_750fx
;
6009 pcc
->check_pow
= check_pow_hid0
;
6010 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6011 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6012 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
6013 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6014 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6015 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6016 PPC_SEGMENT
| PPC_EXTERN
;
6017 pcc
->msr_mask
= (1ull << MSR_POW
) |
6033 pcc
->mmu_model
= POWERPC_MMU_32B
;
6034 #if defined(CONFIG_SOFTMMU)
6035 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
6037 pcc
->excp_model
= POWERPC_EXCP_7x0
;
6038 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6039 pcc
->bfd_mach
= bfd_mach_ppc_750
;
6040 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
6041 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
6044 static void init_proc_750gx (CPUPPCState
*env
)
6046 gen_spr_ne_601(env
);
6048 /* XXX : not implemented (XXX: different from 750fx) */
6049 spr_register(env
, SPR_L2CR
, "L2CR",
6050 SPR_NOACCESS
, SPR_NOACCESS
,
6051 &spr_read_generic
, spr_access_nop
,
6055 /* Thermal management */
6057 /* XXX : not implemented */
6058 spr_register(env
, SPR_750_THRM4
, "THRM4",
6059 SPR_NOACCESS
, SPR_NOACCESS
,
6060 &spr_read_generic
, &spr_write_generic
,
6062 /* Hardware implementation registers */
6063 /* XXX : not implemented (XXX: different from 750fx) */
6064 spr_register(env
, SPR_HID0
, "HID0",
6065 SPR_NOACCESS
, SPR_NOACCESS
,
6066 &spr_read_generic
, &spr_write_generic
,
6068 /* XXX : not implemented */
6069 spr_register(env
, SPR_HID1
, "HID1",
6070 SPR_NOACCESS
, SPR_NOACCESS
,
6071 &spr_read_generic
, &spr_write_generic
,
6073 /* XXX : not implemented (XXX: different from 750fx) */
6074 spr_register(env
, SPR_750FX_HID2
, "HID2",
6075 SPR_NOACCESS
, SPR_NOACCESS
,
6076 &spr_read_generic
, &spr_write_generic
,
6078 /* Memory management */
6080 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6083 env
->dcache_line_size
= 32;
6084 env
->icache_line_size
= 32;
6085 /* Allocate hardware IRQ controller */
6086 ppc6xx_irq_init(env
);
6089 POWERPC_FAMILY(750gx
)(ObjectClass
*oc
, void *data
)
6091 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6092 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6094 dc
->desc
= "PowerPC 750GX";
6095 pcc
->init_proc
= init_proc_750gx
;
6096 pcc
->check_pow
= check_pow_hid0
;
6097 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6098 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6099 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
6100 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6101 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6102 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6103 PPC_SEGMENT
| PPC_EXTERN
;
6104 pcc
->msr_mask
= (1ull << MSR_POW
) |
6120 pcc
->mmu_model
= POWERPC_MMU_32B
;
6121 #if defined(CONFIG_SOFTMMU)
6122 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
6124 pcc
->excp_model
= POWERPC_EXCP_7x0
;
6125 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6126 pcc
->bfd_mach
= bfd_mach_ppc_750
;
6127 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
6128 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
6131 static void init_proc_745 (CPUPPCState
*env
)
6133 gen_spr_ne_601(env
);
6135 gen_spr_G2_755(env
);
6138 /* Thermal management */
6140 /* Hardware implementation registers */
6141 /* XXX : not implemented */
6142 spr_register(env
, SPR_HID0
, "HID0",
6143 SPR_NOACCESS
, SPR_NOACCESS
,
6144 &spr_read_generic
, &spr_write_generic
,
6146 /* XXX : not implemented */
6147 spr_register(env
, SPR_HID1
, "HID1",
6148 SPR_NOACCESS
, SPR_NOACCESS
,
6149 &spr_read_generic
, &spr_write_generic
,
6151 /* XXX : not implemented */
6152 spr_register(env
, SPR_HID2
, "HID2",
6153 SPR_NOACCESS
, SPR_NOACCESS
,
6154 &spr_read_generic
, &spr_write_generic
,
6156 /* Memory management */
6159 gen_6xx_7xx_soft_tlb(env
, 64, 2);
6161 env
->dcache_line_size
= 32;
6162 env
->icache_line_size
= 32;
6163 /* Allocate hardware IRQ controller */
6164 ppc6xx_irq_init(env
);
6167 POWERPC_FAMILY(745)(ObjectClass
*oc
, void *data
)
6169 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6170 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6172 dc
->desc
= "PowerPC 745";
6173 pcc
->init_proc
= init_proc_745
;
6174 pcc
->check_pow
= check_pow_hid0
;
6175 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6176 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6177 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
6178 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6179 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6180 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
6181 PPC_SEGMENT
| PPC_EXTERN
;
6182 pcc
->msr_mask
= (1ull << MSR_POW
) |
6198 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
6199 pcc
->excp_model
= POWERPC_EXCP_7x5
;
6200 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6201 pcc
->bfd_mach
= bfd_mach_ppc_750
;
6202 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
6203 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
6206 static void init_proc_755 (CPUPPCState
*env
)
6208 gen_spr_ne_601(env
);
6210 gen_spr_G2_755(env
);
6213 /* L2 cache control */
6214 /* XXX : not implemented */
6215 spr_register(env
, SPR_L2CR
, "L2CR",
6216 SPR_NOACCESS
, SPR_NOACCESS
,
6217 &spr_read_generic
, spr_access_nop
,
6219 /* XXX : not implemented */
6220 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
6221 SPR_NOACCESS
, SPR_NOACCESS
,
6222 &spr_read_generic
, &spr_write_generic
,
6224 /* Thermal management */
6226 /* Hardware implementation registers */
6227 /* XXX : not implemented */
6228 spr_register(env
, SPR_HID0
, "HID0",
6229 SPR_NOACCESS
, SPR_NOACCESS
,
6230 &spr_read_generic
, &spr_write_generic
,
6232 /* XXX : not implemented */
6233 spr_register(env
, SPR_HID1
, "HID1",
6234 SPR_NOACCESS
, SPR_NOACCESS
,
6235 &spr_read_generic
, &spr_write_generic
,
6237 /* XXX : not implemented */
6238 spr_register(env
, SPR_HID2
, "HID2",
6239 SPR_NOACCESS
, SPR_NOACCESS
,
6240 &spr_read_generic
, &spr_write_generic
,
6242 /* Memory management */
6245 gen_6xx_7xx_soft_tlb(env
, 64, 2);
6247 env
->dcache_line_size
= 32;
6248 env
->icache_line_size
= 32;
6249 /* Allocate hardware IRQ controller */
6250 ppc6xx_irq_init(env
);
6253 POWERPC_FAMILY(755)(ObjectClass
*oc
, void *data
)
6255 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6256 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6258 dc
->desc
= "PowerPC 755";
6259 pcc
->init_proc
= init_proc_755
;
6260 pcc
->check_pow
= check_pow_hid0
;
6261 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6262 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6263 PPC_FLOAT_FRSQRTE
| PPC_FLOAT_STFIWX
|
6264 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
6265 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6266 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
| PPC_6xx_TLB
|
6267 PPC_SEGMENT
| PPC_EXTERN
;
6268 pcc
->msr_mask
= (1ull << MSR_POW
) |
6284 pcc
->mmu_model
= POWERPC_MMU_SOFT_6xx
;
6285 pcc
->excp_model
= POWERPC_EXCP_7x5
;
6286 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6287 pcc
->bfd_mach
= bfd_mach_ppc_750
;
6288 pcc
->flags
= POWERPC_FLAG_SE
| POWERPC_FLAG_BE
|
6289 POWERPC_FLAG_PMM
| POWERPC_FLAG_BUS_CLK
;
6292 static void init_proc_7400 (CPUPPCState
*env
)
6294 gen_spr_ne_601(env
);
6298 /* 74xx specific SPR */
6300 /* XXX : not implemented */
6301 spr_register(env
, SPR_UBAMR
, "UBAMR",
6302 &spr_read_ureg
, SPR_NOACCESS
,
6303 &spr_read_ureg
, SPR_NOACCESS
,
6305 /* XXX: this seems not implemented on all revisions. */
6306 /* XXX : not implemented */
6307 spr_register(env
, SPR_MSSCR1
, "MSSCR1",
6308 SPR_NOACCESS
, SPR_NOACCESS
,
6309 &spr_read_generic
, &spr_write_generic
,
6311 /* Thermal management */
6313 /* Memory management */
6315 init_excp_7400(env
);
6316 env
->dcache_line_size
= 32;
6317 env
->icache_line_size
= 32;
6318 /* Allocate hardware IRQ controller */
6319 ppc6xx_irq_init(env
);
6322 POWERPC_FAMILY(7400)(ObjectClass
*oc
, void *data
)
6324 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6325 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6327 dc
->desc
= "PowerPC 7400 (aka G4)";
6328 pcc
->init_proc
= init_proc_7400
;
6329 pcc
->check_pow
= check_pow_hid0
;
6330 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6331 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6332 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6334 PPC_CACHE
| PPC_CACHE_ICBI
|
6335 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
6336 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6337 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6339 PPC_SEGMENT
| PPC_EXTERN
|
6341 pcc
->msr_mask
= (1ull << MSR_VR
) |
6358 pcc
->mmu_model
= POWERPC_MMU_32B
;
6359 #if defined(CONFIG_SOFTMMU)
6360 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
6362 pcc
->excp_model
= POWERPC_EXCP_74xx
;
6363 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6364 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
6365 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6366 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6367 POWERPC_FLAG_BUS_CLK
;
6370 static void init_proc_7410 (CPUPPCState
*env
)
6372 gen_spr_ne_601(env
);
6376 /* 74xx specific SPR */
6378 /* XXX : not implemented */
6379 spr_register(env
, SPR_UBAMR
, "UBAMR",
6380 &spr_read_ureg
, SPR_NOACCESS
,
6381 &spr_read_ureg
, SPR_NOACCESS
,
6383 /* Thermal management */
6386 /* XXX : not implemented */
6387 spr_register(env
, SPR_L2PMCR
, "L2PMCR",
6388 SPR_NOACCESS
, SPR_NOACCESS
,
6389 &spr_read_generic
, &spr_write_generic
,
6392 /* XXX : not implemented */
6393 spr_register(env
, SPR_LDSTDB
, "LDSTDB",
6394 SPR_NOACCESS
, SPR_NOACCESS
,
6395 &spr_read_generic
, &spr_write_generic
,
6397 /* Memory management */
6399 init_excp_7400(env
);
6400 env
->dcache_line_size
= 32;
6401 env
->icache_line_size
= 32;
6402 /* Allocate hardware IRQ controller */
6403 ppc6xx_irq_init(env
);
6406 POWERPC_FAMILY(7410)(ObjectClass
*oc
, void *data
)
6408 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6409 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6411 dc
->desc
= "PowerPC 7410 (aka G4)";
6412 pcc
->init_proc
= init_proc_7410
;
6413 pcc
->check_pow
= check_pow_hid0
;
6414 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6415 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6416 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6418 PPC_CACHE
| PPC_CACHE_ICBI
|
6419 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
6420 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6421 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6423 PPC_SEGMENT
| PPC_EXTERN
|
6425 pcc
->msr_mask
= (1ull << MSR_VR
) |
6442 pcc
->mmu_model
= POWERPC_MMU_32B
;
6443 #if defined(CONFIG_SOFTMMU)
6444 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
6446 pcc
->excp_model
= POWERPC_EXCP_74xx
;
6447 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6448 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
6449 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6450 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6451 POWERPC_FLAG_BUS_CLK
;
6454 static void init_proc_7440 (CPUPPCState
*env
)
6456 gen_spr_ne_601(env
);
6460 /* 74xx specific SPR */
6462 /* XXX : not implemented */
6463 spr_register(env
, SPR_UBAMR
, "UBAMR",
6464 &spr_read_ureg
, SPR_NOACCESS
,
6465 &spr_read_ureg
, SPR_NOACCESS
,
6468 /* XXX : not implemented */
6469 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
6470 SPR_NOACCESS
, SPR_NOACCESS
,
6471 &spr_read_generic
, &spr_write_generic
,
6474 /* XXX : not implemented */
6475 spr_register(env
, SPR_ICTRL
, "ICTRL",
6476 SPR_NOACCESS
, SPR_NOACCESS
,
6477 &spr_read_generic
, &spr_write_generic
,
6480 /* XXX : not implemented */
6481 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
6482 SPR_NOACCESS
, SPR_NOACCESS
,
6483 &spr_read_generic
, &spr_write_generic
,
6486 /* XXX : not implemented */
6487 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
6488 SPR_NOACCESS
, SPR_NOACCESS
,
6489 &spr_read_generic
, &spr_write_generic
,
6491 /* XXX : not implemented */
6492 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
6493 &spr_read_ureg
, SPR_NOACCESS
,
6494 &spr_read_ureg
, SPR_NOACCESS
,
6496 /* XXX : not implemented */
6497 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
6498 SPR_NOACCESS
, SPR_NOACCESS
,
6499 &spr_read_generic
, &spr_write_generic
,
6501 /* XXX : not implemented */
6502 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
6503 &spr_read_ureg
, SPR_NOACCESS
,
6504 &spr_read_ureg
, SPR_NOACCESS
,
6506 /* Memory management */
6508 gen_74xx_soft_tlb(env
, 128, 2);
6509 init_excp_7450(env
);
6510 env
->dcache_line_size
= 32;
6511 env
->icache_line_size
= 32;
6512 /* Allocate hardware IRQ controller */
6513 ppc6xx_irq_init(env
);
6516 POWERPC_FAMILY(7440)(ObjectClass
*oc
, void *data
)
6518 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6519 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6521 dc
->desc
= "PowerPC 7440 (aka G4)";
6522 pcc
->init_proc
= init_proc_7440
;
6523 pcc
->check_pow
= check_pow_hid0_74xx
;
6524 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6525 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6526 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6528 PPC_CACHE
| PPC_CACHE_ICBI
|
6529 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
6530 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6531 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6532 PPC_MEM_TLBIA
| PPC_74xx_TLB
|
6533 PPC_SEGMENT
| PPC_EXTERN
|
6535 pcc
->msr_mask
= (1ull << MSR_VR
) |
6552 pcc
->mmu_model
= POWERPC_MMU_SOFT_74xx
;
6553 pcc
->excp_model
= POWERPC_EXCP_74xx
;
6554 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6555 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
6556 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6557 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6558 POWERPC_FLAG_BUS_CLK
;
6561 static void init_proc_7450 (CPUPPCState
*env
)
6563 gen_spr_ne_601(env
);
6567 /* 74xx specific SPR */
6569 /* Level 3 cache control */
6572 /* XXX : not implemented */
6573 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
6574 SPR_NOACCESS
, SPR_NOACCESS
,
6575 &spr_read_generic
, &spr_write_generic
,
6578 /* XXX : not implemented */
6579 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
6580 SPR_NOACCESS
, SPR_NOACCESS
,
6581 &spr_read_generic
, &spr_write_generic
,
6584 /* XXX : not implemented */
6585 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
6586 SPR_NOACCESS
, SPR_NOACCESS
,
6587 &spr_read_generic
, &spr_write_generic
,
6590 /* XXX : not implemented */
6591 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
6592 SPR_NOACCESS
, SPR_NOACCESS
,
6593 &spr_read_generic
, &spr_write_generic
,
6595 /* XXX : not implemented */
6596 spr_register(env
, SPR_UBAMR
, "UBAMR",
6597 &spr_read_ureg
, SPR_NOACCESS
,
6598 &spr_read_ureg
, SPR_NOACCESS
,
6601 /* XXX : not implemented */
6602 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
6603 SPR_NOACCESS
, SPR_NOACCESS
,
6604 &spr_read_generic
, &spr_write_generic
,
6607 /* XXX : not implemented */
6608 spr_register(env
, SPR_ICTRL
, "ICTRL",
6609 SPR_NOACCESS
, SPR_NOACCESS
,
6610 &spr_read_generic
, &spr_write_generic
,
6613 /* XXX : not implemented */
6614 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
6615 SPR_NOACCESS
, SPR_NOACCESS
,
6616 &spr_read_generic
, &spr_write_generic
,
6619 /* XXX : not implemented */
6620 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
6621 SPR_NOACCESS
, SPR_NOACCESS
,
6622 &spr_read_generic
, &spr_write_generic
,
6624 /* XXX : not implemented */
6625 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
6626 &spr_read_ureg
, SPR_NOACCESS
,
6627 &spr_read_ureg
, SPR_NOACCESS
,
6629 /* XXX : not implemented */
6630 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
6631 SPR_NOACCESS
, SPR_NOACCESS
,
6632 &spr_read_generic
, &spr_write_generic
,
6634 /* XXX : not implemented */
6635 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
6636 &spr_read_ureg
, SPR_NOACCESS
,
6637 &spr_read_ureg
, SPR_NOACCESS
,
6639 /* Memory management */
6641 gen_74xx_soft_tlb(env
, 128, 2);
6642 init_excp_7450(env
);
6643 env
->dcache_line_size
= 32;
6644 env
->icache_line_size
= 32;
6645 /* Allocate hardware IRQ controller */
6646 ppc6xx_irq_init(env
);
6649 POWERPC_FAMILY(7450)(ObjectClass
*oc
, void *data
)
6651 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6652 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6654 dc
->desc
= "PowerPC 7450 (aka G4)";
6655 pcc
->init_proc
= init_proc_7450
;
6656 pcc
->check_pow
= check_pow_hid0_74xx
;
6657 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6658 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6659 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6661 PPC_CACHE
| PPC_CACHE_ICBI
|
6662 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
6663 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6664 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6665 PPC_MEM_TLBIA
| PPC_74xx_TLB
|
6666 PPC_SEGMENT
| PPC_EXTERN
|
6668 pcc
->msr_mask
= (1ull << MSR_VR
) |
6685 pcc
->mmu_model
= POWERPC_MMU_SOFT_74xx
;
6686 pcc
->excp_model
= POWERPC_EXCP_74xx
;
6687 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6688 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
6689 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6690 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6691 POWERPC_FLAG_BUS_CLK
;
6694 static void init_proc_7445 (CPUPPCState
*env
)
6696 gen_spr_ne_601(env
);
6700 /* 74xx specific SPR */
6703 /* XXX : not implemented */
6704 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
6705 SPR_NOACCESS
, SPR_NOACCESS
,
6706 &spr_read_generic
, &spr_write_generic
,
6709 /* XXX : not implemented */
6710 spr_register(env
, SPR_ICTRL
, "ICTRL",
6711 SPR_NOACCESS
, SPR_NOACCESS
,
6712 &spr_read_generic
, &spr_write_generic
,
6715 /* XXX : not implemented */
6716 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
6717 SPR_NOACCESS
, SPR_NOACCESS
,
6718 &spr_read_generic
, &spr_write_generic
,
6721 /* XXX : not implemented */
6722 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
6723 SPR_NOACCESS
, SPR_NOACCESS
,
6724 &spr_read_generic
, &spr_write_generic
,
6726 /* XXX : not implemented */
6727 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
6728 &spr_read_ureg
, SPR_NOACCESS
,
6729 &spr_read_ureg
, SPR_NOACCESS
,
6731 /* XXX : not implemented */
6732 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
6733 SPR_NOACCESS
, SPR_NOACCESS
,
6734 &spr_read_generic
, &spr_write_generic
,
6736 /* XXX : not implemented */
6737 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
6738 &spr_read_ureg
, SPR_NOACCESS
,
6739 &spr_read_ureg
, SPR_NOACCESS
,
6742 spr_register(env
, SPR_SPRG4
, "SPRG4",
6743 SPR_NOACCESS
, SPR_NOACCESS
,
6744 &spr_read_generic
, &spr_write_generic
,
6746 spr_register(env
, SPR_USPRG4
, "USPRG4",
6747 &spr_read_ureg
, SPR_NOACCESS
,
6748 &spr_read_ureg
, SPR_NOACCESS
,
6750 spr_register(env
, SPR_SPRG5
, "SPRG5",
6751 SPR_NOACCESS
, SPR_NOACCESS
,
6752 &spr_read_generic
, &spr_write_generic
,
6754 spr_register(env
, SPR_USPRG5
, "USPRG5",
6755 &spr_read_ureg
, SPR_NOACCESS
,
6756 &spr_read_ureg
, SPR_NOACCESS
,
6758 spr_register(env
, SPR_SPRG6
, "SPRG6",
6759 SPR_NOACCESS
, SPR_NOACCESS
,
6760 &spr_read_generic
, &spr_write_generic
,
6762 spr_register(env
, SPR_USPRG6
, "USPRG6",
6763 &spr_read_ureg
, SPR_NOACCESS
,
6764 &spr_read_ureg
, SPR_NOACCESS
,
6766 spr_register(env
, SPR_SPRG7
, "SPRG7",
6767 SPR_NOACCESS
, SPR_NOACCESS
,
6768 &spr_read_generic
, &spr_write_generic
,
6770 spr_register(env
, SPR_USPRG7
, "USPRG7",
6771 &spr_read_ureg
, SPR_NOACCESS
,
6772 &spr_read_ureg
, SPR_NOACCESS
,
6774 /* Memory management */
6777 gen_74xx_soft_tlb(env
, 128, 2);
6778 init_excp_7450(env
);
6779 env
->dcache_line_size
= 32;
6780 env
->icache_line_size
= 32;
6781 /* Allocate hardware IRQ controller */
6782 ppc6xx_irq_init(env
);
6785 POWERPC_FAMILY(7445)(ObjectClass
*oc
, void *data
)
6787 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6788 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6790 dc
->desc
= "PowerPC 7445 (aka G4)";
6791 pcc
->init_proc
= init_proc_7445
;
6792 pcc
->check_pow
= check_pow_hid0_74xx
;
6793 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6794 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6795 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6797 PPC_CACHE
| PPC_CACHE_ICBI
|
6798 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
6799 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6800 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6801 PPC_MEM_TLBIA
| PPC_74xx_TLB
|
6802 PPC_SEGMENT
| PPC_EXTERN
|
6804 pcc
->msr_mask
= (1ull << MSR_VR
) |
6821 pcc
->mmu_model
= POWERPC_MMU_SOFT_74xx
;
6822 pcc
->excp_model
= POWERPC_EXCP_74xx
;
6823 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6824 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
6825 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6826 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6827 POWERPC_FLAG_BUS_CLK
;
6830 static void init_proc_7455 (CPUPPCState
*env
)
6832 gen_spr_ne_601(env
);
6836 /* 74xx specific SPR */
6838 /* Level 3 cache control */
6841 /* XXX : not implemented */
6842 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
6843 SPR_NOACCESS
, SPR_NOACCESS
,
6844 &spr_read_generic
, &spr_write_generic
,
6847 /* XXX : not implemented */
6848 spr_register(env
, SPR_ICTRL
, "ICTRL",
6849 SPR_NOACCESS
, SPR_NOACCESS
,
6850 &spr_read_generic
, &spr_write_generic
,
6853 /* XXX : not implemented */
6854 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
6855 SPR_NOACCESS
, SPR_NOACCESS
,
6856 &spr_read_generic
, &spr_write_generic
,
6859 /* XXX : not implemented */
6860 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
6861 SPR_NOACCESS
, SPR_NOACCESS
,
6862 &spr_read_generic
, &spr_write_generic
,
6864 /* XXX : not implemented */
6865 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
6866 &spr_read_ureg
, SPR_NOACCESS
,
6867 &spr_read_ureg
, SPR_NOACCESS
,
6869 /* XXX : not implemented */
6870 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
6871 SPR_NOACCESS
, SPR_NOACCESS
,
6872 &spr_read_generic
, &spr_write_generic
,
6874 /* XXX : not implemented */
6875 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
6876 &spr_read_ureg
, SPR_NOACCESS
,
6877 &spr_read_ureg
, SPR_NOACCESS
,
6880 spr_register(env
, SPR_SPRG4
, "SPRG4",
6881 SPR_NOACCESS
, SPR_NOACCESS
,
6882 &spr_read_generic
, &spr_write_generic
,
6884 spr_register(env
, SPR_USPRG4
, "USPRG4",
6885 &spr_read_ureg
, SPR_NOACCESS
,
6886 &spr_read_ureg
, SPR_NOACCESS
,
6888 spr_register(env
, SPR_SPRG5
, "SPRG5",
6889 SPR_NOACCESS
, SPR_NOACCESS
,
6890 &spr_read_generic
, &spr_write_generic
,
6892 spr_register(env
, SPR_USPRG5
, "USPRG5",
6893 &spr_read_ureg
, SPR_NOACCESS
,
6894 &spr_read_ureg
, SPR_NOACCESS
,
6896 spr_register(env
, SPR_SPRG6
, "SPRG6",
6897 SPR_NOACCESS
, SPR_NOACCESS
,
6898 &spr_read_generic
, &spr_write_generic
,
6900 spr_register(env
, SPR_USPRG6
, "USPRG6",
6901 &spr_read_ureg
, SPR_NOACCESS
,
6902 &spr_read_ureg
, SPR_NOACCESS
,
6904 spr_register(env
, SPR_SPRG7
, "SPRG7",
6905 SPR_NOACCESS
, SPR_NOACCESS
,
6906 &spr_read_generic
, &spr_write_generic
,
6908 spr_register(env
, SPR_USPRG7
, "USPRG7",
6909 &spr_read_ureg
, SPR_NOACCESS
,
6910 &spr_read_ureg
, SPR_NOACCESS
,
6912 /* Memory management */
6915 gen_74xx_soft_tlb(env
, 128, 2);
6916 init_excp_7450(env
);
6917 env
->dcache_line_size
= 32;
6918 env
->icache_line_size
= 32;
6919 /* Allocate hardware IRQ controller */
6920 ppc6xx_irq_init(env
);
6923 POWERPC_FAMILY(7455)(ObjectClass
*oc
, void *data
)
6925 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6926 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
6928 dc
->desc
= "PowerPC 7455 (aka G4)";
6929 pcc
->init_proc
= init_proc_7455
;
6930 pcc
->check_pow
= check_pow_hid0_74xx
;
6931 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
6932 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
6933 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
6935 PPC_CACHE
| PPC_CACHE_ICBI
|
6936 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
6937 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
6938 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
6939 PPC_MEM_TLBIA
| PPC_74xx_TLB
|
6940 PPC_SEGMENT
| PPC_EXTERN
|
6942 pcc
->msr_mask
= (1ull << MSR_VR
) |
6959 pcc
->mmu_model
= POWERPC_MMU_SOFT_74xx
;
6960 pcc
->excp_model
= POWERPC_EXCP_74xx
;
6961 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
6962 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
6963 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
6964 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
6965 POWERPC_FLAG_BUS_CLK
;
6968 static void init_proc_7457 (CPUPPCState
*env
)
6970 gen_spr_ne_601(env
);
6974 /* 74xx specific SPR */
6976 /* Level 3 cache control */
6979 /* XXX : not implemented */
6980 spr_register(env
, SPR_L3ITCR1
, "L3ITCR1",
6981 SPR_NOACCESS
, SPR_NOACCESS
,
6982 &spr_read_generic
, &spr_write_generic
,
6985 /* XXX : not implemented */
6986 spr_register(env
, SPR_L3ITCR2
, "L3ITCR2",
6987 SPR_NOACCESS
, SPR_NOACCESS
,
6988 &spr_read_generic
, &spr_write_generic
,
6991 /* XXX : not implemented */
6992 spr_register(env
, SPR_L3ITCR3
, "L3ITCR3",
6993 SPR_NOACCESS
, SPR_NOACCESS
,
6994 &spr_read_generic
, &spr_write_generic
,
6997 /* XXX : not implemented */
6998 spr_register(env
, SPR_L3OHCR
, "L3OHCR",
6999 SPR_NOACCESS
, SPR_NOACCESS
,
7000 &spr_read_generic
, &spr_write_generic
,
7003 /* XXX : not implemented */
7004 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
7005 SPR_NOACCESS
, SPR_NOACCESS
,
7006 &spr_read_generic
, &spr_write_generic
,
7009 /* XXX : not implemented */
7010 spr_register(env
, SPR_ICTRL
, "ICTRL",
7011 SPR_NOACCESS
, SPR_NOACCESS
,
7012 &spr_read_generic
, &spr_write_generic
,
7015 /* XXX : not implemented */
7016 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
7017 SPR_NOACCESS
, SPR_NOACCESS
,
7018 &spr_read_generic
, &spr_write_generic
,
7021 /* XXX : not implemented */
7022 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
7023 SPR_NOACCESS
, SPR_NOACCESS
,
7024 &spr_read_generic
, &spr_write_generic
,
7026 /* XXX : not implemented */
7027 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
7028 &spr_read_ureg
, SPR_NOACCESS
,
7029 &spr_read_ureg
, SPR_NOACCESS
,
7031 /* XXX : not implemented */
7032 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
7033 SPR_NOACCESS
, SPR_NOACCESS
,
7034 &spr_read_generic
, &spr_write_generic
,
7036 /* XXX : not implemented */
7037 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
7038 &spr_read_ureg
, SPR_NOACCESS
,
7039 &spr_read_ureg
, SPR_NOACCESS
,
7042 spr_register(env
, SPR_SPRG4
, "SPRG4",
7043 SPR_NOACCESS
, SPR_NOACCESS
,
7044 &spr_read_generic
, &spr_write_generic
,
7046 spr_register(env
, SPR_USPRG4
, "USPRG4",
7047 &spr_read_ureg
, SPR_NOACCESS
,
7048 &spr_read_ureg
, SPR_NOACCESS
,
7050 spr_register(env
, SPR_SPRG5
, "SPRG5",
7051 SPR_NOACCESS
, SPR_NOACCESS
,
7052 &spr_read_generic
, &spr_write_generic
,
7054 spr_register(env
, SPR_USPRG5
, "USPRG5",
7055 &spr_read_ureg
, SPR_NOACCESS
,
7056 &spr_read_ureg
, SPR_NOACCESS
,
7058 spr_register(env
, SPR_SPRG6
, "SPRG6",
7059 SPR_NOACCESS
, SPR_NOACCESS
,
7060 &spr_read_generic
, &spr_write_generic
,
7062 spr_register(env
, SPR_USPRG6
, "USPRG6",
7063 &spr_read_ureg
, SPR_NOACCESS
,
7064 &spr_read_ureg
, SPR_NOACCESS
,
7066 spr_register(env
, SPR_SPRG7
, "SPRG7",
7067 SPR_NOACCESS
, SPR_NOACCESS
,
7068 &spr_read_generic
, &spr_write_generic
,
7070 spr_register(env
, SPR_USPRG7
, "USPRG7",
7071 &spr_read_ureg
, SPR_NOACCESS
,
7072 &spr_read_ureg
, SPR_NOACCESS
,
7074 /* Memory management */
7077 gen_74xx_soft_tlb(env
, 128, 2);
7078 init_excp_7450(env
);
7079 env
->dcache_line_size
= 32;
7080 env
->icache_line_size
= 32;
7081 /* Allocate hardware IRQ controller */
7082 ppc6xx_irq_init(env
);
7085 POWERPC_FAMILY(7457)(ObjectClass
*oc
, void *data
)
7087 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7088 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
7090 dc
->desc
= "PowerPC 7457 (aka G4)";
7091 pcc
->init_proc
= init_proc_7457
;
7092 pcc
->check_pow
= check_pow_hid0_74xx
;
7093 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
7094 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
7095 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
7097 PPC_CACHE
| PPC_CACHE_ICBI
|
7098 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
7099 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
7100 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
7101 PPC_MEM_TLBIA
| PPC_74xx_TLB
|
7102 PPC_SEGMENT
| PPC_EXTERN
|
7104 pcc
->msr_mask
= (1ull << MSR_VR
) |
7121 pcc
->mmu_model
= POWERPC_MMU_SOFT_74xx
;
7122 pcc
->excp_model
= POWERPC_EXCP_74xx
;
7123 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
7124 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
7125 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
7126 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
7127 POWERPC_FLAG_BUS_CLK
;
7130 static void init_proc_e600 (CPUPPCState
*env
)
7132 gen_spr_ne_601(env
);
7136 /* 74xx specific SPR */
7138 /* XXX : not implemented */
7139 spr_register(env
, SPR_UBAMR
, "UBAMR",
7140 &spr_read_ureg
, SPR_NOACCESS
,
7141 &spr_read_ureg
, SPR_NOACCESS
,
7143 /* XXX : not implemented */
7144 spr_register(env
, SPR_LDSTCR
, "LDSTCR",
7145 SPR_NOACCESS
, SPR_NOACCESS
,
7146 &spr_read_generic
, &spr_write_generic
,
7148 /* XXX : not implemented */
7149 spr_register(env
, SPR_ICTRL
, "ICTRL",
7150 SPR_NOACCESS
, SPR_NOACCESS
,
7151 &spr_read_generic
, &spr_write_generic
,
7153 /* XXX : not implemented */
7154 spr_register(env
, SPR_MSSSR0
, "MSSSR0",
7155 SPR_NOACCESS
, SPR_NOACCESS
,
7156 &spr_read_generic
, &spr_write_generic
,
7158 /* XXX : not implemented */
7159 spr_register(env
, SPR_7XX_PMC5
, "PMC5",
7160 SPR_NOACCESS
, SPR_NOACCESS
,
7161 &spr_read_generic
, &spr_write_generic
,
7163 /* XXX : not implemented */
7164 spr_register(env
, SPR_7XX_UPMC5
, "UPMC5",
7165 &spr_read_ureg
, SPR_NOACCESS
,
7166 &spr_read_ureg
, SPR_NOACCESS
,
7168 /* XXX : not implemented */
7169 spr_register(env
, SPR_7XX_PMC6
, "PMC6",
7170 SPR_NOACCESS
, SPR_NOACCESS
,
7171 &spr_read_generic
, &spr_write_generic
,
7173 /* XXX : not implemented */
7174 spr_register(env
, SPR_7XX_UPMC6
, "UPMC6",
7175 &spr_read_ureg
, SPR_NOACCESS
,
7176 &spr_read_ureg
, SPR_NOACCESS
,
7179 spr_register(env
, SPR_SPRG4
, "SPRG4",
7180 SPR_NOACCESS
, SPR_NOACCESS
,
7181 &spr_read_generic
, &spr_write_generic
,
7183 spr_register(env
, SPR_USPRG4
, "USPRG4",
7184 &spr_read_ureg
, SPR_NOACCESS
,
7185 &spr_read_ureg
, SPR_NOACCESS
,
7187 spr_register(env
, SPR_SPRG5
, "SPRG5",
7188 SPR_NOACCESS
, SPR_NOACCESS
,
7189 &spr_read_generic
, &spr_write_generic
,
7191 spr_register(env
, SPR_USPRG5
, "USPRG5",
7192 &spr_read_ureg
, SPR_NOACCESS
,
7193 &spr_read_ureg
, SPR_NOACCESS
,
7195 spr_register(env
, SPR_SPRG6
, "SPRG6",
7196 SPR_NOACCESS
, SPR_NOACCESS
,
7197 &spr_read_generic
, &spr_write_generic
,
7199 spr_register(env
, SPR_USPRG6
, "USPRG6",
7200 &spr_read_ureg
, SPR_NOACCESS
,
7201 &spr_read_ureg
, SPR_NOACCESS
,
7203 spr_register(env
, SPR_SPRG7
, "SPRG7",
7204 SPR_NOACCESS
, SPR_NOACCESS
,
7205 &spr_read_generic
, &spr_write_generic
,
7207 spr_register(env
, SPR_USPRG7
, "USPRG7",
7208 &spr_read_ureg
, SPR_NOACCESS
,
7209 &spr_read_ureg
, SPR_NOACCESS
,
7211 /* Memory management */
7214 gen_74xx_soft_tlb(env
, 128, 2);
7215 init_excp_7450(env
);
7216 env
->dcache_line_size
= 32;
7217 env
->icache_line_size
= 32;
7218 /* Allocate hardware IRQ controller */
7219 ppc6xx_irq_init(env
);
7222 POWERPC_FAMILY(e600
)(ObjectClass
*oc
, void *data
)
7224 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7225 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
7227 dc
->desc
= "PowerPC e600";
7228 pcc
->init_proc
= init_proc_e600
;
7229 pcc
->check_pow
= check_pow_hid0_74xx
;
7230 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
7231 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
7232 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
7234 PPC_CACHE
| PPC_CACHE_ICBI
|
7235 PPC_CACHE_DCBA
| PPC_CACHE_DCBZ
|
7236 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
7237 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
7238 PPC_MEM_TLBIA
| PPC_74xx_TLB
|
7239 PPC_SEGMENT
| PPC_EXTERN
|
7241 pcc
->insns_flags2
= PPC_NONE
;
7242 pcc
->msr_mask
= (1ull << MSR_VR
) |
7259 pcc
->mmu_model
= POWERPC_MMU_32B
;
7260 #if defined(CONFIG_SOFTMMU)
7261 pcc
->handle_mmu_fault
= ppc_hash32_handle_mmu_fault
;
7263 pcc
->excp_model
= POWERPC_EXCP_74xx
;
7264 pcc
->bus_model
= PPC_FLAGS_INPUT_6xx
;
7265 pcc
->bfd_mach
= bfd_mach_ppc_7400
;
7266 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
7267 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
7268 POWERPC_FLAG_BUS_CLK
;
7271 #if defined (TARGET_PPC64)
7272 #if defined(CONFIG_USER_ONLY)
7273 #define POWERPC970_HID5_INIT 0x00000080
7275 #define POWERPC970_HID5_INIT 0x00000000
7278 enum BOOK3S_CPU_TYPE
{
7280 BOOK3S_CPU_POWER5PLUS
,
7286 static void gen_fscr_facility_check(void *opaque
, int facility_sprn
, int bit
,
7287 int sprn
, int cause
)
7289 TCGv_i32 t1
= tcg_const_i32(bit
);
7290 TCGv_i32 t2
= tcg_const_i32(sprn
);
7291 TCGv_i32 t3
= tcg_const_i32(cause
);
7293 gen_update_current_nip(opaque
);
7294 gen_helper_fscr_facility_check(cpu_env
, t1
, t2
, t3
);
7296 tcg_temp_free_i32(t3
);
7297 tcg_temp_free_i32(t2
);
7298 tcg_temp_free_i32(t1
);
7301 static void gen_msr_facility_check(void *opaque
, int facility_sprn
, int bit
,
7302 int sprn
, int cause
)
7304 TCGv_i32 t1
= tcg_const_i32(bit
);
7305 TCGv_i32 t2
= tcg_const_i32(sprn
);
7306 TCGv_i32 t3
= tcg_const_i32(cause
);
7308 gen_update_current_nip(opaque
);
7309 gen_helper_msr_facility_check(cpu_env
, t1
, t2
, t3
);
7311 tcg_temp_free_i32(t3
);
7312 tcg_temp_free_i32(t2
);
7313 tcg_temp_free_i32(t1
);
7316 static void spr_read_prev_upper32(void *opaque
, int gprn
, int sprn
)
7318 TCGv spr_up
= tcg_temp_new();
7319 TCGv spr
= tcg_temp_new();
7321 gen_load_spr(spr
, sprn
- 1);
7322 tcg_gen_shri_tl(spr_up
, spr
, 32);
7323 tcg_gen_ext32u_tl(cpu_gpr
[gprn
], spr_up
);
7326 tcg_temp_free(spr_up
);
7329 static void spr_write_prev_upper32(void *opaque
, int sprn
, int gprn
)
7331 TCGv spr
= tcg_temp_new();
7333 gen_load_spr(spr
, sprn
- 1);
7334 tcg_gen_deposit_tl(spr
, spr
, cpu_gpr
[gprn
], 32, 32);
7335 gen_store_spr(sprn
- 1, spr
);
7340 static int check_pow_970 (CPUPPCState
*env
)
7342 if (env
->spr
[SPR_HID0
] & (HID0_DEEPNAP
| HID0_DOZE
| HID0_NAP
)) {
7349 static void gen_spr_970_hid(CPUPPCState
*env
)
7351 /* Hardware implementation registers */
7352 /* XXX : not implemented */
7353 spr_register(env
, SPR_HID0
, "HID0",
7354 SPR_NOACCESS
, SPR_NOACCESS
,
7355 &spr_read_generic
, &spr_write_clear
,
7357 spr_register(env
, SPR_HID1
, "HID1",
7358 SPR_NOACCESS
, SPR_NOACCESS
,
7359 &spr_read_generic
, &spr_write_generic
,
7361 spr_register(env
, SPR_970_HID5
, "HID5",
7362 SPR_NOACCESS
, SPR_NOACCESS
,
7363 &spr_read_generic
, &spr_write_generic
,
7364 POWERPC970_HID5_INIT
);
7367 static void gen_spr_970_hior(CPUPPCState
*env
)
7369 spr_register(env
, SPR_HIOR
, "SPR_HIOR",
7370 SPR_NOACCESS
, SPR_NOACCESS
,
7371 &spr_read_hior
, &spr_write_hior
,
7375 static void gen_spr_970_lpar(CPUPPCState
*env
)
7377 /* Logical partitionning */
7378 /* PPC970: HID4 is effectively the LPCR */
7379 spr_register(env
, SPR_970_HID4
, "HID4",
7380 SPR_NOACCESS
, SPR_NOACCESS
,
7381 &spr_read_generic
, &spr_write_generic
,
7385 static void gen_spr_book3s_common(CPUPPCState
*env
)
7387 spr_register(env
, SPR_CTRL
, "SPR_CTRL",
7388 SPR_NOACCESS
, SPR_NOACCESS
,
7389 SPR_NOACCESS
, &spr_write_generic
,
7391 spr_register(env
, SPR_UCTRL
, "SPR_UCTRL",
7392 &spr_read_ureg
, SPR_NOACCESS
,
7393 &spr_read_ureg
, SPR_NOACCESS
,
7397 static void gen_spr_book3s_altivec(CPUPPCState
*env
)
7399 if (!(env
->insns_flags
& PPC_ALTIVEC
)) {
7403 spr_register_kvm(env
, SPR_VRSAVE
, "VRSAVE",
7404 &spr_read_generic
, &spr_write_generic
,
7405 &spr_read_generic
, &spr_write_generic
,
7406 KVM_REG_PPC_VRSAVE
, 0x00000000);
7408 /* Can't find information on what this should be on reset. This
7409 * value is the one used by 74xx processors. */
7410 vscr_init(env
, 0x00010000);
7413 static void gen_spr_book3s_dbg(CPUPPCState
*env
)
7416 * TODO: different specs define different scopes for these,
7417 * will have to address this:
7418 * 970: super/write and super/read
7419 * powerisa 2.03..2.04: hypv/write and super/read.
7420 * powerisa 2.05 and newer: hypv/write and hypv/read.
7422 spr_register_kvm(env
, SPR_DABR
, "DABR",
7423 SPR_NOACCESS
, SPR_NOACCESS
,
7424 &spr_read_generic
, &spr_write_generic
,
7425 KVM_REG_PPC_DABR
, 0x00000000);
7426 spr_register_kvm(env
, SPR_DABRX
, "DABRX",
7427 SPR_NOACCESS
, SPR_NOACCESS
,
7428 &spr_read_generic
, &spr_write_generic
,
7429 KVM_REG_PPC_DABRX
, 0x00000000);
7432 static void gen_spr_970_dbg(CPUPPCState
*env
)
7435 spr_register(env
, SPR_IABR
, "IABR",
7436 SPR_NOACCESS
, SPR_NOACCESS
,
7437 &spr_read_generic
, &spr_write_generic
,
7441 static void gen_spr_book3s_pmu_sup(CPUPPCState
*env
)
7443 spr_register_kvm(env
, SPR_POWER_MMCR0
, "MMCR0",
7444 SPR_NOACCESS
, SPR_NOACCESS
,
7445 &spr_read_generic
, &spr_write_generic
,
7446 KVM_REG_PPC_MMCR0
, 0x00000000);
7447 spr_register_kvm(env
, SPR_POWER_MMCR1
, "MMCR1",
7448 SPR_NOACCESS
, SPR_NOACCESS
,
7449 &spr_read_generic
, &spr_write_generic
,
7450 KVM_REG_PPC_MMCR1
, 0x00000000);
7451 spr_register_kvm(env
, SPR_POWER_MMCRA
, "MMCRA",
7452 SPR_NOACCESS
, SPR_NOACCESS
,
7453 &spr_read_generic
, &spr_write_generic
,
7454 KVM_REG_PPC_MMCRA
, 0x00000000);
7455 spr_register_kvm(env
, SPR_POWER_PMC1
, "PMC1",
7456 SPR_NOACCESS
, SPR_NOACCESS
,
7457 &spr_read_generic
, &spr_write_generic
,
7458 KVM_REG_PPC_PMC1
, 0x00000000);
7459 spr_register_kvm(env
, SPR_POWER_PMC2
, "PMC2",
7460 SPR_NOACCESS
, SPR_NOACCESS
,
7461 &spr_read_generic
, &spr_write_generic
,
7462 KVM_REG_PPC_PMC2
, 0x00000000);
7463 spr_register_kvm(env
, SPR_POWER_PMC3
, "PMC3",
7464 SPR_NOACCESS
, SPR_NOACCESS
,
7465 &spr_read_generic
, &spr_write_generic
,
7466 KVM_REG_PPC_PMC3
, 0x00000000);
7467 spr_register_kvm(env
, SPR_POWER_PMC4
, "PMC4",
7468 SPR_NOACCESS
, SPR_NOACCESS
,
7469 &spr_read_generic
, &spr_write_generic
,
7470 KVM_REG_PPC_PMC4
, 0x00000000);
7471 spr_register_kvm(env
, SPR_POWER_PMC5
, "PMC5",
7472 SPR_NOACCESS
, SPR_NOACCESS
,
7473 &spr_read_generic
, &spr_write_generic
,
7474 KVM_REG_PPC_PMC5
, 0x00000000);
7475 spr_register_kvm(env
, SPR_POWER_PMC6
, "PMC6",
7476 SPR_NOACCESS
, SPR_NOACCESS
,
7477 &spr_read_generic
, &spr_write_generic
,
7478 KVM_REG_PPC_PMC6
, 0x00000000);
7479 spr_register_kvm(env
, SPR_POWER_SIAR
, "SIAR",
7480 SPR_NOACCESS
, SPR_NOACCESS
,
7481 &spr_read_generic
, &spr_write_generic
,
7482 KVM_REG_PPC_SIAR
, 0x00000000);
7483 spr_register_kvm(env
, SPR_POWER_SDAR
, "SDAR",
7484 SPR_NOACCESS
, SPR_NOACCESS
,
7485 &spr_read_generic
, &spr_write_generic
,
7486 KVM_REG_PPC_SDAR
, 0x00000000);
7489 static void gen_spr_book3s_pmu_user(CPUPPCState
*env
)
7491 spr_register(env
, SPR_POWER_UMMCR0
, "UMMCR0",
7492 &spr_read_ureg
, SPR_NOACCESS
,
7493 &spr_read_ureg
, &spr_write_ureg
,
7495 spr_register(env
, SPR_POWER_UMMCR1
, "UMMCR1",
7496 &spr_read_ureg
, SPR_NOACCESS
,
7497 &spr_read_ureg
, &spr_write_ureg
,
7499 spr_register(env
, SPR_POWER_UMMCRA
, "UMMCRA",
7500 &spr_read_ureg
, SPR_NOACCESS
,
7501 &spr_read_ureg
, &spr_write_ureg
,
7503 spr_register(env
, SPR_POWER_UPMC1
, "UPMC1",
7504 &spr_read_ureg
, SPR_NOACCESS
,
7505 &spr_read_ureg
, &spr_write_ureg
,
7507 spr_register(env
, SPR_POWER_UPMC2
, "UPMC2",
7508 &spr_read_ureg
, SPR_NOACCESS
,
7509 &spr_read_ureg
, &spr_write_ureg
,
7511 spr_register(env
, SPR_POWER_UPMC3
, "UPMC3",
7512 &spr_read_ureg
, SPR_NOACCESS
,
7513 &spr_read_ureg
, &spr_write_ureg
,
7515 spr_register(env
, SPR_POWER_UPMC4
, "UPMC4",
7516 &spr_read_ureg
, SPR_NOACCESS
,
7517 &spr_read_ureg
, &spr_write_ureg
,
7519 spr_register(env
, SPR_POWER_UPMC5
, "UPMC5",
7520 &spr_read_ureg
, SPR_NOACCESS
,
7521 &spr_read_ureg
, &spr_write_ureg
,
7523 spr_register(env
, SPR_POWER_UPMC6
, "UPMC6",
7524 &spr_read_ureg
, SPR_NOACCESS
,
7525 &spr_read_ureg
, &spr_write_ureg
,
7527 spr_register(env
, SPR_POWER_USIAR
, "USIAR",
7528 &spr_read_ureg
, SPR_NOACCESS
,
7529 &spr_read_ureg
, &spr_write_ureg
,
7531 spr_register(env
, SPR_POWER_USDAR
, "USDAR",
7532 &spr_read_ureg
, SPR_NOACCESS
,
7533 &spr_read_ureg
, &spr_write_ureg
,
7537 static void gen_spr_970_pmu_sup(CPUPPCState
*env
)
7539 spr_register_kvm(env
, SPR_970_PMC7
, "PMC7",
7540 SPR_NOACCESS
, SPR_NOACCESS
,
7541 &spr_read_generic
, &spr_write_generic
,
7542 KVM_REG_PPC_PMC7
, 0x00000000);
7543 spr_register_kvm(env
, SPR_970_PMC8
, "PMC8",
7544 SPR_NOACCESS
, SPR_NOACCESS
,
7545 &spr_read_generic
, &spr_write_generic
,
7546 KVM_REG_PPC_PMC8
, 0x00000000);
7549 static void gen_spr_970_pmu_user(CPUPPCState
*env
)
7551 spr_register(env
, SPR_970_UPMC7
, "UPMC7",
7552 &spr_read_ureg
, SPR_NOACCESS
,
7553 &spr_read_ureg
, &spr_write_ureg
,
7555 spr_register(env
, SPR_970_UPMC8
, "UPMC8",
7556 &spr_read_ureg
, SPR_NOACCESS
,
7557 &spr_read_ureg
, &spr_write_ureg
,
7561 static void gen_spr_power8_pmu_sup(CPUPPCState
*env
)
7563 spr_register_kvm(env
, SPR_POWER_MMCR2
, "MMCR2",
7564 SPR_NOACCESS
, SPR_NOACCESS
,
7565 &spr_read_generic
, &spr_write_generic
,
7566 KVM_REG_PPC_MMCR2
, 0x00000000);
7567 spr_register_kvm(env
, SPR_POWER_MMCRS
, "MMCRS",
7568 SPR_NOACCESS
, SPR_NOACCESS
,
7569 &spr_read_generic
, &spr_write_generic
,
7570 KVM_REG_PPC_MMCRS
, 0x00000000);
7573 static void gen_spr_power8_pmu_user(CPUPPCState
*env
)
7575 spr_register(env
, SPR_POWER_UMMCR2
, "UMMCR2",
7576 &spr_read_ureg
, SPR_NOACCESS
,
7577 &spr_read_ureg
, &spr_write_ureg
,
7581 static void gen_spr_power5p_ear(CPUPPCState
*env
)
7583 /* External access control */
7584 spr_register(env
, SPR_EAR
, "EAR",
7585 SPR_NOACCESS
, SPR_NOACCESS
,
7586 &spr_read_generic
, &spr_write_generic
,
7590 static void gen_spr_power5p_lpar(CPUPPCState
*env
)
7592 /* Logical partitionning */
7593 spr_register_kvm(env
, SPR_LPCR
, "LPCR",
7594 SPR_NOACCESS
, SPR_NOACCESS
,
7595 &spr_read_generic
, &spr_write_generic
,
7596 KVM_REG_PPC_LPCR
, 0x00000000);
7599 static void gen_spr_book3s_ids(CPUPPCState
*env
)
7601 /* Processor identification */
7602 spr_register(env
, SPR_PIR
, "PIR",
7603 SPR_NOACCESS
, SPR_NOACCESS
,
7604 &spr_read_generic
, &spr_write_pir
,
7608 static void gen_spr_power8_ids(CPUPPCState
*env
)
7610 /* Thread identification */
7611 spr_register(env
, SPR_TIR
, "TIR",
7612 SPR_NOACCESS
, SPR_NOACCESS
,
7613 &spr_read_generic
, SPR_NOACCESS
,
7617 static void gen_spr_book3s_purr(CPUPPCState
*env
)
7619 #if !defined(CONFIG_USER_ONLY)
7620 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7621 spr_register_kvm(env
, SPR_PURR
, "PURR",
7622 &spr_read_purr
, SPR_NOACCESS
,
7623 &spr_read_purr
, SPR_NOACCESS
,
7624 KVM_REG_PPC_PURR
, 0x00000000);
7625 spr_register_kvm(env
, SPR_SPURR
, "SPURR",
7626 &spr_read_purr
, SPR_NOACCESS
,
7627 &spr_read_purr
, SPR_NOACCESS
,
7628 KVM_REG_PPC_SPURR
, 0x00000000);
7632 static void gen_spr_power6_dbg(CPUPPCState
*env
)
7634 #if !defined(CONFIG_USER_ONLY)
7635 spr_register(env
, SPR_CFAR
, "SPR_CFAR",
7636 SPR_NOACCESS
, SPR_NOACCESS
,
7637 &spr_read_cfar
, &spr_write_cfar
,
7642 static void gen_spr_power5p_common(CPUPPCState
*env
)
7644 spr_register_kvm(env
, SPR_PPR
, "PPR",
7645 &spr_read_generic
, &spr_write_generic
,
7646 &spr_read_generic
, &spr_write_generic
,
7647 KVM_REG_PPC_PPR
, 0x00000000);
7650 static void gen_spr_power6_common(CPUPPCState
*env
)
7652 #if !defined(CONFIG_USER_ONLY)
7653 spr_register_kvm(env
, SPR_DSCR
, "SPR_DSCR",
7654 SPR_NOACCESS
, SPR_NOACCESS
,
7655 &spr_read_generic
, &spr_write_generic
,
7656 KVM_REG_PPC_DSCR
, 0x00000000);
7659 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7660 * POWERPC_EXCP_INVAL_SPR.
7662 spr_register(env
, SPR_PCR
, "PCR",
7663 SPR_NOACCESS
, SPR_NOACCESS
,
7664 SPR_NOACCESS
, SPR_NOACCESS
,
7668 static void spr_read_tar(void *opaque
, int gprn
, int sprn
)
7670 gen_fscr_facility_check(opaque
, SPR_FSCR
, FSCR_TAR
, sprn
, FSCR_IC_TAR
);
7671 spr_read_generic(opaque
, gprn
, sprn
);
7674 static void spr_write_tar(void *opaque
, int sprn
, int gprn
)
7676 gen_fscr_facility_check(opaque
, SPR_FSCR
, FSCR_TAR
, sprn
, FSCR_IC_TAR
);
7677 spr_write_generic(opaque
, sprn
, gprn
);
7680 static void gen_spr_power8_tce_address_control(CPUPPCState
*env
)
7682 spr_register(env
, SPR_TAR
, "TAR",
7683 &spr_read_tar
, &spr_write_tar
,
7684 &spr_read_generic
, &spr_write_generic
,
7688 static void spr_read_tm(void *opaque
, int gprn
, int sprn
)
7690 gen_msr_facility_check(opaque
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
7691 spr_read_generic(opaque
, gprn
, sprn
);
7694 static void spr_write_tm(void *opaque
, int sprn
, int gprn
)
7696 gen_msr_facility_check(opaque
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
7697 spr_write_generic(opaque
, sprn
, gprn
);
7700 static void spr_read_tm_upper32(void *opaque
, int gprn
, int sprn
)
7702 gen_msr_facility_check(opaque
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
7703 spr_read_prev_upper32(opaque
, gprn
, sprn
);
7706 static void spr_write_tm_upper32(void *opaque
, int sprn
, int gprn
)
7708 gen_msr_facility_check(opaque
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
7709 spr_write_prev_upper32(opaque
, sprn
, gprn
);
7712 static void gen_spr_power8_tm(CPUPPCState
*env
)
7714 spr_register_kvm(env
, SPR_TFHAR
, "TFHAR",
7715 &spr_read_tm
, &spr_write_tm
,
7716 &spr_read_tm
, &spr_write_tm
,
7717 KVM_REG_PPC_TFHAR
, 0x00000000);
7718 spr_register_kvm(env
, SPR_TFIAR
, "TFIAR",
7719 &spr_read_tm
, &spr_write_tm
,
7720 &spr_read_tm
, &spr_write_tm
,
7721 KVM_REG_PPC_TFIAR
, 0x00000000);
7722 spr_register_kvm(env
, SPR_TEXASR
, "TEXASR",
7723 &spr_read_tm
, &spr_write_tm
,
7724 &spr_read_tm
, &spr_write_tm
,
7725 KVM_REG_PPC_TEXASR
, 0x00000000);
7726 spr_register(env
, SPR_TEXASRU
, "TEXASRU",
7727 &spr_read_tm_upper32
, &spr_write_tm_upper32
,
7728 &spr_read_tm_upper32
, &spr_write_tm_upper32
,
7732 static void spr_read_ebb(void *opaque
, int gprn
, int sprn
)
7734 gen_fscr_facility_check(opaque
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
7735 spr_read_generic(opaque
, gprn
, sprn
);
7738 static void spr_write_ebb(void *opaque
, int sprn
, int gprn
)
7740 gen_fscr_facility_check(opaque
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
7741 spr_write_generic(opaque
, sprn
, gprn
);
7744 static void spr_read_ebb_upper32(void *opaque
, int gprn
, int sprn
)
7746 gen_fscr_facility_check(opaque
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
7747 spr_read_prev_upper32(opaque
, gprn
, sprn
);
7750 static void spr_write_ebb_upper32(void *opaque
, int sprn
, int gprn
)
7752 gen_fscr_facility_check(opaque
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
7753 spr_write_prev_upper32(opaque
, sprn
, gprn
);
7756 static void gen_spr_power8_ebb(CPUPPCState
*env
)
7758 spr_register(env
, SPR_BESCRS
, "BESCRS",
7759 &spr_read_ebb
, &spr_write_ebb
,
7760 &spr_read_generic
, &spr_write_generic
,
7762 spr_register(env
, SPR_BESCRSU
, "BESCRSU",
7763 &spr_read_ebb_upper32
, &spr_write_ebb_upper32
,
7764 &spr_read_prev_upper32
, &spr_write_prev_upper32
,
7766 spr_register(env
, SPR_BESCRR
, "BESCRR",
7767 &spr_read_ebb
, &spr_write_ebb
,
7768 &spr_read_generic
, &spr_write_generic
,
7770 spr_register(env
, SPR_BESCRRU
, "BESCRRU",
7771 &spr_read_ebb_upper32
, &spr_write_ebb_upper32
,
7772 &spr_read_prev_upper32
, &spr_write_prev_upper32
,
7774 spr_register_kvm(env
, SPR_EBBHR
, "EBBHR",
7775 &spr_read_ebb
, &spr_write_ebb
,
7776 &spr_read_generic
, &spr_write_generic
,
7777 KVM_REG_PPC_EBBHR
, 0x00000000);
7778 spr_register_kvm(env
, SPR_EBBRR
, "EBBRR",
7779 &spr_read_ebb
, &spr_write_ebb
,
7780 &spr_read_generic
, &spr_write_generic
,
7781 KVM_REG_PPC_EBBRR
, 0x00000000);
7782 spr_register_kvm(env
, SPR_BESCR
, "BESCR",
7783 &spr_read_ebb
, &spr_write_ebb
,
7784 &spr_read_generic
, &spr_write_generic
,
7785 KVM_REG_PPC_BESCR
, 0x00000000);
7788 static void gen_spr_power8_fscr(CPUPPCState
*env
)
7790 #if defined(CONFIG_USER_ONLY)
7791 target_ulong initval
= 1ULL << FSCR_TAR
;
7793 target_ulong initval
= 0;
7795 spr_register_kvm(env
, SPR_FSCR
, "FSCR",
7796 SPR_NOACCESS
, SPR_NOACCESS
,
7797 &spr_read_generic
, &spr_write_generic
,
7798 KVM_REG_PPC_FSCR
, initval
);
7801 static void init_proc_book3s_64(CPUPPCState
*env
, int version
)
7803 gen_spr_ne_601(env
);
7805 gen_spr_book3s_altivec(env
);
7806 gen_spr_book3s_pmu_sup(env
);
7807 gen_spr_book3s_pmu_user(env
);
7808 gen_spr_book3s_common(env
);
7811 case BOOK3S_CPU_970
:
7812 case BOOK3S_CPU_POWER5PLUS
:
7813 gen_spr_970_hid(env
);
7814 gen_spr_970_hior(env
);
7816 gen_spr_970_pmu_sup(env
);
7817 gen_spr_970_pmu_user(env
);
7819 case BOOK3S_CPU_POWER7
:
7820 case BOOK3S_CPU_POWER8
:
7821 gen_spr_book3s_ids(env
);
7823 gen_spr_book3s_purr(env
);
7826 g_assert_not_reached();
7828 if (version
>= BOOK3S_CPU_POWER5PLUS
) {
7829 gen_spr_power5p_common(env
);
7830 gen_spr_power5p_lpar(env
);
7831 gen_spr_power5p_ear(env
);
7833 gen_spr_970_lpar(env
);
7835 if (version
== BOOK3S_CPU_970
) {
7836 gen_spr_970_dbg(env
);
7838 if (version
>= BOOK3S_CPU_POWER6
) {
7839 gen_spr_power6_common(env
);
7840 gen_spr_power6_dbg(env
);
7842 if (version
>= BOOK3S_CPU_POWER8
) {
7843 gen_spr_power8_tce_address_control(env
);
7844 gen_spr_power8_ids(env
);
7845 gen_spr_power8_ebb(env
);
7846 gen_spr_power8_fscr(env
);
7847 gen_spr_power8_pmu_sup(env
);
7848 gen_spr_power8_pmu_user(env
);
7849 gen_spr_power8_tm(env
);
7851 if (version
< BOOK3S_CPU_POWER8
) {
7852 gen_spr_book3s_dbg(env
);
7854 #if !defined(CONFIG_USER_ONLY)
7856 case BOOK3S_CPU_970
:
7857 case BOOK3S_CPU_POWER5PLUS
:
7860 case BOOK3S_CPU_POWER7
:
7861 case BOOK3S_CPU_POWER8
:
7867 /* Allocate hardware IRQ controller */
7869 case BOOK3S_CPU_970
:
7870 case BOOK3S_CPU_POWER5PLUS
:
7872 ppc970_irq_init(env
);
7874 case BOOK3S_CPU_POWER7
:
7875 case BOOK3S_CPU_POWER8
:
7876 init_excp_POWER7(env
);
7877 ppcPOWER7_irq_init(env
);
7880 g_assert_not_reached();
7883 env
->dcache_line_size
= 128;
7884 env
->icache_line_size
= 128;
7887 static void init_proc_970(CPUPPCState
*env
)
7889 init_proc_book3s_64(env
, BOOK3S_CPU_970
);
7892 POWERPC_FAMILY(970)(ObjectClass
*oc
, void *data
)
7894 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7895 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
7897 dc
->desc
= "PowerPC 970";
7898 pcc
->init_proc
= init_proc_970
;
7899 pcc
->check_pow
= check_pow_970
;
7900 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
7901 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
7902 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
7904 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
7905 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
7906 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
7907 PPC_64B
| PPC_ALTIVEC
|
7908 PPC_SEGMENT_64B
| PPC_SLBI
;
7909 pcc
->msr_mask
= (1ull << MSR_SF
) |
7924 pcc
->mmu_model
= POWERPC_MMU_64B
;
7925 #if defined(CONFIG_SOFTMMU)
7926 pcc
->handle_mmu_fault
= ppc_hash64_handle_mmu_fault
;
7928 pcc
->excp_model
= POWERPC_EXCP_970
;
7929 pcc
->bus_model
= PPC_FLAGS_INPUT_970
;
7930 pcc
->bfd_mach
= bfd_mach_ppc64
;
7931 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
7932 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
7933 POWERPC_FLAG_BUS_CLK
;
7934 pcc
->l1_dcache_size
= 0x8000;
7935 pcc
->l1_icache_size
= 0x10000;
7938 static void init_proc_power5plus(CPUPPCState
*env
)
7940 init_proc_book3s_64(env
, BOOK3S_CPU_POWER5PLUS
);
7943 POWERPC_FAMILY(POWER5P
)(ObjectClass
*oc
, void *data
)
7945 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7946 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
7948 dc
->fw_name
= "PowerPC,POWER5";
7949 dc
->desc
= "POWER5+";
7950 pcc
->init_proc
= init_proc_power5plus
;
7951 pcc
->check_pow
= check_pow_970
;
7952 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_STRING
| PPC_MFTB
|
7953 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
7954 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
7956 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
7957 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
7958 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
7960 PPC_SEGMENT_64B
| PPC_SLBI
;
7961 pcc
->msr_mask
= (1ull << MSR_SF
) |
7976 pcc
->mmu_model
= POWERPC_MMU_64B
;
7977 #if defined(CONFIG_SOFTMMU)
7978 pcc
->handle_mmu_fault
= ppc_hash64_handle_mmu_fault
;
7980 pcc
->excp_model
= POWERPC_EXCP_970
;
7981 pcc
->bus_model
= PPC_FLAGS_INPUT_970
;
7982 pcc
->bfd_mach
= bfd_mach_ppc64
;
7983 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
7984 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
7985 POWERPC_FLAG_BUS_CLK
;
7986 pcc
->l1_dcache_size
= 0x8000;
7987 pcc
->l1_icache_size
= 0x10000;
7990 static void powerpc_get_compat(Object
*obj
, Visitor
*v
,
7991 void *opaque
, const char *name
, Error
**errp
)
7993 char *value
= (char *)"";
7994 Property
*prop
= opaque
;
7995 uint32_t *max_compat
= qdev_get_prop_ptr(DEVICE(obj
), prop
);
7997 switch (*max_compat
) {
7998 case CPU_POWERPC_LOGICAL_2_05
:
7999 value
= (char *)"power6";
8001 case CPU_POWERPC_LOGICAL_2_06
:
8002 value
= (char *)"power7";
8004 case CPU_POWERPC_LOGICAL_2_07
:
8005 value
= (char *)"power8";
8010 error_setg(errp
, "Internal error: compat is set to %x",
8011 max_compat
? *max_compat
: -1);
8015 visit_type_str(v
, &value
, name
, errp
);
8018 static void powerpc_set_compat(Object
*obj
, Visitor
*v
,
8019 void *opaque
, const char *name
, Error
**errp
)
8021 Error
*error
= NULL
;
8023 Property
*prop
= opaque
;
8024 uint32_t *max_compat
= qdev_get_prop_ptr(DEVICE(obj
), prop
);
8026 visit_type_str(v
, &value
, name
, &error
);
8028 error_propagate(errp
, error
);
8032 if (strcmp(value
, "power6") == 0) {
8033 *max_compat
= CPU_POWERPC_LOGICAL_2_05
;
8034 } else if (strcmp(value
, "power7") == 0) {
8035 *max_compat
= CPU_POWERPC_LOGICAL_2_06
;
8036 } else if (strcmp(value
, "power8") == 0) {
8037 *max_compat
= CPU_POWERPC_LOGICAL_2_07
;
8039 error_setg(errp
, "Invalid compatibility mode \"%s\"", value
);
8045 static PropertyInfo powerpc_compat_propinfo
= {
8047 .description
= "compatibility mode, power6/power7/power8",
8048 .get
= powerpc_get_compat
,
8049 .set
= powerpc_set_compat
,
8052 #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
8053 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
8055 static Property powerpc_servercpu_properties
[] = {
8056 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU
, max_compat
),
8057 DEFINE_PROP_END_OF_LIST(),
8060 static void init_proc_POWER7 (CPUPPCState
*env
)
8062 init_proc_book3s_64(env
, BOOK3S_CPU_POWER7
);
8065 static bool ppc_pvr_match_power7(PowerPCCPUClass
*pcc
, uint32_t pvr
)
8067 if ((pvr
& CPU_POWERPC_POWER_SERVER_MASK
) == CPU_POWERPC_POWER7P_BASE
) {
8070 if ((pvr
& CPU_POWERPC_POWER_SERVER_MASK
) == CPU_POWERPC_POWER7_BASE
) {
8076 POWERPC_FAMILY(POWER7
)(ObjectClass
*oc
, void *data
)
8078 DeviceClass
*dc
= DEVICE_CLASS(oc
);
8079 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
8081 dc
->fw_name
= "PowerPC,POWER7";
8082 dc
->desc
= "POWER7";
8083 dc
->props
= powerpc_servercpu_properties
;
8084 pcc
->pvr_match
= ppc_pvr_match_power7
;
8085 pcc
->pcr_mask
= PCR_COMPAT_2_05
| PCR_COMPAT_2_06
;
8086 pcc
->init_proc
= init_proc_POWER7
;
8087 pcc
->check_pow
= check_pow_nocheck
;
8088 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
|
8089 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
8090 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
8091 PPC_FLOAT_FRSQRTES
|
8094 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
8095 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
8096 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
8097 PPC_64B
| PPC_ALTIVEC
|
8098 PPC_SEGMENT_64B
| PPC_SLBI
|
8099 PPC_POPCNTB
| PPC_POPCNTWD
;
8100 pcc
->insns_flags2
= PPC2_VSX
| PPC2_DFP
| PPC2_DBRX
| PPC2_ISA205
|
8101 PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
|
8102 PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
|
8104 pcc
->msr_mask
= (1ull << MSR_SF
) |
8120 pcc
->mmu_model
= POWERPC_MMU_2_06
;
8121 #if defined(CONFIG_SOFTMMU)
8122 pcc
->handle_mmu_fault
= ppc_hash64_handle_mmu_fault
;
8124 pcc
->excp_model
= POWERPC_EXCP_POWER7
;
8125 pcc
->bus_model
= PPC_FLAGS_INPUT_POWER7
;
8126 pcc
->bfd_mach
= bfd_mach_ppc64
;
8127 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
8128 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
8129 POWERPC_FLAG_BUS_CLK
| POWERPC_FLAG_CFAR
|
8131 pcc
->l1_dcache_size
= 0x8000;
8132 pcc
->l1_icache_size
= 0x8000;
8133 pcc
->interrupts_big_endian
= ppc_cpu_interrupts_big_endian_lpcr
;
8136 static void init_proc_POWER8(CPUPPCState
*env
)
8138 init_proc_book3s_64(env
, BOOK3S_CPU_POWER8
);
8141 static bool ppc_pvr_match_power8(PowerPCCPUClass
*pcc
, uint32_t pvr
)
8143 if ((pvr
& CPU_POWERPC_POWER_SERVER_MASK
) == CPU_POWERPC_POWER8E_BASE
) {
8146 if ((pvr
& CPU_POWERPC_POWER_SERVER_MASK
) == CPU_POWERPC_POWER8_BASE
) {
8152 POWERPC_FAMILY(POWER8
)(ObjectClass
*oc
, void *data
)
8154 DeviceClass
*dc
= DEVICE_CLASS(oc
);
8155 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
8157 dc
->fw_name
= "PowerPC,POWER8";
8158 dc
->desc
= "POWER8";
8159 dc
->props
= powerpc_servercpu_properties
;
8160 pcc
->pvr_match
= ppc_pvr_match_power8
;
8161 pcc
->pcr_mask
= PCR_COMPAT_2_05
| PCR_COMPAT_2_06
;
8162 pcc
->init_proc
= init_proc_POWER8
;
8163 pcc
->check_pow
= check_pow_nocheck
;
8164 pcc
->insns_flags
= PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
|
8165 PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
|
8166 PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
|
8167 PPC_FLOAT_FRSQRTES
|
8170 PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
|
8171 PPC_MEM_SYNC
| PPC_MEM_EIEIO
|
8172 PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
|
8173 PPC_64B
| PPC_64BX
| PPC_ALTIVEC
|
8174 PPC_SEGMENT_64B
| PPC_SLBI
|
8175 PPC_POPCNTB
| PPC_POPCNTWD
;
8176 pcc
->insns_flags2
= PPC2_VSX
| PPC2_VSX207
| PPC2_DFP
| PPC2_DBRX
|
8177 PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
|
8178 PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
|
8179 PPC2_FP_TST_ISA206
| PPC2_BCTAR_ISA207
|
8180 PPC2_LSQ_ISA207
| PPC2_ALTIVEC_207
|
8181 PPC2_ISA205
| PPC2_ISA207S
;
8182 pcc
->msr_mask
= (1ull << MSR_SF
) |
8199 pcc
->mmu_model
= POWERPC_MMU_2_06
;
8200 #if defined(CONFIG_SOFTMMU)
8201 pcc
->handle_mmu_fault
= ppc_hash64_handle_mmu_fault
;
8203 pcc
->excp_model
= POWERPC_EXCP_POWER7
;
8204 pcc
->bus_model
= PPC_FLAGS_INPUT_POWER7
;
8205 pcc
->bfd_mach
= bfd_mach_ppc64
;
8206 pcc
->flags
= POWERPC_FLAG_VRE
| POWERPC_FLAG_SE
|
8207 POWERPC_FLAG_BE
| POWERPC_FLAG_PMM
|
8208 POWERPC_FLAG_BUS_CLK
| POWERPC_FLAG_CFAR
|
8210 pcc
->l1_dcache_size
= 0x8000;
8211 pcc
->l1_icache_size
= 0x8000;
8212 pcc
->interrupts_big_endian
= ppc_cpu_interrupts_big_endian_lpcr
;
8214 #endif /* defined (TARGET_PPC64) */
8217 /*****************************************************************************/
8218 /* Generic CPU instantiation routine */
8219 static void init_ppc_proc(PowerPCCPU
*cpu
)
8221 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
8222 CPUPPCState
*env
= &cpu
->env
;
8223 #if !defined(CONFIG_USER_ONLY)
8226 env
->irq_inputs
= NULL
;
8227 /* Set all exception vectors to an invalid address */
8228 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
8229 env
->excp_vectors
[i
] = (target_ulong
)(-1ULL);
8230 env
->ivor_mask
= 0x00000000;
8231 env
->ivpr_mask
= 0x00000000;
8232 /* Default MMU definitions */
8236 env
->tlb_type
= TLB_NONE
;
8238 /* Register SPR common to all PowerPC implementations */
8239 gen_spr_generic(env
);
8240 spr_register(env
, SPR_PVR
, "PVR",
8241 /* Linux permits userspace to read PVR */
8242 #if defined(CONFIG_LINUX_USER)
8248 &spr_read_generic
, SPR_NOACCESS
,
8250 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8251 if (pcc
->svr
!= POWERPC_SVR_NONE
) {
8252 if (pcc
->svr
& POWERPC_SVR_E500
) {
8253 spr_register(env
, SPR_E500_SVR
, "SVR",
8254 SPR_NOACCESS
, SPR_NOACCESS
,
8255 &spr_read_generic
, SPR_NOACCESS
,
8256 pcc
->svr
& ~POWERPC_SVR_E500
);
8258 spr_register(env
, SPR_SVR
, "SVR",
8259 SPR_NOACCESS
, SPR_NOACCESS
,
8260 &spr_read_generic
, SPR_NOACCESS
,
8264 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8265 (*pcc
->init_proc
)(env
);
8267 /* MSR bits & flags consistency checks */
8268 if (env
->msr_mask
& (1 << 25)) {
8269 switch (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
8270 case POWERPC_FLAG_SPE
:
8271 case POWERPC_FLAG_VRE
:
8274 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8275 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8278 } else if (env
->flags
& (POWERPC_FLAG_SPE
| POWERPC_FLAG_VRE
)) {
8279 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8280 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8283 if (env
->msr_mask
& (1 << 17)) {
8284 switch (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
8285 case POWERPC_FLAG_TGPR
:
8286 case POWERPC_FLAG_CE
:
8289 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8290 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8293 } else if (env
->flags
& (POWERPC_FLAG_TGPR
| POWERPC_FLAG_CE
)) {
8294 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8295 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8298 if (env
->msr_mask
& (1 << 10)) {
8299 switch (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
8300 POWERPC_FLAG_UBLE
)) {
8301 case POWERPC_FLAG_SE
:
8302 case POWERPC_FLAG_DWE
:
8303 case POWERPC_FLAG_UBLE
:
8306 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8307 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8308 "POWERPC_FLAG_UBLE\n");
8311 } else if (env
->flags
& (POWERPC_FLAG_SE
| POWERPC_FLAG_DWE
|
8312 POWERPC_FLAG_UBLE
)) {
8313 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8314 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8315 "POWERPC_FLAG_UBLE\n");
8318 if (env
->msr_mask
& (1 << 9)) {
8319 switch (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
8320 case POWERPC_FLAG_BE
:
8321 case POWERPC_FLAG_DE
:
8324 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8325 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8328 } else if (env
->flags
& (POWERPC_FLAG_BE
| POWERPC_FLAG_DE
)) {
8329 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8330 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8333 if (env
->msr_mask
& (1 << 2)) {
8334 switch (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
8335 case POWERPC_FLAG_PX
:
8336 case POWERPC_FLAG_PMM
:
8339 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8340 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8343 } else if (env
->flags
& (POWERPC_FLAG_PX
| POWERPC_FLAG_PMM
)) {
8344 fprintf(stderr
, "PowerPC MSR definition inconsistency\n"
8345 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8348 if ((env
->flags
& (POWERPC_FLAG_RTC_CLK
| POWERPC_FLAG_BUS_CLK
)) == 0) {
8349 fprintf(stderr
, "PowerPC flags inconsistency\n"
8350 "Should define the time-base and decrementer clock source\n");
8353 /* Allocate TLBs buffer when needed */
8354 #if !defined(CONFIG_USER_ONLY)
8355 if (env
->nb_tlb
!= 0) {
8356 int nb_tlb
= env
->nb_tlb
;
8357 if (env
->id_tlbs
!= 0)
8359 switch (env
->tlb_type
) {
8361 env
->tlb
.tlb6
= g_malloc0(nb_tlb
* sizeof(ppc6xx_tlb_t
));
8364 env
->tlb
.tlbe
= g_malloc0(nb_tlb
* sizeof(ppcemb_tlb_t
));
8367 env
->tlb
.tlbm
= g_malloc0(nb_tlb
* sizeof(ppcmas_tlb_t
));
8370 /* Pre-compute some useful values */
8371 env
->tlb_per_way
= env
->nb_tlb
/ env
->nb_ways
;
8373 if (env
->irq_inputs
== NULL
) {
8374 fprintf(stderr
, "WARNING: no internal IRQ controller registered.\n"
8375 " Attempt QEMU to crash very soon !\n");
8378 if (env
->check_pow
== NULL
) {
8379 fprintf(stderr
, "WARNING: no power management check handler "
8381 " Attempt QEMU to crash very soon !\n");
8385 #if defined(PPC_DUMP_CPU)
8386 static void dump_ppc_sprs (CPUPPCState
*env
)
8389 #if !defined(CONFIG_USER_ONLY)
8395 printf("Special purpose registers:\n");
8396 for (i
= 0; i
< 32; i
++) {
8397 for (j
= 0; j
< 32; j
++) {
8399 spr
= &env
->spr_cb
[n
];
8400 uw
= spr
->uea_write
!= NULL
&& spr
->uea_write
!= SPR_NOACCESS
;
8401 ur
= spr
->uea_read
!= NULL
&& spr
->uea_read
!= SPR_NOACCESS
;
8402 #if !defined(CONFIG_USER_ONLY)
8403 sw
= spr
->oea_write
!= NULL
&& spr
->oea_write
!= SPR_NOACCESS
;
8404 sr
= spr
->oea_read
!= NULL
&& spr
->oea_read
!= SPR_NOACCESS
;
8405 if (sw
|| sr
|| uw
|| ur
) {
8406 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8407 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
8408 sw
? 'w' : '-', sr
? 'r' : '-',
8409 uw
? 'w' : '-', ur
? 'r' : '-');
8413 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8414 (i
<< 5) | j
, (i
<< 5) | j
, spr
->name
,
8415 uw
? 'w' : '-', ur
? 'r' : '-');
8425 /*****************************************************************************/
8431 PPC_DIRECT
= 0, /* Opcode routine */
8432 PPC_INDIRECT
= 1, /* Indirect opcode table */
8435 static inline int is_indirect_opcode (void *handler
)
8437 return ((uintptr_t)handler
& 0x03) == PPC_INDIRECT
;
8440 static inline opc_handler_t
**ind_table(void *handler
)
8442 return (opc_handler_t
**)((uintptr_t)handler
& ~3);
8445 /* Instruction table creation */
8446 /* Opcodes tables creation */
8447 static void fill_new_table (opc_handler_t
**table
, int len
)
8451 for (i
= 0; i
< len
; i
++)
8452 table
[i
] = &invalid_handler
;
8455 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
8457 opc_handler_t
**tmp
;
8459 tmp
= g_new(opc_handler_t
*, 0x20);
8460 fill_new_table(tmp
, 0x20);
8461 table
[idx
] = (opc_handler_t
*)((uintptr_t)tmp
| PPC_INDIRECT
);
8466 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
8467 opc_handler_t
*handler
)
8469 if (table
[idx
] != &invalid_handler
)
8471 table
[idx
] = handler
;
8476 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
8477 unsigned char idx
, opc_handler_t
*handler
)
8479 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
8480 printf("*** ERROR: opcode %02x already assigned in main "
8481 "opcode table\n", idx
);
8482 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8483 printf(" Registered handler '%s' - new handler '%s'\n",
8484 ppc_opcodes
[idx
]->oname
, handler
->oname
);
8492 static int register_ind_in_table (opc_handler_t
**table
,
8493 unsigned char idx1
, unsigned char idx2
,
8494 opc_handler_t
*handler
)
8496 if (table
[idx1
] == &invalid_handler
) {
8497 if (create_new_table(table
, idx1
) < 0) {
8498 printf("*** ERROR: unable to create indirect table "
8499 "idx=%02x\n", idx1
);
8503 if (!is_indirect_opcode(table
[idx1
])) {
8504 printf("*** ERROR: idx %02x already assigned to a direct "
8506 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8507 printf(" Registered handler '%s' - new handler '%s'\n",
8508 ind_table(table
[idx1
])[idx2
]->oname
, handler
->oname
);
8513 if (handler
!= NULL
&&
8514 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
8515 printf("*** ERROR: opcode %02x already assigned in "
8516 "opcode table %02x\n", idx2
, idx1
);
8517 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8518 printf(" Registered handler '%s' - new handler '%s'\n",
8519 ind_table(table
[idx1
])[idx2
]->oname
, handler
->oname
);
8527 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
8528 unsigned char idx1
, unsigned char idx2
,
8529 opc_handler_t
*handler
)
8533 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
8538 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
8539 unsigned char idx1
, unsigned char idx2
,
8540 unsigned char idx3
, opc_handler_t
*handler
)
8542 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
8543 printf("*** ERROR: unable to join indirect table idx "
8544 "[%02x-%02x]\n", idx1
, idx2
);
8547 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
8549 printf("*** ERROR: unable to insert opcode "
8550 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
8557 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
8559 if (insn
->opc2
!= 0xFF) {
8560 if (insn
->opc3
!= 0xFF) {
8561 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
8562 insn
->opc3
, &insn
->handler
) < 0)
8565 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
8566 insn
->opc2
, &insn
->handler
) < 0)
8570 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
8577 static int test_opcode_table (opc_handler_t
**table
, int len
)
8581 for (i
= 0, count
= 0; i
< len
; i
++) {
8582 /* Consistency fixup */
8583 if (table
[i
] == NULL
)
8584 table
[i
] = &invalid_handler
;
8585 if (table
[i
] != &invalid_handler
) {
8586 if (is_indirect_opcode(table
[i
])) {
8587 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
8590 table
[i
] = &invalid_handler
;
8603 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
8605 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
8606 printf("*** WARNING: no opcode defined !\n");
8609 /*****************************************************************************/
8610 static void create_ppc_opcodes(PowerPCCPU
*cpu
, Error
**errp
)
8612 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
8613 CPUPPCState
*env
= &cpu
->env
;
8616 fill_new_table(env
->opcodes
, 0x40);
8617 for (opc
= opcodes
; opc
< &opcodes
[ARRAY_SIZE(opcodes
)]; opc
++) {
8618 if (((opc
->handler
.type
& pcc
->insns_flags
) != 0) ||
8619 ((opc
->handler
.type2
& pcc
->insns_flags2
) != 0)) {
8620 if (register_insn(env
->opcodes
, opc
) < 0) {
8621 error_setg(errp
, "ERROR initializing PowerPC instruction "
8622 "0x%02x 0x%02x 0x%02x", opc
->opc1
, opc
->opc2
,
8628 fix_opcode_tables(env
->opcodes
);
8633 #if defined(PPC_DUMP_CPU)
8634 static void dump_ppc_insns (CPUPPCState
*env
)
8636 opc_handler_t
**table
, *handler
;
8638 uint8_t opc1
, opc2
, opc3
;
8640 printf("Instructions set:\n");
8641 /* opc1 is 6 bits long */
8642 for (opc1
= 0x00; opc1
< 0x40; opc1
++) {
8643 table
= env
->opcodes
;
8644 handler
= table
[opc1
];
8645 if (is_indirect_opcode(handler
)) {
8646 /* opc2 is 5 bits long */
8647 for (opc2
= 0; opc2
< 0x20; opc2
++) {
8648 table
= env
->opcodes
;
8649 handler
= env
->opcodes
[opc1
];
8650 table
= ind_table(handler
);
8651 handler
= table
[opc2
];
8652 if (is_indirect_opcode(handler
)) {
8653 table
= ind_table(handler
);
8654 /* opc3 is 5 bits long */
8655 for (opc3
= 0; opc3
< 0x20; opc3
++) {
8656 handler
= table
[opc3
];
8657 if (handler
->handler
!= &gen_invalid
) {
8658 /* Special hack to properly dump SPE insns */
8659 p
= strchr(handler
->oname
, '_');
8661 printf("INSN: %02x %02x %02x (%02d %04d) : "
8663 opc1
, opc2
, opc3
, opc1
,
8668 if ((p
- handler
->oname
) != strlen(q
) ||
8669 memcmp(handler
->oname
, q
, strlen(q
)) != 0) {
8670 /* First instruction */
8671 printf("INSN: %02x %02x %02x (%02d %04d) : "
8673 opc1
, opc2
<< 1, opc3
, opc1
,
8674 (opc3
<< 6) | (opc2
<< 1),
8675 (int)(p
- handler
->oname
),
8678 if (strcmp(p
+ 1, q
) != 0) {
8679 /* Second instruction */
8680 printf("INSN: %02x %02x %02x (%02d %04d) : "
8682 opc1
, (opc2
<< 1) | 1, opc3
, opc1
,
8683 (opc3
<< 6) | (opc2
<< 1) | 1,
8690 if (handler
->handler
!= &gen_invalid
) {
8691 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8692 opc1
, opc2
, opc1
, opc2
, handler
->oname
);
8697 if (handler
->handler
!= &gen_invalid
) {
8698 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8699 opc1
, opc1
, handler
->oname
);
8706 static int gdb_get_float_reg(CPUPPCState
*env
, uint8_t *mem_buf
, int n
)
8709 stfq_p(mem_buf
, env
->fpr
[n
]);
8713 stl_p(mem_buf
, env
->fpscr
);
8719 static int gdb_set_float_reg(CPUPPCState
*env
, uint8_t *mem_buf
, int n
)
8722 env
->fpr
[n
] = ldfq_p(mem_buf
);
8726 helper_store_fpscr(env
, ldl_p(mem_buf
), 0xffffffff);
8732 static int gdb_get_avr_reg(CPUPPCState
*env
, uint8_t *mem_buf
, int n
)
8735 #ifdef HOST_WORDS_BIGENDIAN
8736 stq_p(mem_buf
, env
->avr
[n
].u64
[0]);
8737 stq_p(mem_buf
+8, env
->avr
[n
].u64
[1]);
8739 stq_p(mem_buf
, env
->avr
[n
].u64
[1]);
8740 stq_p(mem_buf
+8, env
->avr
[n
].u64
[0]);
8745 stl_p(mem_buf
, env
->vscr
);
8749 stl_p(mem_buf
, (uint32_t)env
->spr
[SPR_VRSAVE
]);
8755 static int gdb_set_avr_reg(CPUPPCState
*env
, uint8_t *mem_buf
, int n
)
8758 #ifdef HOST_WORDS_BIGENDIAN
8759 env
->avr
[n
].u64
[0] = ldq_p(mem_buf
);
8760 env
->avr
[n
].u64
[1] = ldq_p(mem_buf
+8);
8762 env
->avr
[n
].u64
[1] = ldq_p(mem_buf
);
8763 env
->avr
[n
].u64
[0] = ldq_p(mem_buf
+8);
8768 env
->vscr
= ldl_p(mem_buf
);
8772 env
->spr
[SPR_VRSAVE
] = (target_ulong
)ldl_p(mem_buf
);
8778 static int gdb_get_spe_reg(CPUPPCState
*env
, uint8_t *mem_buf
, int n
)
8781 #if defined(TARGET_PPC64)
8782 stl_p(mem_buf
, env
->gpr
[n
] >> 32);
8784 stl_p(mem_buf
, env
->gprh
[n
]);
8789 stq_p(mem_buf
, env
->spe_acc
);
8793 stl_p(mem_buf
, env
->spe_fscr
);
8799 static int gdb_set_spe_reg(CPUPPCState
*env
, uint8_t *mem_buf
, int n
)
8802 #if defined(TARGET_PPC64)
8803 target_ulong lo
= (uint32_t)env
->gpr
[n
];
8804 target_ulong hi
= (target_ulong
)ldl_p(mem_buf
) << 32;
8805 env
->gpr
[n
] = lo
| hi
;
8807 env
->gprh
[n
] = ldl_p(mem_buf
);
8812 env
->spe_acc
= ldq_p(mem_buf
);
8816 env
->spe_fscr
= ldl_p(mem_buf
);
8822 static int ppc_fixup_cpu(PowerPCCPU
*cpu
)
8824 CPUPPCState
*env
= &cpu
->env
;
8826 /* TCG doesn't (yet) emulate some groups of instructions that
8827 * are implemented on some otherwise supported CPUs (e.g. VSX
8828 * and decimal floating point instructions on POWER7). We
8829 * remove unsupported instruction groups from the cpu state's
8830 * instruction masks and hope the guest can cope. For at
8831 * least the pseries machine, the unavailability of these
8832 * instructions can be advertised to the guest via the device
8834 if ((env
->insns_flags
& ~PPC_TCG_INSNS
)
8835 || (env
->insns_flags2
& ~PPC_TCG_INSNS2
)) {
8836 fprintf(stderr
, "Warning: Disabling some instructions which are not "
8837 "emulated by TCG (0x%" PRIx64
", 0x%" PRIx64
")\n",
8838 env
->insns_flags
& ~PPC_TCG_INSNS
,
8839 env
->insns_flags2
& ~PPC_TCG_INSNS2
);
8841 env
->insns_flags
&= PPC_TCG_INSNS
;
8842 env
->insns_flags2
&= PPC_TCG_INSNS2
;
8846 static inline bool ppc_cpu_is_valid(PowerPCCPUClass
*pcc
)
8848 #ifdef TARGET_PPCEMB
8849 return pcc
->mmu_model
== POWERPC_MMU_BOOKE
||
8850 pcc
->mmu_model
== POWERPC_MMU_SOFT_4xx
||
8851 pcc
->mmu_model
== POWERPC_MMU_SOFT_4xx_Z
;
8857 static void ppc_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
8859 CPUState
*cs
= CPU(dev
);
8860 PowerPCCPU
*cpu
= POWERPC_CPU(dev
);
8861 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
8862 Error
*local_err
= NULL
;
8863 #if !defined(CONFIG_USER_ONLY)
8864 int max_smt
= kvm_enabled() ? kvmppc_smt_threads() : 1;
8867 #if !defined(CONFIG_USER_ONLY)
8868 if (smp_threads
> max_smt
) {
8869 error_setg(errp
, "Cannot support more than %d threads on PPC with %s",
8870 max_smt
, kvm_enabled() ? "KVM" : "TCG");
8873 if (!is_power_of_2(smp_threads
)) {
8874 error_setg(errp
, "Cannot support %d threads on PPC with %s, "
8875 "threads count must be a power of 2.",
8876 smp_threads
, kvm_enabled() ? "KVM" : "TCG");
8880 cpu
->cpu_dt_id
= (cs
->cpu_index
/ smp_threads
) * max_smt
8881 + (cs
->cpu_index
% smp_threads
);
8884 if (tcg_enabled()) {
8885 if (ppc_fixup_cpu(cpu
) != 0) {
8886 error_setg(errp
, "Unable to emulate selected CPU with TCG");
8891 #if defined(TARGET_PPCEMB)
8892 if (!ppc_cpu_is_valid(pcc
)) {
8893 error_setg(errp
, "CPU does not possess a BookE or 4xx MMU. "
8894 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
8895 "or choose another CPU model.");
8900 create_ppc_opcodes(cpu
, &local_err
);
8901 if (local_err
!= NULL
) {
8902 error_propagate(errp
, local_err
);
8907 if (pcc
->insns_flags
& PPC_FLOAT
) {
8908 gdb_register_coprocessor(cs
, gdb_get_float_reg
, gdb_set_float_reg
,
8909 33, "power-fpu.xml", 0);
8911 if (pcc
->insns_flags
& PPC_ALTIVEC
) {
8912 gdb_register_coprocessor(cs
, gdb_get_avr_reg
, gdb_set_avr_reg
,
8913 34, "power-altivec.xml", 0);
8915 if (pcc
->insns_flags
& PPC_SPE
) {
8916 gdb_register_coprocessor(cs
, gdb_get_spe_reg
, gdb_set_spe_reg
,
8917 34, "power-spe.xml", 0);
8922 pcc
->parent_realize(dev
, errp
);
8924 #if defined(PPC_DUMP_CPU)
8926 CPUPPCState
*env
= &cpu
->env
;
8927 const char *mmu_model
, *excp_model
, *bus_model
;
8928 switch (env
->mmu_model
) {
8929 case POWERPC_MMU_32B
:
8930 mmu_model
= "PowerPC 32";
8932 case POWERPC_MMU_SOFT_6xx
:
8933 mmu_model
= "PowerPC 6xx/7xx with software driven TLBs";
8935 case POWERPC_MMU_SOFT_74xx
:
8936 mmu_model
= "PowerPC 74xx with software driven TLBs";
8938 case POWERPC_MMU_SOFT_4xx
:
8939 mmu_model
= "PowerPC 4xx with software driven TLBs";
8941 case POWERPC_MMU_SOFT_4xx_Z
:
8942 mmu_model
= "PowerPC 4xx with software driven TLBs "
8943 "and zones protections";
8945 case POWERPC_MMU_REAL
:
8946 mmu_model
= "PowerPC real mode only";
8948 case POWERPC_MMU_MPC8xx
:
8949 mmu_model
= "PowerPC MPC8xx";
8951 case POWERPC_MMU_BOOKE
:
8952 mmu_model
= "PowerPC BookE";
8954 case POWERPC_MMU_BOOKE206
:
8955 mmu_model
= "PowerPC BookE 2.06";
8957 case POWERPC_MMU_601
:
8958 mmu_model
= "PowerPC 601";
8960 #if defined (TARGET_PPC64)
8961 case POWERPC_MMU_64B
:
8962 mmu_model
= "PowerPC 64";
8966 mmu_model
= "Unknown or invalid";
8969 switch (env
->excp_model
) {
8970 case POWERPC_EXCP_STD
:
8971 excp_model
= "PowerPC";
8973 case POWERPC_EXCP_40x
:
8974 excp_model
= "PowerPC 40x";
8976 case POWERPC_EXCP_601
:
8977 excp_model
= "PowerPC 601";
8979 case POWERPC_EXCP_602
:
8980 excp_model
= "PowerPC 602";
8982 case POWERPC_EXCP_603
:
8983 excp_model
= "PowerPC 603";
8985 case POWERPC_EXCP_603E
:
8986 excp_model
= "PowerPC 603e";
8988 case POWERPC_EXCP_604
:
8989 excp_model
= "PowerPC 604";
8991 case POWERPC_EXCP_7x0
:
8992 excp_model
= "PowerPC 740/750";
8994 case POWERPC_EXCP_7x5
:
8995 excp_model
= "PowerPC 745/755";
8997 case POWERPC_EXCP_74xx
:
8998 excp_model
= "PowerPC 74xx";
9000 case POWERPC_EXCP_BOOKE
:
9001 excp_model
= "PowerPC BookE";
9003 #if defined (TARGET_PPC64)
9004 case POWERPC_EXCP_970
:
9005 excp_model
= "PowerPC 970";
9009 excp_model
= "Unknown or invalid";
9012 switch (env
->bus_model
) {
9013 case PPC_FLAGS_INPUT_6xx
:
9014 bus_model
= "PowerPC 6xx";
9016 case PPC_FLAGS_INPUT_BookE
:
9017 bus_model
= "PowerPC BookE";
9019 case PPC_FLAGS_INPUT_405
:
9020 bus_model
= "PowerPC 405";
9022 case PPC_FLAGS_INPUT_401
:
9023 bus_model
= "PowerPC 401/403";
9025 case PPC_FLAGS_INPUT_RCPU
:
9026 bus_model
= "RCPU / MPC8xx";
9028 #if defined (TARGET_PPC64)
9029 case PPC_FLAGS_INPUT_970
:
9030 bus_model
= "PowerPC 970";
9034 bus_model
= "Unknown or invalid";
9037 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64
"\n"
9038 " MMU model : %s\n",
9039 object_class_get_name(OBJECT_CLASS(pcc
)),
9040 pcc
->pvr
, pcc
->msr_mask
, mmu_model
);
9041 #if !defined(CONFIG_USER_ONLY)
9042 if (env
->tlb
.tlb6
) {
9043 printf(" %d %s TLB in %d ways\n",
9044 env
->nb_tlb
, env
->id_tlbs
? "splitted" : "merged",
9048 printf(" Exceptions model : %s\n"
9049 " Bus model : %s\n",
9050 excp_model
, bus_model
);
9051 printf(" MSR features :\n");
9052 if (env
->flags
& POWERPC_FLAG_SPE
)
9053 printf(" signal processing engine enable"
9055 else if (env
->flags
& POWERPC_FLAG_VRE
)
9056 printf(" vector processor enable\n");
9057 if (env
->flags
& POWERPC_FLAG_TGPR
)
9058 printf(" temporary GPRs\n");
9059 else if (env
->flags
& POWERPC_FLAG_CE
)
9060 printf(" critical input enable\n");
9061 if (env
->flags
& POWERPC_FLAG_SE
)
9062 printf(" single-step trace mode\n");
9063 else if (env
->flags
& POWERPC_FLAG_DWE
)
9064 printf(" debug wait enable\n");
9065 else if (env
->flags
& POWERPC_FLAG_UBLE
)
9066 printf(" user BTB lock enable\n");
9067 if (env
->flags
& POWERPC_FLAG_BE
)
9068 printf(" branch-step trace mode\n");
9069 else if (env
->flags
& POWERPC_FLAG_DE
)
9070 printf(" debug interrupt enable\n");
9071 if (env
->flags
& POWERPC_FLAG_PX
)
9072 printf(" inclusive protection\n");
9073 else if (env
->flags
& POWERPC_FLAG_PMM
)
9074 printf(" performance monitor mark\n");
9075 if (env
->flags
== POWERPC_FLAG_NONE
)
9077 printf(" Time-base/decrementer clock source: %s\n",
9078 env
->flags
& POWERPC_FLAG_RTC_CLK
? "RTC clock" : "bus clock");
9079 dump_ppc_insns(env
);
9086 static void ppc_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
9088 PowerPCCPU
*cpu
= POWERPC_CPU(dev
);
9089 CPUPPCState
*env
= &cpu
->env
;
9092 for (i
= 0; i
< PPC_CPU_OPCODES_LEN
; i
++) {
9093 if (env
->opcodes
[i
] != &invalid_handler
) {
9094 g_free(env
->opcodes
[i
]);
9099 int ppc_get_compat_smt_threads(PowerPCCPU
*cpu
)
9101 int ret
= MIN(smp_threads
, kvmppc_smt_threads());
9103 switch (cpu
->cpu_version
) {
9104 case CPU_POWERPC_LOGICAL_2_05
:
9107 case CPU_POWERPC_LOGICAL_2_06
:
9110 case CPU_POWERPC_LOGICAL_2_07
:
9118 int ppc_set_compat(PowerPCCPU
*cpu
, uint32_t cpu_version
)
9121 CPUPPCState
*env
= &cpu
->env
;
9123 cpu
->cpu_version
= cpu_version
;
9125 switch (cpu_version
) {
9126 case CPU_POWERPC_LOGICAL_2_05
:
9127 env
->spr
[SPR_PCR
] = PCR_COMPAT_2_05
;
9129 case CPU_POWERPC_LOGICAL_2_06
:
9130 env
->spr
[SPR_PCR
] = PCR_COMPAT_2_06
;
9132 case CPU_POWERPC_LOGICAL_2_06_PLUS
:
9133 env
->spr
[SPR_PCR
] = PCR_COMPAT_2_06
;
9136 env
->spr
[SPR_PCR
] = 0;
9140 if (kvm_enabled() && kvmppc_set_compat(cpu
, cpu
->cpu_version
) < 0) {
9141 error_report("Unable to set compatibility mode in KVM");
9148 static gint
ppc_cpu_compare_class_pvr(gconstpointer a
, gconstpointer b
)
9150 ObjectClass
*oc
= (ObjectClass
*)a
;
9151 uint32_t pvr
= *(uint32_t *)b
;
9152 PowerPCCPUClass
*pcc
= (PowerPCCPUClass
*)a
;
9154 /* -cpu host does a PVR lookup during construction */
9155 if (unlikely(strcmp(object_class_get_name(oc
),
9156 TYPE_HOST_POWERPC_CPU
) == 0)) {
9160 if (!ppc_cpu_is_valid(pcc
)) {
9164 return pcc
->pvr
== pvr
? 0 : -1;
9167 PowerPCCPUClass
*ppc_cpu_class_by_pvr(uint32_t pvr
)
9169 GSList
*list
, *item
;
9170 PowerPCCPUClass
*pcc
= NULL
;
9172 list
= object_class_get_list(TYPE_POWERPC_CPU
, false);
9173 item
= g_slist_find_custom(list
, &pvr
, ppc_cpu_compare_class_pvr
);
9175 pcc
= POWERPC_CPU_CLASS(item
->data
);
9182 static gint
ppc_cpu_compare_class_pvr_mask(gconstpointer a
, gconstpointer b
)
9184 ObjectClass
*oc
= (ObjectClass
*)a
;
9185 uint32_t pvr
= *(uint32_t *)b
;
9186 PowerPCCPUClass
*pcc
= (PowerPCCPUClass
*)a
;
9188 /* -cpu host does a PVR lookup during construction */
9189 if (unlikely(strcmp(object_class_get_name(oc
),
9190 TYPE_HOST_POWERPC_CPU
) == 0)) {
9194 if (!ppc_cpu_is_valid(pcc
)) {
9198 if (pcc
->pvr_match(pcc
, pvr
)) {
9205 PowerPCCPUClass
*ppc_cpu_class_by_pvr_mask(uint32_t pvr
)
9207 GSList
*list
, *item
;
9208 PowerPCCPUClass
*pcc
= NULL
;
9210 list
= object_class_get_list(TYPE_POWERPC_CPU
, true);
9211 item
= g_slist_find_custom(list
, &pvr
, ppc_cpu_compare_class_pvr_mask
);
9213 pcc
= POWERPC_CPU_CLASS(item
->data
);
9220 static gint
ppc_cpu_compare_class_name(gconstpointer a
, gconstpointer b
)
9222 ObjectClass
*oc
= (ObjectClass
*)a
;
9223 const char *name
= b
;
9224 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
9226 if (strncasecmp(name
, object_class_get_name(oc
), strlen(name
)) == 0 &&
9227 ppc_cpu_is_valid(pcc
) &&
9228 strcmp(object_class_get_name(oc
) + strlen(name
),
9229 "-" TYPE_POWERPC_CPU
) == 0) {
9237 static ObjectClass
*ppc_cpu_class_by_name(const char *name
);
9239 static ObjectClass
*ppc_cpu_class_by_alias(PowerPCCPUAlias
*alias
)
9241 ObjectClass
*invalid_class
= (void*)ppc_cpu_class_by_alias
;
9243 /* Cache target class lookups in the alias table */
9245 alias
->oc
= ppc_cpu_class_by_name(alias
->model
);
9247 /* Fast check for non-existing aliases */
9248 alias
->oc
= invalid_class
;
9252 if (alias
->oc
== invalid_class
) {
9259 static ObjectClass
*ppc_cpu_class_by_name(const char *name
)
9261 GSList
*list
, *item
;
9262 ObjectClass
*ret
= NULL
;
9266 /* Check if the given name is a PVR */
9268 if (len
== 10 && name
[0] == '0' && name
[1] == 'x') {
9271 } else if (len
== 8) {
9274 for (i
= 0; i
< 8; i
++) {
9275 if (!qemu_isxdigit(*p
++))
9279 ret
= OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name
, NULL
, 16)));
9284 list
= object_class_get_list(TYPE_POWERPC_CPU
, false);
9285 item
= g_slist_find_custom(list
, name
, ppc_cpu_compare_class_name
);
9287 ret
= OBJECT_CLASS(item
->data
);
9295 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
9296 if (strcmp(ppc_cpu_aliases
[i
].alias
, name
) == 0) {
9297 return ppc_cpu_class_by_alias(&ppc_cpu_aliases
[i
]);
9304 PowerPCCPU
*cpu_ppc_init(const char *cpu_model
)
9306 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU
, cpu_model
));
9309 /* Sort by PVR, ordering special case "host" last. */
9310 static gint
ppc_cpu_list_compare(gconstpointer a
, gconstpointer b
)
9312 ObjectClass
*oc_a
= (ObjectClass
*)a
;
9313 ObjectClass
*oc_b
= (ObjectClass
*)b
;
9314 PowerPCCPUClass
*pcc_a
= POWERPC_CPU_CLASS(oc_a
);
9315 PowerPCCPUClass
*pcc_b
= POWERPC_CPU_CLASS(oc_b
);
9316 const char *name_a
= object_class_get_name(oc_a
);
9317 const char *name_b
= object_class_get_name(oc_b
);
9319 if (strcmp(name_a
, TYPE_HOST_POWERPC_CPU
) == 0) {
9321 } else if (strcmp(name_b
, TYPE_HOST_POWERPC_CPU
) == 0) {
9324 /* Avoid an integer overflow during subtraction */
9325 if (pcc_a
->pvr
< pcc_b
->pvr
) {
9327 } else if (pcc_a
->pvr
> pcc_b
->pvr
) {
9335 static void ppc_cpu_list_entry(gpointer data
, gpointer user_data
)
9337 ObjectClass
*oc
= data
;
9338 CPUListState
*s
= user_data
;
9339 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
9340 const char *typename
= object_class_get_name(oc
);
9344 if (!ppc_cpu_is_valid(pcc
)) {
9347 if (unlikely(strcmp(typename
, TYPE_HOST_POWERPC_CPU
) == 0)) {
9351 name
= g_strndup(typename
,
9352 strlen(typename
) - strlen("-" TYPE_POWERPC_CPU
));
9353 (*s
->cpu_fprintf
)(s
->file
, "PowerPC %-16s PVR %08x\n",
9355 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
9356 PowerPCCPUAlias
*alias
= &ppc_cpu_aliases
[i
];
9357 ObjectClass
*alias_oc
= ppc_cpu_class_by_alias(alias
);
9359 if (alias_oc
!= oc
) {
9362 (*s
->cpu_fprintf
)(s
->file
, "PowerPC %-16s (alias for %s)\n",
9363 alias
->alias
, name
);
9368 void ppc_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
9372 .cpu_fprintf
= cpu_fprintf
,
9376 list
= object_class_get_list(TYPE_POWERPC_CPU
, false);
9377 list
= g_slist_sort(list
, ppc_cpu_list_compare
);
9378 g_slist_foreach(list
, ppc_cpu_list_entry
, &s
);
9382 cpu_fprintf(f
, "\n");
9383 cpu_fprintf(f
, "PowerPC %-16s\n", "host");
9387 static void ppc_cpu_defs_entry(gpointer data
, gpointer user_data
)
9389 ObjectClass
*oc
= data
;
9390 CpuDefinitionInfoList
**first
= user_data
;
9391 const char *typename
;
9392 CpuDefinitionInfoList
*entry
;
9393 CpuDefinitionInfo
*info
;
9394 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
9396 if (!ppc_cpu_is_valid(pcc
)) {
9400 typename
= object_class_get_name(oc
);
9401 info
= g_malloc0(sizeof(*info
));
9402 info
->name
= g_strndup(typename
,
9403 strlen(typename
) - strlen("-" TYPE_POWERPC_CPU
));
9405 entry
= g_malloc0(sizeof(*entry
));
9406 entry
->value
= info
;
9407 entry
->next
= *first
;
9411 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
9413 CpuDefinitionInfoList
*cpu_list
= NULL
;
9417 list
= object_class_get_list(TYPE_POWERPC_CPU
, false);
9418 g_slist_foreach(list
, ppc_cpu_defs_entry
, &cpu_list
);
9421 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
9422 PowerPCCPUAlias
*alias
= &ppc_cpu_aliases
[i
];
9424 CpuDefinitionInfoList
*entry
;
9425 CpuDefinitionInfo
*info
;
9427 oc
= ppc_cpu_class_by_alias(alias
);
9432 info
= g_malloc0(sizeof(*info
));
9433 info
->name
= g_strdup(alias
->alias
);
9435 entry
= g_malloc0(sizeof(*entry
));
9436 entry
->value
= info
;
9437 entry
->next
= cpu_list
;
9444 static void ppc_cpu_set_pc(CPUState
*cs
, vaddr value
)
9446 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
9448 cpu
->env
.nip
= value
;
9451 static bool ppc_cpu_has_work(CPUState
*cs
)
9453 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
9454 CPUPPCState
*env
= &cpu
->env
;
9456 return msr_ee
&& (cs
->interrupt_request
& CPU_INTERRUPT_HARD
);
9459 static void ppc_cpu_exec_enter(CPUState
*cs
)
9461 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
9462 CPUPPCState
*env
= &cpu
->env
;
9464 env
->reserve_addr
= -1;
9467 /* CPUClass::reset() */
9468 static void ppc_cpu_reset(CPUState
*s
)
9470 PowerPCCPU
*cpu
= POWERPC_CPU(s
);
9471 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
9472 CPUPPCState
*env
= &cpu
->env
;
9476 pcc
->parent_reset(s
);
9478 msr
= (target_ulong
)0;
9480 /* XXX: find a suitable condition to enable the hypervisor mode */
9481 msr
|= (target_ulong
)MSR_HVB
;
9483 msr
|= (target_ulong
)0 << MSR_AP
; /* TO BE CHECKED */
9484 msr
|= (target_ulong
)0 << MSR_SA
; /* TO BE CHECKED */
9485 msr
|= (target_ulong
)1 << MSR_EP
;
9486 #if defined(DO_SINGLE_STEP) && 0
9487 /* Single step trace mode */
9488 msr
|= (target_ulong
)1 << MSR_SE
;
9489 msr
|= (target_ulong
)1 << MSR_BE
;
9491 #if defined(CONFIG_USER_ONLY)
9492 msr
|= (target_ulong
)1 << MSR_FP
; /* Allow floating point usage */
9493 msr
|= (target_ulong
)1 << MSR_VR
; /* Allow altivec usage */
9494 msr
|= (target_ulong
)1 << MSR_VSX
; /* Allow VSX usage */
9495 msr
|= (target_ulong
)1 << MSR_SPE
; /* Allow SPE usage */
9496 msr
|= (target_ulong
)1 << MSR_PR
;
9497 #if defined(TARGET_PPC64)
9498 msr
|= (target_ulong
)1 << MSR_TM
; /* Transactional memory */
9500 #if !defined(TARGET_WORDS_BIGENDIAN)
9501 msr
|= (target_ulong
)1 << MSR_LE
; /* Little-endian user mode */
9502 if (!((env
->msr_mask
>> MSR_LE
) & 1)) {
9503 fprintf(stderr
, "Selected CPU does not support little-endian.\n");
9509 #if defined(TARGET_PPC64)
9510 if (env
->mmu_model
& POWERPC_MMU_64
) {
9511 env
->msr
|= (1ULL << MSR_SF
);
9515 hreg_store_msr(env
, msr
, 1);
9517 #if !defined(CONFIG_USER_ONLY)
9518 env
->nip
= env
->hreset_vector
| env
->excp_prefix
;
9519 if (env
->mmu_model
!= POWERPC_MMU_REAL
) {
9520 ppc_tlb_invalidate_all(env
);
9524 hreg_compute_hflags(env
);
9525 env
->reserve_addr
= (target_ulong
)-1ULL;
9526 /* Be sure no exception or interrupt is pending */
9527 env
->pending_interrupts
= 0;
9528 s
->exception_index
= POWERPC_EXCP_NONE
;
9529 env
->error_code
= 0;
9531 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9533 env
->slb_shadow_addr
= 0;
9534 env
->slb_shadow_size
= 0;
9537 #endif /* TARGET_PPC64 */
9539 for (i
= 0; i
< ARRAY_SIZE(env
->spr_cb
); i
++) {
9540 ppc_spr_t
*spr
= &env
->spr_cb
[i
];
9545 env
->spr
[i
] = spr
->default_value
;
9548 /* Flush all TLBs */
9552 #ifndef CONFIG_USER_ONLY
9553 static bool ppc_cpu_is_big_endian(CPUState
*cs
)
9555 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
9556 CPUPPCState
*env
= &cpu
->env
;
9558 cpu_synchronize_state(cs
);
9564 static void ppc_cpu_initfn(Object
*obj
)
9566 CPUState
*cs
= CPU(obj
);
9567 PowerPCCPU
*cpu
= POWERPC_CPU(obj
);
9568 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
9569 CPUPPCState
*env
= &cpu
->env
;
9573 cpu
->cpu_dt_id
= cs
->cpu_index
;
9575 env
->msr_mask
= pcc
->msr_mask
;
9576 env
->mmu_model
= pcc
->mmu_model
;
9577 env
->excp_model
= pcc
->excp_model
;
9578 env
->bus_model
= pcc
->bus_model
;
9579 env
->insns_flags
= pcc
->insns_flags
;
9580 env
->insns_flags2
= pcc
->insns_flags2
;
9581 env
->flags
= pcc
->flags
;
9582 env
->bfd_mach
= pcc
->bfd_mach
;
9583 env
->check_pow
= pcc
->check_pow
;
9585 #if defined(TARGET_PPC64)
9587 env
->sps
= *pcc
->sps
;
9588 } else if (env
->mmu_model
& POWERPC_MMU_64
) {
9589 /* Use default sets of page sizes */
9590 static const struct ppc_segment_page_sizes defsps
= {
9592 { .page_shift
= 12, /* 4K */
9594 .enc
= { { .page_shift
= 12, .pte_enc
= 0 } }
9596 { .page_shift
= 24, /* 16M */
9598 .enc
= { { .page_shift
= 24, .pte_enc
= 0 } }
9604 #endif /* defined(TARGET_PPC64) */
9606 if (tcg_enabled()) {
9607 ppc_translate_init();
9611 static bool ppc_pvr_match_default(PowerPCCPUClass
*pcc
, uint32_t pvr
)
9613 return pcc
->pvr
== pvr
;
9616 static void ppc_cpu_class_init(ObjectClass
*oc
, void *data
)
9618 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
9619 CPUClass
*cc
= CPU_CLASS(oc
);
9620 DeviceClass
*dc
= DEVICE_CLASS(oc
);
9622 pcc
->parent_realize
= dc
->realize
;
9623 pcc
->pvr_match
= ppc_pvr_match_default
;
9624 pcc
->interrupts_big_endian
= ppc_cpu_interrupts_big_endian_always
;
9625 dc
->realize
= ppc_cpu_realizefn
;
9626 dc
->unrealize
= ppc_cpu_unrealizefn
;
9628 pcc
->parent_reset
= cc
->reset
;
9629 cc
->reset
= ppc_cpu_reset
;
9631 cc
->class_by_name
= ppc_cpu_class_by_name
;
9632 cc
->has_work
= ppc_cpu_has_work
;
9633 cc
->do_interrupt
= ppc_cpu_do_interrupt
;
9634 cc
->cpu_exec_interrupt
= ppc_cpu_exec_interrupt
;
9635 cc
->dump_state
= ppc_cpu_dump_state
;
9636 cc
->dump_statistics
= ppc_cpu_dump_statistics
;
9637 cc
->set_pc
= ppc_cpu_set_pc
;
9638 cc
->gdb_read_register
= ppc_cpu_gdb_read_register
;
9639 cc
->gdb_write_register
= ppc_cpu_gdb_write_register
;
9640 #ifdef CONFIG_USER_ONLY
9641 cc
->handle_mmu_fault
= ppc_cpu_handle_mmu_fault
;
9643 cc
->get_phys_page_debug
= ppc_cpu_get_phys_page_debug
;
9644 cc
->vmsd
= &vmstate_ppc_cpu
;
9645 #if defined(TARGET_PPC64)
9646 cc
->write_elf64_note
= ppc64_cpu_write_elf64_note
;
9647 cc
->write_elf64_qemunote
= ppc64_cpu_write_elf64_qemunote
;
9650 cc
->cpu_exec_enter
= ppc_cpu_exec_enter
;
9652 cc
->gdb_num_core_regs
= 71;
9654 #ifdef USE_APPLE_GDB
9655 cc
->gdb_read_register
= ppc_cpu_gdb_read_register_apple
;
9656 cc
->gdb_write_register
= ppc_cpu_gdb_write_register_apple
;
9657 cc
->gdb_num_core_regs
= 71 + 32;
9660 #if defined(TARGET_PPC64)
9661 cc
->gdb_core_xml_file
= "power64-core.xml";
9663 cc
->gdb_core_xml_file
= "power-core.xml";
9665 #ifndef CONFIG_USER_ONLY
9666 cc
->virtio_is_big_endian
= ppc_cpu_is_big_endian
;
9669 dc
->fw_name
= "PowerPC,UNKNOWN";
9672 static const TypeInfo ppc_cpu_type_info
= {
9673 .name
= TYPE_POWERPC_CPU
,
9675 .instance_size
= sizeof(PowerPCCPU
),
9676 .instance_init
= ppc_cpu_initfn
,
9678 .class_size
= sizeof(PowerPCCPUClass
),
9679 .class_init
= ppc_cpu_class_init
,
9682 static void ppc_cpu_register_types(void)
9684 type_register_static(&ppc_cpu_type_info
);
9687 type_init(ppc_cpu_register_types
)