hw/pci-host/gpex.c

   1 /*
   2  * QEMU Generic PCI Express Bridge Emulation
   3  *
   4  * Copyright (C) 2015 Alexander Graf <agraf@suse.de>
   5  *
   6  * Code loosely based on q35.c.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  * Check out these documents for more information on the device:
  27  *
  28  * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt
  29  * http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
  30  */
  31
  32 #include "qemu/osdep.h"
  33 #include "qapi/error.h"
  34 #include "hw/irq.h"
  35 #include "hw/pci-host/gpex.h"
  36 #include "hw/qdev-properties.h"
  37 #include "migration/vmstate.h"
  38 #include "qemu/module.h"
  39
  40 /****************************************************************************
  41  * GPEX host
  42  */
  43
  44 static void gpex_set_irq(void *opaque, int irq_num, int level)
  45 {
  46     GPEXHost *s = opaque;
  47
  48     qemu_set_irq(s->irq[irq_num], level);
  49 }
  50
  51 int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
  52 {
  53     if (index >= GPEX_NUM_IRQS) {
  54         return -EINVAL;
  55     }
  56
  57     s->irq_num[index] = gsi;
  58     return 0;
  59 }
  60
  61 static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
  62 {
  63     PCIINTxRoute route;
  64     GPEXHost *s = opaque;
  65     int gsi = s->irq_num[pin];
  66
  67     route.irq = gsi;
  68     if (gsi < 0) {
  69         route.mode = PCI_INTX_DISABLED;
  70     } else {
  71         route.mode = PCI_INTX_ENABLED;
  72     }
  73
  74     return route;
  75 }
  76
  77 static void gpex_host_realize(DeviceState *dev, Error **errp)
  78 {
  79     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
  80     GPEXHost *s = GPEX_HOST(dev);
  81     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  82     PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
  83     int i;
  84
  85     pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
  86     sysbus_init_mmio(sbd, &pex->mmio);
  87
  88     /*
  89      * Note that the MemoryRegions io_mmio and io_ioport that we pass
  90      * to pci_register_root_bus() are not the same as the
  91      * MemoryRegions io_mmio_window and io_ioport_window that we
  92      * expose as SysBus MRs. The difference is in the behaviour of
  93      * accesses to addresses where no PCI device has been mapped.
  94      *
  95      * io_mmio and io_ioport are the underlying PCI view of the PCI
  96      * address space, and when a PCI device does a bus master access
  97      * to a bad address this is reported back to it as a transaction
  98      * failure.
  99      *
 100      * io_mmio_window and io_ioport_window implement "unmapped
 101      * addresses read as -1 and ignore writes"; this is traditional
 102      * x86 PC behaviour, which is not mandated by the PCI spec proper
 103      * but expected by much PCI-using guest software, including Linux.
 104      *
 105      * In the interests of not being unnecessarily surprising, we
 106      * implement it in the gpex PCI host controller, by providing the
 107      * _window MRs, which are containers with io ops that implement
 108      * the 'background' behaviour and which hold the real PCI MRs as
 109      * subregions.
 110      */
 111     memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
 112     memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
 113
 114     if (s->allow_unmapped_accesses) {
 115         memory_region_init_io(&s->io_mmio_window, OBJECT(s),
 116                               &unassigned_io_ops, OBJECT(s),
 117                               "gpex_mmio_window", UINT64_MAX);
 118         memory_region_init_io(&s->io_ioport_window, OBJECT(s),
 119                               &unassigned_io_ops, OBJECT(s),
 120                               "gpex_ioport_window", 64 * 1024);
 121
 122         memory_region_add_subregion(&s->io_mmio_window, 0, &s->io_mmio);
 123         memory_region_add_subregion(&s->io_ioport_window, 0, &s->io_ioport);
 124         sysbus_init_mmio(sbd, &s->io_mmio_window);
 125         sysbus_init_mmio(sbd, &s->io_ioport_window);
 126     } else {
 127         sysbus_init_mmio(sbd, &s->io_mmio);
 128         sysbus_init_mmio(sbd, &s->io_ioport);
 129     }
 130
 131     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 132         sysbus_init_irq(sbd, &s->irq[i]);
 133         s->irq_num[i] = -1;
 134     }
 135
 136     pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq,
 137                                      pci_swizzle_map_irq_fn, s, &s->io_mmio,
 138                                      &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
 139
 140     pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
 141     qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal);
 142 }
 143
 144 static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
 145                                           PCIBus *rootbus)
 146 {
 147     return "0000:00";
 148 }
 149
 150 static Property gpex_host_properties[] = {
 151     /*
 152      * Permit CPU accesses to unmapped areas of the PIO and MMIO windows
 153      * (discarding writes and returning -1 for reads) rather than aborting.
 154      */
 155     DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
 156                      allow_unmapped_accesses, true),
 157     DEFINE_PROP_END_OF_LIST(),
 158 };
 159
 160 static void gpex_host_class_init(ObjectClass *klass, void *data)
 161 {
 162     DeviceClass *dc = DEVICE_CLASS(klass);
 163     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 164
 165     hc->root_bus_path = gpex_host_root_bus_path;
 166     dc->realize = gpex_host_realize;
 167     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 168     dc->fw_name = "pci";
 169     device_class_set_props(dc, gpex_host_properties);
 170 }
 171
 172 static void gpex_host_initfn(Object *obj)
 173 {
 174     GPEXHost *s = GPEX_HOST(obj);
 175     GPEXRootState *root = &s->gpex_root;
 176
 177     object_initialize_child(obj, "gpex_root", root, TYPE_GPEX_ROOT_DEVICE);
 178     qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
 179     qdev_prop_set_bit(DEVICE(root), "multifunction", false);
 180 }
 181
 182 static const TypeInfo gpex_host_info = {
 183     .name       = TYPE_GPEX_HOST,
 184     .parent     = TYPE_PCIE_HOST_BRIDGE,
 185     .instance_size = sizeof(GPEXHost),
 186     .instance_init = gpex_host_initfn,
 187     .class_init = gpex_host_class_init,
 188 };
 189
 190 /****************************************************************************
 191  * GPEX Root D0:F0
 192  */
 193
 194 static const VMStateDescription vmstate_gpex_root = {
 195     .name = "gpex_root",
 196     .version_id = 1,
 197     .minimum_version_id = 1,
 198     .fields = (VMStateField[]) {
 199         VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState),
 200         VMSTATE_END_OF_LIST()
 201     }
 202 };
 203
 204 static void gpex_root_class_init(ObjectClass *klass, void *data)
 205 {
 206     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 207     DeviceClass *dc = DEVICE_CLASS(klass);
 208
 209     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 210     dc->desc = "QEMU generic PCIe host bridge";
 211     dc->vmsd = &vmstate_gpex_root;
 212     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 213     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST;
 214     k->revision = 0;
 215     k->class_id = PCI_CLASS_BRIDGE_HOST;
 216     /*
 217      * PCI-facing part of the host bridge, not usable without the
 218      * host-facing part, which can't be device_add'ed, yet.
 219      */
 220     dc->user_creatable = false;
 221 }
 222
 223 static const TypeInfo gpex_root_info = {
 224     .name = TYPE_GPEX_ROOT_DEVICE,
 225     .parent = TYPE_PCI_DEVICE,
 226     .instance_size = sizeof(GPEXRootState),
 227     .class_init = gpex_root_class_init,
 228     .interfaces = (InterfaceInfo[]) {
 229         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 230         { },
 231     },
 232 };
 233
 234 static void gpex_register(void)
 235 {
 236     type_register_static(&gpex_root_info);
 237     type_register_static(&gpex_host_info);
 238 }
 239
 240 type_init(gpex_register)