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hw/arm/virt: eliminate struct VirtGuestInfoState
[qemu/rayw.git] / disas / arm.c
blob93c650344cec2f6a8220a41c4293bbc769cd7f93
1 /* Instruction printing code for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 2007, Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modification by James G. Smith (jsmith@cygnus.co.uk)
6
7 This file is part of libopcodes.
8
9 This program is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2 of the License, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, see <http://www.gnu.org/licenses/>. */
21
22 /* Start of qemu specific additions. Mostly this is stub definitions
23 for things we don't care about. */
24
25 #include "qemu/osdep.h"
26 #include "disas/bfd.h"
27
28 #define ARM_EXT_V1 0
29 #define ARM_EXT_V2 0
30 #define ARM_EXT_V2S 0
31 #define ARM_EXT_V3 0
32 #define ARM_EXT_V3M 0
33 #define ARM_EXT_V4 0
34 #define ARM_EXT_V4T 0
35 #define ARM_EXT_V5 0
36 #define ARM_EXT_V5T 0
37 #define ARM_EXT_V5ExP 0
38 #define ARM_EXT_V5E 0
39 #define ARM_EXT_V5J 0
40 #define ARM_EXT_V6 0
41 #define ARM_EXT_V6K 0
42 #define ARM_EXT_V6Z 0
43 #define ARM_EXT_V6T2 0
44 #define ARM_EXT_V7 0
45 #define ARM_EXT_DIV 0
46
47 /* Co-processor space extensions. */
48 #define ARM_CEXT_XSCALE 0
49 #define ARM_CEXT_MAVERICK 0
50 #define ARM_CEXT_IWMMXT 0
51
52 #define FPU_FPA_EXT_V1 0
53 #define FPU_FPA_EXT_V2 0
54 #define FPU_VFP_EXT_NONE 0
55 #define FPU_VFP_EXT_V1xD 0
56 #define FPU_VFP_EXT_V1 0
57 #define FPU_VFP_EXT_V2 0
58 #define FPU_MAVERICK 0
59 #define FPU_VFP_EXT_V3 0
60 #define FPU_NEON_EXT_V1 0
61
62 /* Assume host uses ieee float. */
63 static void floatformat_to_double (unsigned char *data, double *dest)
64 {
65 union {
66 uint32_t i;
67 float f;
68 } u;
69 u.i = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
70 *dest = u.f;
71 }
72
73 /* End of qemu specific additions. */
74
75 struct opcode32
76 {
77 unsigned long arch; /* Architecture defining this insn. */
78 unsigned long value, mask; /* Recognise insn if (op&mask)==value. */
79 const char *assembler; /* How to disassemble this insn. */
80 };
81
82 struct opcode16
83 {
84 unsigned long arch; /* Architecture defining this insn. */
85 unsigned short value, mask; /* Recognise insn if (op&mask)==value. */
86 const char *assembler; /* How to disassemble this insn. */
87 };
88
89 /* print_insn_coprocessor recognizes the following format control codes:
90
91 %% %
92
93 %c print condition code (always bits 28-31 in ARM mode)
94 %q print shifter argument
95 %u print condition code (unconditional in ARM mode)
96 %A print address for ldc/stc/ldf/stf instruction
97 %B print vstm/vldm register list
98 %C print vstr/vldr address operand
99 %I print cirrus signed shift immediate: bits 0..3|4..6
100 %F print the COUNT field of a LFM/SFM instruction.
101 %P print floating point precision in arithmetic insn
102 %Q print floating point precision in ldf/stf insn
103 %R print floating point rounding mode
104
105 %<bitfield>r print as an ARM register
106 %<bitfield>d print the bitfield in decimal
107 %<bitfield>k print immediate for VFPv3 conversion instruction
108 %<bitfield>x print the bitfield in hex
109 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
110 %<bitfield>f print a floating point constant if >7 else a
111 floating point register
112 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
113 %<bitfield>g print as an iWMMXt 64-bit register
114 %<bitfield>G print as an iWMMXt general purpose or control register
115 %<bitfield>D print as a NEON D register
116 %<bitfield>Q print as a NEON Q register
117
118 %y<code> print a single precision VFP reg.
119 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
120 %z<code> print a double precision VFP reg
121 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
122
123 %<bitfield>'c print specified char iff bitfield is all ones
124 %<bitfield>`c print specified char iff bitfield is all zeroes
125 %<bitfield>?ab... select from array of values in big endian order
126
127 %L print as an iWMMXt N/M width field.
128 %Z print the Immediate of a WSHUFH instruction.
129 %l like 'A' except use byte offsets for 'B' & 'H'
130 versions.
131 %i print 5-bit immediate in bits 8,3..0
132 (print "32" when 0)
133 %r print register offset address for wldt/wstr instruction
134 */
135
136 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
137
138 static const struct opcode32 coprocessor_opcodes[] =
139 {
140 /* XScale instructions. */
141 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
142 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
143 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
144 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
145 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
146
147 /* Intel Wireless MMX technology instructions. */
148 #define FIRST_IWMMXT_INSN 0x0e130130
149 #define IWMMXT_INSN_COUNT 73
150 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
151 {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
152 {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
153 {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
154 {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
155 {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
156 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
157 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
158 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
159 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
160 {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
161 {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
162 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
163 {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
164 {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
165 {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
166 {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
167 {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
168 {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
169 {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
170 {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
171 {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
172 {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
173 {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
174 {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
175 {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
176 {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
177 {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
178 {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
179 {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
180 {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
181 {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
182 {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
183 {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
184 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
185 {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
186 {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
187 {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
188 {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
189 {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
190 {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
191 {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
192 {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
193 {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
194 {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
195 {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
196 {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
197 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
198 {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
199 {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
200 {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
201 {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
203 {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
204 {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
205 {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
206 {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
207 {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
209 {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
210 {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
211 {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
212 {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
213 {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
214 {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
215 {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
217 {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
219 {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
220 {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
221 {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
222 {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
223 {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
224 {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
225
226 /* Floating point coprocessor (FPA) instructions */
227 {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
228 {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
229 {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
230 {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
231 {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
232 {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
233 {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
234 {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
235 {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
236 {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
237 {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
238 {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
239 {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
240 {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
241 {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
242 {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
243 {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
244 {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
245 {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
246 {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
247 {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
248 {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
249 {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
250 {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
251 {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
252 {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
253 {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
254 {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
255 {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
256 {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
257 {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
258 {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
259 {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
260 {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
261 {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
262 {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
263 {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
264 {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
265 {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
266 {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
267 {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
268 {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
269 {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
270
271 /* Register load/store */
272 {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"},
273 {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"},
274 {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
275 {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
276 {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
277 {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
278
279 /* Data transfer between ARM and NEON registers */
280 {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
281 {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
282 {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
283 {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
284 {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
285 {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
286 {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
287 {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
288 {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
289 {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
290 {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
291 {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
292 {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
293 {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
294
295 /* Floating point coprocessor (VFP) instructions */
296 {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
297 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
298 {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
299 {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"},
300 {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"},
301 {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
302 {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
303 {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
304 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
305 {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
306 {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"},
307 {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"},
308 {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
309 {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
310 {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
311 {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"},
312 {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
313 {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
314 {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
315 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"},
316 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"},
317 {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
318 {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
319 {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
320 {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"},
321 {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"},
322 {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"},
323 {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"},
324 {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"},
325 {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"},
326 {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"},
327 {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"},
328 {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"},
329 {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"},
330 {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"},
331 {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"},
332 {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"},
333 {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"},
334 {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"},
335 {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"},
336 {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"},
337 {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"},
338 {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"},
339 {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"},
340 {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"},
341 {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"},
342 {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"},
343 {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
344 {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"},
345 {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"},
346 {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
347 {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
348 {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
349 {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},
350 {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"},
351 {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"},
352 {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"},
353 {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"},
354 {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"},
355 {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"},
356 {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"},
357 {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"},
358 {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"},
359 {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"},
360 {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"},
361 {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"},
362 {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"},
363 {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"},
364 {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"},
365 {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"},
366 {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"},
367 {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"},
368 {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"},
369 {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"},
370 {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"},
371 {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"},
372 {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"},
373 {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"},
374 {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"},
375 {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"},
376 {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"},
377 {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"},
378 {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"},
379
380 /* Cirrus coprocessor instructions. */
381 {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
382 {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
383 {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
384 {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
385 {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
386 {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
387 {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
388 {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
389 {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
390 {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
391 {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
392 {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
393 {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
394 {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
395 {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
396 {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
397 {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
398 {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
399 {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
400 {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
401 {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
402 {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
403 {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
404 {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
405 {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
406 {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
407 {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
408 {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
409 {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
410 {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
411 {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
412 {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
413 {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
414 {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
415 {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
416 {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
417 {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
418 {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
419 {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
420 {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
421 {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
422 {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
423 {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
424 {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
425 {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
426 {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
427 {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
428 {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
429 {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
430 {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
431 {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
432 {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
433 {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
434 {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
435 {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
436 {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
437 {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
438 {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
439 {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
440 {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
441 {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
442 {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
443 {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
444 {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
445 {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
446 {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
447 {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
448 {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
449 {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
450 {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
451 {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
452 {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
453 {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
454 {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
455 {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
456 {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
457 {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
458 {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
459 {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
460 {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
461 {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
462 {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
463 {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
464 {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
465
466 /* Generic coprocessor instructions */
467 {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
468 {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
469 {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
470 {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
471 {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
472 {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
473 {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
474
475 /* V6 coprocessor instructions */
476 {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
477 {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
478
479 /* V5 coprocessor instructions */
480 {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
481 {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
482 {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
483 {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
484 {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
485
486 {0, 0, 0, 0}
487 };
488
489 /* Neon opcode table: This does not encode the top byte -- that is
490 checked by the print_insn_neon routine, as it depends on whether we are
491 doing thumb32 or arm32 disassembly. */
492
493 /* print_insn_neon recognizes the following format control codes:
494
495 %% %
496
497 %c print condition code
498 %A print v{st,ld}[1234] operands
499 %B print v{st,ld}[1234] any one operands
500 %C print v{st,ld}[1234] single->all operands
501 %D print scalar
502 %E print vmov, vmvn, vorr, vbic encoded constant
503 %F print vtbl,vtbx register list
504
505 %<bitfield>r print as an ARM register
506 %<bitfield>d print the bitfield in decimal
507 %<bitfield>e print the 2^N - bitfield in decimal
508 %<bitfield>D print as a NEON D register
509 %<bitfield>Q print as a NEON Q register
510 %<bitfield>R print as a NEON D or Q register
511 %<bitfield>Sn print byte scaled width limited by n
512 %<bitfield>Tn print short scaled width limited by n
513 %<bitfield>Un print long scaled width limited by n
514
515 %<bitfield>'c print specified char iff bitfield is all ones
516 %<bitfield>`c print specified char iff bitfield is all zeroes
517 %<bitfield>?ab... select from array of values in big endian order */
518
519 static const struct opcode32 neon_opcodes[] =
520 {
521 /* Extract */
522 {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
523 {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
524
525 /* Move data element to all lanes */
526 {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
527 {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
528 {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
529
530 /* Table lookup */
531 {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
532 {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
533
534 /* Two registers, miscellaneous */
535 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
536 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
537 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
538 {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
539 {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
540 {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
541 {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
542 {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
543 {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
544 {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
545 {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
546 {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
547 {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
548 {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
549 {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
550 {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
551 {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
552 {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
553 {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
554 {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
555 {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
556 {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
557 {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
558 {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
559 {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
560 {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
561 {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
562 {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
563 {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
564 {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
565 {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
566 {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
567 {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
568
569 /* Three registers of the same length */
570 {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
571 {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
572 {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
573 {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
574 {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
575 {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
576 {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
577 {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
578 {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
579 {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
580 {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
581 {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
582 {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
583 {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
584 {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
585 {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
586 {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
587 {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
588 {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
589 {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
590 {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
591 {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
592 {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
593 {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
594 {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
595 {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
596 {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
597 {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
598 {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
599 {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
600 {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
601 {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
602 {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
603 {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
604 {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
605 {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
606 {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
607 {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
608 {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
609 {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
610 {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
611 {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
612 {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
613 {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
614 {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
615 {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
616 {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
617 {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
618 {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
619 {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
620 {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
621 {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
622 {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
623
624 /* One register and an immediate value */
625 {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
626 {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
627 {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
628 {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
629 {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
630 {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
631 {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
632 {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
633 {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
634 {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
635 {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
636 {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
637 {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
638
639 /* Two registers and a shift amount */
640 {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
641 {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
642 {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
643 {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
644 {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
645 {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
646 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
647 {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
648 {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
649 {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
650 {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
651 {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
652 {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
653 {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
654 {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
655 {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
656 {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
657 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
658 {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
659 {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
660 {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
661 {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
662 {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
663 {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
664 {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
665 {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
666 {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
667 {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
668 {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
669 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
670 {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
671 {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
672 {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
673 {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
674 {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
675 {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
676 {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
677 {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
678 {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
679 {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
680 {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
681 {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
682 {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
683 {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
684 {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
685 {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
686 {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
687 {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
688 {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
689 {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
690 {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
691 {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
692 {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
693 {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
694 {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
695 {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
696 {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
697 {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
698
699 /* Three registers of different lengths */
700 {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
701 {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
702 {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
703 {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
704 {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
705 {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
706 {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
707 {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
708 {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
709 {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
710 {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
711 {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
712 {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
713 {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
714 {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
715 {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
716 {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
717
718 /* Two registers and a scalar */
719 {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
720 {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
721 {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
722 {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
723 {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
724 {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
725 {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
726 {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
727 {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
728 {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
729 {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
730 {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
731 {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
732 {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
733 {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
734 {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
735 {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
736 {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
737 {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
738 {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
739 {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
740 {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
741
742 /* Element and structure load/store */
743 {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
744 {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
745 {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
746 {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
747 {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
748 {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
749 {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
750 {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
751 {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
752 {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
753 {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
754 {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
755 {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
756 {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
757 {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
758 {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
759 {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
760 {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
761 {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
762
763 {0,0 ,0, 0}
764 };
765
766 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
767 ordered: they must be searched linearly from the top to obtain a correct
768 match. */
769
770 /* print_insn_arm recognizes the following format control codes:
771
772 %% %
773
774 %a print address for ldr/str instruction
775 %s print address for ldr/str halfword/signextend instruction
776 %b print branch destination
777 %c print condition code (always bits 28-31)
778 %m print register mask for ldm/stm instruction
779 %o print operand2 (immediate or register + shift)
780 %p print 'p' iff bits 12-15 are 15
781 %t print 't' iff bit 21 set and bit 24 clear
782 %B print arm BLX(1) destination
783 %C print the PSR sub type.
784 %U print barrier type.
785 %P print address for pli instruction.
786
787 %<bitfield>r print as an ARM register
788 %<bitfield>d print the bitfield in decimal
789 %<bitfield>W print the bitfield plus one in decimal
790 %<bitfield>x print the bitfield in hex
791 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
792
793 %<bitfield>'c print specified char iff bitfield is all ones
794 %<bitfield>`c print specified char iff bitfield is all zeroes
795 %<bitfield>?ab... select from array of values in big endian order
796
797 %e print arm SMI operand (bits 0..7,8..19).
798 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
799 %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
800
801 static const struct opcode32 arm_opcodes[] =
802 {
803 /* ARM instructions. */
804 {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
805 {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
806 {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"},
807 {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
808 {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"},
809 {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
810 {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
811
812 /* IDIV instructions. */
813 {ARM_EXT_DIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
814 {ARM_EXT_DIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
815
816 /* V7 instructions. */
817 {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
818 {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
819 {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
820 {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
821 {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
822
823 /* ARM V6T2 instructions. */
824 {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
825 {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
826 {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
827 {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"},
828 {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"},
829 {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
830 {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
831 {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
832 {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
833
834 /* ARM V6Z instructions. */
835 {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
836
837 /* ARM V6K instructions. */
838 {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
839 {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
840 {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
841 {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
842 {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
843 {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
844 {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
845
846 /* ARM V6K NOP hints. */
847 {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
848 {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
849 {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
850 {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
851 {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
852
853 /* ARM V6 instructions. */
854 {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
855 {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
856 {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
857 {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
858 {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
859 {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
860 {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"},
861 {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"},
862 {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"},
863 {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
864 {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
865 {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
866 {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
867 {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
868 {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
869 {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
870 {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
871 {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
872 {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
873 {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
874 {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
875 {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
876 {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
877 {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
878 {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
879 {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
880 {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
881 {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
882 {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
883 {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
884 {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
885 {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
886 {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
887 {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
888 {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
889 {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
890 {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
891 {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
892 {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
893 {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
894 {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
895 {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
896 {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
897 {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
898 {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
899 {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
900 {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
901 {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
902 {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
903 {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
904 {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"},
905 {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"},
906 {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"},
907 {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"},
908 {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"},
909 {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"},
910 {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"},
911 {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"},
912 {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"},
913 {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"},
914 {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"},
915 {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"},
916 {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"},
917 {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"},
918 {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"},
919 {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"},
920 {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"},
921 {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"},
922 {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"},
923 {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"},
924 {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"},
925 {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"},
926 {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"},
927 {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"},
928 {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
929 {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"},
930 {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"},
931 {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"},
932 {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
933 {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"},
934 {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"},
935 {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"},
936 {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
937 {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"},
938 {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"},
939 {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"},
940 {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
941 {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"},
942 {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"},
943 {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"},
944 {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
945 {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"},
946 {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"},
947 {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
948 {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
949 {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"},
950 {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"},
951 {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"},
952 {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
953 {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
954 {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
955 {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
956 {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
957 {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
958 {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
959 {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
960 {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
961 {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
962 {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
963 {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
964 {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
965 {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"},
966 {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"},
967 {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
968 {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
969 {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
970 {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
971 {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
972 {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
973 {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"},
974 {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"},
975 {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
976
977 /* V5J instruction. */
978 {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
979
980 /* V5 Instructions. */
981 {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
982 {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
983 {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
984 {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
985
986 /* V5E "El Segundo" Instructions. */
987 {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
988 {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
989 {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
990 {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
991 {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
992 {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
993 {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
994
995 {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
996 {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
997
998 {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
999 {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
1000 {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
1001 {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
1002
1003 {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
1004 {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
1005 {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
1006 {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
1007
1008 {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
1009 {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
1010
1011 {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
1012 {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
1013 {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
1014 {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
1015
1016 /* ARM Instructions. */
1017 {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"},
1018 {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"},
1019 {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1020 {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1021 {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1022 {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1023 {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1024 {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1025 {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1026 {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1027 {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
1028 {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
1029 {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"},
1030 {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"},
1031 {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"},
1032 {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"},
1033 {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1034 {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1035 {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1036 {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"},
1037 {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"},
1038 {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"},
1039 {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1040 {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"},
1041 {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1042 {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"},
1043 {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1044 {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"},
1045 {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"},
1046 {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
1047 {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
1048 {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1049 {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"},
1050 {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1051 {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"},
1052 {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
1053 {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1054 {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"},
1055 {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
1056 {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1057 {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1058
1059 /* The rest. */
1060 {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
1061 {0, 0x00000000, 0x00000000, 0}
1062 };
1063
1064 /* print_insn_thumb16 recognizes the following format control codes:
1065
1066 %S print Thumb register (bits 3..5 as high number if bit 6 set)
1067 %D print Thumb register (bits 0..2 as high number if bit 7 set)
1068 %<bitfield>I print bitfield as a signed decimal
1069 (top bit of range being the sign bit)
1070 %N print Thumb register mask (with LR)
1071 %O print Thumb register mask (with PC)
1072 %M print Thumb register mask
1073 %b print CZB's 6-bit unsigned branch destination
1074 %s print Thumb right-shift immediate (6..10; 0 == 32).
1075 %c print the condition code
1076 %C print the condition code, or "s" if not conditional
1077 %x print warning if conditional an not at end of IT block"
1078 %X print "\t; unpredictable <IT:code>" if conditional
1079 %I print IT instruction suffix and operands
1080 %<bitfield>r print bitfield as an ARM register
1081 %<bitfield>d print bitfield as a decimal
1082 %<bitfield>H print (bitfield * 2) as a decimal
1083 %<bitfield>W print (bitfield * 4) as a decimal
1084 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
1085 %<bitfield>B print Thumb branch destination (signed displacement)
1086 %<bitfield>c print bitfield as a condition code
1087 %<bitnum>'c print specified char iff bit is one
1088 %<bitnum>?ab print a if bit is one else print b. */
1089
1090 static const struct opcode16 thumb_opcodes[] =
1091 {
1092 /* Thumb instructions. */
1093
1094 /* ARM V6K no-argument instructions. */
1095 {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1096 {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1097 {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1098 {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1099 {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1100 {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1101
1102 /* ARM V6T2 instructions. */
1103 {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1104 {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1105 {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
1106
1107 /* ARM V6. */
1108 {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1109 {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1110 {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1111 {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1112 {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1113 {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1114 {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1115 {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1116 {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1117 {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1118 {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1119
1120 /* ARM V5 ISA extends Thumb. */
1121 {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
1122 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
1123 {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
1124 /* ARM V4T ISA (Thumb v1). */
1125 {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"},
1126 /* Format 4. */
1127 {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1128 {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1129 {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1130 {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1131 {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1132 {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1133 {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1134 {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1135 {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1136 {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1137 {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1138 {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1139 {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1140 {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1141 {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1142 {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1143 /* format 13 */
1144 {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1145 {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1146 /* format 5 */
1147 {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1148 {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1149 {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1150 {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1151 /* format 14 */
1152 {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1153 {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
1154 /* format 2 */
1155 {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1156 {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1157 {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1158 {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1159 /* format 8 */
1160 {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1161 {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1162 {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1163 /* format 7 */
1164 {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1165 {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1166 /* format 1 */
1167 {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1168 {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1169 {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1170 /* format 3 */
1171 {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1172 {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1173 {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1174 {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1175 /* format 6 */
1176 {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1177 /* format 9 */
1178 {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1179 {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1180 {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1181 {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1182 /* format 10 */
1183 {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1184 {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1185 /* format 11 */
1186 {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1187 {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1188 /* format 12 */
1189 {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"},
1190 {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1191 /* format 15 */
1192 {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1193 {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
1194 /* format 17 */
1195 {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1196 /* format 16 */
1197 {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"},
1198 {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1199 /* format 18 */
1200 {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1201
1202 /* The E800 .. FFFF range is unconditionally redirected to the
1203 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1204 are processed via that table. Thus, we can never encounter a
1205 bare "second half of BL/BLX(1)" instruction here. */
1206 {ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
1207 {0, 0, 0, 0}
1208 };
1209
1210 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1211 We adopt the convention that hw1 is the high 16 bits of .value and
1212 .mask, hw2 the low 16 bits.
1213
1214 print_insn_thumb32 recognizes the following format control codes:
1215
1216 %% %
1217
1218 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1219 %M print a modified 12-bit immediate (same location)
1220 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1221 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1222 %S print a possibly-shifted Rm
1223
1224 %a print the address of a plain load/store
1225 %w print the width and signedness of a core load/store
1226 %m print register mask for ldm/stm
1227
1228 %E print the lsb and width fields of a bfc/bfi instruction
1229 %F print the lsb and width fields of a sbfx/ubfx instruction
1230 %b print a conditional branch offset
1231 %B print an unconditional branch offset
1232 %s print the shift field of an SSAT instruction
1233 %R print the rotation field of an SXT instruction
1234 %U print barrier type.
1235 %P print address for pli instruction.
1236 %c print the condition code
1237 %x print warning if conditional an not at end of IT block"
1238 %X print "\t; unpredictable <IT:code>" if conditional
1239
1240 %<bitfield>d print bitfield in decimal
1241 %<bitfield>W print bitfield*4 in decimal
1242 %<bitfield>r print bitfield as an ARM register
1243 %<bitfield>c print bitfield as a condition code
1244
1245 %<bitfield>'c print specified char iff bitfield is all ones
1246 %<bitfield>`c print specified char iff bitfield is all zeroes
1247 %<bitfield>?ab... select from array of values in big endian order
1248
1249 With one exception at the bottom (done because BL and BLX(1) need
1250 to come dead last), this table was machine-sorted first in
1251 decreasing order of number of bits set in the mask, then in
1252 increasing numeric order of mask, then in increasing numeric order
1253 of opcode. This order is not the clearest for a human reader, but
1254 is guaranteed never to catch a special-case bit pattern with a more
1255 general mask, which is important, because this instruction encoding
1256 makes heavy use of special-case bit patterns. */
1257 static const struct opcode32 thumb32_opcodes[] =
1258 {
1259 /* V7 instructions. */
1260 {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1261 {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1262 {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1263 {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1264 {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1265 {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1266 {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1267
1268 /* Instructions defined in the basic V6T2 set. */
1269 {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1270 {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1271 {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1272 {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1273 {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
1274 {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1275
1276 {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1277 {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1278 {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1279 {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1280 {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1281 {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1282 {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"},
1283 {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1284 {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1285 {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1286 {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1287 {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1288 {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1289 {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1290 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1291 {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1292 {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1293 {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1294 {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1295 {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1296 {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1297 {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1298 {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1299 {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1300 {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1301 {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1302 {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1303 {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1304 {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1305 {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1306 {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1307 {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1308 {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1309 {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1310 {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1311 {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1312 {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1313 {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1314 {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1315 {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1316 {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1317 {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1318 {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1319 {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1320 {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1321 {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1322 {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"},
1323 {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1324 {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1325 {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1326 {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1327 {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1328 {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1329 {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1330 {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1331 {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1332 {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1333 {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1334 {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1335 {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1336 {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1337 {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1338 {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1339 {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1340 {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1341 {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1342 {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"},
1343 {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1344 {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1345 {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"},
1346 {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1347 {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1348 {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1349 {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1350 {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1351 {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1352 {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1353 {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1354 {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1355 {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1356 {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1357 {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1358 {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1359 {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1360 {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1361 {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1362 {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1363 {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1364 {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1365 {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1366 {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1367 {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1368 {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1369 {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1370 {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1371 {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1372 {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1373 {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1374 {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1375 {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1376 {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1377 {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1378 {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1379 {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1380 {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1381 {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1382 {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1383 {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1384 {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1385 {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1386 {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1387 {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1388 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1389 {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1390 {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1391 {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1392 {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1393 {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1394 {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1395 {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1396 {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1397 {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1398 {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1399 {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1400 {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1401 {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1402 {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1403 {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1404 {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1405 {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1406 {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1407 {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1408 {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1409 {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1410 {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1411 {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1412 {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1413 {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1414 {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1415 {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1416 {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1417 {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1418 {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1419 {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1420 {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1421 {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1422 {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1423 {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1424 {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1425 {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1426 {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1427 {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1428 {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1429 {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1430 {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1431 {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1432 {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1433 {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1434 {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1435 {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1436 {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1437 {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1438 {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1439 {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1440 {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1441 {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1442 {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
1443 {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
1444 {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
1445 {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
1446 {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1447 {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1448
1449 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1450 {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1451 {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1452 {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1453 {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1454
1455 /* These have been 32-bit since the invention of Thumb. */
1456 {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"},
1457 {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1458
1459 /* Fallback. */
1460 {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
1461 {0, 0, 0, 0}
1462 };
1463
1464 static const char *const arm_conditional[] =
1465 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1466 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1467
1468 static const char *const arm_fp_const[] =
1469 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1470
1471 static const char *const arm_shift[] =
1472 {"lsl", "lsr", "asr", "ror"};
1473
1474 typedef struct
1475 {
1476 const char *name;
1477 const char *description;
1478 const char *reg_names[16];
1479 }
1480 arm_regname;
1481
1482 static const arm_regname regnames[] =
1483 {
1484 { "raw" , "Select raw register names",
1485 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1486 { "gcc", "Select register names used by GCC",
1487 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1488 { "std", "Select register names used in ARM's ISA documentation",
1489 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1490 { "apcs", "Select register names used in the APCS",
1491 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1492 { "atpcs", "Select register names used in the ATPCS",
1493 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1494 { "special-atpcs", "Select special register names used in the ATPCS",
1495 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1496 };
1497
1498 static const char *const iwmmxt_wwnames[] =
1499 {"b", "h", "w", "d"};
1500
1501 static const char *const iwmmxt_wwssnames[] =
1502 {"b", "bus", "bc", "bss",
1503 "h", "hus", "hc", "hss",
1504 "w", "wus", "wc", "wss",
1505 "d", "dus", "dc", "dss"
1506 };
1507
1508 static const char *const iwmmxt_regnames[] =
1509 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1510 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1511 };
1512
1513 static const char *const iwmmxt_cregnames[] =
1514 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1515 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1516 };
1517
1518 /* Default to GCC register name set. */
1519 static unsigned int regname_selected = 1;
1520
1521 #define arm_regnames regnames[regname_selected].reg_names
1522
1523 static bfd_boolean force_thumb = false;
1524
1525 /* Current IT instruction state. This contains the same state as the IT
1526 bits in the CPSR. */
1527 static unsigned int ifthen_state;
1528 /* IT state for the next instruction. */
1529 static unsigned int ifthen_next_state;
1530 /* The address of the insn for which the IT state is valid. */
1531 static bfd_vma ifthen_address;
1532 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1533
1534 /* Cached mapping symbol state. */
1535 enum map_type {
1536 MAP_ARM,
1537 MAP_THUMB,
1538 MAP_DATA
1539 };
1540
1541 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1542 Returns pointer to following character of the format string and
1543 fills in *VALUEP and *WIDTHP with the extracted value and number of
1544 bits extracted. WIDTHP can be NULL. */
1545
1546 static const char *
1547 arm_decode_bitfield (const char *ptr, unsigned long insn,
1548 unsigned long *valuep, int *widthp)
1549 {
1550 unsigned long value = 0;
1551 int width = 0;
1552
1553 do
1554 {
1555 int start, end;
1556 int bits;
1557
1558 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1559 start = start * 10 + *ptr - '0';
1560 if (*ptr == '-')
1561 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1562 end = end * 10 + *ptr - '0';
1563 else
1564 end = start;
1565 bits = end - start;
1566 if (bits < 0)
1567 abort ();
1568 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1569 width += bits + 1;
1570 }
1571 while (*ptr++ == ',');
1572 *valuep = value;
1573 if (widthp)
1574 *widthp = width;
1575 return ptr - 1;
1576 }
1577
1578 static void
1579 arm_decode_shift (long given, fprintf_function func, void *stream,
1580 int print_shift)
1581 {
1582 func (stream, "%s", arm_regnames[given & 0xf]);
1583
1584 if ((given & 0xff0) != 0)
1585 {
1586 if ((given & 0x10) == 0)
1587 {
1588 int amount = (given & 0xf80) >> 7;
1589 int shift = (given & 0x60) >> 5;
1590
1591 if (amount == 0)
1592 {
1593 if (shift == 3)
1594 {
1595 func (stream, ", rrx");
1596 return;
1597 }
1598
1599 amount = 32;
1600 }
1601
1602 if (print_shift)
1603 func (stream, ", %s #%d", arm_shift[shift], amount);
1604 else
1605 func (stream, ", #%d", amount);
1606 }
1607 else if (print_shift)
1608 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1609 arm_regnames[(given & 0xf00) >> 8]);
1610 else
1611 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
1612 }
1613 }
1614
1615 /* Print one coprocessor instruction on INFO->STREAM.
1616 Return true if the instruction matched, false if this is not a
1617 recognised coprocessor instruction. */
1618
1619 static bfd_boolean
1620 print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
1621 bfd_boolean thumb)
1622 {
1623 const struct opcode32 *insn;
1624 void *stream = info->stream;
1625 fprintf_function func = info->fprintf_func;
1626 unsigned long mask;
1627 unsigned long value;
1628 int cond;
1629
1630 for (insn = coprocessor_opcodes; insn->assembler; insn++)
1631 {
1632 if (insn->value == FIRST_IWMMXT_INSN
1633 && info->mach != bfd_mach_arm_XScale
1634 && info->mach != bfd_mach_arm_iWMMXt
1635 && info->mach != bfd_mach_arm_iWMMXt2)
1636 insn = insn + IWMMXT_INSN_COUNT;
1637
1638 mask = insn->mask;
1639 value = insn->value;
1640 if (thumb)
1641 {
1642 /* The high 4 bits are 0xe for Arm conditional instructions, and
1643 0xe for arm unconditional instructions. The rest of the
1644 encoding is the same. */
1645 mask |= 0xf0000000;
1646 value |= 0xe0000000;
1647 if (ifthen_state)
1648 cond = IFTHEN_COND;
1649 else
1650 cond = 16;
1651 }
1652 else
1653 {
1654 /* Only match unconditional instuctions against unconditional
1655 patterns. */
1656 if ((given & 0xf0000000) == 0xf0000000)
1657 {
1658 mask |= 0xf0000000;
1659 cond = 16;
1660 }
1661 else
1662 {
1663 cond = (given >> 28) & 0xf;
1664 if (cond == 0xe)
1665 cond = 16;
1666 }
1667 }
1668 if ((given & mask) == value)
1669 {
1670 const char *c;
1671
1672 for (c = insn->assembler; *c; c++)
1673 {
1674 if (*c == '%')
1675 {
1676 switch (*++c)
1677 {
1678 case '%':
1679 func (stream, "%%");
1680 break;
1681
1682 case 'A':
1683 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1684
1685 if ((given & (1 << 24)) != 0)
1686 {
1687 int offset = given & 0xff;
1688
1689 if (offset)
1690 func (stream, ", #%s%d]%s",
1691 ((given & 0x00800000) == 0 ? "-" : ""),
1692 offset * 4,
1693 ((given & 0x00200000) != 0 ? "!" : ""));
1694 else
1695 func (stream, "]");
1696 }
1697 else
1698 {
1699 int offset = given & 0xff;
1700
1701 func (stream, "]");
1702
1703 if (given & (1 << 21))
1704 {
1705 if (offset)
1706 func (stream, ", #%s%d",
1707 ((given & 0x00800000) == 0 ? "-" : ""),
1708 offset * 4);
1709 }
1710 else
1711 func (stream, ", {%d}", offset);
1712 }
1713 break;
1714
1715 case 'B':
1716 {
1717 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
1718 int offset = (given >> 1) & 0x3f;
1719
1720 if (offset == 1)
1721 func (stream, "{d%d}", regno);
1722 else if (regno + offset > 32)
1723 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
1724 else
1725 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
1726 }
1727 break;
1728
1729 case 'C':
1730 {
1731 int rn = (given >> 16) & 0xf;
1732 int offset = (given & 0xff) * 4;
1733 int add = (given >> 23) & 1;
1734
1735 func (stream, "[%s", arm_regnames[rn]);
1736
1737 if (offset)
1738 {
1739 if (!add)
1740 offset = -offset;
1741 func (stream, ", #%d", offset);
1742 }
1743 func (stream, "]");
1744 if (rn == 15)
1745 {
1746 func (stream, "\t; ");
1747 /* FIXME: Unsure if info->bytes_per_chunk is the
1748 right thing to use here. */
1749 info->print_address_func (offset + pc
1750 + info->bytes_per_chunk * 2, info);
1751 }
1752 }
1753 break;
1754
1755 case 'c':
1756 func (stream, "%s", arm_conditional[cond]);
1757 break;
1758
1759 case 'I':
1760 /* Print a Cirrus/DSP shift immediate. */
1761 /* Immediates are 7bit signed ints with bits 0..3 in
1762 bits 0..3 of opcode and bits 4..6 in bits 5..7
1763 of opcode. */
1764 {
1765 int imm;
1766
1767 imm = (given & 0xf) | ((given & 0xe0) >> 1);
1768
1769 /* Is ``imm'' a negative number? */
1770 if (imm & 0x40)
1771 imm |= (~0u << 7);
1772
1773 func (stream, "%d", imm);
1774 }
1775
1776 break;
1777
1778 case 'F':
1779 switch (given & 0x00408000)
1780 {
1781 case 0:
1782 func (stream, "4");
1783 break;
1784 case 0x8000:
1785 func (stream, "1");
1786 break;
1787 case 0x00400000:
1788 func (stream, "2");
1789 break;
1790 default:
1791 func (stream, "3");
1792 }
1793 break;
1794
1795 case 'P':
1796 switch (given & 0x00080080)
1797 {
1798 case 0:
1799 func (stream, "s");
1800 break;
1801 case 0x80:
1802 func (stream, "d");
1803 break;
1804 case 0x00080000:
1805 func (stream, "e");
1806 break;
1807 default:
1808 func (stream, "<illegal precision>");
1809 break;
1810 }
1811 break;
1812 case 'Q':
1813 switch (given & 0x00408000)
1814 {
1815 case 0:
1816 func (stream, "s");
1817 break;
1818 case 0x8000:
1819 func (stream, "d");
1820 break;
1821 case 0x00400000:
1822 func (stream, "e");
1823 break;
1824 default:
1825 func (stream, "p");
1826 break;
1827 }
1828 break;
1829 case 'R':
1830 switch (given & 0x60)
1831 {
1832 case 0:
1833 break;
1834 case 0x20:
1835 func (stream, "p");
1836 break;
1837 case 0x40:
1838 func (stream, "m");
1839 break;
1840 default:
1841 func (stream, "z");
1842 break;
1843 }
1844 break;
1845
1846 case '0': case '1': case '2': case '3': case '4':
1847 case '5': case '6': case '7': case '8': case '9':
1848 {
1849 int width;
1850 unsigned long value;
1851
1852 c = arm_decode_bitfield (c, given, &value, &width);
1853
1854 switch (*c)
1855 {
1856 case 'r':
1857 func (stream, "%s", arm_regnames[value]);
1858 break;
1859 case 'D':
1860 func (stream, "d%ld", value);
1861 break;
1862 case 'Q':
1863 if (value & 1)
1864 func (stream, "<illegal reg q%ld.5>", value >> 1);
1865 else
1866 func (stream, "q%ld", value >> 1);
1867 break;
1868 case 'd':
1869 func (stream, "%ld", value);
1870 break;
1871 case 'k':
1872 {
1873 int from = (given & (1 << 7)) ? 32 : 16;
1874 func (stream, "%ld", from - value);
1875 }
1876 break;
1877
1878 case 'f':
1879 if (value > 7)
1880 func (stream, "#%s", arm_fp_const[value & 7]);
1881 else
1882 func (stream, "f%ld", value);
1883 break;
1884
1885 case 'w':
1886 if (width == 2)
1887 func (stream, "%s", iwmmxt_wwnames[value]);
1888 else
1889 func (stream, "%s", iwmmxt_wwssnames[value]);
1890 break;
1891
1892 case 'g':
1893 func (stream, "%s", iwmmxt_regnames[value]);
1894 break;
1895 case 'G':
1896 func (stream, "%s", iwmmxt_cregnames[value]);
1897 break;
1898
1899 case 'x':
1900 func (stream, "0x%lx", value);
1901 break;
1902
1903 case '`':
1904 c++;
1905 if (value == 0)
1906 func (stream, "%c", *c);
1907 break;
1908 case '\'':
1909 c++;
1910 if (value == ((1ul << width) - 1))
1911 func (stream, "%c", *c);
1912 break;
1913 case '?':
1914 func (stream, "%c", c[(1 << width) - (int)value]);
1915 c += 1 << width;
1916 break;
1917 default:
1918 abort ();
1919 }
1920 break;
1921
1922 case 'y':
1923 case 'z':
1924 {
1925 int single = *c++ == 'y';
1926 int regno;
1927
1928 switch (*c)
1929 {
1930 case '4': /* Sm pair */
1931 func (stream, "{");
1932 /* Fall through. */
1933 case '0': /* Sm, Dm */
1934 regno = given & 0x0000000f;
1935 if (single)
1936 {
1937 regno <<= 1;
1938 regno += (given >> 5) & 1;
1939 }
1940 else
1941 regno += ((given >> 5) & 1) << 4;
1942 break;
1943
1944 case '1': /* Sd, Dd */
1945 regno = (given >> 12) & 0x0000000f;
1946 if (single)
1947 {
1948 regno <<= 1;
1949 regno += (given >> 22) & 1;
1950 }
1951 else
1952 regno += ((given >> 22) & 1) << 4;
1953 break;
1954
1955 case '2': /* Sn, Dn */
1956 regno = (given >> 16) & 0x0000000f;
1957 if (single)
1958 {
1959 regno <<= 1;
1960 regno += (given >> 7) & 1;
1961 }
1962 else
1963 regno += ((given >> 7) & 1) << 4;
1964 break;
1965
1966 case '3': /* List */
1967 func (stream, "{");
1968 regno = (given >> 12) & 0x0000000f;
1969 if (single)
1970 {
1971 regno <<= 1;
1972 regno += (given >> 22) & 1;
1973 }
1974 else
1975 regno += ((given >> 22) & 1) << 4;
1976 break;
1977
1978 default:
1979 abort ();
1980 }
1981
1982 func (stream, "%c%d", single ? 's' : 'd', regno);
1983
1984 if (*c == '3')
1985 {
1986 int count = given & 0xff;
1987
1988 if (single == 0)
1989 count >>= 1;
1990
1991 if (--count)
1992 {
1993 func (stream, "-%c%d",
1994 single ? 's' : 'd',
1995 regno + count);
1996 }
1997
1998 func (stream, "}");
1999 }
2000 else if (*c == '4')
2001 func (stream, ", %c%d}", single ? 's' : 'd',
2002 regno + 1);
2003 }
2004 break;
2005
2006 case 'L':
2007 switch (given & 0x00400100)
2008 {
2009 case 0x00000000: func (stream, "b"); break;
2010 case 0x00400000: func (stream, "h"); break;
2011 case 0x00000100: func (stream, "w"); break;
2012 case 0x00400100: func (stream, "d"); break;
2013 default:
2014 break;
2015 }
2016 break;
2017
2018 case 'Z':
2019 {
2020 int value;
2021 /* given (20, 23) | given (0, 3) */
2022 value = ((given >> 16) & 0xf0) | (given & 0xf);
2023 func (stream, "%d", value);
2024 }
2025 break;
2026
2027 case 'l':
2028 /* This is like the 'A' operator, except that if
2029 the width field "M" is zero, then the offset is
2030 *not* multiplied by four. */
2031 {
2032 int offset = given & 0xff;
2033 int multiplier = (given & 0x00000100) ? 4 : 1;
2034
2035 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2036
2037 if (offset)
2038 {
2039 if ((given & 0x01000000) != 0)
2040 func (stream, ", #%s%d]%s",
2041 ((given & 0x00800000) == 0 ? "-" : ""),
2042 offset * multiplier,
2043 ((given & 0x00200000) != 0 ? "!" : ""));
2044 else
2045 func (stream, "], #%s%d",
2046 ((given & 0x00800000) == 0 ? "-" : ""),
2047 offset * multiplier);
2048 }
2049 else
2050 func (stream, "]");
2051 }
2052 break;
2053
2054 case 'r':
2055 {
2056 int imm4 = (given >> 4) & 0xf;
2057 int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1);
2058 int ubit = (given >> 23) & 1;
2059 const char *rm = arm_regnames [given & 0xf];
2060 const char *rn = arm_regnames [(given >> 16) & 0xf];
2061
2062 switch (puw_bits)
2063 {
2064 case 1:
2065 /* fall through */
2066 case 3:
2067 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2068 if (imm4)
2069 func (stream, ", lsl #%d", imm4);
2070 break;
2071
2072 case 4:
2073 /* fall through */
2074 case 5:
2075 /* fall through */
2076 case 6:
2077 /* fall through */
2078 case 7:
2079 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2080 if (imm4 > 0)
2081 func (stream, ", lsl #%d", imm4);
2082 func (stream, "]");
2083 if (puw_bits == 5 || puw_bits == 7)
2084 func (stream, "!");
2085 break;
2086
2087 default:
2088 func (stream, "INVALID");
2089 }
2090 }
2091 break;
2092
2093 case 'i':
2094 {
2095 long imm5;
2096 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
2097 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
2098 }
2099 break;
2100
2101 default:
2102 abort ();
2103 }
2104 }
2105 }
2106 else
2107 func (stream, "%c", *c);
2108 }
2109 return true;
2110 }
2111 }
2112 return false;
2113 }
2114
2115 static void
2116 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
2117 {
2118 void *stream = info->stream;
2119 fprintf_function func = info->fprintf_func;
2120
2121 if (((given & 0x000f0000) == 0x000f0000)
2122 && ((given & 0x02000000) == 0))
2123 {
2124 int offset = given & 0xfff;
2125
2126 func (stream, "[pc");
2127
2128 if (given & 0x01000000)
2129 {
2130 if ((given & 0x00800000) == 0)
2131 offset = - offset;
2132
2133 /* Pre-indexed. */
2134 func (stream, ", #%d]", offset);
2135
2136 offset += pc + 8;
2137
2138 /* Cope with the possibility of write-back
2139 being used. Probably a very dangerous thing
2140 for the programmer to do, but who are we to
2141 argue ? */
2142 if (given & 0x00200000)
2143 func (stream, "!");
2144 }
2145 else
2146 {
2147 /* Post indexed. */
2148 func (stream, "], #%d", offset);
2149
2150 /* ie ignore the offset. */
2151 offset = pc + 8;
2152 }
2153
2154 func (stream, "\t; ");
2155 info->print_address_func (offset, info);
2156 }
2157 else
2158 {
2159 func (stream, "[%s",
2160 arm_regnames[(given >> 16) & 0xf]);
2161 if ((given & 0x01000000) != 0)
2162 {
2163 if ((given & 0x02000000) == 0)
2164 {
2165 int offset = given & 0xfff;
2166 if (offset)
2167 func (stream, ", #%s%d",
2168 (((given & 0x00800000) == 0)
2169 ? "-" : ""), offset);
2170 }
2171 else
2172 {
2173 func (stream, ", %s",
2174 (((given & 0x00800000) == 0)
2175 ? "-" : ""));
2176 arm_decode_shift (given, func, stream, 1);
2177 }
2178
2179 func (stream, "]%s",
2180 ((given & 0x00200000) != 0) ? "!" : "");
2181 }
2182 else
2183 {
2184 if ((given & 0x02000000) == 0)
2185 {
2186 int offset = given & 0xfff;
2187 if (offset)
2188 func (stream, "], #%s%d",
2189 (((given & 0x00800000) == 0)
2190 ? "-" : ""), offset);
2191 else
2192 func (stream, "]");
2193 }
2194 else
2195 {
2196 func (stream, "], %s",
2197 (((given & 0x00800000) == 0)
2198 ? "-" : ""));
2199 arm_decode_shift (given, func, stream, 1);
2200 }
2201 }
2202 }
2203 }
2204
2205 /* Print one neon instruction on INFO->STREAM.
2206 Return true if the instruction matched, false if this is not a
2207 recognised neon instruction. */
2208
2209 static bfd_boolean
2210 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2211 {
2212 const struct opcode32 *insn;
2213 void *stream = info->stream;
2214 fprintf_function func = info->fprintf_func;
2215
2216 if (thumb)
2217 {
2218 if ((given & 0xef000000) == 0xef000000)
2219 {
2220 /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
2221 unsigned long bit28 = given & (1 << 28);
2222
2223 given &= 0x00ffffff;
2224 if (bit28)
2225 given |= 0xf3000000;
2226 else
2227 given |= 0xf2000000;
2228 }
2229 else if ((given & 0xff000000) == 0xf9000000)
2230 given ^= 0xf9000000 ^ 0xf4000000;
2231 else
2232 return false;
2233 }
2234
2235 for (insn = neon_opcodes; insn->assembler; insn++)
2236 {
2237 if ((given & insn->mask) == insn->value)
2238 {
2239 const char *c;
2240
2241 for (c = insn->assembler; *c; c++)
2242 {
2243 if (*c == '%')
2244 {
2245 switch (*++c)
2246 {
2247 case '%':
2248 func (stream, "%%");
2249 break;
2250
2251 case 'c':
2252 if (thumb && ifthen_state)
2253 func (stream, "%s", arm_conditional[IFTHEN_COND]);
2254 break;
2255
2256 case 'A':
2257 {
2258 static const unsigned char enc[16] =
2259 {
2260 0x4, 0x14, /* st4 0,1 */
2261 0x4, /* st1 2 */
2262 0x4, /* st2 3 */
2263 0x3, /* st3 4 */
2264 0x13, /* st3 5 */
2265 0x3, /* st1 6 */
2266 0x1, /* st1 7 */
2267 0x2, /* st2 8 */
2268 0x12, /* st2 9 */
2269 0x2, /* st1 10 */
2270 0, 0, 0, 0, 0
2271 };
2272 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2273 int rn = ((given >> 16) & 0xf);
2274 int rm = ((given >> 0) & 0xf);
2275 int align = ((given >> 4) & 0x3);
2276 int type = ((given >> 8) & 0xf);
2277 int n = enc[type] & 0xf;
2278 int stride = (enc[type] >> 4) + 1;
2279 int ix;
2280
2281 func (stream, "{");
2282 if (stride > 1)
2283 for (ix = 0; ix != n; ix++)
2284 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2285 else if (n == 1)
2286 func (stream, "d%d", rd);
2287 else
2288 func (stream, "d%d-d%d", rd, rd + n - 1);
2289 func (stream, "}, [%s", arm_regnames[rn]);
2290 if (align)
2291 func (stream, ", :%d", 32 << align);
2292 func (stream, "]");
2293 if (rm == 0xd)
2294 func (stream, "!");
2295 else if (rm != 0xf)
2296 func (stream, ", %s", arm_regnames[rm]);
2297 }
2298 break;
2299
2300 case 'B':
2301 {
2302 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2303 int rn = ((given >> 16) & 0xf);
2304 int rm = ((given >> 0) & 0xf);
2305 int idx_align = ((given >> 4) & 0xf);
2306 int align = 0;
2307 int size = ((given >> 10) & 0x3);
2308 int idx = idx_align >> (size + 1);
2309 int length = ((given >> 8) & 3) + 1;
2310 int stride = 1;
2311 int i;
2312
2313 if (length > 1 && size > 0)
2314 stride = (idx_align & (1 << size)) ? 2 : 1;
2315
2316 switch (length)
2317 {
2318 case 1:
2319 {
2320 int amask = (1 << size) - 1;
2321 if ((idx_align & (1 << size)) != 0)
2322 return false;
2323 if (size > 0)
2324 {
2325 if ((idx_align & amask) == amask)
2326 align = 8 << size;
2327 else if ((idx_align & amask) != 0)
2328 return false;
2329 }
2330 }
2331 break;
2332
2333 case 2:
2334 if (size == 2 && (idx_align & 2) != 0)
2335 return false;
2336 align = (idx_align & 1) ? 16 << size : 0;
2337 break;
2338
2339 case 3:
2340 if ((size == 2 && (idx_align & 3) != 0)
2341 || (idx_align & 1) != 0)
2342 return false;
2343 break;
2344
2345 case 4:
2346 if (size == 2)
2347 {
2348 if ((idx_align & 3) == 3)
2349 return false;
2350 align = (idx_align & 3) * 64;
2351 }
2352 else
2353 align = (idx_align & 1) ? 32 << size : 0;
2354 break;
2355
2356 default:
2357 abort ();
2358 }
2359
2360 func (stream, "{");
2361 for (i = 0; i < length; i++)
2362 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2363 rd + i * stride, idx);
2364 func (stream, "}, [%s", arm_regnames[rn]);
2365 if (align)
2366 func (stream, ", :%d", align);
2367 func (stream, "]");
2368 if (rm == 0xd)
2369 func (stream, "!");
2370 else if (rm != 0xf)
2371 func (stream, ", %s", arm_regnames[rm]);
2372 }
2373 break;
2374
2375 case 'C':
2376 {
2377 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2378 int rn = ((given >> 16) & 0xf);
2379 int rm = ((given >> 0) & 0xf);
2380 int align = ((given >> 4) & 0x1);
2381 int size = ((given >> 6) & 0x3);
2382 int type = ((given >> 8) & 0x3);
2383 int n = type + 1;
2384 int stride = ((given >> 5) & 0x1);
2385 int ix;
2386
2387 if (stride && (n == 1))
2388 n++;
2389 else
2390 stride++;
2391
2392 func (stream, "{");
2393 if (stride > 1)
2394 for (ix = 0; ix != n; ix++)
2395 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2396 else if (n == 1)
2397 func (stream, "d%d[]", rd);
2398 else
2399 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2400 func (stream, "}, [%s", arm_regnames[rn]);
2401 if (align)
2402 {
2403 int align = (8 * (type + 1)) << size;
2404 if (type == 3)
2405 align = (size > 1) ? align >> 1 : align;
2406 if (type == 2 || (type == 0 && !size))
2407 func (stream, ", :<bad align %d>", align);
2408 else
2409 func (stream, ", :%d", align);
2410 }
2411 func (stream, "]");
2412 if (rm == 0xd)
2413 func (stream, "!");
2414 else if (rm != 0xf)
2415 func (stream, ", %s", arm_regnames[rm]);
2416 }
2417 break;
2418
2419 case 'D':
2420 {
2421 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2422 int size = (given >> 20) & 3;
2423 int reg = raw_reg & ((4 << size) - 1);
2424 int ix = raw_reg >> size >> 2;
2425
2426 func (stream, "d%d[%d]", reg, ix);
2427 }
2428 break;
2429
2430 case 'E':
2431 /* Neon encoded constant for mov, mvn, vorr, vbic */
2432 {
2433 int bits = 0;
2434 int cmode = (given >> 8) & 0xf;
2435 int op = (given >> 5) & 0x1;
2436 unsigned long value = 0, hival = 0;
2437 unsigned shift;
2438 int size = 0;
2439 int isfloat = 0;
2440
2441 bits |= ((given >> 24) & 1) << 7;
2442 bits |= ((given >> 16) & 7) << 4;
2443 bits |= ((given >> 0) & 15) << 0;
2444
2445 if (cmode < 8)
2446 {
2447 shift = (cmode >> 1) & 3;
2448 value = (unsigned long)bits << (8 * shift);
2449 size = 32;
2450 }
2451 else if (cmode < 12)
2452 {
2453 shift = (cmode >> 1) & 1;
2454 value = (unsigned long)bits << (8 * shift);
2455 size = 16;
2456 }
2457 else if (cmode < 14)
2458 {
2459 shift = (cmode & 1) + 1;
2460 value = (unsigned long)bits << (8 * shift);
2461 value |= (1ul << (8 * shift)) - 1;
2462 size = 32;
2463 }
2464 else if (cmode == 14)
2465 {
2466 if (op)
2467 {
2468 /* bit replication into bytes */
2469 int ix;
2470 unsigned long mask;
2471
2472 value = 0;
2473 hival = 0;
2474 for (ix = 7; ix >= 0; ix--)
2475 {
2476 mask = ((bits >> ix) & 1) ? 0xff : 0;
2477 if (ix <= 3)
2478 value = (value << 8) | mask;
2479 else
2480 hival = (hival << 8) | mask;
2481 }
2482 size = 64;
2483 }
2484 else
2485 {
2486 /* byte replication */
2487 value = (unsigned long)bits;
2488 size = 8;
2489 }
2490 }
2491 else if (!op)
2492 {
2493 /* floating point encoding */
2494 int tmp;
2495
2496 value = (unsigned long)(bits & 0x7f) << 19;
2497 value |= (unsigned long)(bits & 0x80) << 24;
2498 tmp = bits & 0x40 ? 0x3c : 0x40;
2499 value |= (unsigned long)tmp << 24;
2500 size = 32;
2501 isfloat = 1;
2502 }
2503 else
2504 {
2505 func (stream, "<illegal constant %.8x:%x:%x>",
2506 bits, cmode, op);
2507 break;
2508 }
2509 switch (size)
2510 {
2511 case 8:
2512 func (stream, "#%ld\t; 0x%.2lx", value, value);
2513 break;
2514
2515 case 16:
2516 func (stream, "#%ld\t; 0x%.4lx", value, value);
2517 break;
2518
2519 case 32:
2520 if (isfloat)
2521 {
2522 unsigned char valbytes[4];
2523 double fvalue;
2524
2525 /* Do this a byte at a time so we don't have to
2526 worry about the host's endianness. */
2527 valbytes[0] = value & 0xff;
2528 valbytes[1] = (value >> 8) & 0xff;
2529 valbytes[2] = (value >> 16) & 0xff;
2530 valbytes[3] = (value >> 24) & 0xff;
2531
2532 floatformat_to_double (valbytes, &fvalue);
2533
2534 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2535 value);
2536 }
2537 else
2538 func (stream, "#%ld\t; 0x%.8lx",
2539 (long) ((value & 0x80000000)
2540 ? value | ~0xffffffffl : value), value);
2541 break;
2542
2543 case 64:
2544 func (stream, "#0x%.8lx%.8lx", hival, value);
2545 break;
2546
2547 default:
2548 abort ();
2549 }
2550 }
2551 break;
2552
2553 case 'F':
2554 {
2555 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2556 int num = (given >> 8) & 0x3;
2557
2558 if (!num)
2559 func (stream, "{d%d}", regno);
2560 else if (num + regno >= 32)
2561 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2562 else
2563 func (stream, "{d%d-d%d}", regno, regno + num);
2564 }
2565 break;
2566
2567
2568 case '0': case '1': case '2': case '3': case '4':
2569 case '5': case '6': case '7': case '8': case '9':
2570 {
2571 int width;
2572 unsigned long value;
2573
2574 c = arm_decode_bitfield (c, given, &value, &width);
2575
2576 switch (*c)
2577 {
2578 case 'r':
2579 func (stream, "%s", arm_regnames[value]);
2580 break;
2581 case 'd':
2582 func (stream, "%ld", value);
2583 break;
2584 case 'e':
2585 func (stream, "%ld", (1ul << width) - value);
2586 break;
2587
2588 case 'S':
2589 case 'T':
2590 case 'U':
2591 /* various width encodings */
2592 {
2593 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2594 int limit;
2595 unsigned low, high;
2596
2597 c++;
2598 if (*c >= '0' && *c <= '9')
2599 limit = *c - '0';
2600 else if (*c >= 'a' && *c <= 'f')
2601 limit = *c - 'a' + 10;
2602 else
2603 abort ();
2604 low = limit >> 2;
2605 high = limit & 3;
2606
2607 if (value < low || value > high)
2608 func (stream, "<illegal width %d>", base << value);
2609 else
2610 func (stream, "%d", base << value);
2611 }
2612 break;
2613 case 'R':
2614 if (given & (1 << 6))
2615 goto Q;
2616 /* FALLTHROUGH */
2617 case 'D':
2618 func (stream, "d%ld", value);
2619 break;
2620 case 'Q':
2621 Q:
2622 if (value & 1)
2623 func (stream, "<illegal reg q%ld.5>", value >> 1);
2624 else
2625 func (stream, "q%ld", value >> 1);
2626 break;
2627
2628 case '`':
2629 c++;
2630 if (value == 0)
2631 func (stream, "%c", *c);
2632 break;
2633 case '\'':
2634 c++;
2635 if (value == ((1ul << width) - 1))
2636 func (stream, "%c", *c);
2637 break;
2638 case '?':
2639 func (stream, "%c", c[(1 << width) - (int)value]);
2640 c += 1 << width;
2641 break;
2642 default:
2643 abort ();
2644 }
2645 break;
2646
2647 default:
2648 abort ();
2649 }
2650 }
2651 }
2652 else
2653 func (stream, "%c", *c);
2654 }
2655 return true;
2656 }
2657 }
2658 return false;
2659 }
2660
2661 /* Print one ARM instruction from PC on INFO->STREAM. */
2662
2663 static void
2664 print_insn_arm_internal (bfd_vma pc, struct disassemble_info *info, long given)
2665 {
2666 const struct opcode32 *insn;
2667 void *stream = info->stream;
2668 fprintf_function func = info->fprintf_func;
2669
2670 if (print_insn_coprocessor (pc, info, given, false))
2671 return;
2672
2673 if (print_insn_neon (info, given, false))
2674 return;
2675
2676 for (insn = arm_opcodes; insn->assembler; insn++)
2677 {
2678 if (insn->value == FIRST_IWMMXT_INSN
2679 && info->mach != bfd_mach_arm_XScale
2680 && info->mach != bfd_mach_arm_iWMMXt)
2681 insn = insn + IWMMXT_INSN_COUNT;
2682
2683 if ((given & insn->mask) == insn->value
2684 /* Special case: an instruction with all bits set in the condition field
2685 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
2686 or by the catchall at the end of the table. */
2687 && ((given & 0xF0000000) != 0xF0000000
2688 || (insn->mask & 0xF0000000) == 0xF0000000
2689 || (insn->mask == 0 && insn->value == 0)))
2690 {
2691 const char *c;
2692
2693 for (c = insn->assembler; *c; c++)
2694 {
2695 if (*c == '%')
2696 {
2697 switch (*++c)
2698 {
2699 case '%':
2700 func (stream, "%%");
2701 break;
2702
2703 case 'a':
2704 print_arm_address (pc, info, given);
2705 break;
2706
2707 case 'P':
2708 /* Set P address bit and use normal address
2709 printing routine. */
2710 print_arm_address (pc, info, given | (1 << 24));
2711 break;
2712
2713 case 's':
2714 if ((given & 0x004f0000) == 0x004f0000)
2715 {
2716 /* PC relative with immediate offset. */
2717 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2718
2719 if ((given & 0x00800000) == 0)
2720 offset = -offset;
2721
2722 func (stream, "[pc, #%d]\t; ", offset);
2723 info->print_address_func (offset + pc + 8, info);
2724 }
2725 else
2726 {
2727 func (stream, "[%s",
2728 arm_regnames[(given >> 16) & 0xf]);
2729 if ((given & 0x01000000) != 0)
2730 {
2731 /* Pre-indexed. */
2732 if ((given & 0x00400000) == 0x00400000)
2733 {
2734 /* Immediate. */
2735 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2736 if (offset)
2737 func (stream, ", #%s%d",
2738 (((given & 0x00800000) == 0)
2739 ? "-" : ""), offset);
2740 }
2741 else
2742 {
2743 /* Register. */
2744 func (stream, ", %s%s",
2745 (((given & 0x00800000) == 0)
2746 ? "-" : ""),
2747 arm_regnames[given & 0xf]);
2748 }
2749
2750 func (stream, "]%s",
2751 ((given & 0x00200000) != 0) ? "!" : "");
2752 }
2753 else
2754 {
2755 /* Post-indexed. */
2756 if ((given & 0x00400000) == 0x00400000)
2757 {
2758 /* Immediate. */
2759 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2760 if (offset)
2761 func (stream, "], #%s%d",
2762 (((given & 0x00800000) == 0)
2763 ? "-" : ""), offset);
2764 else
2765 func (stream, "]");
2766 }
2767 else
2768 {
2769 /* Register. */
2770 func (stream, "], %s%s",
2771 (((given & 0x00800000) == 0)
2772 ? "-" : ""),
2773 arm_regnames[given & 0xf]);
2774 }
2775 }
2776 }
2777 break;
2778
2779 case 'b':
2780 {
2781 int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
2782 info->print_address_func (disp*4 + pc + 8, info);
2783 }
2784 break;
2785
2786 case 'c':
2787 if (((given >> 28) & 0xf) != 0xe)
2788 func (stream, "%s",
2789 arm_conditional [(given >> 28) & 0xf]);
2790 break;
2791
2792 case 'm':
2793 {
2794 int started = 0;
2795 int reg;
2796
2797 func (stream, "{");
2798 for (reg = 0; reg < 16; reg++)
2799 if ((given & (1 << reg)) != 0)
2800 {
2801 if (started)
2802 func (stream, ", ");
2803 started = 1;
2804 func (stream, "%s", arm_regnames[reg]);
2805 }
2806 func (stream, "}");
2807 }
2808 break;
2809
2810 case 'q':
2811 arm_decode_shift (given, func, stream, 0);
2812 break;
2813
2814 case 'o':
2815 if ((given & 0x02000000) != 0)
2816 {
2817 int rotate = (given & 0xf00) >> 7;
2818 int immed = (given & 0xff);
2819 immed = (((immed << (32 - rotate))
2820 | (immed >> rotate)) & 0xffffffff);
2821 func (stream, "#%d\t; 0x%x", immed, immed);
2822 }
2823 else
2824 arm_decode_shift (given, func, stream, 1);
2825 break;
2826
2827 case 'p':
2828 if ((given & 0x0000f000) == 0x0000f000)
2829 func (stream, "p");
2830 break;
2831
2832 case 't':
2833 if ((given & 0x01200000) == 0x00200000)
2834 func (stream, "t");
2835 break;
2836
2837 case 'A':
2838 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2839
2840 if ((given & (1 << 24)) != 0)
2841 {
2842 int offset = given & 0xff;
2843
2844 if (offset)
2845 func (stream, ", #%s%d]%s",
2846 ((given & 0x00800000) == 0 ? "-" : ""),
2847 offset * 4,
2848 ((given & 0x00200000) != 0 ? "!" : ""));
2849 else
2850 func (stream, "]");
2851 }
2852 else
2853 {
2854 int offset = given & 0xff;
2855
2856 func (stream, "]");
2857
2858 if (given & (1 << 21))
2859 {
2860 if (offset)
2861 func (stream, ", #%s%d",
2862 ((given & 0x00800000) == 0 ? "-" : ""),
2863 offset * 4);
2864 }
2865 else
2866 func (stream, ", {%d}", offset);
2867 }
2868 break;
2869
2870 case 'B':
2871 /* Print ARM V5 BLX(1) address: pc+25 bits. */
2872 {
2873 bfd_vma address;
2874 bfd_vma offset = 0;
2875
2876 if (given & 0x00800000)
2877 /* Is signed, hi bits should be ones. */
2878 offset = (-1) ^ 0x00ffffff;
2879
2880 /* Offset is (SignExtend(offset field)<<2). */
2881 offset += given & 0x00ffffff;
2882 offset <<= 2;
2883 address = offset + pc + 8;
2884
2885 if (given & 0x01000000)
2886 /* H bit allows addressing to 2-byte boundaries. */
2887 address += 2;
2888
2889 info->print_address_func (address, info);
2890 }
2891 break;
2892
2893 case 'C':
2894 func (stream, "_");
2895 if (given & 0x80000)
2896 func (stream, "f");
2897 if (given & 0x40000)
2898 func (stream, "s");
2899 if (given & 0x20000)
2900 func (stream, "x");
2901 if (given & 0x10000)
2902 func (stream, "c");
2903 break;
2904
2905 case 'U':
2906 switch (given & 0xf)
2907 {
2908 case 0xf: func(stream, "sy"); break;
2909 case 0x7: func(stream, "un"); break;
2910 case 0xe: func(stream, "st"); break;
2911 case 0x6: func(stream, "unst"); break;
2912 default:
2913 func(stream, "#%d", (int)given & 0xf);
2914 break;
2915 }
2916 break;
2917
2918 case '0': case '1': case '2': case '3': case '4':
2919 case '5': case '6': case '7': case '8': case '9':
2920 {
2921 int width;
2922 unsigned long value;
2923
2924 c = arm_decode_bitfield (c, given, &value, &width);
2925
2926 switch (*c)
2927 {
2928 case 'r':
2929 func (stream, "%s", arm_regnames[value]);
2930 break;
2931 case 'd':
2932 func (stream, "%ld", value);
2933 break;
2934 case 'b':
2935 func (stream, "%ld", value * 8);
2936 break;
2937 case 'W':
2938 func (stream, "%ld", value + 1);
2939 break;
2940 case 'x':
2941 func (stream, "0x%08lx", value);
2942
2943 /* Some SWI instructions have special
2944 meanings. */
2945 if ((given & 0x0fffffff) == 0x0FF00000)
2946 func (stream, "\t; IMB");
2947 else if ((given & 0x0fffffff) == 0x0FF00001)
2948 func (stream, "\t; IMBRange");
2949 break;
2950 case 'X':
2951 func (stream, "%01lx", value & 0xf);
2952 break;
2953 case '`':
2954 c++;
2955 if (value == 0)
2956 func (stream, "%c", *c);
2957 break;
2958 case '\'':
2959 c++;
2960 if (value == ((1ul << width) - 1))
2961 func (stream, "%c", *c);
2962 break;
2963 case '?':
2964 func (stream, "%c", c[(1 << width) - (int)value]);
2965 c += 1 << width;
2966 break;
2967 default:
2968 abort ();
2969 }
2970 break;
2971
2972 case 'e':
2973 {
2974 int imm;
2975
2976 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
2977 func (stream, "%d", imm);
2978 }
2979 break;
2980
2981 case 'E':
2982 /* LSB and WIDTH fields of BFI or BFC. The machine-
2983 language instruction encodes LSB and MSB. */
2984 {
2985 long msb = (given & 0x001f0000) >> 16;
2986 long lsb = (given & 0x00000f80) >> 7;
2987
2988 long width = msb - lsb + 1;
2989 if (width > 0)
2990 func (stream, "#%lu, #%lu", lsb, width);
2991 else
2992 func (stream, "(invalid: %lu:%lu)", lsb, msb);
2993 }
2994 break;
2995
2996 case 'V':
2997 /* 16-bit unsigned immediate from a MOVT or MOVW
2998 instruction, encoded in bits 0:11 and 15:19. */
2999 {
3000 long hi = (given & 0x000f0000) >> 4;
3001 long lo = (given & 0x00000fff);
3002 long imm16 = hi | lo;
3003 func (stream, "#%lu\t; 0x%lx", imm16, imm16);
3004 }
3005 break;
3006
3007 default:
3008 abort ();
3009 }
3010 }
3011 }
3012 else
3013 func (stream, "%c", *c);
3014 }
3015 return;
3016 }
3017 }
3018 abort ();
3019 }
3020
3021 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
3022
3023 static void
3024 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
3025 {
3026 const struct opcode16 *insn;
3027 void *stream = info->stream;
3028 fprintf_function func = info->fprintf_func;
3029
3030 for (insn = thumb_opcodes; insn->assembler; insn++)
3031 if ((given & insn->mask) == insn->value)
3032 {
3033 const char *c = insn->assembler;
3034 for (; *c; c++)
3035 {
3036 int domaskpc = 0;
3037 int domasklr = 0;
3038
3039 if (*c != '%')
3040 {
3041 func (stream, "%c", *c);
3042 continue;
3043 }
3044
3045 switch (*++c)
3046 {
3047 case '%':
3048 func (stream, "%%");
3049 break;
3050
3051 case 'c':
3052 if (ifthen_state)
3053 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3054 break;
3055
3056 case 'C':
3057 if (ifthen_state)
3058 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3059 else
3060 func (stream, "s");
3061 break;
3062
3063 case 'I':
3064 {
3065 unsigned int tmp;
3066
3067 ifthen_next_state = given & 0xff;
3068 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3069 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3070 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3071 }
3072 break;
3073
3074 case 'x':
3075 if (ifthen_next_state)
3076 func (stream, "\t; unpredictable branch in IT block\n");
3077 break;
3078
3079 case 'X':
3080 if (ifthen_state)
3081 func (stream, "\t; unpredictable <IT:%s>",
3082 arm_conditional[IFTHEN_COND]);
3083 break;
3084
3085 case 'S':
3086 {
3087 long reg;
3088
3089 reg = (given >> 3) & 0x7;
3090 if (given & (1 << 6))
3091 reg += 8;
3092
3093 func (stream, "%s", arm_regnames[reg]);
3094 }
3095 break;
3096
3097 case 'D':
3098 {
3099 long reg;
3100
3101 reg = given & 0x7;
3102 if (given & (1 << 7))
3103 reg += 8;
3104
3105 func (stream, "%s", arm_regnames[reg]);
3106 }
3107 break;
3108
3109 case 'N':
3110 if (given & (1 << 8))
3111 domasklr = 1;
3112 /* Fall through. */
3113 case 'O':
3114 if (*c == 'O' && (given & (1 << 8)))
3115 domaskpc = 1;
3116 /* Fall through. */
3117 case 'M':
3118 {
3119 int started = 0;
3120 int reg;
3121
3122 func (stream, "{");
3123
3124 /* It would be nice if we could spot
3125 ranges, and generate the rS-rE format: */
3126 for (reg = 0; (reg < 8); reg++)
3127 if ((given & (1 << reg)) != 0)
3128 {
3129 if (started)
3130 func (stream, ", ");
3131 started = 1;
3132 func (stream, "%s", arm_regnames[reg]);
3133 }
3134
3135 if (domasklr)
3136 {
3137 if (started)
3138 func (stream, ", ");
3139 started = 1;
3140 func (stream, "%s", arm_regnames[14] /* "lr" */);
3141 }
3142
3143 if (domaskpc)
3144 {
3145 if (started)
3146 func (stream, ", ");
3147 func (stream, "%s", arm_regnames[15] /* "pc" */);
3148 }
3149
3150 func (stream, "}");
3151 }
3152 break;
3153
3154 case 'b':
3155 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
3156 {
3157 bfd_vma address = (pc + 4
3158 + ((given & 0x00f8) >> 2)
3159 + ((given & 0x0200) >> 3));
3160 info->print_address_func (address, info);
3161 }
3162 break;
3163
3164 case 's':
3165 /* Right shift immediate -- bits 6..10; 1-31 print
3166 as themselves, 0 prints as 32. */
3167 {
3168 long imm = (given & 0x07c0) >> 6;
3169 if (imm == 0)
3170 imm = 32;
3171 func (stream, "#%ld", imm);
3172 }
3173 break;
3174
3175 case '0': case '1': case '2': case '3': case '4':
3176 case '5': case '6': case '7': case '8': case '9':
3177 {
3178 int bitstart = *c++ - '0';
3179 int bitend = 0;
3180
3181 while (*c >= '0' && *c <= '9')
3182 bitstart = (bitstart * 10) + *c++ - '0';
3183
3184 switch (*c)
3185 {
3186 case '-':
3187 {
3188 long reg;
3189
3190 c++;
3191 while (*c >= '0' && *c <= '9')
3192 bitend = (bitend * 10) + *c++ - '0';
3193 if (!bitend)
3194 abort ();
3195 reg = given >> bitstart;
3196 reg &= (2 << (bitend - bitstart)) - 1;
3197 switch (*c)
3198 {
3199 case 'r':
3200 func (stream, "%s", arm_regnames[reg]);
3201 break;
3202
3203 case 'd':
3204 func (stream, "%ld", reg);
3205 break;
3206
3207 case 'H':
3208 func (stream, "%ld", reg << 1);
3209 break;
3210
3211 case 'W':
3212 func (stream, "%ld", reg << 2);
3213 break;
3214
3215 case 'a':
3216 /* PC-relative address -- the bottom two
3217 bits of the address are dropped
3218 before the calculation. */
3219 info->print_address_func
3220 (((pc + 4) & ~3) + (reg << 2), info);
3221 break;
3222
3223 case 'x':
3224 func (stream, "0x%04lx", reg);
3225 break;
3226
3227 case 'B':
3228 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3229 info->print_address_func (reg * 2 + pc + 4, info);
3230 break;
3231
3232 case 'c':
3233 func (stream, "%s", arm_conditional [reg]);
3234 break;
3235
3236 default:
3237 abort ();
3238 }
3239 }
3240 break;
3241
3242 case '\'':
3243 c++;
3244 if ((given & (1 << bitstart)) != 0)
3245 func (stream, "%c", *c);
3246 break;
3247
3248 case '?':
3249 ++c;
3250 if ((given & (1 << bitstart)) != 0)
3251 func (stream, "%c", *c++);
3252 else
3253 func (stream, "%c", *++c);
3254 break;
3255
3256 default:
3257 abort ();
3258 }
3259 }
3260 break;
3261
3262 default:
3263 abort ();
3264 }
3265 }
3266 return;
3267 }
3268
3269 /* No match. */
3270 abort ();
3271 }
3272
3273 /* Return the name of an V7M special register. */
3274 static const char *
3275 psr_name (int regno)
3276 {
3277 switch (regno)
3278 {
3279 case 0: return "APSR";
3280 case 1: return "IAPSR";
3281 case 2: return "EAPSR";
3282 case 3: return "PSR";
3283 case 5: return "IPSR";
3284 case 6: return "EPSR";
3285 case 7: return "IEPSR";
3286 case 8: return "MSP";
3287 case 9: return "PSP";
3288 case 16: return "PRIMASK";
3289 case 17: return "BASEPRI";
3290 case 18: return "BASEPRI_MASK";
3291 case 19: return "FAULTMASK";
3292 case 20: return "CONTROL";
3293 default: return "<unknown>";
3294 }
3295 }
3296
3297 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3298
3299 static void
3300 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3301 {
3302 const struct opcode32 *insn;
3303 void *stream = info->stream;
3304 fprintf_function func = info->fprintf_func;
3305
3306 if (print_insn_coprocessor (pc, info, given, true))
3307 return;
3308
3309 if (print_insn_neon (info, given, true))
3310 return;
3311
3312 for (insn = thumb32_opcodes; insn->assembler; insn++)
3313 if ((given & insn->mask) == insn->value)
3314 {
3315 const char *c = insn->assembler;
3316 for (; *c; c++)
3317 {
3318 if (*c != '%')
3319 {
3320 func (stream, "%c", *c);
3321 continue;
3322 }
3323
3324 switch (*++c)
3325 {
3326 case '%':
3327 func (stream, "%%");
3328 break;
3329
3330 case 'c':
3331 if (ifthen_state)
3332 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3333 break;
3334
3335 case 'x':
3336 if (ifthen_next_state)
3337 func (stream, "\t; unpredictable branch in IT block\n");
3338 break;
3339
3340 case 'X':
3341 if (ifthen_state)
3342 func (stream, "\t; unpredictable <IT:%s>",
3343 arm_conditional[IFTHEN_COND]);
3344 break;
3345
3346 case 'I':
3347 {
3348 unsigned int imm12 = 0;
3349 imm12 |= (given & 0x000000ffu);
3350 imm12 |= (given & 0x00007000u) >> 4;
3351 imm12 |= (given & 0x04000000u) >> 15;
3352 func (stream, "#%u\t; 0x%x", imm12, imm12);
3353 }
3354 break;
3355
3356 case 'M':
3357 {
3358 unsigned int bits = 0, imm, imm8, mod;
3359 bits |= (given & 0x000000ffu);
3360 bits |= (given & 0x00007000u) >> 4;
3361 bits |= (given & 0x04000000u) >> 15;
3362 imm8 = (bits & 0x0ff);
3363 mod = (bits & 0xf00) >> 8;
3364 switch (mod)
3365 {
3366 case 0: imm = imm8; break;
3367 case 1: imm = ((imm8<<16) | imm8); break;
3368 case 2: imm = ((imm8<<24) | (imm8 << 8)); break;
3369 case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3370 default:
3371 mod = (bits & 0xf80) >> 7;
3372 imm8 = (bits & 0x07f) | 0x80;
3373 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3374 }
3375 func (stream, "#%u\t; 0x%x", imm, imm);
3376 }
3377 break;
3378
3379 case 'J':
3380 {
3381 unsigned int imm = 0;
3382 imm |= (given & 0x000000ffu);
3383 imm |= (given & 0x00007000u) >> 4;
3384 imm |= (given & 0x04000000u) >> 15;
3385 imm |= (given & 0x000f0000u) >> 4;
3386 func (stream, "#%u\t; 0x%x", imm, imm);
3387 }
3388 break;
3389
3390 case 'K':
3391 {
3392 unsigned int imm = 0;
3393 imm |= (given & 0x000f0000u) >> 16;
3394 imm |= (given & 0x00000ff0u) >> 0;
3395 imm |= (given & 0x0000000fu) << 12;
3396 func (stream, "#%u\t; 0x%x", imm, imm);
3397 }
3398 break;
3399
3400 case 'S':
3401 {
3402 unsigned int reg = (given & 0x0000000fu);
3403 unsigned int stp = (given & 0x00000030u) >> 4;
3404 unsigned int imm = 0;
3405 imm |= (given & 0x000000c0u) >> 6;
3406 imm |= (given & 0x00007000u) >> 10;
3407
3408 func (stream, "%s", arm_regnames[reg]);
3409 switch (stp)
3410 {
3411 case 0:
3412 if (imm > 0)
3413 func (stream, ", lsl #%u", imm);
3414 break;
3415
3416 case 1:
3417 if (imm == 0)
3418 imm = 32;
3419 func (stream, ", lsr #%u", imm);
3420 break;
3421
3422 case 2:
3423 if (imm == 0)
3424 imm = 32;
3425 func (stream, ", asr #%u", imm);
3426 break;
3427
3428 case 3:
3429 if (imm == 0)
3430 func (stream, ", rrx");
3431 else
3432 func (stream, ", ror #%u", imm);
3433 }
3434 }
3435 break;
3436
3437 case 'a':
3438 {
3439 unsigned int Rn = (given & 0x000f0000) >> 16;
3440 unsigned int U = (given & 0x00800000) >> 23;
3441 unsigned int op = (given & 0x00000f00) >> 8;
3442 unsigned int i12 = (given & 0x00000fff);
3443 unsigned int i8 = (given & 0x000000ff);
3444 bfd_boolean writeback = false, postind = false;
3445 int offset = 0;
3446
3447 func (stream, "[%s", arm_regnames[Rn]);
3448 if (U) /* 12-bit positive immediate offset */
3449 offset = i12;
3450 else if (Rn == 15) /* 12-bit negative immediate offset */
3451 offset = -(int)i12;
3452 else if (op == 0x0) /* shifted register offset */
3453 {
3454 unsigned int Rm = (i8 & 0x0f);
3455 unsigned int sh = (i8 & 0x30) >> 4;
3456 func (stream, ", %s", arm_regnames[Rm]);
3457 if (sh)
3458 func (stream, ", lsl #%u", sh);
3459 func (stream, "]");
3460 break;
3461 }
3462 else switch (op)
3463 {
3464 case 0xE: /* 8-bit positive immediate offset */
3465 offset = i8;
3466 break;
3467
3468 case 0xC: /* 8-bit negative immediate offset */
3469 offset = -i8;
3470 break;
3471
3472 case 0xF: /* 8-bit + preindex with wb */
3473 offset = i8;
3474 writeback = true;
3475 break;
3476
3477 case 0xD: /* 8-bit - preindex with wb */
3478 offset = -i8;
3479 writeback = true;
3480 break;
3481
3482 case 0xB: /* 8-bit + postindex */
3483 offset = i8;
3484 postind = true;
3485 break;
3486
3487 case 0x9: /* 8-bit - postindex */
3488 offset = -i8;
3489 postind = true;
3490 break;
3491
3492 default:
3493 func (stream, ", <undefined>]");
3494 goto skip;
3495 }
3496
3497 if (postind)
3498 func (stream, "], #%d", offset);
3499 else
3500 {
3501 if (offset)
3502 func (stream, ", #%d", offset);
3503 func (stream, writeback ? "]!" : "]");
3504 }
3505
3506 if (Rn == 15)
3507 {
3508 func (stream, "\t; ");
3509 info->print_address_func (((pc + 4) & ~3) + offset, info);
3510 }
3511 }
3512 skip:
3513 break;
3514
3515 case 'A':
3516 {
3517 unsigned int P = (given & 0x01000000) >> 24;
3518 unsigned int U = (given & 0x00800000) >> 23;
3519 unsigned int W = (given & 0x00400000) >> 21;
3520 unsigned int Rn = (given & 0x000f0000) >> 16;
3521 unsigned int off = (given & 0x000000ff);
3522
3523 func (stream, "[%s", arm_regnames[Rn]);
3524 if (P)
3525 {
3526 if (off || !U)
3527 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
3528 func (stream, "]");
3529 if (W)
3530 func (stream, "!");
3531 }
3532 else
3533 {
3534 func (stream, "], ");
3535 if (W)
3536 func (stream, "#%c%u", U ? '+' : '-', off * 4);
3537 else
3538 func (stream, "{%u}", off);
3539 }
3540 }
3541 break;
3542
3543 case 'w':
3544 {
3545 unsigned int Sbit = (given & 0x01000000) >> 24;
3546 unsigned int type = (given & 0x00600000) >> 21;
3547 switch (type)
3548 {
3549 case 0: func (stream, Sbit ? "sb" : "b"); break;
3550 case 1: func (stream, Sbit ? "sh" : "h"); break;
3551 case 2:
3552 if (Sbit)
3553 func (stream, "??");
3554 break;
3555 case 3:
3556 func (stream, "??");
3557 break;
3558 }
3559 }
3560 break;
3561
3562 case 'm':
3563 {
3564 int started = 0;
3565 int reg;
3566
3567 func (stream, "{");
3568 for (reg = 0; reg < 16; reg++)
3569 if ((given & (1 << reg)) != 0)
3570 {
3571 if (started)
3572 func (stream, ", ");
3573 started = 1;
3574 func (stream, "%s", arm_regnames[reg]);
3575 }
3576 func (stream, "}");
3577 }
3578 break;
3579
3580 case 'E':
3581 {
3582 unsigned int msb = (given & 0x0000001f);
3583 unsigned int lsb = 0;
3584 lsb |= (given & 0x000000c0u) >> 6;
3585 lsb |= (given & 0x00007000u) >> 10;
3586 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
3587 }
3588 break;
3589
3590 case 'F':
3591 {
3592 unsigned int width = (given & 0x0000001f) + 1;
3593 unsigned int lsb = 0;
3594 lsb |= (given & 0x000000c0u) >> 6;
3595 lsb |= (given & 0x00007000u) >> 10;
3596 func (stream, "#%u, #%u", lsb, width);
3597 }
3598 break;
3599
3600 case 'b':
3601 {
3602 unsigned int S = (given & 0x04000000u) >> 26;
3603 unsigned int J1 = (given & 0x00002000u) >> 13;
3604 unsigned int J2 = (given & 0x00000800u) >> 11;
3605 int offset = 0;
3606
3607 offset |= !S << 20;
3608 offset |= J2 << 19;
3609 offset |= J1 << 18;
3610 offset |= (given & 0x003f0000) >> 4;
3611 offset |= (given & 0x000007ff) << 1;
3612 offset -= (1 << 20);
3613
3614 info->print_address_func (pc + 4 + offset, info);
3615 }
3616 break;
3617
3618 case 'B':
3619 {
3620 unsigned int S = (given & 0x04000000u) >> 26;
3621 unsigned int I1 = (given & 0x00002000u) >> 13;
3622 unsigned int I2 = (given & 0x00000800u) >> 11;
3623 int offset = 0;
3624
3625 offset |= !S << 24;
3626 offset |= !(I1 ^ S) << 23;
3627 offset |= !(I2 ^ S) << 22;
3628 offset |= (given & 0x03ff0000u) >> 4;
3629 offset |= (given & 0x000007ffu) << 1;
3630 offset -= (1 << 24);
3631 offset += pc + 4;
3632
3633 /* BLX target addresses are always word aligned. */
3634 if ((given & 0x00001000u) == 0)
3635 offset &= ~2u;
3636
3637 info->print_address_func (offset, info);
3638 }
3639 break;
3640
3641 case 's':
3642 {
3643 unsigned int shift = 0;
3644 shift |= (given & 0x000000c0u) >> 6;
3645 shift |= (given & 0x00007000u) >> 10;
3646 if (given & 0x00200000u)
3647 func (stream, ", asr #%u", shift);
3648 else if (shift)
3649 func (stream, ", lsl #%u", shift);
3650 /* else print nothing - lsl #0 */
3651 }
3652 break;
3653
3654 case 'R':
3655 {
3656 unsigned int rot = (given & 0x00000030) >> 4;
3657 if (rot)
3658 func (stream, ", ror #%u", rot * 8);
3659 }
3660 break;
3661
3662 case 'U':
3663 switch (given & 0xf)
3664 {
3665 case 0xf: func(stream, "sy"); break;
3666 case 0x7: func(stream, "un"); break;
3667 case 0xe: func(stream, "st"); break;
3668 case 0x6: func(stream, "unst"); break;
3669 default:
3670 func(stream, "#%d", (int)given & 0xf);
3671 break;
3672 }
3673 break;
3674
3675 case 'C':
3676 if ((given & 0xff) == 0)
3677 {
3678 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
3679 if (given & 0x800)
3680 func (stream, "f");
3681 if (given & 0x400)
3682 func (stream, "s");
3683 if (given & 0x200)
3684 func (stream, "x");
3685 if (given & 0x100)
3686 func (stream, "c");
3687 }
3688 else
3689 {
3690 func (stream, "%s", psr_name (given & 0xff));
3691 }
3692 break;
3693
3694 case 'D':
3695 if ((given & 0xff) == 0)
3696 func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
3697 else
3698 func (stream, "%s", psr_name (given & 0xff));
3699 break;
3700
3701 case '0': case '1': case '2': case '3': case '4':
3702 case '5': case '6': case '7': case '8': case '9':
3703 {
3704 int width;
3705 unsigned long val;
3706
3707 c = arm_decode_bitfield (c, given, &val, &width);
3708
3709 switch (*c)
3710 {
3711 case 'd': func (stream, "%lu", val); break;
3712 case 'W': func (stream, "%lu", val * 4); break;
3713 case 'r': func (stream, "%s", arm_regnames[val]); break;
3714
3715 case 'c':
3716 func (stream, "%s", arm_conditional[val]);
3717 break;
3718
3719 case '\'':
3720 c++;
3721 if (val == ((1ul << width) - 1))
3722 func (stream, "%c", *c);
3723 break;
3724
3725 case '`':
3726 c++;
3727 if (val == 0)
3728 func (stream, "%c", *c);
3729 break;
3730
3731 case '?':
3732 func (stream, "%c", c[(1 << width) - (int)val]);
3733 c += 1 << width;
3734 break;
3735
3736 default:
3737 abort ();
3738 }
3739 }
3740 break;
3741
3742 default:
3743 abort ();
3744 }
3745 }
3746 return;
3747 }
3748
3749 /* No match. */
3750 abort ();
3751 }
3752
3753 /* Print data bytes on INFO->STREAM. */
3754
3755 static void
3756 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info,
3757 long given)
3758 {
3759 switch (info->bytes_per_chunk)
3760 {
3761 case 1:
3762 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
3763 break;
3764 case 2:
3765 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
3766 break;
3767 case 4:
3768 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
3769 break;
3770 default:
3771 abort ();
3772 }
3773 }
3774
3775 /* Search back through the insn stream to determine if this instruction is
3776 conditionally executed. */
3777 static void
3778 find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
3779 bfd_boolean little)
3780 {
3781 unsigned char b[2];
3782 unsigned int insn;
3783 int status;
3784 /* COUNT is twice the number of instructions seen. It will be odd if we
3785 just crossed an instruction boundary. */
3786 int count;
3787 int it_count;
3788 unsigned int seen_it;
3789 bfd_vma addr;
3790
3791 ifthen_address = pc;
3792 ifthen_state = 0;
3793
3794 addr = pc;
3795 count = 1;
3796 it_count = 0;
3797 seen_it = 0;
3798 /* Scan backwards looking for IT instructions, keeping track of where
3799 instruction boundaries are. We don't know if something is actually an
3800 IT instruction until we find a definite instruction boundary. */
3801 for (;;)
3802 {
3803 if (addr == 0 || info->symbol_at_address_func(addr, info))
3804 {
3805 /* A symbol must be on an instruction boundary, and will not
3806 be within an IT block. */
3807 if (seen_it && (count & 1))
3808 break;
3809
3810 return;
3811 }
3812 addr -= 2;
3813 status = info->read_memory_func (addr, (bfd_byte *)b, 2, info);
3814 if (status)
3815 return;
3816
3817 if (little)
3818 insn = (b[0]) | (b[1] << 8);
3819 else
3820 insn = (b[1]) | (b[0] << 8);
3821 if (seen_it)
3822 {
3823 if ((insn & 0xf800) < 0xe800)
3824 {
3825 /* Addr + 2 is an instruction boundary. See if this matches
3826 the expected boundary based on the position of the last
3827 IT candidate. */
3828 if (count & 1)
3829 break;
3830 seen_it = 0;
3831 }
3832 }
3833 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
3834 {
3835 /* This could be an IT instruction. */
3836 seen_it = insn;
3837 it_count = count >> 1;
3838 }
3839 if ((insn & 0xf800) >= 0xe800)
3840 count++;
3841 else
3842 count = (count + 2) | 1;
3843 /* IT blocks contain at most 4 instructions. */
3844 if (count >= 8 && !seen_it)
3845 return;
3846 }
3847 /* We found an IT instruction. */
3848 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
3849 if ((ifthen_state & 0xf) == 0)
3850 ifthen_state = 0;
3851 }
3852
3853 /* NOTE: There are no checks in these routines that
3854 the relevant number of data bytes exist. */
3855
3856 int
3857 print_insn_arm (bfd_vma pc, struct disassemble_info *info)
3858 {
3859 unsigned char b[4];
3860 long given;
3861 int status;
3862 int is_thumb = false;
3863 int is_data = false;
3864 unsigned int size = 4;
3865 void (*printer) (bfd_vma, struct disassemble_info *, long);
3866 int little;
3867
3868 little = (info->endian == BFD_ENDIAN_LITTLE);
3869 is_thumb |= (pc & 1);
3870 pc &= ~(bfd_vma)1;
3871
3872 if (force_thumb)
3873 is_thumb = true;
3874
3875 info->bytes_per_line = 4;
3876
3877 if (is_data)
3878 {
3879 int i;
3880
3881 /* size was already set above. */
3882 info->bytes_per_chunk = size;
3883 printer = print_insn_data;
3884
3885 status = info->read_memory_func (pc, (bfd_byte *)b, size, info);
3886 given = 0;
3887 if (little)
3888 for (i = size - 1; i >= 0; i--)
3889 given = b[i] | (given << 8);
3890 else
3891 for (i = 0; i < (int) size; i++)
3892 given = b[i] | (given << 8);
3893 }
3894 else if (!is_thumb)
3895 {
3896 /* In ARM mode endianness is a straightforward issue: the instruction
3897 is four bytes long and is either ordered 0123 or 3210. */
3898 printer = print_insn_arm_internal;
3899 info->bytes_per_chunk = 4;
3900 size = 4;
3901
3902 status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
3903 if (little)
3904 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
3905 else
3906 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
3907 }
3908 else
3909 {
3910 /* In Thumb mode we have the additional wrinkle of two
3911 instruction lengths. Fortunately, the bits that determine
3912 the length of the current instruction are always to be found
3913 in the first two bytes. */
3914 printer = print_insn_thumb16;
3915 info->bytes_per_chunk = 2;
3916 size = 2;
3917
3918 status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
3919 if (little)
3920 given = (b[0]) | (b[1] << 8);
3921 else
3922 given = (b[1]) | (b[0] << 8);
3923
3924 if (!status)
3925 {
3926 /* These bit patterns signal a four-byte Thumb
3927 instruction. */
3928 if ((given & 0xF800) == 0xF800
3929 || (given & 0xF800) == 0xF000
3930 || (given & 0xF800) == 0xE800)
3931 {
3932 status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info);
3933 if (little)
3934 given = (b[0]) | (b[1] << 8) | (given << 16);
3935 else
3936 given = (b[1]) | (b[0] << 8) | (given << 16);
3937
3938 printer = print_insn_thumb32;
3939 size = 4;
3940 }
3941 }
3942
3943 if (ifthen_address != pc)
3944 find_ifthen_state(pc, info, little);
3945
3946 if (ifthen_state)
3947 {
3948 if ((ifthen_state & 0xf) == 0x8)
3949 ifthen_next_state = 0;
3950 else
3951 ifthen_next_state = (ifthen_state & 0xe0)
3952 | ((ifthen_state & 0xf) << 1);
3953 }
3954 }
3955
3956 if (status)
3957 {
3958 info->memory_error_func (status, pc, info);
3959 return -1;
3960 }
3961 if (info->flags & INSN_HAS_RELOC)
3962 /* If the instruction has a reloc associated with it, then
3963 the offset field in the instruction will actually be the
3964 addend for the reloc. (We are using REL type relocs).
3965 In such cases, we can ignore the pc when computing
3966 addresses, since the addend is not currently pc-relative. */
3967 pc = 0;
3968
3969 /* We include the hexdump of the instruction. The format here
3970 matches that used by objdump and the ARM ARM (in particular,
3971 32 bit Thumb instructions are displayed as pairs of halfwords,
3972 not as a single word.) */
3973 if (is_thumb)
3974 {
3975 if (size == 2)
3976 {
3977 info->fprintf_func(info->stream, "%04lx ",
3978 ((unsigned long)given) & 0xffff);
3979 }
3980 else
3981 {
3982 info->fprintf_func(info->stream, "%04lx %04lx ",
3983 (((unsigned long)given) >> 16) & 0xffff,
3984 ((unsigned long)given) & 0xffff);
3985 }
3986 }
3987 else
3988 {
3989 info->fprintf_func(info->stream, "%08lx ",
3990 ((unsigned long)given) & 0xffffffff);
3991 }
3992
3993 printer (pc, info, given);
3994
3995 if (is_thumb)
3996 {
3997 ifthen_state = ifthen_next_state;
3998 ifthen_address += size;
3999 }
4000 return size;
4001 }
Ray Wang's QEMU Repository