target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  24                               int mmu_idx)
  25 {
  26     LM32CPU *cpu = LM32_CPU(cs);
  27     CPULM32State *env = &cpu->env;
  28     int prot;
  29
  30     address &= TARGET_PAGE_MASK;
  31     prot = PAGE_BITS;
  32     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  33         tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
  34                 TARGET_PAGE_SIZE);
  35     } else {
  36         tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  37     }
  38
  39     return 0;
  40 }
  41
  42 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
  43 {
  44     LM32CPU *cpu = LM32_CPU(cs);
  45
  46     addr &= TARGET_PAGE_MASK;
  47     if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
  48         return addr & 0x7fffffff;
  49     } else {
  50         return addr;
  51     }
  52 }
  53
  54 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
  55 {
  56     cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]);
  57 }
  58
  59 void lm32_breakpoint_remove(CPULM32State *env, int idx)
  60 {
  61     if (!env->cpu_breakpoint[idx]) {
  62         return;
  63     }
  64
  65     cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]);
  66     env->cpu_breakpoint[idx] = NULL;
  67 }
  68
  69 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
  70                             lm32_wp_t wp_type)
  71 {
  72     int flags = 0;
  73
  74     switch (wp_type) {
  75     case LM32_WP_DISABLED:
  76         /* nothing to to */
  77         break;
  78     case LM32_WP_READ:
  79         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
  80         break;
  81     case LM32_WP_WRITE:
  82         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
  83         break;
  84     case LM32_WP_READ_WRITE:
  85         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
  86         break;
  87     }
  88
  89     if (flags != 0) {
  90         cpu_watchpoint_insert(env, address, 1, flags,
  91                 &env->cpu_watchpoint[idx]);
  92     }
  93 }
  94
  95 void lm32_watchpoint_remove(CPULM32State *env, int idx)
  96 {
  97     if (!env->cpu_watchpoint[idx]) {
  98         return;
  99     }
 100
 101     cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]);
 102     env->cpu_watchpoint[idx] = NULL;
 103 }
 104
 105 static bool check_watchpoints(CPULM32State *env)
 106 {
 107     LM32CPU *cpu = lm32_env_get_cpu(env);
 108     int i;
 109
 110     for (i = 0; i < cpu->num_watchpoints; i++) {
 111         if (env->cpu_watchpoint[i] &&
 112                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
 113             return true;
 114         }
 115     }
 116     return false;
 117 }
 118
 119 void lm32_debug_excp_handler(CPULM32State *env)
 120 {
 121     CPUState *cs = CPU(lm32_env_get_cpu(env));
 122     CPUBreakpoint *bp;
 123
 124     if (cs->watchpoint_hit) {
 125         if (cs->watchpoint_hit->flags & BP_CPU) {
 126             cs->watchpoint_hit = NULL;
 127             if (check_watchpoints(env)) {
 128                 raise_exception(env, EXCP_WATCHPOINT);
 129             } else {
 130                 cpu_resume_from_signal(env, NULL);
 131             }
 132         }
 133     } else {
 134         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 135             if (bp->pc == env->pc) {
 136                 if (bp->flags & BP_CPU) {
 137                     raise_exception(env, EXCP_BREAKPOINT);
 138                 }
 139                 break;
 140             }
 141         }
 142     }
 143 }
 144
 145 void lm32_cpu_do_interrupt(CPUState *cs)
 146 {
 147     LM32CPU *cpu = LM32_CPU(cs);
 148     CPULM32State *env = &cpu->env;
 149
 150     qemu_log_mask(CPU_LOG_INT,
 151             "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
 152
 153     switch (cs->exception_index) {
 154     case EXCP_INSN_BUS_ERROR:
 155     case EXCP_DATA_BUS_ERROR:
 156     case EXCP_DIVIDE_BY_ZERO:
 157     case EXCP_IRQ:
 158     case EXCP_SYSTEMCALL:
 159         /* non-debug exceptions */
 160         env->regs[R_EA] = env->pc;
 161         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
 162         env->ie &= ~IE_IE;
 163         if (env->dc & DC_RE) {
 164             env->pc = env->deba + (cs->exception_index * 32);
 165         } else {
 166             env->pc = env->eba + (cs->exception_index * 32);
 167         }
 168         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 169         break;
 170     case EXCP_BREAKPOINT:
 171     case EXCP_WATCHPOINT:
 172         /* debug exceptions */
 173         env->regs[R_BA] = env->pc;
 174         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
 175         env->ie &= ~IE_IE;
 176         env->pc = env->deba + (cs->exception_index * 32);
 177         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 178         break;
 179     default:
 180         cpu_abort(env, "unhandled exception type=%d\n",
 181                   cs->exception_index);
 182         break;
 183     }
 184 }
 185
 186 LM32CPU *cpu_lm32_init(const char *cpu_model)
 187 {
 188     return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
 189 }
 190
 191 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 192  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 193  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 194 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
 195 {
 196     if (value) {
 197         env->flags |= LM32_FLAG_IGNORE_MSB;
 198     } else {
 199         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 200     }
 201 }