target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 1
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     CPU_DoubleU fregs[16]; /* FP registers */
  85     uint32_t aregs[16];    /* access registers */
  86
  87     uint32_t fpc;          /* floating-point control register */
  88     uint32_t cc_op;
  89
  90     float_status fpu_status; /* passed to softfloat lib */
  91
  92     /* The low part of a 128-bit return, or remainder of a divide.  */
  93     uint64_t retxl;
  94
  95     PSW psw;
  96
  97     uint64_t cc_src;
  98     uint64_t cc_dst;
  99     uint64_t cc_vr;
 100
 101     uint64_t __excp_addr;
 102     uint64_t psa;
 103
 104     uint32_t int_pgm_code;
 105     uint32_t int_pgm_ilen;
 106
 107     uint32_t int_svc_code;
 108     uint32_t int_svc_ilen;
 109
 110     uint64_t cregs[16]; /* control registers */
 111
 112     ExtQueue ext_queue[MAX_EXT_QUEUE];
 113     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 114     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 115
 116     int pending_int;
 117     int ext_index;
 118     int io_index[8];
 119     int mchk_index;
 120
 121     uint64_t ckc;
 122     uint64_t cputm;
 123     uint32_t todpr;
 124
 125     uint64_t pfault_token;
 126     uint64_t pfault_compare;
 127     uint64_t pfault_select;
 128
 129     uint64_t gbea;
 130     uint64_t pp;
 131
 132     CPU_COMMON
 133
 134     /* reset does memset(0) up to here */
 135
 136     int cpu_num;
 137     uint8_t *storage_keys;
 138
 139     uint64_t tod_offset;
 140     uint64_t tod_basetime;
 141     QEMUTimer *tod_timer;
 142
 143     QEMUTimer *cpu_timer;
 144 } CPUS390XState;
 145
 146 #include "cpu-qom.h"
 147 #include <sysemu/kvm.h>
 148
 149 /* distinguish between 24 bit and 31 bit addressing */
 150 #define HIGH_ORDER_BIT 0x80000000
 151
 152 /* Interrupt Codes */
 153 /* Program Interrupts */
 154 #define PGM_OPERATION                   0x0001
 155 #define PGM_PRIVILEGED                  0x0002
 156 #define PGM_EXECUTE                     0x0003
 157 #define PGM_PROTECTION                  0x0004
 158 #define PGM_ADDRESSING                  0x0005
 159 #define PGM_SPECIFICATION               0x0006
 160 #define PGM_DATA                        0x0007
 161 #define PGM_FIXPT_OVERFLOW              0x0008
 162 #define PGM_FIXPT_DIVIDE                0x0009
 163 #define PGM_DEC_OVERFLOW                0x000a
 164 #define PGM_DEC_DIVIDE                  0x000b
 165 #define PGM_HFP_EXP_OVERFLOW            0x000c
 166 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 167 #define PGM_HFP_SIGNIFICANCE            0x000e
 168 #define PGM_HFP_DIVIDE                  0x000f
 169 #define PGM_SEGMENT_TRANS               0x0010
 170 #define PGM_PAGE_TRANS                  0x0011
 171 #define PGM_TRANS_SPEC                  0x0012
 172 #define PGM_SPECIAL_OP                  0x0013
 173 #define PGM_OPERAND                     0x0015
 174 #define PGM_TRACE_TABLE                 0x0016
 175 #define PGM_SPACE_SWITCH                0x001c
 176 #define PGM_HFP_SQRT                    0x001d
 177 #define PGM_PC_TRANS_SPEC               0x001f
 178 #define PGM_AFX_TRANS                   0x0020
 179 #define PGM_ASX_TRANS                   0x0021
 180 #define PGM_LX_TRANS                    0x0022
 181 #define PGM_EX_TRANS                    0x0023
 182 #define PGM_PRIM_AUTH                   0x0024
 183 #define PGM_SEC_AUTH                    0x0025
 184 #define PGM_ALET_SPEC                   0x0028
 185 #define PGM_ALEN_SPEC                   0x0029
 186 #define PGM_ALE_SEQ                     0x002a
 187 #define PGM_ASTE_VALID                  0x002b
 188 #define PGM_ASTE_SEQ                    0x002c
 189 #define PGM_EXT_AUTH                    0x002d
 190 #define PGM_STACK_FULL                  0x0030
 191 #define PGM_STACK_EMPTY                 0x0031
 192 #define PGM_STACK_SPEC                  0x0032
 193 #define PGM_STACK_TYPE                  0x0033
 194 #define PGM_STACK_OP                    0x0034
 195 #define PGM_ASCE_TYPE                   0x0038
 196 #define PGM_REG_FIRST_TRANS             0x0039
 197 #define PGM_REG_SEC_TRANS               0x003a
 198 #define PGM_REG_THIRD_TRANS             0x003b
 199 #define PGM_MONITOR                     0x0040
 200 #define PGM_PER                         0x0080
 201 #define PGM_CRYPTO                      0x0119
 202
 203 /* External Interrupts */
 204 #define EXT_INTERRUPT_KEY               0x0040
 205 #define EXT_CLOCK_COMP                  0x1004
 206 #define EXT_CPU_TIMER                   0x1005
 207 #define EXT_MALFUNCTION                 0x1200
 208 #define EXT_EMERGENCY                   0x1201
 209 #define EXT_EXTERNAL_CALL               0x1202
 210 #define EXT_ETR                         0x1406
 211 #define EXT_SERVICE                     0x2401
 212 #define EXT_VIRTIO                      0x2603
 213
 214 /* PSW defines */
 215 #undef PSW_MASK_PER
 216 #undef PSW_MASK_DAT
 217 #undef PSW_MASK_IO
 218 #undef PSW_MASK_EXT
 219 #undef PSW_MASK_KEY
 220 #undef PSW_SHIFT_KEY
 221 #undef PSW_MASK_MCHECK
 222 #undef PSW_MASK_WAIT
 223 #undef PSW_MASK_PSTATE
 224 #undef PSW_MASK_ASC
 225 #undef PSW_MASK_CC
 226 #undef PSW_MASK_PM
 227 #undef PSW_MASK_64
 228 #undef PSW_MASK_32
 229 #undef PSW_MASK_ESA_ADDR
 230
 231 #define PSW_MASK_PER            0x4000000000000000ULL
 232 #define PSW_MASK_DAT            0x0400000000000000ULL
 233 #define PSW_MASK_IO             0x0200000000000000ULL
 234 #define PSW_MASK_EXT            0x0100000000000000ULL
 235 #define PSW_MASK_KEY            0x00F0000000000000ULL
 236 #define PSW_SHIFT_KEY           56
 237 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 238 #define PSW_MASK_WAIT           0x0002000000000000ULL
 239 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 240 #define PSW_MASK_ASC            0x0000C00000000000ULL
 241 #define PSW_MASK_CC             0x0000300000000000ULL
 242 #define PSW_MASK_PM             0x00000F0000000000ULL
 243 #define PSW_MASK_64             0x0000000100000000ULL
 244 #define PSW_MASK_32             0x0000000080000000ULL
 245 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 246
 247 #undef PSW_ASC_PRIMARY
 248 #undef PSW_ASC_ACCREG
 249 #undef PSW_ASC_SECONDARY
 250 #undef PSW_ASC_HOME
 251
 252 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 253 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 254 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 255 #define PSW_ASC_HOME            0x0000C00000000000ULL
 256
 257 /* tb flags */
 258
 259 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 260 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 261 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 262 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 263 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 264 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 265 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 266 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 267 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 268 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 269 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 270 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 271 #define FLAG_MASK_32            0x00001000
 272
 273 /* Control register 0 bits */
 274 #define CR0_EDAT                0x0000000000800000ULL
 275
 276 static inline int cpu_mmu_index (CPUS390XState *env)
 277 {
 278     if (env->psw.mask & PSW_MASK_PSTATE) {
 279         return 1;
 280     }
 281
 282     return 0;
 283 }
 284
 285 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 286                                         target_ulong *cs_base, int *flags)
 287 {
 288     *pc = env->psw.addr;
 289     *cs_base = 0;
 290     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 291              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 292 }
 293
 294 /* While the PoO talks about ILC (a number between 1-3) what is actually
 295    stored in LowCore is shifted left one bit (an even between 2-6).  As
 296    this is the actual length of the insn and therefore more useful, that
 297    is what we want to pass around and manipulate.  To make sure that we
 298    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 299 static inline int get_ilen(uint8_t opc)
 300 {
 301     switch (opc >> 6) {
 302     case 0:
 303         return 2;
 304     case 1:
 305     case 2:
 306         return 4;
 307     default:
 308         return 6;
 309     }
 310 }
 311
 312 #ifndef CONFIG_USER_ONLY
 313 /* In several cases of runtime exceptions, we havn't recorded the true
 314    instruction length.  Use these codes when raising exceptions in order
 315    to re-compute the length by examining the insn in memory.  */
 316 #define ILEN_LATER       0x20
 317 #define ILEN_LATER_INC   0x21
 318 #endif
 319
 320 S390CPU *cpu_s390x_init(const char *cpu_model);
 321 void s390x_translate_init(void);
 322 int cpu_s390x_exec(CPUS390XState *s);
 323
 324 /* you can call this signal handler from your SIGBUS and SIGSEGV
 325    signal handlers to inform the virtual CPU of exceptions. non zero
 326    is returned if the signal was handled by the virtual CPU.  */
 327 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 328                            void *puc);
 329 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 330                               int mmu_idx);
 331
 332 #include "ioinst.h"
 333
 334 #ifndef CONFIG_USER_ONLY
 335 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 336                                    int is_write);
 337 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 338                                     int is_write);
 339 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 340 {
 341     hwaddr addr = 0;
 342     uint8_t reg;
 343
 344     reg = ipb >> 28;
 345     if (reg > 0) {
 346         addr = env->regs[reg];
 347     }
 348     addr += (ipb >> 16) & 0xfff;
 349
 350     return addr;
 351 }
 352
 353 /* Base/displacement are at the same locations. */
 354 #define decode_basedisp_rs decode_basedisp_s
 355
 356 void s390x_tod_timer(void *opaque);
 357 void s390x_cpu_timer(void *opaque);
 358
 359 int s390_virtio_hypercall(CPUS390XState *env);
 360 void s390_virtio_irq(int config_change, uint64_t token);
 361
 362 #ifdef CONFIG_KVM
 363 void kvm_s390_reset_vcpu(S390CPU *cpu);
 364 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 365 void kvm_s390_service_interrupt(uint32_t parm);
 366 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 367 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 368 #else
 369 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
 370 {
 371 }
 372 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 373 {
 374 }
 375 static inline void kvm_s390_service_interrupt(uint32_t parm)
 376 {
 377 }
 378 #endif
 379 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 380 void s390_add_running_cpu(S390CPU *cpu);
 381 unsigned s390_del_running_cpu(S390CPU *cpu);
 382
 383 /* service interrupts are floating therefore we must not pass an cpustate */
 384 void s390_sclp_extint(uint32_t parm);
 385
 386 /* from s390-virtio-bus */
 387 extern const hwaddr virtio_size;
 388
 389 #else
 390 static inline void s390_add_running_cpu(S390CPU *cpu)
 391 {
 392 }
 393
 394 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
 395 {
 396     return 0;
 397 }
 398 #endif
 399 void cpu_lock(void);
 400 void cpu_unlock(void);
 401
 402 typedef struct SubchDev SubchDev;
 403
 404 #ifndef CONFIG_USER_ONLY
 405 extern void io_subsystem_reset(void);
 406 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 407                          uint16_t schid);
 408 bool css_subch_visible(SubchDev *sch);
 409 void css_conditional_io_interrupt(SubchDev *sch);
 410 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 411 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 412 int css_do_msch(SubchDev *sch, SCHIB *schib);
 413 int css_do_xsch(SubchDev *sch);
 414 int css_do_csch(SubchDev *sch);
 415 int css_do_hsch(SubchDev *sch);
 416 int css_do_ssch(SubchDev *sch, ORB *orb);
 417 int css_do_tsch(SubchDev *sch, IRB *irb);
 418 int css_do_stcrw(CRW *crw);
 419 int css_do_tpi(IOIntCode *int_code, int lowcore);
 420 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 421                          int rfmt, void *buf);
 422 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 423 int css_enable_mcsse(void);
 424 int css_enable_mss(void);
 425 int css_do_rsch(SubchDev *sch);
 426 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 427 bool css_present(uint8_t cssid);
 428 #else
 429 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 430                                        uint16_t schid)
 431 {
 432     return NULL;
 433 }
 434 static inline bool css_subch_visible(SubchDev *sch)
 435 {
 436     return false;
 437 }
 438 static inline void css_conditional_io_interrupt(SubchDev *sch)
 439 {
 440 }
 441 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
 442 {
 443     return -ENODEV;
 444 }
 445 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
 446 {
 447     return true;
 448 }
 449 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
 450 {
 451     return -ENODEV;
 452 }
 453 static inline int css_do_xsch(SubchDev *sch)
 454 {
 455     return -ENODEV;
 456 }
 457 static inline int css_do_csch(SubchDev *sch)
 458 {
 459     return -ENODEV;
 460 }
 461 static inline int css_do_hsch(SubchDev *sch)
 462 {
 463     return -ENODEV;
 464 }
 465 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
 466 {
 467     return -ENODEV;
 468 }
 469 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
 470 {
 471     return -ENODEV;
 472 }
 473 static inline int css_do_stcrw(CRW *crw)
 474 {
 475     return 1;
 476 }
 477 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
 478 {
 479     return 0;
 480 }
 481 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
 482                                        int rfmt, uint8_t l_chpid, void *buf)
 483 {
 484     return 0;
 485 }
 486 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
 487 {
 488 }
 489 static inline int css_enable_mss(void)
 490 {
 491     return -EINVAL;
 492 }
 493 static inline int css_enable_mcsse(void)
 494 {
 495     return -EINVAL;
 496 }
 497 static inline int css_do_rsch(SubchDev *sch)
 498 {
 499     return -ENODEV;
 500 }
 501 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
 502 {
 503     return -ENODEV;
 504 }
 505 static inline bool css_present(uint8_t cssid)
 506 {
 507     return false;
 508 }
 509 #endif
 510
 511 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 512 #define cpu_exec cpu_s390x_exec
 513 #define cpu_gen_code cpu_s390x_gen_code
 514 #define cpu_signal_handler cpu_s390x_signal_handler
 515
 516 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 517 #define cpu_list s390_cpu_list
 518
 519 #include "exec/exec-all.h"
 520
 521 #define EXCP_EXT 1 /* external interrupt */
 522 #define EXCP_SVC 2 /* supervisor call (syscall) */
 523 #define EXCP_PGM 3 /* program interruption */
 524 #define EXCP_IO  7 /* I/O interrupt */
 525 #define EXCP_MCHK 8 /* machine check */
 526
 527 #define INTERRUPT_EXT        (1 << 0)
 528 #define INTERRUPT_TOD        (1 << 1)
 529 #define INTERRUPT_CPUTIMER   (1 << 2)
 530 #define INTERRUPT_IO         (1 << 3)
 531 #define INTERRUPT_MCHK       (1 << 4)
 532
 533 /* Program Status Word.  */
 534 #define S390_PSWM_REGNUM 0
 535 #define S390_PSWA_REGNUM 1
 536 /* General Purpose Registers.  */
 537 #define S390_R0_REGNUM 2
 538 #define S390_R1_REGNUM 3
 539 #define S390_R2_REGNUM 4
 540 #define S390_R3_REGNUM 5
 541 #define S390_R4_REGNUM 6
 542 #define S390_R5_REGNUM 7
 543 #define S390_R6_REGNUM 8
 544 #define S390_R7_REGNUM 9
 545 #define S390_R8_REGNUM 10
 546 #define S390_R9_REGNUM 11
 547 #define S390_R10_REGNUM 12
 548 #define S390_R11_REGNUM 13
 549 #define S390_R12_REGNUM 14
 550 #define S390_R13_REGNUM 15
 551 #define S390_R14_REGNUM 16
 552 #define S390_R15_REGNUM 17
 553 /* Access Registers.  */
 554 #define S390_A0_REGNUM 18
 555 #define S390_A1_REGNUM 19
 556 #define S390_A2_REGNUM 20
 557 #define S390_A3_REGNUM 21
 558 #define S390_A4_REGNUM 22
 559 #define S390_A5_REGNUM 23
 560 #define S390_A6_REGNUM 24
 561 #define S390_A7_REGNUM 25
 562 #define S390_A8_REGNUM 26
 563 #define S390_A9_REGNUM 27
 564 #define S390_A10_REGNUM 28
 565 #define S390_A11_REGNUM 29
 566 #define S390_A12_REGNUM 30
 567 #define S390_A13_REGNUM 31
 568 #define S390_A14_REGNUM 32
 569 #define S390_A15_REGNUM 33
 570 /* Floating Point Control Word.  */
 571 #define S390_FPC_REGNUM 34
 572 /* Floating Point Registers.  */
 573 #define S390_F0_REGNUM 35
 574 #define S390_F1_REGNUM 36
 575 #define S390_F2_REGNUM 37
 576 #define S390_F3_REGNUM 38
 577 #define S390_F4_REGNUM 39
 578 #define S390_F5_REGNUM 40
 579 #define S390_F6_REGNUM 41
 580 #define S390_F7_REGNUM 42
 581 #define S390_F8_REGNUM 43
 582 #define S390_F9_REGNUM 44
 583 #define S390_F10_REGNUM 45
 584 #define S390_F11_REGNUM 46
 585 #define S390_F12_REGNUM 47
 586 #define S390_F13_REGNUM 48
 587 #define S390_F14_REGNUM 49
 588 #define S390_F15_REGNUM 50
 589 /* Total.  */
 590 #define S390_NUM_REGS 51
 591
 592 /* CC optimization */
 593
 594 enum cc_op {
 595     CC_OP_CONST0 = 0,           /* CC is 0 */
 596     CC_OP_CONST1,               /* CC is 1 */
 597     CC_OP_CONST2,               /* CC is 2 */
 598     CC_OP_CONST3,               /* CC is 3 */
 599
 600     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 601     CC_OP_STATIC,               /* CC value is env->cc_op */
 602
 603     CC_OP_NZ,                   /* env->cc_dst != 0 */
 604     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 605     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 606     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 607     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 608     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 609     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 610
 611     CC_OP_ADD_64,               /* overflow on add (64bit) */
 612     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 613     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 614     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 615     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 616     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 617     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 618     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 619
 620     CC_OP_ADD_32,               /* overflow on add (32bit) */
 621     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 622     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 623     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 624     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 625     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 626     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 627     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 628
 629     CC_OP_COMP_32,              /* complement */
 630     CC_OP_COMP_64,              /* complement */
 631
 632     CC_OP_TM_32,                /* test under mask (32bit) */
 633     CC_OP_TM_64,                /* test under mask (64bit) */
 634
 635     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 636     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 637     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 638
 639     CC_OP_ICM,                  /* insert characters under mask */
 640     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 641     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 642     CC_OP_FLOGR,                /* find leftmost one */
 643     CC_OP_MAX
 644 };
 645
 646 static const char *cc_names[] = {
 647     [CC_OP_CONST0]    = "CC_OP_CONST0",
 648     [CC_OP_CONST1]    = "CC_OP_CONST1",
 649     [CC_OP_CONST2]    = "CC_OP_CONST2",
 650     [CC_OP_CONST3]    = "CC_OP_CONST3",
 651     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 652     [CC_OP_STATIC]    = "CC_OP_STATIC",
 653     [CC_OP_NZ]        = "CC_OP_NZ",
 654     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 655     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 656     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 657     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 658     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 659     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 660     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 661     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 662     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 663     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 664     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 665     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 666     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 667     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 668     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 669     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 670     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 671     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 672     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 673     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 674     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 675     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 676     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 677     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 678     [CC_OP_TM_32]     = "CC_OP_TM_32",
 679     [CC_OP_TM_64]     = "CC_OP_TM_64",
 680     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 681     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 682     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 683     [CC_OP_ICM]       = "CC_OP_ICM",
 684     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 685     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 686     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 687 };
 688
 689 static inline const char *cc_name(int cc_op)
 690 {
 691     return cc_names[cc_op];
 692 }
 693
 694 static inline void setcc(S390CPU *cpu, uint64_t cc)
 695 {
 696     CPUS390XState *env = &cpu->env;
 697
 698     env->psw.mask &= ~(3ull << 44);
 699     env->psw.mask |= (cc & 3) << 44;
 700 }
 701
 702 typedef struct LowCore
 703 {
 704     /* prefix area: defined by architecture */
 705     uint32_t        ccw1[2];                  /* 0x000 */
 706     uint32_t        ccw2[4];                  /* 0x008 */
 707     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 708     uint32_t        ext_params;               /* 0x080 */
 709     uint16_t        cpu_addr;                 /* 0x084 */
 710     uint16_t        ext_int_code;             /* 0x086 */
 711     uint16_t        svc_ilen;                 /* 0x088 */
 712     uint16_t        svc_code;                 /* 0x08a */
 713     uint16_t        pgm_ilen;                 /* 0x08c */
 714     uint16_t        pgm_code;                 /* 0x08e */
 715     uint32_t        data_exc_code;            /* 0x090 */
 716     uint16_t        mon_class_num;            /* 0x094 */
 717     uint16_t        per_perc_atmid;           /* 0x096 */
 718     uint64_t        per_address;              /* 0x098 */
 719     uint8_t         exc_access_id;            /* 0x0a0 */
 720     uint8_t         per_access_id;            /* 0x0a1 */
 721     uint8_t         op_access_id;             /* 0x0a2 */
 722     uint8_t         ar_access_id;             /* 0x0a3 */
 723     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 724     uint64_t        trans_exc_code;           /* 0x0a8 */
 725     uint64_t        monitor_code;             /* 0x0b0 */
 726     uint16_t        subchannel_id;            /* 0x0b8 */
 727     uint16_t        subchannel_nr;            /* 0x0ba */
 728     uint32_t        io_int_parm;              /* 0x0bc */
 729     uint32_t        io_int_word;              /* 0x0c0 */
 730     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 731     uint32_t        stfl_fac_list;            /* 0x0c8 */
 732     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 733     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 734     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 735     uint32_t        external_damage_code;     /* 0x0f4 */
 736     uint64_t        failing_storage_address;  /* 0x0f8 */
 737     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 738     PSW             restart_old_psw;          /* 0x120 */
 739     PSW             external_old_psw;         /* 0x130 */
 740     PSW             svc_old_psw;              /* 0x140 */
 741     PSW             program_old_psw;          /* 0x150 */
 742     PSW             mcck_old_psw;             /* 0x160 */
 743     PSW             io_old_psw;               /* 0x170 */
 744     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 745     PSW             restart_psw;              /* 0x1a0 */
 746     PSW             external_new_psw;         /* 0x1b0 */
 747     PSW             svc_new_psw;              /* 0x1c0 */
 748     PSW             program_new_psw;          /* 0x1d0 */
 749     PSW             mcck_new_psw;             /* 0x1e0 */
 750     PSW             io_new_psw;               /* 0x1f0 */
 751     PSW             return_psw;               /* 0x200 */
 752     uint8_t         irb[64];                  /* 0x210 */
 753     uint64_t        sync_enter_timer;         /* 0x250 */
 754     uint64_t        async_enter_timer;        /* 0x258 */
 755     uint64_t        exit_timer;               /* 0x260 */
 756     uint64_t        last_update_timer;        /* 0x268 */
 757     uint64_t        user_timer;               /* 0x270 */
 758     uint64_t        system_timer;             /* 0x278 */
 759     uint64_t        last_update_clock;        /* 0x280 */
 760     uint64_t        steal_clock;              /* 0x288 */
 761     PSW             return_mcck_psw;          /* 0x290 */
 762     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 763     /* System info area */
 764     uint64_t        save_area[16];            /* 0xc00 */
 765     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 766     uint64_t        kernel_stack;             /* 0xd40 */
 767     uint64_t        thread_info;              /* 0xd48 */
 768     uint64_t        async_stack;              /* 0xd50 */
 769     uint64_t        kernel_asce;              /* 0xd58 */
 770     uint64_t        user_asce;                /* 0xd60 */
 771     uint64_t        panic_stack;              /* 0xd68 */
 772     uint64_t        user_exec_asce;           /* 0xd70 */
 773     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 774
 775     /* SMP info area: defined by DJB */
 776     uint64_t        clock_comparator;         /* 0xdc0 */
 777     uint64_t        ext_call_fast;            /* 0xdc8 */
 778     uint64_t        percpu_offset;            /* 0xdd0 */
 779     uint64_t        current_task;             /* 0xdd8 */
 780     uint32_t        softirq_pending;          /* 0xde0 */
 781     uint32_t        pad_0x0de4;               /* 0xde4 */
 782     uint64_t        int_clock;                /* 0xde8 */
 783     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 784
 785     /* 0xe00 is used as indicator for dump tools */
 786     /* whether the kernel died with panic() or not */
 787     uint32_t        panic_magic;              /* 0xe00 */
 788
 789     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 790
 791     /* 64 bit extparam used for pfault, diag 250 etc  */
 792     uint64_t        ext_params2;               /* 0x11B8 */
 793
 794     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 795
 796     /* System info area */
 797
 798     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 799     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 800     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 801     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 802     uint32_t        prefixreg_save_area;       /* 0x1318 */
 803     uint32_t        fpt_creg_save_area;        /* 0x131c */
 804     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 805     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 806     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 807     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 808     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 809     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 810     uint64_t        cregs_save_area[16];       /* 0x1380 */
 811
 812     /* align to the top of the prefix area */
 813
 814     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 815 } QEMU_PACKED LowCore;
 816
 817 /* STSI */
 818 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 819 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 820 #define STSI_LEVEL_1            0x0000000010000000ULL
 821 #define STSI_LEVEL_2            0x0000000020000000ULL
 822 #define STSI_LEVEL_3            0x0000000030000000ULL
 823 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 824 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 825 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 826 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 827
 828 /* Basic Machine Configuration */
 829 struct sysib_111 {
 830     uint32_t res1[8];
 831     uint8_t  manuf[16];
 832     uint8_t  type[4];
 833     uint8_t  res2[12];
 834     uint8_t  model[16];
 835     uint8_t  sequence[16];
 836     uint8_t  plant[4];
 837     uint8_t  res3[156];
 838 };
 839
 840 /* Basic Machine CPU */
 841 struct sysib_121 {
 842     uint32_t res1[80];
 843     uint8_t  sequence[16];
 844     uint8_t  plant[4];
 845     uint8_t  res2[2];
 846     uint16_t cpu_addr;
 847     uint8_t  res3[152];
 848 };
 849
 850 /* Basic Machine CPUs */
 851 struct sysib_122 {
 852     uint8_t res1[32];
 853     uint32_t capability;
 854     uint16_t total_cpus;
 855     uint16_t active_cpus;
 856     uint16_t standby_cpus;
 857     uint16_t reserved_cpus;
 858     uint16_t adjustments[2026];
 859 };
 860
 861 /* LPAR CPU */
 862 struct sysib_221 {
 863     uint32_t res1[80];
 864     uint8_t  sequence[16];
 865     uint8_t  plant[4];
 866     uint16_t cpu_id;
 867     uint16_t cpu_addr;
 868     uint8_t  res3[152];
 869 };
 870
 871 /* LPAR CPUs */
 872 struct sysib_222 {
 873     uint32_t res1[32];
 874     uint16_t lpar_num;
 875     uint8_t  res2;
 876     uint8_t  lcpuc;
 877     uint16_t total_cpus;
 878     uint16_t conf_cpus;
 879     uint16_t standby_cpus;
 880     uint16_t reserved_cpus;
 881     uint8_t  name[8];
 882     uint32_t caf;
 883     uint8_t  res3[16];
 884     uint16_t dedicated_cpus;
 885     uint16_t shared_cpus;
 886     uint8_t  res4[180];
 887 };
 888
 889 /* VM CPUs */
 890 struct sysib_322 {
 891     uint8_t  res1[31];
 892     uint8_t  count;
 893     struct {
 894         uint8_t  res2[4];
 895         uint16_t total_cpus;
 896         uint16_t conf_cpus;
 897         uint16_t standby_cpus;
 898         uint16_t reserved_cpus;
 899         uint8_t  name[8];
 900         uint32_t caf;
 901         uint8_t  cpi[16];
 902         uint8_t  res3[24];
 903     } vm[8];
 904     uint8_t res4[3552];
 905 };
 906
 907 /* MMU defines */
 908 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 909 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 910 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 911 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 912 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 913 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 914 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 915 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 916 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 917 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 918 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 919 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 920
 921 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 922 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 923 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 924 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 925 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 926 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 927 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 928
 929 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 930 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 931 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 932 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 933
 934 #define _PAGE_RO        0x200            /* HW read-only bit  */
 935 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 936
 937 #define SK_C                    (0x1 << 1)
 938 #define SK_R                    (0x1 << 2)
 939 #define SK_F                    (0x1 << 3)
 940 #define SK_ACC_MASK             (0xf << 4)
 941
 942 #define SIGP_SENSE             0x01
 943 #define SIGP_EXTERNAL_CALL     0x02
 944 #define SIGP_EMERGENCY         0x03
 945 #define SIGP_START             0x04
 946 #define SIGP_STOP              0x05
 947 #define SIGP_RESTART           0x06
 948 #define SIGP_STOP_STORE_STATUS 0x09
 949 #define SIGP_INITIAL_CPU_RESET 0x0b
 950 #define SIGP_CPU_RESET         0x0c
 951 #define SIGP_SET_PREFIX        0x0d
 952 #define SIGP_STORE_STATUS_ADDR 0x0e
 953 #define SIGP_SET_ARCH          0x12
 954
 955 /* cpu status bits */
 956 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 957 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 958 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 959 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 960 #define SIGP_STAT_STOPPED           0x00000040UL
 961 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 962 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 963 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 964 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 965 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 966
 967 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 968 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 969                   target_ulong *raddr, int *flags);
 970 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 971 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 972                  uint64_t vr);
 973
 974 #define TARGET_HAS_ICE 1
 975
 976 /* The value of the TOD clock for 1.1.1970. */
 977 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 978
 979 /* Converts ns to s390's clock format */
 980 static inline uint64_t time2tod(uint64_t ns) {
 981     return (ns << 9) / 125;
 982 }
 983
 984 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 985                                   uint64_t param64)
 986 {
 987     CPUS390XState *env = &cpu->env;
 988
 989     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 990         /* ugh - can't queue anymore. Let's drop. */
 991         return;
 992     }
 993
 994     env->ext_index++;
 995     assert(env->ext_index < MAX_EXT_QUEUE);
 996
 997     env->ext_queue[env->ext_index].code = code;
 998     env->ext_queue[env->ext_index].param = param;
 999     env->ext_queue[env->ext_index].param64 = param64;
1000
1001     env->pending_int |= INTERRUPT_EXT;
1002     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1003 }
1004
1005 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1006                                  uint16_t subchannel_number,
1007                                  uint32_t io_int_parm, uint32_t io_int_word)
1008 {
1009     CPUS390XState *env = &cpu->env;
1010     int isc = IO_INT_WORD_ISC(io_int_word);
1011
1012     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1013         /* ugh - can't queue anymore. Let's drop. */
1014         return;
1015     }
1016
1017     env->io_index[isc]++;
1018     assert(env->io_index[isc] < MAX_IO_QUEUE);
1019
1020     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1021     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1022     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1023     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1024
1025     env->pending_int |= INTERRUPT_IO;
1026     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1027 }
1028
1029 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1030 {
1031     CPUS390XState *env = &cpu->env;
1032
1033     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1034         /* ugh - can't queue anymore. Let's drop. */
1035         return;
1036     }
1037
1038     env->mchk_index++;
1039     assert(env->mchk_index < MAX_MCHK_QUEUE);
1040
1041     env->mchk_queue[env->mchk_index].type = 1;
1042
1043     env->pending_int |= INTERRUPT_MCHK;
1044     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1045 }
1046
1047 /* fpu_helper.c */
1048 uint32_t set_cc_nz_f32(float32 v);
1049 uint32_t set_cc_nz_f64(float64 v);
1050 uint32_t set_cc_nz_f128(float128 v);
1051
1052 /* misc_helper.c */
1053 #ifndef CONFIG_USER_ONLY
1054 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1055 #endif
1056 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1057 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1058                                      uintptr_t retaddr);
1059
1060 #ifdef CONFIG_KVM
1061 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1062                            uint16_t subchannel_nr, uint32_t io_int_parm,
1063                            uint32_t io_int_word);
1064 void kvm_s390_crw_mchk(void);
1065 void kvm_s390_enable_css_support(S390CPU *cpu);
1066 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1067                                     int vq, bool assign);
1068 int kvm_s390_cpu_restart(S390CPU *cpu);
1069 void kvm_s390_clear_cmma_callback(void *opaque);
1070 #else
1071 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1072                                         uint16_t subchannel_nr,
1073                                         uint32_t io_int_parm,
1074                                         uint32_t io_int_word)
1075 {
1076 }
1077 static inline void kvm_s390_crw_mchk(void)
1078 {
1079 }
1080 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1081 {
1082 }
1083 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1084                                                   uint32_t sch, int vq,
1085                                                   bool assign)
1086 {
1087     return -ENOSYS;
1088 }
1089 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1090 {
1091     return -ENOSYS;
1092 }
1093 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1094 {
1095 }
1096 #endif
1097
1098 static inline void cmma_reset(S390CPU *cpu)
1099 {
1100     if (kvm_enabled()) {
1101         CPUState *cs = CPU(cpu);
1102         kvm_s390_clear_cmma_callback(cs->kvm_state);
1103     }
1104 }
1105
1106 static inline int s390_cpu_restart(S390CPU *cpu)
1107 {
1108     if (kvm_enabled()) {
1109         return kvm_s390_cpu_restart(cpu);
1110     }
1111     return -ENOSYS;
1112 }
1113
1114 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1115                        uint32_t io_int_parm, uint32_t io_int_word);
1116 void s390_crw_mchk(void);
1117
1118 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1119                                               uint32_t sch_id, int vq,
1120                                               bool assign)
1121 {
1122     if (kvm_enabled()) {
1123         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1124     } else {
1125         return -ENOSYS;
1126     }
1127 }
1128
1129 #endif