target-s390x/ioinst.c

   1 /*
   2  * I/O instructions for S/390
   3  *
   4  * Copyright 2012, 2015 IBM Corp.
   5  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or (at
   8  * your option) any later version. See the COPYING file in the top-level
   9  * directory.
  10  */
  11
  12 #include <sys/types.h>
  13
  14 #include "cpu.h"
  15 #include "ioinst.h"
  16 #include "trace.h"
  17 #include "hw/s390x/s390-pci-bus.h"
  18
  19 int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
  20                                  int *schid)
  21 {
  22     if (!IOINST_SCHID_ONE(value)) {
  23         return -EINVAL;
  24     }
  25     if (!IOINST_SCHID_M(value)) {
  26         if (IOINST_SCHID_CSSID(value)) {
  27             return -EINVAL;
  28         }
  29         *cssid = 0;
  30         *m = 0;
  31     } else {
  32         *cssid = IOINST_SCHID_CSSID(value);
  33         *m = 1;
  34     }
  35     *ssid = IOINST_SCHID_SSID(value);
  36     *schid = IOINST_SCHID_NR(value);
  37     return 0;
  38 }
  39
  40 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1)
  41 {
  42     int cssid, ssid, schid, m;
  43     SubchDev *sch;
  44     int ret = -ENODEV;
  45     int cc;
  46
  47     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  48         program_interrupt(&cpu->env, PGM_OPERAND, 2);
  49         return;
  50     }
  51     trace_ioinst_sch_id("xsch", cssid, ssid, schid);
  52     sch = css_find_subch(m, cssid, ssid, schid);
  53     if (sch && css_subch_visible(sch)) {
  54         ret = css_do_xsch(sch);
  55     }
  56     switch (ret) {
  57     case -ENODEV:
  58         cc = 3;
  59         break;
  60     case -EBUSY:
  61         cc = 2;
  62         break;
  63     case 0:
  64         cc = 0;
  65         break;
  66     default:
  67         cc = 1;
  68         break;
  69     }
  70     setcc(cpu, cc);
  71 }
  72
  73 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1)
  74 {
  75     int cssid, ssid, schid, m;
  76     SubchDev *sch;
  77     int ret = -ENODEV;
  78     int cc;
  79
  80     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  81         program_interrupt(&cpu->env, PGM_OPERAND, 2);
  82         return;
  83     }
  84     trace_ioinst_sch_id("csch", cssid, ssid, schid);
  85     sch = css_find_subch(m, cssid, ssid, schid);
  86     if (sch && css_subch_visible(sch)) {
  87         ret = css_do_csch(sch);
  88     }
  89     if (ret == -ENODEV) {
  90         cc = 3;
  91     } else {
  92         cc = 0;
  93     }
  94     setcc(cpu, cc);
  95 }
  96
  97 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1)
  98 {
  99     int cssid, ssid, schid, m;
 100     SubchDev *sch;
 101     int ret = -ENODEV;
 102     int cc;
 103
 104     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 105         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 106         return;
 107     }
 108     trace_ioinst_sch_id("hsch", cssid, ssid, schid);
 109     sch = css_find_subch(m, cssid, ssid, schid);
 110     if (sch && css_subch_visible(sch)) {
 111         ret = css_do_hsch(sch);
 112     }
 113     switch (ret) {
 114     case -ENODEV:
 115         cc = 3;
 116         break;
 117     case -EBUSY:
 118         cc = 2;
 119         break;
 120     case 0:
 121         cc = 0;
 122         break;
 123     default:
 124         cc = 1;
 125         break;
 126     }
 127     setcc(cpu, cc);
 128 }
 129
 130 static int ioinst_schib_valid(SCHIB *schib)
 131 {
 132     if ((schib->pmcw.flags & PMCW_FLAGS_MASK_INVALID) ||
 133         (schib->pmcw.chars & PMCW_CHARS_MASK_INVALID)) {
 134         return 0;
 135     }
 136     /* Disallow extended measurements for now. */
 137     if (schib->pmcw.chars & PMCW_CHARS_MASK_XMWME) {
 138         return 0;
 139     }
 140     return 1;
 141 }
 142
 143 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 144 {
 145     int cssid, ssid, schid, m;
 146     SubchDev *sch;
 147     SCHIB schib;
 148     uint64_t addr;
 149     int ret = -ENODEV;
 150     int cc;
 151     CPUS390XState *env = &cpu->env;
 152
 153     addr = decode_basedisp_s(env, ipb);
 154     if (addr & 3) {
 155         program_interrupt(env, PGM_SPECIFICATION, 2);
 156         return;
 157     }
 158     if (s390_cpu_virt_mem_read(cpu, addr, &schib, sizeof(schib))) {
 159         return;
 160     }
 161     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 162         !ioinst_schib_valid(&schib)) {
 163         program_interrupt(env, PGM_OPERAND, 2);
 164         return;
 165     }
 166     trace_ioinst_sch_id("msch", cssid, ssid, schid);
 167     sch = css_find_subch(m, cssid, ssid, schid);
 168     if (sch && css_subch_visible(sch)) {
 169         ret = css_do_msch(sch, &schib);
 170     }
 171     switch (ret) {
 172     case -ENODEV:
 173         cc = 3;
 174         break;
 175     case -EBUSY:
 176         cc = 2;
 177         break;
 178     case 0:
 179         cc = 0;
 180         break;
 181     default:
 182         cc = 1;
 183         break;
 184     }
 185     setcc(cpu, cc);
 186 }
 187
 188 static void copy_orb_from_guest(ORB *dest, const ORB *src)
 189 {
 190     dest->intparm = be32_to_cpu(src->intparm);
 191     dest->ctrl0 = be16_to_cpu(src->ctrl0);
 192     dest->lpm = src->lpm;
 193     dest->ctrl1 = src->ctrl1;
 194     dest->cpa = be32_to_cpu(src->cpa);
 195 }
 196
 197 static int ioinst_orb_valid(ORB *orb)
 198 {
 199     if ((orb->ctrl0 & ORB_CTRL0_MASK_INVALID) ||
 200         (orb->ctrl1 & ORB_CTRL1_MASK_INVALID)) {
 201         return 0;
 202     }
 203     if ((orb->cpa & HIGH_ORDER_BIT) != 0) {
 204         return 0;
 205     }
 206     return 1;
 207 }
 208
 209 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 210 {
 211     int cssid, ssid, schid, m;
 212     SubchDev *sch;
 213     ORB orig_orb, orb;
 214     uint64_t addr;
 215     int ret = -ENODEV;
 216     int cc;
 217     CPUS390XState *env = &cpu->env;
 218
 219     addr = decode_basedisp_s(env, ipb);
 220     if (addr & 3) {
 221         program_interrupt(env, PGM_SPECIFICATION, 2);
 222         return;
 223     }
 224     if (s390_cpu_virt_mem_read(cpu, addr, &orig_orb, sizeof(orb))) {
 225         return;
 226     }
 227     copy_orb_from_guest(&orb, &orig_orb);
 228     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 229         !ioinst_orb_valid(&orb)) {
 230         program_interrupt(env, PGM_OPERAND, 2);
 231         return;
 232     }
 233     trace_ioinst_sch_id("ssch", cssid, ssid, schid);
 234     sch = css_find_subch(m, cssid, ssid, schid);
 235     if (sch && css_subch_visible(sch)) {
 236         ret = css_do_ssch(sch, &orb);
 237     }
 238     switch (ret) {
 239     case -ENODEV:
 240         cc = 3;
 241         break;
 242     case -EBUSY:
 243         cc = 2;
 244         break;
 245     case 0:
 246         cc = 0;
 247         break;
 248     default:
 249         cc = 1;
 250         break;
 251     }
 252     setcc(cpu, cc);
 253 }
 254
 255 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb)
 256 {
 257     CRW *crw;
 258     uint64_t addr;
 259     int cc;
 260     hwaddr len = sizeof(*crw);
 261     CPUS390XState *env = &cpu->env;
 262
 263     addr = decode_basedisp_s(env, ipb);
 264     if (addr & 3) {
 265         program_interrupt(env, PGM_SPECIFICATION, 2);
 266         return;
 267     }
 268     crw = s390_cpu_physical_memory_map(env, addr, &len, 1);
 269     if (!crw || len != sizeof(*crw)) {
 270         program_interrupt(env, PGM_ADDRESSING, 2);
 271         goto out;
 272     }
 273     cc = css_do_stcrw(crw);
 274     /* 0 - crw stored, 1 - zeroes stored */
 275     setcc(cpu, cc);
 276
 277 out:
 278     s390_cpu_physical_memory_unmap(env, crw, len, 1);
 279 }
 280
 281 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 282 {
 283     int cssid, ssid, schid, m;
 284     SubchDev *sch;
 285     uint64_t addr;
 286     int cc;
 287     SCHIB schib;
 288     CPUS390XState *env = &cpu->env;
 289
 290     addr = decode_basedisp_s(env, ipb);
 291     if (addr & 3) {
 292         program_interrupt(env, PGM_SPECIFICATION, 2);
 293         return;
 294     }
 295
 296     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 297         /*
 298          * As operand exceptions have a lower priority than access exceptions,
 299          * we check whether the memory area is writeable (injecting the
 300          * access execption if it is not) first.
 301          */
 302         if (!s390_cpu_virt_mem_check_write(cpu, addr, sizeof(schib))) {
 303             program_interrupt(env, PGM_OPERAND, 2);
 304         }
 305         return;
 306     }
 307     trace_ioinst_sch_id("stsch", cssid, ssid, schid);
 308     sch = css_find_subch(m, cssid, ssid, schid);
 309     if (sch) {
 310         if (css_subch_visible(sch)) {
 311             css_do_stsch(sch, &schib);
 312             cc = 0;
 313         } else {
 314             /* Indicate no more subchannels in this css/ss */
 315             cc = 3;
 316         }
 317     } else {
 318         if (css_schid_final(m, cssid, ssid, schid)) {
 319             cc = 3; /* No more subchannels in this css/ss */
 320         } else {
 321             /* Store an empty schib. */
 322             memset(&schib, 0, sizeof(schib));
 323             cc = 0;
 324         }
 325     }
 326     if (cc != 3) {
 327         if (s390_cpu_virt_mem_write(cpu, addr, &schib, sizeof(schib)) != 0) {
 328             return;
 329         }
 330     } else {
 331         /* Access exceptions have a higher priority than cc3 */
 332         if (s390_cpu_virt_mem_check_write(cpu, addr, sizeof(schib)) != 0) {
 333             return;
 334         }
 335     }
 336     setcc(cpu, cc);
 337 }
 338
 339 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 340 {
 341     CPUS390XState *env = &cpu->env;
 342     int cssid, ssid, schid, m;
 343     SubchDev *sch;
 344     IRB irb;
 345     uint64_t addr;
 346     int cc, irb_len;
 347
 348     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 349         program_interrupt(env, PGM_OPERAND, 2);
 350         return -EIO;
 351     }
 352     trace_ioinst_sch_id("tsch", cssid, ssid, schid);
 353     addr = decode_basedisp_s(env, ipb);
 354     if (addr & 3) {
 355         program_interrupt(env, PGM_SPECIFICATION, 2);
 356         return -EIO;
 357     }
 358
 359     sch = css_find_subch(m, cssid, ssid, schid);
 360     if (sch && css_subch_visible(sch)) {
 361         cc = css_do_tsch_get_irb(sch, &irb, &irb_len);
 362     } else {
 363         cc = 3;
 364     }
 365     /* 0 - status pending, 1 - not status pending, 3 - not operational */
 366     if (cc != 3) {
 367         if (s390_cpu_virt_mem_write(cpu, addr, &irb, irb_len) != 0) {
 368             return -EFAULT;
 369         }
 370         css_do_tsch_update_subch(sch);
 371     } else {
 372         irb_len = sizeof(irb) - sizeof(irb.emw);
 373         /* Access exceptions have a higher priority than cc3 */
 374         if (s390_cpu_virt_mem_check_write(cpu, addr, irb_len) != 0) {
 375             return -EFAULT;
 376         }
 377     }
 378
 379     setcc(cpu, cc);
 380     return 0;
 381 }
 382
 383 typedef struct ChscReq {
 384     uint16_t len;
 385     uint16_t command;
 386     uint32_t param0;
 387     uint32_t param1;
 388     uint32_t param2;
 389 } QEMU_PACKED ChscReq;
 390
 391 typedef struct ChscResp {
 392     uint16_t len;
 393     uint16_t code;
 394     uint32_t param;
 395     char data[0];
 396 } QEMU_PACKED ChscResp;
 397
 398 #define CHSC_MIN_RESP_LEN 0x0008
 399
 400 #define CHSC_SCPD 0x0002
 401 #define CHSC_SCSC 0x0010
 402 #define CHSC_SDA  0x0031
 403 #define CHSC_SEI  0x000e
 404
 405 #define CHSC_SCPD_0_M 0x20000000
 406 #define CHSC_SCPD_0_C 0x10000000
 407 #define CHSC_SCPD_0_FMT 0x0f000000
 408 #define CHSC_SCPD_0_CSSID 0x00ff0000
 409 #define CHSC_SCPD_0_RFMT 0x00000f00
 410 #define CHSC_SCPD_0_RES 0xc000f000
 411 #define CHSC_SCPD_1_RES 0xffffff00
 412 #define CHSC_SCPD_01_CHPID 0x000000ff
 413 static void ioinst_handle_chsc_scpd(ChscReq *req, ChscResp *res)
 414 {
 415     uint16_t len = be16_to_cpu(req->len);
 416     uint32_t param0 = be32_to_cpu(req->param0);
 417     uint32_t param1 = be32_to_cpu(req->param1);
 418     uint16_t resp_code;
 419     int rfmt;
 420     uint16_t cssid;
 421     uint8_t f_chpid, l_chpid;
 422     int desc_size;
 423     int m;
 424
 425     rfmt = (param0 & CHSC_SCPD_0_RFMT) >> 8;
 426     if ((rfmt == 0) ||  (rfmt == 1)) {
 427         rfmt = !!(param0 & CHSC_SCPD_0_C);
 428     }
 429     if ((len != 0x0010) || (param0 & CHSC_SCPD_0_RES) ||
 430         (param1 & CHSC_SCPD_1_RES) || req->param2) {
 431         resp_code = 0x0003;
 432         goto out_err;
 433     }
 434     if (param0 & CHSC_SCPD_0_FMT) {
 435         resp_code = 0x0007;
 436         goto out_err;
 437     }
 438     cssid = (param0 & CHSC_SCPD_0_CSSID) >> 16;
 439     m = param0 & CHSC_SCPD_0_M;
 440     if (cssid != 0) {
 441         if (!m || !css_present(cssid)) {
 442             resp_code = 0x0008;
 443             goto out_err;
 444         }
 445     }
 446     f_chpid = param0 & CHSC_SCPD_01_CHPID;
 447     l_chpid = param1 & CHSC_SCPD_01_CHPID;
 448     if (l_chpid < f_chpid) {
 449         resp_code = 0x0003;
 450         goto out_err;
 451     }
 452     /* css_collect_chp_desc() is endian-aware */
 453     desc_size = css_collect_chp_desc(m, cssid, f_chpid, l_chpid, rfmt,
 454                                      &res->data);
 455     res->code = cpu_to_be16(0x0001);
 456     res->len = cpu_to_be16(8 + desc_size);
 457     res->param = cpu_to_be32(rfmt);
 458     return;
 459
 460   out_err:
 461     res->code = cpu_to_be16(resp_code);
 462     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 463     res->param = cpu_to_be32(rfmt);
 464 }
 465
 466 #define CHSC_SCSC_0_M 0x20000000
 467 #define CHSC_SCSC_0_FMT 0x000f0000
 468 #define CHSC_SCSC_0_CSSID 0x0000ff00
 469 #define CHSC_SCSC_0_RES 0xdff000ff
 470 static void ioinst_handle_chsc_scsc(ChscReq *req, ChscResp *res)
 471 {
 472     uint16_t len = be16_to_cpu(req->len);
 473     uint32_t param0 = be32_to_cpu(req->param0);
 474     uint8_t cssid;
 475     uint16_t resp_code;
 476     uint32_t general_chars[510];
 477     uint32_t chsc_chars[508];
 478
 479     if (len != 0x0010) {
 480         resp_code = 0x0003;
 481         goto out_err;
 482     }
 483
 484     if (param0 & CHSC_SCSC_0_FMT) {
 485         resp_code = 0x0007;
 486         goto out_err;
 487     }
 488     cssid = (param0 & CHSC_SCSC_0_CSSID) >> 8;
 489     if (cssid != 0) {
 490         if (!(param0 & CHSC_SCSC_0_M) || !css_present(cssid)) {
 491             resp_code = 0x0008;
 492             goto out_err;
 493         }
 494     }
 495     if ((param0 & CHSC_SCSC_0_RES) || req->param1 || req->param2) {
 496         resp_code = 0x0003;
 497         goto out_err;
 498     }
 499     res->code = cpu_to_be16(0x0001);
 500     res->len = cpu_to_be16(4080);
 501     res->param = 0;
 502
 503     memset(general_chars, 0, sizeof(general_chars));
 504     memset(chsc_chars, 0, sizeof(chsc_chars));
 505
 506     general_chars[0] = cpu_to_be32(0x03000000);
 507     general_chars[1] = cpu_to_be32(0x00059000);
 508
 509     chsc_chars[0] = cpu_to_be32(0x40000000);
 510     chsc_chars[3] = cpu_to_be32(0x00040000);
 511
 512     memcpy(res->data, general_chars, sizeof(general_chars));
 513     memcpy(res->data + sizeof(general_chars), chsc_chars, sizeof(chsc_chars));
 514     return;
 515
 516   out_err:
 517     res->code = cpu_to_be16(resp_code);
 518     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 519     res->param = 0;
 520 }
 521
 522 #define CHSC_SDA_0_FMT 0x0f000000
 523 #define CHSC_SDA_0_OC 0x0000ffff
 524 #define CHSC_SDA_0_RES 0xf0ff0000
 525 #define CHSC_SDA_OC_MCSSE 0x0
 526 #define CHSC_SDA_OC_MSS 0x2
 527 static void ioinst_handle_chsc_sda(ChscReq *req, ChscResp *res)
 528 {
 529     uint16_t resp_code = 0x0001;
 530     uint16_t len = be16_to_cpu(req->len);
 531     uint32_t param0 = be32_to_cpu(req->param0);
 532     uint16_t oc;
 533     int ret;
 534
 535     if ((len != 0x0400) || (param0 & CHSC_SDA_0_RES)) {
 536         resp_code = 0x0003;
 537         goto out;
 538     }
 539
 540     if (param0 & CHSC_SDA_0_FMT) {
 541         resp_code = 0x0007;
 542         goto out;
 543     }
 544
 545     oc = param0 & CHSC_SDA_0_OC;
 546     switch (oc) {
 547     case CHSC_SDA_OC_MCSSE:
 548         ret = css_enable_mcsse();
 549         if (ret == -EINVAL) {
 550             resp_code = 0x0101;
 551             goto out;
 552         }
 553         break;
 554     case CHSC_SDA_OC_MSS:
 555         ret = css_enable_mss();
 556         if (ret == -EINVAL) {
 557             resp_code = 0x0101;
 558             goto out;
 559         }
 560         break;
 561     default:
 562         resp_code = 0x0003;
 563         goto out;
 564     }
 565
 566 out:
 567     res->code = cpu_to_be16(resp_code);
 568     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 569     res->param = 0;
 570 }
 571
 572 static int chsc_sei_nt0_get_event(void *res)
 573 {
 574     /* no events yet */
 575     return 1;
 576 }
 577
 578 static int chsc_sei_nt0_have_event(void)
 579 {
 580     /* no events yet */
 581     return 0;
 582 }
 583
 584 #define CHSC_SEI_NT0    (1ULL << 63)
 585 #define CHSC_SEI_NT2    (1ULL << 61)
 586 static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)
 587 {
 588     uint64_t selection_mask = ldq_p(&req->param1);
 589     uint8_t *res_flags = (uint8_t *)res->data;
 590     int have_event = 0;
 591     int have_more = 0;
 592
 593     /* regarding architecture nt0 can not be masked */
 594     have_event = !chsc_sei_nt0_get_event(res);
 595     have_more = chsc_sei_nt0_have_event();
 596
 597     if (selection_mask & CHSC_SEI_NT2) {
 598         if (!have_event) {
 599             have_event = !chsc_sei_nt2_get_event(res);
 600         }
 601
 602         if (!have_more) {
 603             have_more = chsc_sei_nt2_have_event();
 604         }
 605     }
 606
 607     if (have_event) {
 608         res->code = cpu_to_be16(0x0001);
 609         if (have_more) {
 610             (*res_flags) |= 0x80;
 611         } else {
 612             (*res_flags) &= ~0x80;
 613         }
 614     } else {
 615         res->code = cpu_to_be16(0x0004);
 616     }
 617 }
 618
 619 static void ioinst_handle_chsc_unimplemented(ChscResp *res)
 620 {
 621     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 622     res->code = cpu_to_be16(0x0004);
 623     res->param = 0;
 624 }
 625
 626 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb)
 627 {
 628     ChscReq *req;
 629     ChscResp *res;
 630     uint64_t addr;
 631     int reg;
 632     uint16_t len;
 633     uint16_t command;
 634     hwaddr map_size = TARGET_PAGE_SIZE;
 635     CPUS390XState *env = &cpu->env;
 636
 637     trace_ioinst("chsc");
 638     reg = (ipb >> 20) & 0x00f;
 639     addr = env->regs[reg];
 640     /* Page boundary? */
 641     if (addr & 0xfff) {
 642         program_interrupt(env, PGM_SPECIFICATION, 2);
 643         return;
 644     }
 645     req = s390_cpu_physical_memory_map(env, addr, &map_size, 1);
 646     if (!req || map_size != TARGET_PAGE_SIZE) {
 647         program_interrupt(env, PGM_ADDRESSING, 2);
 648         goto out;
 649     }
 650     len = be16_to_cpu(req->len);
 651     /* Length field valid? */
 652     if ((len < 16) || (len > 4088) || (len & 7)) {
 653         program_interrupt(env, PGM_OPERAND, 2);
 654         goto out;
 655     }
 656     memset((char *)req + len, 0, TARGET_PAGE_SIZE - len);
 657     res = (void *)((char *)req + len);
 658     command = be16_to_cpu(req->command);
 659     trace_ioinst_chsc_cmd(command, len);
 660     switch (command) {
 661     case CHSC_SCSC:
 662         ioinst_handle_chsc_scsc(req, res);
 663         break;
 664     case CHSC_SCPD:
 665         ioinst_handle_chsc_scpd(req, res);
 666         break;
 667     case CHSC_SDA:
 668         ioinst_handle_chsc_sda(req, res);
 669         break;
 670     case CHSC_SEI:
 671         ioinst_handle_chsc_sei(req, res);
 672         break;
 673     default:
 674         ioinst_handle_chsc_unimplemented(res);
 675         break;
 676     }
 677
 678     setcc(cpu, 0);    /* Command execution complete */
 679 out:
 680     s390_cpu_physical_memory_unmap(env, req, map_size, 1);
 681 }
 682
 683 int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb)
 684 {
 685     uint64_t addr;
 686     int lowcore;
 687     IOIntCode *int_code;
 688     hwaddr len, orig_len;
 689     int ret;
 690
 691     trace_ioinst("tpi");
 692     addr = decode_basedisp_s(env, ipb);
 693     if (addr & 3) {
 694         program_interrupt(env, PGM_SPECIFICATION, 2);
 695         return -EIO;
 696     }
 697
 698     lowcore = addr ? 0 : 1;
 699     len = lowcore ? 8 /* two words */ : 12 /* three words */;
 700     orig_len = len;
 701     int_code = s390_cpu_physical_memory_map(env, addr, &len, 1);
 702     if (!int_code || (len != orig_len)) {
 703         program_interrupt(env, PGM_ADDRESSING, 2);
 704         ret = -EIO;
 705         goto out;
 706     }
 707     ret = css_do_tpi(int_code, lowcore);
 708 out:
 709     s390_cpu_physical_memory_unmap(env, int_code, len, 1);
 710     return ret;
 711 }
 712
 713 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
 714 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
 715 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
 716 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
 717
 718 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
 719                         uint32_t ipb)
 720 {
 721     uint8_t mbk;
 722     int update;
 723     int dct;
 724     CPUS390XState *env = &cpu->env;
 725
 726     trace_ioinst("schm");
 727
 728     if (SCHM_REG1_RES(reg1)) {
 729         program_interrupt(env, PGM_OPERAND, 2);
 730         return;
 731     }
 732
 733     mbk = SCHM_REG1_MBK(reg1);
 734     update = SCHM_REG1_UPD(reg1);
 735     dct = SCHM_REG1_DCT(reg1);
 736
 737     if (update && (reg2 & 0x000000000000001f)) {
 738         program_interrupt(env, PGM_OPERAND, 2);
 739         return;
 740     }
 741
 742     css_do_schm(mbk, update, dct, update ? reg2 : 0);
 743 }
 744
 745 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1)
 746 {
 747     int cssid, ssid, schid, m;
 748     SubchDev *sch;
 749     int ret = -ENODEV;
 750     int cc;
 751
 752     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 753         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 754         return;
 755     }
 756     trace_ioinst_sch_id("rsch", cssid, ssid, schid);
 757     sch = css_find_subch(m, cssid, ssid, schid);
 758     if (sch && css_subch_visible(sch)) {
 759         ret = css_do_rsch(sch);
 760     }
 761     switch (ret) {
 762     case -ENODEV:
 763         cc = 3;
 764         break;
 765     case -EINVAL:
 766         cc = 2;
 767         break;
 768     case 0:
 769         cc = 0;
 770         break;
 771     default:
 772         cc = 1;
 773         break;
 774     }
 775     setcc(cpu, cc);
 776 }
 777
 778 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
 779 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
 780 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
 781 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1)
 782 {
 783     int cc;
 784     uint8_t cssid;
 785     uint8_t chpid;
 786     int ret;
 787     CPUS390XState *env = &cpu->env;
 788
 789     if (RCHP_REG1_RES(reg1)) {
 790         program_interrupt(env, PGM_OPERAND, 2);
 791         return;
 792     }
 793
 794     cssid = RCHP_REG1_CSSID(reg1);
 795     chpid = RCHP_REG1_CHPID(reg1);
 796
 797     trace_ioinst_chp_id("rchp", cssid, chpid);
 798
 799     ret = css_do_rchp(cssid, chpid);
 800
 801     switch (ret) {
 802     case -ENODEV:
 803         cc = 3;
 804         break;
 805     case -EBUSY:
 806         cc = 2;
 807         break;
 808     case 0:
 809         cc = 0;
 810         break;
 811     default:
 812         /* Invalid channel subsystem. */
 813         program_interrupt(env, PGM_OPERAND, 2);
 814         return;
 815     }
 816     setcc(cpu, cc);
 817 }
 818
 819 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
 820 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1)
 821 {
 822     /* We do not provide address limit checking, so let's suppress it. */
 823     if (SAL_REG1_INVALID(reg1) || reg1 & 0x000000000000ffff) {
 824         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 825     }
 826 }