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target-arm: Implement AArch64 memory attribute registers
[qemu/qmp-unstable.git] / target-lm32 / translate.c
blob80bffc7b275e02da38e46890e88f53330106441c
1 /*
2 * LatticeMico32 main translation routines.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "disas/disas.h"
22 #include "helper.h"
23 #include "tcg-op.h"
24
25 #include "hw/lm32/lm32_pic.h"
26
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define DISAS_LM32 1
31 #if DISAS_LM32
32 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
33 #else
34 # define LOG_DIS(...) do { } while (0)
35 #endif
36
37 #define EXTRACT_FIELD(src, start, end) \
38 (((src) >> start) & ((1 << (end - start + 1)) - 1))
39
40 #define MEM_INDEX 0
41
42 static TCGv_ptr cpu_env;
43 static TCGv cpu_R[32];
44 static TCGv cpu_pc;
45 static TCGv cpu_ie;
46 static TCGv cpu_icc;
47 static TCGv cpu_dcc;
48 static TCGv cpu_cc;
49 static TCGv cpu_cfg;
50 static TCGv cpu_eba;
51 static TCGv cpu_dc;
52 static TCGv cpu_deba;
53 static TCGv cpu_bp[4];
54 static TCGv cpu_wp[4];
55
56 #include "exec/gen-icount.h"
57
58 enum {
59 OP_FMT_RI,
60 OP_FMT_RR,
61 OP_FMT_CR,
62 OP_FMT_I
63 };
64
65 /* This is the state at translation time. */
66 typedef struct DisasContext {
67 target_ulong pc;
68
69 /* Decoder. */
70 int format;
71 uint32_t ir;
72 uint8_t opcode;
73 uint8_t r0, r1, r2, csr;
74 uint16_t imm5;
75 uint16_t imm16;
76 uint32_t imm26;
77
78 unsigned int delayed_branch;
79 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
80 int is_jmp;
81
82 struct TranslationBlock *tb;
83 int singlestep_enabled;
84
85 uint32_t features;
86 uint8_t num_breakpoints;
87 uint8_t num_watchpoints;
88 } DisasContext;
89
90 static const char *regnames[] = {
91 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
92 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
93 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
94 "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
95 "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
96 "wp1", "wp2", "wp3"
97 };
98
99 static inline int zero_extend(unsigned int val, int width)
100 {
101 return val & ((1 << width) - 1);
102 }
103
104 static inline int sign_extend(unsigned int val, int width)
105 {
106 int sval;
107
108 /* LSL. */
109 val <<= 32 - width;
110 sval = val;
111 /* ASR. */
112 sval >>= 32 - width;
113
114 return sval;
115 }
116
117 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
118 {
119 TCGv_i32 tmp = tcg_const_i32(index);
120
121 gen_helper_raise_exception(cpu_env, tmp);
122 tcg_temp_free_i32(tmp);
123 }
124
125 static inline void t_gen_illegal_insn(DisasContext *dc)
126 {
127 tcg_gen_movi_tl(cpu_pc, dc->pc);
128 gen_helper_ill(cpu_env);
129 }
130
131 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
132 {
133 TranslationBlock *tb;
134
135 tb = dc->tb;
136 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
137 likely(!dc->singlestep_enabled)) {
138 tcg_gen_goto_tb(n);
139 tcg_gen_movi_tl(cpu_pc, dest);
140 tcg_gen_exit_tb((uintptr_t)tb + n);
141 } else {
142 tcg_gen_movi_tl(cpu_pc, dest);
143 if (dc->singlestep_enabled) {
144 t_gen_raise_exception(dc, EXCP_DEBUG);
145 }
146 tcg_gen_exit_tb(0);
147 }
148 }
149
150 static void dec_add(DisasContext *dc)
151 {
152 if (dc->format == OP_FMT_RI) {
153 if (dc->r0 == R_R0) {
154 if (dc->r1 == R_R0 && dc->imm16 == 0) {
155 LOG_DIS("nop\n");
156 } else {
157 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
158 }
159 } else {
160 LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
161 sign_extend(dc->imm16, 16));
162 }
163 } else {
164 LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
165 }
166
167 if (dc->format == OP_FMT_RI) {
168 tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
169 sign_extend(dc->imm16, 16));
170 } else {
171 tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
172 }
173 }
174
175 static void dec_and(DisasContext *dc)
176 {
177 if (dc->format == OP_FMT_RI) {
178 LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
179 zero_extend(dc->imm16, 16));
180 } else {
181 LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
182 }
183
184 if (dc->format == OP_FMT_RI) {
185 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
186 zero_extend(dc->imm16, 16));
187 } else {
188 if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
189 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
190 gen_helper_hlt(cpu_env);
191 } else {
192 tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
193 }
194 }
195 }
196
197 static void dec_andhi(DisasContext *dc)
198 {
199 LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
200
201 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
202 }
203
204 static void dec_b(DisasContext *dc)
205 {
206 if (dc->r0 == R_RA) {
207 LOG_DIS("ret\n");
208 } else if (dc->r0 == R_EA) {
209 LOG_DIS("eret\n");
210 } else if (dc->r0 == R_BA) {
211 LOG_DIS("bret\n");
212 } else {
213 LOG_DIS("b r%d\n", dc->r0);
214 }
215
216 /* restore IE.IE in case of an eret */
217 if (dc->r0 == R_EA) {
218 TCGv t0 = tcg_temp_new();
219 int l1 = gen_new_label();
220 tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
221 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
222 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
223 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
224 gen_set_label(l1);
225 tcg_temp_free(t0);
226 } else if (dc->r0 == R_BA) {
227 TCGv t0 = tcg_temp_new();
228 int l1 = gen_new_label();
229 tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
230 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
231 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
232 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
233 gen_set_label(l1);
234 tcg_temp_free(t0);
235 }
236 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
237
238 dc->is_jmp = DISAS_JUMP;
239 }
240
241 static void dec_bi(DisasContext *dc)
242 {
243 LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
244
245 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
246
247 dc->is_jmp = DISAS_TB_JUMP;
248 }
249
250 static inline void gen_cond_branch(DisasContext *dc, int cond)
251 {
252 int l1;
253
254 l1 = gen_new_label();
255 tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
256 gen_goto_tb(dc, 0, dc->pc + 4);
257 gen_set_label(l1);
258 gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
259 dc->is_jmp = DISAS_TB_JUMP;
260 }
261
262 static void dec_be(DisasContext *dc)
263 {
264 LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
265 sign_extend(dc->imm16, 16) * 4);
266
267 gen_cond_branch(dc, TCG_COND_EQ);
268 }
269
270 static void dec_bg(DisasContext *dc)
271 {
272 LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
273 sign_extend(dc->imm16, 16 * 4));
274
275 gen_cond_branch(dc, TCG_COND_GT);
276 }
277
278 static void dec_bge(DisasContext *dc)
279 {
280 LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
281 sign_extend(dc->imm16, 16) * 4);
282
283 gen_cond_branch(dc, TCG_COND_GE);
284 }
285
286 static void dec_bgeu(DisasContext *dc)
287 {
288 LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
289 sign_extend(dc->imm16, 16) * 4);
290
291 gen_cond_branch(dc, TCG_COND_GEU);
292 }
293
294 static void dec_bgu(DisasContext *dc)
295 {
296 LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
297 sign_extend(dc->imm16, 16) * 4);
298
299 gen_cond_branch(dc, TCG_COND_GTU);
300 }
301
302 static void dec_bne(DisasContext *dc)
303 {
304 LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
305 sign_extend(dc->imm16, 16) * 4);
306
307 gen_cond_branch(dc, TCG_COND_NE);
308 }
309
310 static void dec_call(DisasContext *dc)
311 {
312 LOG_DIS("call r%d\n", dc->r0);
313
314 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
315 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
316
317 dc->is_jmp = DISAS_JUMP;
318 }
319
320 static void dec_calli(DisasContext *dc)
321 {
322 LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
323
324 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
325 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
326
327 dc->is_jmp = DISAS_TB_JUMP;
328 }
329
330 static inline void gen_compare(DisasContext *dc, int cond)
331 {
332 int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
333 int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
334 int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
335 int i;
336
337 if (dc->format == OP_FMT_RI) {
338 switch (cond) {
339 case TCG_COND_GEU:
340 case TCG_COND_GTU:
341 i = zero_extend(dc->imm16, 16);
342 break;
343 default:
344 i = sign_extend(dc->imm16, 16);
345 break;
346 }
347
348 tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], i);
349 } else {
350 tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
351 }
352 }
353
354 static void dec_cmpe(DisasContext *dc)
355 {
356 if (dc->format == OP_FMT_RI) {
357 LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
358 sign_extend(dc->imm16, 16));
359 } else {
360 LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
361 }
362
363 gen_compare(dc, TCG_COND_EQ);
364 }
365
366 static void dec_cmpg(DisasContext *dc)
367 {
368 if (dc->format == OP_FMT_RI) {
369 LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
370 sign_extend(dc->imm16, 16));
371 } else {
372 LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
373 }
374
375 gen_compare(dc, TCG_COND_GT);
376 }
377
378 static void dec_cmpge(DisasContext *dc)
379 {
380 if (dc->format == OP_FMT_RI) {
381 LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
382 sign_extend(dc->imm16, 16));
383 } else {
384 LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
385 }
386
387 gen_compare(dc, TCG_COND_GE);
388 }
389
390 static void dec_cmpgeu(DisasContext *dc)
391 {
392 if (dc->format == OP_FMT_RI) {
393 LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
394 zero_extend(dc->imm16, 16));
395 } else {
396 LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
397 }
398
399 gen_compare(dc, TCG_COND_GEU);
400 }
401
402 static void dec_cmpgu(DisasContext *dc)
403 {
404 if (dc->format == OP_FMT_RI) {
405 LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
406 zero_extend(dc->imm16, 16));
407 } else {
408 LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
409 }
410
411 gen_compare(dc, TCG_COND_GTU);
412 }
413
414 static void dec_cmpne(DisasContext *dc)
415 {
416 if (dc->format == OP_FMT_RI) {
417 LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
418 sign_extend(dc->imm16, 16));
419 } else {
420 LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
421 }
422
423 gen_compare(dc, TCG_COND_NE);
424 }
425
426 static void dec_divu(DisasContext *dc)
427 {
428 int l1;
429
430 LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
431
432 if (!(dc->features & LM32_FEATURE_DIVIDE)) {
433 qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
434 t_gen_illegal_insn(dc);
435 return;
436 }
437
438 l1 = gen_new_label();
439 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
440 tcg_gen_movi_tl(cpu_pc, dc->pc);
441 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
442 gen_set_label(l1);
443 tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
444 }
445
446 static void dec_lb(DisasContext *dc)
447 {
448 TCGv t0;
449
450 LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
451
452 t0 = tcg_temp_new();
453 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
454 tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
455 tcg_temp_free(t0);
456 }
457
458 static void dec_lbu(DisasContext *dc)
459 {
460 TCGv t0;
461
462 LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
463
464 t0 = tcg_temp_new();
465 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
466 tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
467 tcg_temp_free(t0);
468 }
469
470 static void dec_lh(DisasContext *dc)
471 {
472 TCGv t0;
473
474 LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
475
476 t0 = tcg_temp_new();
477 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
478 tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
479 tcg_temp_free(t0);
480 }
481
482 static void dec_lhu(DisasContext *dc)
483 {
484 TCGv t0;
485
486 LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
487
488 t0 = tcg_temp_new();
489 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
490 tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
491 tcg_temp_free(t0);
492 }
493
494 static void dec_lw(DisasContext *dc)
495 {
496 TCGv t0;
497
498 LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
499
500 t0 = tcg_temp_new();
501 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
502 tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
503 tcg_temp_free(t0);
504 }
505
506 static void dec_modu(DisasContext *dc)
507 {
508 int l1;
509
510 LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
511
512 if (!(dc->features & LM32_FEATURE_DIVIDE)) {
513 qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
514 t_gen_illegal_insn(dc);
515 return;
516 }
517
518 l1 = gen_new_label();
519 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
520 tcg_gen_movi_tl(cpu_pc, dc->pc);
521 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
522 gen_set_label(l1);
523 tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
524 }
525
526 static void dec_mul(DisasContext *dc)
527 {
528 if (dc->format == OP_FMT_RI) {
529 LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
530 sign_extend(dc->imm16, 16));
531 } else {
532 LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
533 }
534
535 if (!(dc->features & LM32_FEATURE_MULTIPLY)) {
536 qemu_log_mask(LOG_GUEST_ERROR,
537 "hardware multiplier is not available\n");
538 t_gen_illegal_insn(dc);
539 return;
540 }
541
542 if (dc->format == OP_FMT_RI) {
543 tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
544 sign_extend(dc->imm16, 16));
545 } else {
546 tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
547 }
548 }
549
550 static void dec_nor(DisasContext *dc)
551 {
552 if (dc->format == OP_FMT_RI) {
553 LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
554 zero_extend(dc->imm16, 16));
555 } else {
556 LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
557 }
558
559 if (dc->format == OP_FMT_RI) {
560 TCGv t0 = tcg_temp_new();
561 tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
562 tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
563 tcg_temp_free(t0);
564 } else {
565 tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
566 }
567 }
568
569 static void dec_or(DisasContext *dc)
570 {
571 if (dc->format == OP_FMT_RI) {
572 LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
573 zero_extend(dc->imm16, 16));
574 } else {
575 if (dc->r1 == R_R0) {
576 LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
577 } else {
578 LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
579 }
580 }
581
582 if (dc->format == OP_FMT_RI) {
583 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
584 zero_extend(dc->imm16, 16));
585 } else {
586 tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
587 }
588 }
589
590 static void dec_orhi(DisasContext *dc)
591 {
592 if (dc->r0 == R_R0) {
593 LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
594 } else {
595 LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
596 }
597
598 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
599 }
600
601 static void dec_scall(DisasContext *dc)
602 {
603 switch (dc->imm5) {
604 case 2:
605 LOG_DIS("break\n");
606 tcg_gen_movi_tl(cpu_pc, dc->pc);
607 t_gen_raise_exception(dc, EXCP_BREAKPOINT);
608 break;
609 case 7:
610 LOG_DIS("scall\n");
611 tcg_gen_movi_tl(cpu_pc, dc->pc);
612 t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
613 break;
614 default:
615 qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode @0x%x", dc->pc);
616 t_gen_illegal_insn(dc);
617 break;
618 }
619 }
620
621 static void dec_rcsr(DisasContext *dc)
622 {
623 LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
624
625 switch (dc->csr) {
626 case CSR_IE:
627 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
628 break;
629 case CSR_IM:
630 gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
631 break;
632 case CSR_IP:
633 gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
634 break;
635 case CSR_CC:
636 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
637 break;
638 case CSR_CFG:
639 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
640 break;
641 case CSR_EBA:
642 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
643 break;
644 case CSR_DC:
645 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
646 break;
647 case CSR_DEBA:
648 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
649 break;
650 case CSR_JTX:
651 gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
652 break;
653 case CSR_JRX:
654 gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
655 break;
656 case CSR_ICC:
657 case CSR_DCC:
658 case CSR_BP0:
659 case CSR_BP1:
660 case CSR_BP2:
661 case CSR_BP3:
662 case CSR_WP0:
663 case CSR_WP1:
664 case CSR_WP2:
665 case CSR_WP3:
666 qemu_log_mask(LOG_GUEST_ERROR, "invalid read access csr=%x\n", dc->csr);
667 break;
668 default:
669 qemu_log_mask(LOG_GUEST_ERROR, "read_csr: unknown csr=%x\n", dc->csr);
670 break;
671 }
672 }
673
674 static void dec_sb(DisasContext *dc)
675 {
676 TCGv t0;
677
678 LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
679
680 t0 = tcg_temp_new();
681 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
682 tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
683 tcg_temp_free(t0);
684 }
685
686 static void dec_sextb(DisasContext *dc)
687 {
688 LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
689
690 if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
691 qemu_log_mask(LOG_GUEST_ERROR,
692 "hardware sign extender is not available\n");
693 t_gen_illegal_insn(dc);
694 return;
695 }
696
697 tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
698 }
699
700 static void dec_sexth(DisasContext *dc)
701 {
702 LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
703
704 if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
705 qemu_log_mask(LOG_GUEST_ERROR,
706 "hardware sign extender is not available\n");
707 t_gen_illegal_insn(dc);
708 return;
709 }
710
711 tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
712 }
713
714 static void dec_sh(DisasContext *dc)
715 {
716 TCGv t0;
717
718 LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
719
720 t0 = tcg_temp_new();
721 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
722 tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
723 tcg_temp_free(t0);
724 }
725
726 static void dec_sl(DisasContext *dc)
727 {
728 if (dc->format == OP_FMT_RI) {
729 LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
730 } else {
731 LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
732 }
733
734 if (!(dc->features & LM32_FEATURE_SHIFT)) {
735 qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not available\n");
736 t_gen_illegal_insn(dc);
737 return;
738 }
739
740 if (dc->format == OP_FMT_RI) {
741 tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
742 } else {
743 TCGv t0 = tcg_temp_new();
744 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
745 tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
746 tcg_temp_free(t0);
747 }
748 }
749
750 static void dec_sr(DisasContext *dc)
751 {
752 if (dc->format == OP_FMT_RI) {
753 LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
754 } else {
755 LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
756 }
757
758 /* The real CPU (w/o hardware shifter) only supports right shift by exactly
759 * one bit */
760 if (dc->format == OP_FMT_RI) {
761 if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
762 qemu_log_mask(LOG_GUEST_ERROR,
763 "hardware shifter is not available\n");
764 t_gen_illegal_insn(dc);
765 return;
766 }
767 tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
768 } else {
769 int l1 = gen_new_label();
770 int l2 = gen_new_label();
771 TCGv t0 = tcg_temp_local_new();
772 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
773
774 if (!(dc->features & LM32_FEATURE_SHIFT)) {
775 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
776 t_gen_illegal_insn(dc);
777 tcg_gen_br(l2);
778 }
779
780 gen_set_label(l1);
781 tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
782 gen_set_label(l2);
783
784 tcg_temp_free(t0);
785 }
786 }
787
788 static void dec_sru(DisasContext *dc)
789 {
790 if (dc->format == OP_FMT_RI) {
791 LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
792 } else {
793 LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
794 }
795
796 if (dc->format == OP_FMT_RI) {
797 if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
798 qemu_log_mask(LOG_GUEST_ERROR,
799 "hardware shifter is not available\n");
800 t_gen_illegal_insn(dc);
801 return;
802 }
803 tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
804 } else {
805 int l1 = gen_new_label();
806 int l2 = gen_new_label();
807 TCGv t0 = tcg_temp_local_new();
808 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
809
810 if (!(dc->features & LM32_FEATURE_SHIFT)) {
811 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
812 t_gen_illegal_insn(dc);
813 tcg_gen_br(l2);
814 }
815
816 gen_set_label(l1);
817 tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
818 gen_set_label(l2);
819
820 tcg_temp_free(t0);
821 }
822 }
823
824 static void dec_sub(DisasContext *dc)
825 {
826 LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
827
828 tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
829 }
830
831 static void dec_sw(DisasContext *dc)
832 {
833 TCGv t0;
834
835 LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
836
837 t0 = tcg_temp_new();
838 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
839 tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
840 tcg_temp_free(t0);
841 }
842
843 static void dec_user(DisasContext *dc)
844 {
845 LOG_DIS("user");
846
847 qemu_log_mask(LOG_GUEST_ERROR, "user instruction undefined\n");
848 t_gen_illegal_insn(dc);
849 }
850
851 static void dec_wcsr(DisasContext *dc)
852 {
853 int no;
854
855 LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
856
857 switch (dc->csr) {
858 case CSR_IE:
859 tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
860 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
861 dc->is_jmp = DISAS_UPDATE;
862 break;
863 case CSR_IM:
864 /* mark as an io operation because it could cause an interrupt */
865 if (use_icount) {
866 gen_io_start();
867 }
868 gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
869 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
870 if (use_icount) {
871 gen_io_end();
872 }
873 dc->is_jmp = DISAS_UPDATE;
874 break;
875 case CSR_IP:
876 /* mark as an io operation because it could cause an interrupt */
877 if (use_icount) {
878 gen_io_start();
879 }
880 gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
881 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
882 if (use_icount) {
883 gen_io_end();
884 }
885 dc->is_jmp = DISAS_UPDATE;
886 break;
887 case CSR_ICC:
888 /* TODO */
889 break;
890 case CSR_DCC:
891 /* TODO */
892 break;
893 case CSR_EBA:
894 tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
895 break;
896 case CSR_DEBA:
897 tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
898 break;
899 case CSR_JTX:
900 gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
901 break;
902 case CSR_JRX:
903 gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
904 break;
905 case CSR_DC:
906 gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]);
907 break;
908 case CSR_BP0:
909 case CSR_BP1:
910 case CSR_BP2:
911 case CSR_BP3:
912 no = dc->csr - CSR_BP0;
913 if (dc->num_breakpoints <= no) {
914 qemu_log_mask(LOG_GUEST_ERROR,
915 "breakpoint #%i is not available\n", no);
916 t_gen_illegal_insn(dc);
917 break;
918 }
919 gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
920 break;
921 case CSR_WP0:
922 case CSR_WP1:
923 case CSR_WP2:
924 case CSR_WP3:
925 no = dc->csr - CSR_WP0;
926 if (dc->num_watchpoints <= no) {
927 qemu_log_mask(LOG_GUEST_ERROR,
928 "watchpoint #%i is not available\n", no);
929 t_gen_illegal_insn(dc);
930 break;
931 }
932 gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
933 break;
934 case CSR_CC:
935 case CSR_CFG:
936 qemu_log_mask(LOG_GUEST_ERROR, "invalid write access csr=%x\n",
937 dc->csr);
938 break;
939 default:
940 qemu_log_mask(LOG_GUEST_ERROR, "write_csr: unknown csr=%x\n",
941 dc->csr);
942 break;
943 }
944 }
945
946 static void dec_xnor(DisasContext *dc)
947 {
948 if (dc->format == OP_FMT_RI) {
949 LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
950 zero_extend(dc->imm16, 16));
951 } else {
952 if (dc->r1 == R_R0) {
953 LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
954 } else {
955 LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
956 }
957 }
958
959 if (dc->format == OP_FMT_RI) {
960 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
961 zero_extend(dc->imm16, 16));
962 tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
963 } else {
964 tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
965 }
966 }
967
968 static void dec_xor(DisasContext *dc)
969 {
970 if (dc->format == OP_FMT_RI) {
971 LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
972 zero_extend(dc->imm16, 16));
973 } else {
974 LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
975 }
976
977 if (dc->format == OP_FMT_RI) {
978 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
979 zero_extend(dc->imm16, 16));
980 } else {
981 tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
982 }
983 }
984
985 static void dec_ill(DisasContext *dc)
986 {
987 qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode 0x%02x\n", dc->opcode);
988 t_gen_illegal_insn(dc);
989 }
990
991 typedef void (*DecoderInfo)(DisasContext *dc);
992 static const DecoderInfo decinfo[] = {
993 dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
994 dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
995 dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
996 dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
997 dec_cmpne,
998 dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
999 dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
1000 dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
1001 dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
1002 dec_cmpne
1003 };
1004
1005 static inline void decode(DisasContext *dc, uint32_t ir)
1006 {
1007 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1008 tcg_gen_debug_insn_start(dc->pc);
1009 }
1010
1011 dc->ir = ir;
1012 LOG_DIS("%8.8x\t", dc->ir);
1013
1014 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1015
1016 dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
1017 dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
1018 dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
1019
1020 dc->csr = EXTRACT_FIELD(ir, 21, 25);
1021 dc->r0 = EXTRACT_FIELD(ir, 21, 25);
1022 dc->r1 = EXTRACT_FIELD(ir, 16, 20);
1023 dc->r2 = EXTRACT_FIELD(ir, 11, 15);
1024
1025 /* bit 31 seems to indicate insn type. */
1026 if (ir & (1 << 31)) {
1027 dc->format = OP_FMT_RR;
1028 } else {
1029 dc->format = OP_FMT_RI;
1030 }
1031
1032 assert(ARRAY_SIZE(decinfo) == 64);
1033 assert(dc->opcode < 64);
1034
1035 decinfo[dc->opcode](dc);
1036 }
1037
1038 static void check_breakpoint(CPULM32State *env, DisasContext *dc)
1039 {
1040 CPUBreakpoint *bp;
1041
1042 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1043 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1044 if (bp->pc == dc->pc) {
1045 tcg_gen_movi_tl(cpu_pc, dc->pc);
1046 t_gen_raise_exception(dc, EXCP_DEBUG);
1047 dc->is_jmp = DISAS_UPDATE;
1048 }
1049 }
1050 }
1051 }
1052
1053 /* generate intermediate code for basic block 'tb'. */
1054 static inline
1055 void gen_intermediate_code_internal(LM32CPU *cpu,
1056 TranslationBlock *tb, bool search_pc)
1057 {
1058 CPUState *cs = CPU(cpu);
1059 CPULM32State *env = &cpu->env;
1060 struct DisasContext ctx, *dc = &ctx;
1061 uint16_t *gen_opc_end;
1062 uint32_t pc_start;
1063 int j, lj;
1064 uint32_t next_page_start;
1065 int num_insns;
1066 int max_insns;
1067
1068 pc_start = tb->pc;
1069 dc->features = cpu->features;
1070 dc->num_breakpoints = cpu->num_breakpoints;
1071 dc->num_watchpoints = cpu->num_watchpoints;
1072 dc->tb = tb;
1073
1074 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1075
1076 dc->is_jmp = DISAS_NEXT;
1077 dc->pc = pc_start;
1078 dc->singlestep_enabled = cs->singlestep_enabled;
1079
1080 if (pc_start & 3) {
1081 qemu_log_mask(LOG_GUEST_ERROR,
1082 "unaligned PC=%x. Ignoring lowest bits.\n", pc_start);
1083 pc_start &= ~3;
1084 }
1085
1086 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1087 lj = -1;
1088 num_insns = 0;
1089 max_insns = tb->cflags & CF_COUNT_MASK;
1090 if (max_insns == 0) {
1091 max_insns = CF_COUNT_MASK;
1092 }
1093
1094 gen_tb_start();
1095 do {
1096 check_breakpoint(env, dc);
1097
1098 if (search_pc) {
1099 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1100 if (lj < j) {
1101 lj++;
1102 while (lj < j) {
1103 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1104 }
1105 }
1106 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1107 tcg_ctx.gen_opc_instr_start[lj] = 1;
1108 tcg_ctx.gen_opc_icount[lj] = num_insns;
1109 }
1110
1111 /* Pretty disas. */
1112 LOG_DIS("%8.8x:\t", dc->pc);
1113
1114 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1115 gen_io_start();
1116 }
1117
1118 decode(dc, cpu_ldl_code(env, dc->pc));
1119 dc->pc += 4;
1120 num_insns++;
1121
1122 } while (!dc->is_jmp
1123 && tcg_ctx.gen_opc_ptr < gen_opc_end
1124 && !cs->singlestep_enabled
1125 && !singlestep
1126 && (dc->pc < next_page_start)
1127 && num_insns < max_insns);
1128
1129 if (tb->cflags & CF_LAST_IO) {
1130 gen_io_end();
1131 }
1132
1133 if (unlikely(cs->singlestep_enabled)) {
1134 if (dc->is_jmp == DISAS_NEXT) {
1135 tcg_gen_movi_tl(cpu_pc, dc->pc);
1136 }
1137 t_gen_raise_exception(dc, EXCP_DEBUG);
1138 } else {
1139 switch (dc->is_jmp) {
1140 case DISAS_NEXT:
1141 gen_goto_tb(dc, 1, dc->pc);
1142 break;
1143 default:
1144 case DISAS_JUMP:
1145 case DISAS_UPDATE:
1146 /* indicate that the hash table must be used
1147 to find the next TB */
1148 tcg_gen_exit_tb(0);
1149 break;
1150 case DISAS_TB_JUMP:
1151 /* nothing more to generate */
1152 break;
1153 }
1154 }
1155
1156 gen_tb_end(tb, num_insns);
1157 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1158 if (search_pc) {
1159 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1160 lj++;
1161 while (lj <= j) {
1162 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1163 }
1164 } else {
1165 tb->size = dc->pc - pc_start;
1166 tb->icount = num_insns;
1167 }
1168
1169 #ifdef DEBUG_DISAS
1170 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1171 qemu_log("\n");
1172 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
1173 qemu_log("\nisize=%d osize=%td\n",
1174 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1175 tcg_ctx.gen_opc_buf);
1176 }
1177 #endif
1178 }
1179
1180 void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
1181 {
1182 gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, false);
1183 }
1184
1185 void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb)
1186 {
1187 gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, true);
1188 }
1189
1190 void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1191 int flags)
1192 {
1193 LM32CPU *cpu = LM32_CPU(cs);
1194 CPULM32State *env = &cpu->env;
1195 int i;
1196
1197 if (!env || !f) {
1198 return;
1199 }
1200
1201 cpu_fprintf(f, "IN: PC=%x %s\n",
1202 env->pc, lookup_symbol(env->pc));
1203
1204 cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1205 env->ie,
1206 (env->ie & IE_IE) ? 1 : 0,
1207 (env->ie & IE_EIE) ? 1 : 0,
1208 (env->ie & IE_BIE) ? 1 : 0,
1209 lm32_pic_get_im(env->pic_state),
1210 lm32_pic_get_ip(env->pic_state));
1211 cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1212 env->eba,
1213 env->deba);
1214
1215 for (i = 0; i < 32; i++) {
1216 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1217 if ((i + 1) % 4 == 0) {
1218 cpu_fprintf(f, "\n");
1219 }
1220 }
1221 cpu_fprintf(f, "\n\n");
1222 }
1223
1224 void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos)
1225 {
1226 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1227 }
1228
1229 void lm32_translate_init(void)
1230 {
1231 int i;
1232
1233 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1234
1235 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1236 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1237 offsetof(CPULM32State, regs[i]),
1238 regnames[i]);
1239 }
1240
1241 for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
1242 cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
1243 offsetof(CPULM32State, bp[i]),
1244 regnames[32+i]);
1245 }
1246
1247 for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
1248 cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
1249 offsetof(CPULM32State, wp[i]),
1250 regnames[36+i]);
1251 }
1252
1253 cpu_pc = tcg_global_mem_new(TCG_AREG0,
1254 offsetof(CPULM32State, pc),
1255 "pc");
1256 cpu_ie = tcg_global_mem_new(TCG_AREG0,
1257 offsetof(CPULM32State, ie),
1258 "ie");
1259 cpu_icc = tcg_global_mem_new(TCG_AREG0,
1260 offsetof(CPULM32State, icc),
1261 "icc");
1262 cpu_dcc = tcg_global_mem_new(TCG_AREG0,
1263 offsetof(CPULM32State, dcc),
1264 "dcc");
1265 cpu_cc = tcg_global_mem_new(TCG_AREG0,
1266 offsetof(CPULM32State, cc),
1267 "cc");
1268 cpu_cfg = tcg_global_mem_new(TCG_AREG0,
1269 offsetof(CPULM32State, cfg),
1270 "cfg");
1271 cpu_eba = tcg_global_mem_new(TCG_AREG0,
1272 offsetof(CPULM32State, eba),
1273 "eba");
1274 cpu_dc = tcg_global_mem_new(TCG_AREG0,
1275 offsetof(CPULM32State, dc),
1276 "dc");
1277 cpu_deba = tcg_global_mem_new(TCG_AREG0,
1278 offsetof(CPULM32State, deba),
1279 "deba");
1280 }
1281
QEMU Monitor Protocol