target-arm: Implement AArch64 memory attribute registers
[qemu/qmp-unstable.git] / target-lm32 / cpu.c
blob7e716fb3366e01d0b544d706712cf7ff3f5291e8
1 /*
2 * QEMU LatticeMico32 CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "cpu.h"
22 #include "qemu-common.h"
25 static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
27 LM32CPU *cpu = LM32_CPU(cs);
29 cpu->env.pc = value;
32 /* Sort alphabetically by type name. */
33 static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
35 ObjectClass *class_a = (ObjectClass *)a;
36 ObjectClass *class_b = (ObjectClass *)b;
37 const char *name_a, *name_b;
39 name_a = object_class_get_name(class_a);
40 name_b = object_class_get_name(class_b);
41 return strcmp(name_a, name_b);
44 static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
46 ObjectClass *oc = data;
47 CPUListState *s = user_data;
48 const char *typename = object_class_get_name(oc);
49 char *name;
51 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU));
52 (*s->cpu_fprintf)(s->file, " %s\n", name);
53 g_free(name);
57 void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
59 CPUListState s = {
60 .file = f,
61 .cpu_fprintf = cpu_fprintf,
63 GSList *list;
65 list = object_class_get_list(TYPE_LM32_CPU, false);
66 list = g_slist_sort(list, lm32_cpu_list_compare);
67 (*cpu_fprintf)(f, "Available CPUs:\n");
68 g_slist_foreach(list, lm32_cpu_list_entry, &s);
69 g_slist_free(list);
72 static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
74 CPULM32State *env = &cpu->env;
75 uint32_t cfg = 0;
77 if (cpu->features & LM32_FEATURE_MULTIPLY) {
78 cfg |= CFG_M;
81 if (cpu->features & LM32_FEATURE_DIVIDE) {
82 cfg |= CFG_D;
85 if (cpu->features & LM32_FEATURE_SHIFT) {
86 cfg |= CFG_S;
89 if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
90 cfg |= CFG_X;
93 if (cpu->features & LM32_FEATURE_I_CACHE) {
94 cfg |= CFG_IC;
97 if (cpu->features & LM32_FEATURE_D_CACHE) {
98 cfg |= CFG_DC;
101 if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
102 cfg |= CFG_CC;
105 cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
106 cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
107 cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
108 cfg |= (cpu->revision << CFG_REV_SHIFT);
110 env->cfg = cfg;
113 /* CPUClass::reset() */
114 static void lm32_cpu_reset(CPUState *s)
116 LM32CPU *cpu = LM32_CPU(s);
117 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
118 CPULM32State *env = &cpu->env;
120 lcc->parent_reset(s);
122 /* reset cpu state */
123 memset(env, 0, offsetof(CPULM32State, breakpoints));
125 lm32_cpu_init_cfg_reg(cpu);
126 tlb_flush(env, 1);
129 static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
131 CPUState *cs = CPU(dev);
132 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
134 cpu_reset(cs);
136 qemu_init_vcpu(cs);
138 lcc->parent_realize(dev, errp);
141 static void lm32_cpu_initfn(Object *obj)
143 CPUState *cs = CPU(obj);
144 LM32CPU *cpu = LM32_CPU(obj);
145 CPULM32State *env = &cpu->env;
146 static bool tcg_initialized;
148 cs->env_ptr = env;
149 cpu_exec_init(env);
151 env->flags = 0;
153 if (tcg_enabled() && !tcg_initialized) {
154 tcg_initialized = true;
155 lm32_translate_init();
156 cpu_set_debug_excp_handler(lm32_debug_excp_handler);
160 static void lm32_basic_cpu_initfn(Object *obj)
162 LM32CPU *cpu = LM32_CPU(obj);
164 cpu->revision = 3;
165 cpu->num_interrupts = 32;
166 cpu->num_breakpoints = 4;
167 cpu->num_watchpoints = 4;
168 cpu->features = LM32_FEATURE_SHIFT
169 | LM32_FEATURE_SIGN_EXTEND
170 | LM32_FEATURE_CYCLE_COUNT;
173 static void lm32_standard_cpu_initfn(Object *obj)
175 LM32CPU *cpu = LM32_CPU(obj);
177 cpu->revision = 3;
178 cpu->num_interrupts = 32;
179 cpu->num_breakpoints = 4;
180 cpu->num_watchpoints = 4;
181 cpu->features = LM32_FEATURE_MULTIPLY
182 | LM32_FEATURE_DIVIDE
183 | LM32_FEATURE_SHIFT
184 | LM32_FEATURE_SIGN_EXTEND
185 | LM32_FEATURE_I_CACHE
186 | LM32_FEATURE_CYCLE_COUNT;
189 static void lm32_full_cpu_initfn(Object *obj)
191 LM32CPU *cpu = LM32_CPU(obj);
193 cpu->revision = 3;
194 cpu->num_interrupts = 32;
195 cpu->num_breakpoints = 4;
196 cpu->num_watchpoints = 4;
197 cpu->features = LM32_FEATURE_MULTIPLY
198 | LM32_FEATURE_DIVIDE
199 | LM32_FEATURE_SHIFT
200 | LM32_FEATURE_SIGN_EXTEND
201 | LM32_FEATURE_I_CACHE
202 | LM32_FEATURE_D_CACHE
203 | LM32_FEATURE_CYCLE_COUNT;
206 typedef struct LM32CPUInfo {
207 const char *name;
208 void (*initfn)(Object *obj);
209 } LM32CPUInfo;
211 static const LM32CPUInfo lm32_cpus[] = {
213 .name = "lm32-basic",
214 .initfn = lm32_basic_cpu_initfn,
217 .name = "lm32-standard",
218 .initfn = lm32_standard_cpu_initfn,
221 .name = "lm32-full",
222 .initfn = lm32_full_cpu_initfn,
226 static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
228 ObjectClass *oc;
229 char *typename;
231 if (cpu_model == NULL) {
232 return NULL;
235 typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model);
236 oc = object_class_by_name(typename);
237 g_free(typename);
238 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
239 object_class_is_abstract(oc))) {
240 oc = NULL;
242 return oc;
245 static void lm32_cpu_class_init(ObjectClass *oc, void *data)
247 LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
248 CPUClass *cc = CPU_CLASS(oc);
249 DeviceClass *dc = DEVICE_CLASS(oc);
251 lcc->parent_realize = dc->realize;
252 dc->realize = lm32_cpu_realizefn;
254 lcc->parent_reset = cc->reset;
255 cc->reset = lm32_cpu_reset;
257 cc->class_by_name = lm32_cpu_class_by_name;
258 cc->do_interrupt = lm32_cpu_do_interrupt;
259 cc->dump_state = lm32_cpu_dump_state;
260 cc->set_pc = lm32_cpu_set_pc;
261 cc->gdb_read_register = lm32_cpu_gdb_read_register;
262 cc->gdb_write_register = lm32_cpu_gdb_write_register;
263 #ifndef CONFIG_USER_ONLY
264 cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
265 cc->vmsd = &vmstate_lm32_cpu;
266 #endif
267 cc->gdb_num_core_regs = 32 + 7;
270 static void lm32_register_cpu_type(const LM32CPUInfo *info)
272 TypeInfo type_info = {
273 .parent = TYPE_LM32_CPU,
274 .instance_init = info->initfn,
277 type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name);
278 type_register(&type_info);
279 g_free((void *)type_info.name);
282 static const TypeInfo lm32_cpu_type_info = {
283 .name = TYPE_LM32_CPU,
284 .parent = TYPE_CPU,
285 .instance_size = sizeof(LM32CPU),
286 .instance_init = lm32_cpu_initfn,
287 .abstract = true,
288 .class_size = sizeof(LM32CPUClass),
289 .class_init = lm32_cpu_class_init,
292 static void lm32_cpu_register_types(void)
294 int i;
296 type_register_static(&lm32_cpu_type_info);
297 for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
298 lm32_register_cpu_type(&lm32_cpus[i]);
302 type_init(lm32_cpu_register_types)