target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/i386/pc.h"
   4 #include "hw/isa/isa.h"
   5
   6 #include "cpu.h"
   7 #include "sysemu/kvm.h"
   8
   9 static const VMStateDescription vmstate_segment = {
  10     .name = "segment",
  11     .version_id = 1,
  12     .minimum_version_id = 1,
  13     .minimum_version_id_old = 1,
  14     .fields      = (VMStateField []) {
  15         VMSTATE_UINT32(selector, SegmentCache),
  16         VMSTATE_UINTTL(base, SegmentCache),
  17         VMSTATE_UINT32(limit, SegmentCache),
  18         VMSTATE_UINT32(flags, SegmentCache),
  19         VMSTATE_END_OF_LIST()
  20     }
  21 };
  22
  23 #define VMSTATE_SEGMENT(_field, _state) {                            \
  24     .name       = (stringify(_field)),                               \
  25     .size       = sizeof(SegmentCache),                              \
  26     .vmsd       = &vmstate_segment,                                  \
  27     .flags      = VMS_STRUCT,                                        \
  28     .offset     = offsetof(_state, _field)                           \
  29             + type_check(SegmentCache,typeof_field(_state, _field))  \
  30 }
  31
  32 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  33     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  34
  35 static const VMStateDescription vmstate_xmm_reg = {
  36     .name = "xmm_reg",
  37     .version_id = 1,
  38     .minimum_version_id = 1,
  39     .minimum_version_id_old = 1,
  40     .fields      = (VMStateField []) {
  41         VMSTATE_UINT64(XMM_Q(0), XMMReg),
  42         VMSTATE_UINT64(XMM_Q(1), XMMReg),
  43         VMSTATE_END_OF_LIST()
  44     }
  45 };
  46
  47 #define VMSTATE_XMM_REGS(_field, _state, _n)                         \
  48     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
  49
  50 /* YMMH format is the same as XMM */
  51 static const VMStateDescription vmstate_ymmh_reg = {
  52     .name = "ymmh_reg",
  53     .version_id = 1,
  54     .minimum_version_id = 1,
  55     .minimum_version_id_old = 1,
  56     .fields      = (VMStateField []) {
  57         VMSTATE_UINT64(XMM_Q(0), XMMReg),
  58         VMSTATE_UINT64(XMM_Q(1), XMMReg),
  59         VMSTATE_END_OF_LIST()
  60     }
  61 };
  62
  63 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)                         \
  64     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
  65
  66 static const VMStateDescription vmstate_bnd_regs = {
  67     .name = "bnd_regs",
  68     .version_id = 1,
  69     .minimum_version_id = 1,
  70     .minimum_version_id_old = 1,
  71     .fields      = (VMStateField[]) {
  72         VMSTATE_UINT64(lb, BNDReg),
  73         VMSTATE_UINT64(ub, BNDReg),
  74         VMSTATE_END_OF_LIST()
  75     }
  76 };
  77
  78 #define VMSTATE_BND_REGS(_field, _state, _n)          \
  79     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
  80
  81 static const VMStateDescription vmstate_mtrr_var = {
  82     .name = "mtrr_var",
  83     .version_id = 1,
  84     .minimum_version_id = 1,
  85     .minimum_version_id_old = 1,
  86     .fields      = (VMStateField []) {
  87         VMSTATE_UINT64(base, MTRRVar),
  88         VMSTATE_UINT64(mask, MTRRVar),
  89         VMSTATE_END_OF_LIST()
  90     }
  91 };
  92
  93 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
  94     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
  95
  96 static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
  97 {
  98     fprintf(stderr, "call put_fpreg() with invalid arguments\n");
  99     exit(0);
 100 }
 101
 102 /* XXX: add that in a FPU generic layer */
 103 union x86_longdouble {
 104     uint64_t mant;
 105     uint16_t exp;
 106 };
 107
 108 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
 109 #define EXPBIAS1 1023
 110 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
 111 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
 112
 113 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
 114 {
 115     int e;
 116     /* mantissa */
 117     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 118     /* exponent + sign */
 119     e = EXPD1(temp) - EXPBIAS1 + 16383;
 120     e |= SIGND1(temp) >> 16;
 121     p->exp = e;
 122 }
 123
 124 static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
 125 {
 126     FPReg *fp_reg = opaque;
 127     uint64_t mant;
 128     uint16_t exp;
 129
 130     qemu_get_be64s(f, &mant);
 131     qemu_get_be16s(f, &exp);
 132     fp_reg->d = cpu_set_fp80(mant, exp);
 133     return 0;
 134 }
 135
 136 static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
 137 {
 138     FPReg *fp_reg = opaque;
 139     uint64_t mant;
 140     uint16_t exp;
 141     /* we save the real CPU data (in case of MMX usage only 'mant'
 142        contains the MMX register */
 143     cpu_get_fp80(&mant, &exp, fp_reg->d);
 144     qemu_put_be64s(f, &mant);
 145     qemu_put_be16s(f, &exp);
 146 }
 147
 148 static const VMStateInfo vmstate_fpreg = {
 149     .name = "fpreg",
 150     .get  = get_fpreg,
 151     .put  = put_fpreg,
 152 };
 153
 154 static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
 155 {
 156     union x86_longdouble *p = opaque;
 157     uint64_t mant;
 158
 159     qemu_get_be64s(f, &mant);
 160     p->mant = mant;
 161     p->exp = 0xffff;
 162     return 0;
 163 }
 164
 165 static const VMStateInfo vmstate_fpreg_1_mmx = {
 166     .name = "fpreg_1_mmx",
 167     .get  = get_fpreg_1_mmx,
 168     .put  = put_fpreg_error,
 169 };
 170
 171 static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
 172 {
 173     union x86_longdouble *p = opaque;
 174     uint64_t mant;
 175
 176     qemu_get_be64s(f, &mant);
 177     fp64_to_fp80(p, mant);
 178     return 0;
 179 }
 180
 181 static const VMStateInfo vmstate_fpreg_1_no_mmx = {
 182     .name = "fpreg_1_no_mmx",
 183     .get  = get_fpreg_1_no_mmx,
 184     .put  = put_fpreg_error,
 185 };
 186
 187 static bool fpregs_is_0(void *opaque, int version_id)
 188 {
 189     X86CPU *cpu = opaque;
 190     CPUX86State *env = &cpu->env;
 191
 192     return (env->fpregs_format_vmstate == 0);
 193 }
 194
 195 static bool fpregs_is_1_mmx(void *opaque, int version_id)
 196 {
 197     X86CPU *cpu = opaque;
 198     CPUX86State *env = &cpu->env;
 199     int guess_mmx;
 200
 201     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 202                  (env->fpus_vmstate & 0x3800) == 0);
 203     return (guess_mmx && (env->fpregs_format_vmstate == 1));
 204 }
 205
 206 static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
 207 {
 208     X86CPU *cpu = opaque;
 209     CPUX86State *env = &cpu->env;
 210     int guess_mmx;
 211
 212     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 213                  (env->fpus_vmstate & 0x3800) == 0);
 214     return (!guess_mmx && (env->fpregs_format_vmstate == 1));
 215 }
 216
 217 #define VMSTATE_FP_REGS(_field, _state, _n)                               \
 218     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
 219     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
 220     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
 221
 222 static bool version_is_5(void *opaque, int version_id)
 223 {
 224     return version_id == 5;
 225 }
 226
 227 #ifdef TARGET_X86_64
 228 static bool less_than_7(void *opaque, int version_id)
 229 {
 230     return version_id < 7;
 231 }
 232
 233 static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 234 {
 235     uint64_t *v = pv;
 236     *v = qemu_get_be32(f);
 237     return 0;
 238 }
 239
 240 static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 241 {
 242     uint64_t *v = pv;
 243     qemu_put_be32(f, *v);
 244 }
 245
 246 static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
 247     .name = "uint64_as_uint32",
 248     .get  = get_uint64_as_uint32,
 249     .put  = put_uint64_as_uint32,
 250 };
 251
 252 #define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
 253     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
 254 #endif
 255
 256 static void cpu_pre_save(void *opaque)
 257 {
 258     X86CPU *cpu = opaque;
 259     CPUX86State *env = &cpu->env;
 260     int i;
 261
 262     /* FPU */
 263     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 264     env->fptag_vmstate = 0;
 265     for(i = 0; i < 8; i++) {
 266         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 267     }
 268
 269     env->fpregs_format_vmstate = 0;
 270
 271     /*
 272      * Real mode guest segments register DPL should be zero.
 273      * Older KVM version were setting it wrongly.
 274      * Fixing it will allow live migration to host with unrestricted guest
 275      * support (otherwise the migration will fail with invalid guest state
 276      * error).
 277      */
 278     if (!(env->cr[0] & CR0_PE_MASK) &&
 279         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 280         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 281         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 282         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 283         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 284         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 285         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 286     }
 287
 288 }
 289
 290 static int cpu_post_load(void *opaque, int version_id)
 291 {
 292     X86CPU *cpu = opaque;
 293     CPUState *cs = CPU(cpu);
 294     CPUX86State *env = &cpu->env;
 295     int i;
 296
 297     /*
 298      * Real mode guest segments register DPL should be zero.
 299      * Older KVM version were setting it wrongly.
 300      * Fixing it will allow live migration from such host that don't have
 301      * restricted guest support to a host with unrestricted guest support
 302      * (otherwise the migration will fail with invalid guest state
 303      * error).
 304      */
 305     if (!(env->cr[0] & CR0_PE_MASK) &&
 306         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 307         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 308         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 309         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 310         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 311         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 312         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 313     }
 314
 315     /* XXX: restore FPU round state */
 316     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 317     env->fpus = env->fpus_vmstate & ~0x3800;
 318     env->fptag_vmstate ^= 0xff;
 319     for(i = 0; i < 8; i++) {
 320         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 321     }
 322
 323     cpu_breakpoint_remove_all(cs, BP_CPU);
 324     cpu_watchpoint_remove_all(cs, BP_CPU);
 325     for (i = 0; i < DR7_MAX_BP; i++) {
 326         hw_breakpoint_insert(env, i);
 327     }
 328     tlb_flush(cs, 1);
 329
 330     return 0;
 331 }
 332
 333 static bool async_pf_msr_needed(void *opaque)
 334 {
 335     X86CPU *cpu = opaque;
 336
 337     return cpu->env.async_pf_en_msr != 0;
 338 }
 339
 340 static bool pv_eoi_msr_needed(void *opaque)
 341 {
 342     X86CPU *cpu = opaque;
 343
 344     return cpu->env.pv_eoi_en_msr != 0;
 345 }
 346
 347 static bool steal_time_msr_needed(void *opaque)
 348 {
 349     X86CPU *cpu = opaque;
 350
 351     return cpu->env.steal_time_msr != 0;
 352 }
 353
 354 static const VMStateDescription vmstate_steal_time_msr = {
 355     .name = "cpu/steal_time_msr",
 356     .version_id = 1,
 357     .minimum_version_id = 1,
 358     .minimum_version_id_old = 1,
 359     .fields      = (VMStateField []) {
 360         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
 361         VMSTATE_END_OF_LIST()
 362     }
 363 };
 364
 365 static const VMStateDescription vmstate_async_pf_msr = {
 366     .name = "cpu/async_pf_msr",
 367     .version_id = 1,
 368     .minimum_version_id = 1,
 369     .minimum_version_id_old = 1,
 370     .fields      = (VMStateField []) {
 371         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 372         VMSTATE_END_OF_LIST()
 373     }
 374 };
 375
 376 static const VMStateDescription vmstate_pv_eoi_msr = {
 377     .name = "cpu/async_pv_eoi_msr",
 378     .version_id = 1,
 379     .minimum_version_id = 1,
 380     .minimum_version_id_old = 1,
 381     .fields      = (VMStateField []) {
 382         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 383         VMSTATE_END_OF_LIST()
 384     }
 385 };
 386
 387 static bool fpop_ip_dp_needed(void *opaque)
 388 {
 389     X86CPU *cpu = opaque;
 390     CPUX86State *env = &cpu->env;
 391
 392     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 393 }
 394
 395 static const VMStateDescription vmstate_fpop_ip_dp = {
 396     .name = "cpu/fpop_ip_dp",
 397     .version_id = 1,
 398     .minimum_version_id = 1,
 399     .minimum_version_id_old = 1,
 400     .fields      = (VMStateField []) {
 401         VMSTATE_UINT16(env.fpop, X86CPU),
 402         VMSTATE_UINT64(env.fpip, X86CPU),
 403         VMSTATE_UINT64(env.fpdp, X86CPU),
 404         VMSTATE_END_OF_LIST()
 405     }
 406 };
 407
 408 static bool tsc_adjust_needed(void *opaque)
 409 {
 410     X86CPU *cpu = opaque;
 411     CPUX86State *env = &cpu->env;
 412
 413     return env->tsc_adjust != 0;
 414 }
 415
 416 static const VMStateDescription vmstate_msr_tsc_adjust = {
 417     .name = "cpu/msr_tsc_adjust",
 418     .version_id = 1,
 419     .minimum_version_id = 1,
 420     .minimum_version_id_old = 1,
 421     .fields      = (VMStateField[]) {
 422         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 423         VMSTATE_END_OF_LIST()
 424     }
 425 };
 426
 427 static bool tscdeadline_needed(void *opaque)
 428 {
 429     X86CPU *cpu = opaque;
 430     CPUX86State *env = &cpu->env;
 431
 432     return env->tsc_deadline != 0;
 433 }
 434
 435 static const VMStateDescription vmstate_msr_tscdeadline = {
 436     .name = "cpu/msr_tscdeadline",
 437     .version_id = 1,
 438     .minimum_version_id = 1,
 439     .minimum_version_id_old = 1,
 440     .fields      = (VMStateField []) {
 441         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 442         VMSTATE_END_OF_LIST()
 443     }
 444 };
 445
 446 static bool misc_enable_needed(void *opaque)
 447 {
 448     X86CPU *cpu = opaque;
 449     CPUX86State *env = &cpu->env;
 450
 451     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 452 }
 453
 454 static bool feature_control_needed(void *opaque)
 455 {
 456     X86CPU *cpu = opaque;
 457     CPUX86State *env = &cpu->env;
 458
 459     return env->msr_ia32_feature_control != 0;
 460 }
 461
 462 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 463     .name = "cpu/msr_ia32_misc_enable",
 464     .version_id = 1,
 465     .minimum_version_id = 1,
 466     .minimum_version_id_old = 1,
 467     .fields      = (VMStateField []) {
 468         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 469         VMSTATE_END_OF_LIST()
 470     }
 471 };
 472
 473 static const VMStateDescription vmstate_msr_ia32_feature_control = {
 474     .name = "cpu/msr_ia32_feature_control",
 475     .version_id = 1,
 476     .minimum_version_id = 1,
 477     .minimum_version_id_old = 1,
 478     .fields      = (VMStateField []) {
 479         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
 480         VMSTATE_END_OF_LIST()
 481     }
 482 };
 483
 484 static bool pmu_enable_needed(void *opaque)
 485 {
 486     X86CPU *cpu = opaque;
 487     CPUX86State *env = &cpu->env;
 488     int i;
 489
 490     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
 491         env->msr_global_status || env->msr_global_ovf_ctrl) {
 492         return true;
 493     }
 494     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
 495         if (env->msr_fixed_counters[i]) {
 496             return true;
 497         }
 498     }
 499     for (i = 0; i < MAX_GP_COUNTERS; i++) {
 500         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
 501             return true;
 502         }
 503     }
 504
 505     return false;
 506 }
 507
 508 static const VMStateDescription vmstate_msr_architectural_pmu = {
 509     .name = "cpu/msr_architectural_pmu",
 510     .version_id = 1,
 511     .minimum_version_id = 1,
 512     .minimum_version_id_old = 1,
 513     .fields      = (VMStateField []) {
 514         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
 515         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
 516         VMSTATE_UINT64(env.msr_global_status, X86CPU),
 517         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
 518         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
 519         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
 520         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
 521         VMSTATE_END_OF_LIST()
 522     }
 523 };
 524
 525 static bool mpx_needed(void *opaque)
 526 {
 527     X86CPU *cpu = opaque;
 528     CPUX86State *env = &cpu->env;
 529     unsigned int i;
 530
 531     for (i = 0; i < 4; i++) {
 532         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
 533             return true;
 534         }
 535     }
 536
 537     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
 538         return true;
 539     }
 540
 541     return !!env->msr_bndcfgs;
 542 }
 543
 544 static const VMStateDescription vmstate_mpx = {
 545     .name = "cpu/mpx",
 546     .version_id = 1,
 547     .minimum_version_id = 1,
 548     .minimum_version_id_old = 1,
 549     .fields      = (VMStateField[]) {
 550         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
 551         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
 552         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
 553         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
 554         VMSTATE_END_OF_LIST()
 555     }
 556 };
 557
 558 static bool hyperv_hypercall_enable_needed(void *opaque)
 559 {
 560     X86CPU *cpu = opaque;
 561     CPUX86State *env = &cpu->env;
 562
 563     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
 564 }
 565
 566 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
 567     .name = "cpu/msr_hyperv_hypercall",
 568     .version_id = 1,
 569     .minimum_version_id = 1,
 570     .minimum_version_id_old = 1,
 571     .fields      = (VMStateField []) {
 572         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
 573         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
 574         VMSTATE_END_OF_LIST()
 575     }
 576 };
 577
 578 static bool hyperv_vapic_enable_needed(void *opaque)
 579 {
 580     X86CPU *cpu = opaque;
 581     CPUX86State *env = &cpu->env;
 582
 583     return env->msr_hv_vapic != 0;
 584 }
 585
 586 static const VMStateDescription vmstate_msr_hyperv_vapic = {
 587     .name = "cpu/msr_hyperv_vapic",
 588     .version_id = 1,
 589     .minimum_version_id = 1,
 590     .minimum_version_id_old = 1,
 591     .fields      = (VMStateField []) {
 592         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
 593         VMSTATE_END_OF_LIST()
 594     }
 595 };
 596
 597 static bool hyperv_time_enable_needed(void *opaque)
 598 {
 599     X86CPU *cpu = opaque;
 600     CPUX86State *env = &cpu->env;
 601
 602     return env->msr_hv_tsc != 0;
 603 }
 604
 605 static const VMStateDescription vmstate_msr_hyperv_time = {
 606     .name = "cpu/msr_hyperv_time",
 607     .version_id = 1,
 608     .minimum_version_id = 1,
 609     .minimum_version_id_old = 1,
 610     .fields      = (VMStateField []) {
 611         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
 612         VMSTATE_END_OF_LIST()
 613     }
 614 };
 615
 616 const VMStateDescription vmstate_x86_cpu = {
 617     .name = "cpu",
 618     .version_id = 12,
 619     .minimum_version_id = 3,
 620     .minimum_version_id_old = 3,
 621     .pre_save = cpu_pre_save,
 622     .post_load = cpu_post_load,
 623     .fields      = (VMStateField []) {
 624         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
 625         VMSTATE_UINTTL(env.eip, X86CPU),
 626         VMSTATE_UINTTL(env.eflags, X86CPU),
 627         VMSTATE_UINT32(env.hflags, X86CPU),
 628         /* FPU */
 629         VMSTATE_UINT16(env.fpuc, X86CPU),
 630         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
 631         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
 632         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
 633         VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
 634
 635         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
 636         VMSTATE_SEGMENT(env.ldt, X86CPU),
 637         VMSTATE_SEGMENT(env.tr, X86CPU),
 638         VMSTATE_SEGMENT(env.gdt, X86CPU),
 639         VMSTATE_SEGMENT(env.idt, X86CPU),
 640
 641         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 642 #ifdef TARGET_X86_64
 643         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
 644         VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
 645         VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
 646         VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
 647         VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
 648 #else
 649         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
 650         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 651 #endif
 652
 653         VMSTATE_UINTTL(env.cr[0], X86CPU),
 654         VMSTATE_UINTTL(env.cr[2], X86CPU),
 655         VMSTATE_UINTTL(env.cr[3], X86CPU),
 656         VMSTATE_UINTTL(env.cr[4], X86CPU),
 657         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
 658         /* MMU */
 659         VMSTATE_INT32(env.a20_mask, X86CPU),
 660         /* XMM */
 661         VMSTATE_UINT32(env.mxcsr, X86CPU),
 662         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS),
 663
 664 #ifdef TARGET_X86_64
 665         VMSTATE_UINT64(env.efer, X86CPU),
 666         VMSTATE_UINT64(env.star, X86CPU),
 667         VMSTATE_UINT64(env.lstar, X86CPU),
 668         VMSTATE_UINT64(env.cstar, X86CPU),
 669         VMSTATE_UINT64(env.fmask, X86CPU),
 670         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 671 #endif
 672         VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
 673
 674         VMSTATE_UINT64_V(env.pat, X86CPU, 5),
 675         VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
 676
 677         VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
 678         VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
 679         VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
 680         VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
 681         VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
 682         VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
 683         VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
 684         VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
 685         VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
 686         VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
 687         VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
 688         /* MTRRs */
 689         VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
 690         VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
 691         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8),
 692         /* KVM-related states */
 693         VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
 694         VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
 695         VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
 696         VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
 697         VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
 698         VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
 699         VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
 700         VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
 701         VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
 702         /* MCE */
 703         VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
 704         VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
 705         VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
 706         VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
 707         /* rdtscp */
 708         VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
 709         /* KVM pvclock msr */
 710         VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
 711         VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
 712         /* XSAVE related fields */
 713         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
 714         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
 715         VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
 716         VMSTATE_END_OF_LIST()
 717         /* The above list is not sorted /wrt version numbers, watch out! */
 718     },
 719     .subsections = (VMStateSubsection []) {
 720         {
 721             .vmsd = &vmstate_async_pf_msr,
 722             .needed = async_pf_msr_needed,
 723         } , {
 724             .vmsd = &vmstate_pv_eoi_msr,
 725             .needed = pv_eoi_msr_needed,
 726         } , {
 727             .vmsd = &vmstate_steal_time_msr,
 728             .needed = steal_time_msr_needed,
 729         } , {
 730             .vmsd = &vmstate_fpop_ip_dp,
 731             .needed = fpop_ip_dp_needed,
 732         }, {
 733             .vmsd = &vmstate_msr_tsc_adjust,
 734             .needed = tsc_adjust_needed,
 735         }, {
 736             .vmsd = &vmstate_msr_tscdeadline,
 737             .needed = tscdeadline_needed,
 738         }, {
 739             .vmsd = &vmstate_msr_ia32_misc_enable,
 740             .needed = misc_enable_needed,
 741         }, {
 742             .vmsd = &vmstate_msr_ia32_feature_control,
 743             .needed = feature_control_needed,
 744         }, {
 745             .vmsd = &vmstate_msr_architectural_pmu,
 746             .needed = pmu_enable_needed,
 747         } , {
 748             .vmsd = &vmstate_mpx,
 749             .needed = mpx_needed,
 750         }, {
 751             .vmsd = &vmstate_msr_hypercall_hypercall,
 752             .needed = hyperv_hypercall_enable_needed,
 753         }, {
 754             .vmsd = &vmstate_msr_hyperv_vapic,
 755             .needed = hyperv_vapic_enable_needed,
 756         }, {
 757             .vmsd = &vmstate_msr_hyperv_time,
 758             .needed = hyperv_time_enable_needed,
 759         } , {
 760             /* empty */
 761         }
 762     }
 763 };