hw/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "hw.h"
  14 #include "pc.h"
  15 #include "vt82c686.h"
  16 #include "i2c.h"
  17 #include "smbus.h"
  18 #include "pci.h"
  19 #include "isa.h"
  20 #include "sysbus.h"
  21 #include "mips.h"
  22 #include "apm.h"
  23 #include "acpi.h"
  24 #include "pm_smbus.h"
  25 #include "sysemu.h"
  26 #include "qemu-timer.h"
  27
  28 typedef uint32_t pci_addr_t;
  29 #include "pci_host.h"
  30 //#define DEBUG_VT82C686B
  31
  32 #ifdef DEBUG_VT82C686B
  33 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  34 #else
  35 #define DPRINTF(fmt, ...)
  36 #endif
  37
  38 typedef struct SuperIOConfig
  39 {
  40     uint8_t config[0xff];
  41     uint8_t index;
  42     uint8_t data;
  43 } SuperIOConfig;
  44
  45 typedef struct VT82C686BState {
  46     PCIDevice dev;
  47     SuperIOConfig superio_conf;
  48 } VT82C686BState;
  49
  50 static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
  51 {
  52     int can_write;
  53     SuperIOConfig *superio_conf = opaque;
  54
  55     DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x\n", addr, data);
  56     if (addr == 0x3f0) {
  57         superio_conf->index = data & 0xff;
  58     } else {
  59         /* 0x3f1 */
  60         switch (superio_conf->index) {
  61         case 0x00 ... 0xdf:
  62         case 0xe4:
  63         case 0xe5:
  64         case 0xe9 ... 0xed:
  65         case 0xf3:
  66         case 0xf5:
  67         case 0xf7:
  68         case 0xf9 ... 0xfb:
  69         case 0xfd ... 0xff:
  70             can_write = 0;
  71             break;
  72         default:
  73             can_write = 1;
  74
  75             if (can_write) {
  76                 switch (superio_conf->index) {
  77                 case 0xe7:
  78                     if ((data & 0xff) != 0xfe) {
  79                         DPRINTF("chage uart 1 base. unsupported yet\n");
  80                     }
  81                     break;
  82                 case 0xe8:
  83                     if ((data & 0xff) != 0xbe) {
  84                         DPRINTF("chage uart 2 base. unsupported yet\n");
  85                     }
  86                     break;
  87
  88                 default:
  89                     superio_conf->config[superio_conf->index] = data & 0xff;
  90                 }
  91             }
  92         }
  93         superio_conf->config[superio_conf->index] = data & 0xff;
  94     }
  95 }
  96
  97 static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
  98 {
  99     SuperIOConfig *superio_conf = opaque;
 100
 101     DPRINTF("superio_ioport_readb  address 0x%x\n", addr);
 102     return (superio_conf->config[superio_conf->index]);
 103 }
 104
 105 static void vt82c686b_reset(void * opaque)
 106 {
 107     PCIDevice *d = opaque;
 108     uint8_t *pci_conf = d->config;
 109     VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
 110
 111     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 112     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 113                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 114     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 115
 116     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 117     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 118     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 119     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 120     pci_conf[0x59] = 0x04;
 121     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 122     pci_conf[0x5f] = 0x04;
 123     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 124
 125     vt82c->superio_conf.config[0xe0] = 0x3c;
 126     vt82c->superio_conf.config[0xe2] = 0x03;
 127     vt82c->superio_conf.config[0xe3] = 0xfc;
 128     vt82c->superio_conf.config[0xe6] = 0xde;
 129     vt82c->superio_conf.config[0xe7] = 0xfe;
 130     vt82c->superio_conf.config[0xe8] = 0xbe;
 131 }
 132
 133 /* write config pci function0 registers. PCI-ISA bridge */
 134 static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
 135                                    uint32_t val, int len)
 136 {
 137     VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
 138
 139     DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x\n",
 140            address, val, len);
 141
 142     pci_default_write_config(d, address, val, len);
 143     if (address == 0x85) {  /* enable or disable super IO configure */
 144         if (val & 0x2) {
 145             /* floppy also uses 0x3f0 and 0x3f1.
 146              * But we do not emulate flopy,so just set it here. */
 147             isa_unassign_ioport(0x3f0, 2);
 148             register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
 149                                  &vt686->superio_conf);
 150             register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
 151                                   &vt686->superio_conf);
 152         } else {
 153             isa_unassign_ioport(0x3f0, 2);
 154         }
 155     }
 156 }
 157
 158 #define ACPI_DBG_IO_ADDR  0xb044
 159
 160 typedef struct VT686PMState {
 161     PCIDevice dev;
 162     ACPIREGS ar;
 163     APMState apm;
 164     PMSMBus smb;
 165     uint32_t smb_io_base;
 166 } VT686PMState;
 167
 168 typedef struct VT686AC97State {
 169     PCIDevice dev;
 170 } VT686AC97State;
 171
 172 typedef struct VT686MC97State {
 173     PCIDevice dev;
 174 } VT686MC97State;
 175
 176 static void pm_update_sci(VT686PMState *s)
 177 {
 178     int sci_level, pmsts;
 179
 180     pmsts = acpi_pm1_evt_get_sts(&s->ar);
 181     sci_level = (((pmsts & s->ar.pm1.evt.en) &
 182                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 183                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 184                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 185                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 186     qemu_set_irq(s->dev.irq[0], sci_level);
 187     /* schedule a timer interruption if needed */
 188     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 189                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 190 }
 191
 192 static void pm_tmr_timer(ACPIREGS *ar)
 193 {
 194     VT686PMState *s = container_of(ar, VT686PMState, ar);
 195     pm_update_sci(s);
 196 }
 197
 198 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 199 {
 200     VT686PMState *s = opaque;
 201
 202     addr &= 0x0f;
 203     switch (addr) {
 204     case 0x00:
 205         acpi_pm1_evt_write_sts(&s->ar, val);
 206         pm_update_sci(s);
 207         break;
 208     case 0x02:
 209         acpi_pm1_evt_write_en(&s->ar, val);
 210         pm_update_sci(s);
 211         break;
 212     case 0x04:
 213         acpi_pm1_cnt_write(&s->ar, val, 0);
 214         break;
 215     default:
 216         break;
 217     }
 218     DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
 219 }
 220
 221 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 222 {
 223     VT686PMState *s = opaque;
 224     uint32_t val;
 225
 226     addr &= 0x0f;
 227     switch (addr) {
 228     case 0x00:
 229         val = acpi_pm1_evt_get_sts(&s->ar);
 230         break;
 231     case 0x02:
 232         val = s->ar.pm1.evt.en;
 233         break;
 234     case 0x04:
 235         val = s->ar.pm1.cnt.cnt;
 236         break;
 237     default:
 238         val = 0;
 239         break;
 240     }
 241     DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
 242     return val;
 243 }
 244
 245 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 246 {
 247     addr &= 0x0f;
 248     DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
 249 }
 250
 251 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 252 {
 253     VT686PMState *s = opaque;
 254     uint32_t val;
 255
 256     addr &= 0x0f;
 257     switch (addr) {
 258     case 0x08:
 259         val = acpi_pm_tmr_get(&s->ar);
 260         break;
 261     default:
 262         val = 0;
 263         break;
 264     }
 265     DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 266     return val;
 267 }
 268
 269 static void pm_io_space_update(VT686PMState *s)
 270 {
 271     uint32_t pm_io_base;
 272
 273     if (s->dev.config[0x80] & 1) {
 274         pm_io_base = pci_get_long(s->dev.config + 0x40);
 275         pm_io_base &= 0xffc0;
 276
 277         /* XXX: need to improve memory and ioport allocation */
 278         DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 279         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 280         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 281         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 282         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 283     }
 284 }
 285
 286 static void pm_write_config(PCIDevice *d,
 287                             uint32_t address, uint32_t val, int len)
 288 {
 289     DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x\n",
 290            address, val, len);
 291     pci_default_write_config(d, address, val, len);
 292 }
 293
 294 static int vmstate_acpi_post_load(void *opaque, int version_id)
 295 {
 296     VT686PMState *s = opaque;
 297
 298     pm_io_space_update(s);
 299     return 0;
 300 }
 301
 302 static const VMStateDescription vmstate_acpi = {
 303     .name = "vt82c686b_pm",
 304     .version_id = 1,
 305     .minimum_version_id = 1,
 306     .minimum_version_id_old = 1,
 307     .post_load = vmstate_acpi_post_load,
 308     .fields      = (VMStateField []) {
 309         VMSTATE_PCI_DEVICE(dev, VT686PMState),
 310         VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
 311         VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
 312         VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
 313         VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
 314         VMSTATE_TIMER(ar.tmr.timer, VT686PMState),
 315         VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
 316         VMSTATE_END_OF_LIST()
 317     }
 318 };
 319
 320 /*
 321  * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 322  * just register a PCI device now, functionalities will be implemented later.
 323  */
 324
 325 static int vt82c686b_ac97_initfn(PCIDevice *dev)
 326 {
 327     VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
 328     uint8_t *pci_conf = s->dev.config;
 329
 330     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 331                  PCI_COMMAND_PARITY);
 332     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
 333                  PCI_STATUS_DEVSEL_MEDIUM);
 334     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 335
 336     return 0;
 337 }
 338
 339 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
 340 {
 341     PCIDevice *dev;
 342
 343     dev = pci_create(bus, devfn, "VT82C686B_AC97");
 344     qdev_init_nofail(&dev->qdev);
 345 }
 346
 347 static void via_ac97_class_init(ObjectClass *klass, void *data)
 348 {
 349     DeviceClass *dc = DEVICE_CLASS(klass);
 350     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 351
 352     k->init = vt82c686b_ac97_initfn;
 353     k->vendor_id = PCI_VENDOR_ID_VIA;
 354     k->device_id = PCI_DEVICE_ID_VIA_AC97;
 355     k->revision = 0x50;
 356     k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
 357     dc->desc = "AC97";
 358 }
 359
 360 static TypeInfo via_ac97_info = {
 361     .name          = "VT82C686B_AC97",
 362     .parent        = TYPE_PCI_DEVICE,
 363     .instance_size = sizeof(VT686AC97State),
 364     .class_init    = via_ac97_class_init,
 365 };
 366
 367 static int vt82c686b_mc97_initfn(PCIDevice *dev)
 368 {
 369     VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
 370     uint8_t *pci_conf = s->dev.config;
 371
 372     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 373                  PCI_COMMAND_VGA_PALETTE);
 374     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 375     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 376
 377     return 0;
 378 }
 379
 380 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
 381 {
 382     PCIDevice *dev;
 383
 384     dev = pci_create(bus, devfn, "VT82C686B_MC97");
 385     qdev_init_nofail(&dev->qdev);
 386 }
 387
 388 static void via_mc97_class_init(ObjectClass *klass, void *data)
 389 {
 390     DeviceClass *dc = DEVICE_CLASS(klass);
 391     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 392
 393     k->init = vt82c686b_mc97_initfn;
 394     k->vendor_id = PCI_VENDOR_ID_VIA;
 395     k->device_id = PCI_DEVICE_ID_VIA_MC97;
 396     k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
 397     k->revision = 0x30;
 398     dc->desc = "MC97";
 399 }
 400
 401 static TypeInfo via_mc97_info = {
 402     .name          = "VT82C686B_MC97",
 403     .parent        = TYPE_PCI_DEVICE,
 404     .instance_size = sizeof(VT686MC97State),
 405     .class_init    = via_mc97_class_init,
 406 };
 407
 408 /* vt82c686 pm init */
 409 static int vt82c686b_pm_initfn(PCIDevice *dev)
 410 {
 411     VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
 412     uint8_t *pci_conf;
 413
 414     pci_conf = s->dev.config;
 415     pci_set_word(pci_conf + PCI_COMMAND, 0);
 416     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 417                  PCI_STATUS_DEVSEL_MEDIUM);
 418
 419     /* 0x48-0x4B is Power Management I/O Base */
 420     pci_set_long(pci_conf + 0x48, 0x00000001);
 421
 422     /* SMB ports:0xeee0~0xeeef */
 423     s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
 424     pci_conf[0x90] = s->smb_io_base | 1;
 425     pci_conf[0x91] = s->smb_io_base >> 8;
 426     pci_conf[0xd2] = 0x90;
 427     register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
 428     register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
 429
 430     apm_init(&s->apm, NULL, s);
 431
 432     acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
 433     acpi_pm1_cnt_init(&s->ar);
 434
 435     pm_smbus_init(&s->dev.qdev, &s->smb);
 436
 437     return 0;
 438 }
 439
 440 i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 441                        qemu_irq sci_irq)
 442 {
 443     PCIDevice *dev;
 444     VT686PMState *s;
 445
 446     dev = pci_create(bus, devfn, "VT82C686B_PM");
 447     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 448
 449     s = DO_UPCAST(VT686PMState, dev, dev);
 450
 451     qdev_init_nofail(&dev->qdev);
 452
 453     return s->smb.smbus;
 454 }
 455
 456 static Property via_pm_properties[] = {
 457     DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
 458     DEFINE_PROP_END_OF_LIST(),
 459 };
 460
 461 static void via_pm_class_init(ObjectClass *klass, void *data)
 462 {
 463     DeviceClass *dc = DEVICE_CLASS(klass);
 464     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 465
 466     k->init = vt82c686b_pm_initfn;
 467     k->config_write = pm_write_config;
 468     k->vendor_id = PCI_VENDOR_ID_VIA;
 469     k->device_id = PCI_DEVICE_ID_VIA_ACPI;
 470     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 471     k->revision = 0x40;
 472     dc->desc = "PM";
 473     dc->vmsd = &vmstate_acpi;
 474     dc->props = via_pm_properties;
 475 }
 476
 477 static TypeInfo via_pm_info = {
 478     .name          = "VT82C686B_PM",
 479     .parent        = TYPE_PCI_DEVICE,
 480     .instance_size = sizeof(VT686PMState),
 481     .class_init    = via_pm_class_init,
 482 };
 483
 484 static const VMStateDescription vmstate_via = {
 485     .name = "vt82c686b",
 486     .version_id = 1,
 487     .minimum_version_id = 1,
 488     .minimum_version_id_old = 1,
 489     .fields      = (VMStateField []) {
 490         VMSTATE_PCI_DEVICE(dev, VT82C686BState),
 491         VMSTATE_END_OF_LIST()
 492     }
 493 };
 494
 495 /* init the PCI-to-ISA bridge */
 496 static int vt82c686b_initfn(PCIDevice *d)
 497 {
 498     uint8_t *pci_conf;
 499     uint8_t *wmask;
 500     int i;
 501
 502     isa_bus_new(&d->qdev, pci_address_space_io(d));
 503
 504     pci_conf = d->config;
 505     pci_config_set_prog_interface(pci_conf, 0x0);
 506
 507     wmask = d->wmask;
 508     for (i = 0x00; i < 0xff; i++) {
 509        if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
 510            wmask[i] = 0x00;
 511        }
 512     }
 513
 514     qemu_register_reset(vt82c686b_reset, d);
 515
 516     return 0;
 517 }
 518
 519 ISABus *vt82c686b_init(PCIBus *bus, int devfn)
 520 {
 521     PCIDevice *d;
 522
 523     d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
 524
 525     return DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0"));
 526 }
 527
 528 static void via_class_init(ObjectClass *klass, void *data)
 529 {
 530     DeviceClass *dc = DEVICE_CLASS(klass);
 531     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 532
 533     k->init = vt82c686b_initfn;
 534     k->config_write = vt82c686b_write_config;
 535     k->vendor_id = PCI_VENDOR_ID_VIA;
 536     k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
 537     k->class_id = PCI_CLASS_BRIDGE_ISA;
 538     k->revision = 0x40;
 539     dc->desc = "ISA bridge";
 540     dc->no_user = 1;
 541     dc->vmsd = &vmstate_via;
 542 }
 543
 544 static TypeInfo via_info = {
 545     .name          = "VT82C686B",
 546     .parent        = TYPE_PCI_DEVICE,
 547     .instance_size = sizeof(VT82C686BState),
 548     .class_init    = via_class_init,
 549 };
 550
 551 static void vt82c686b_register_types(void)
 552 {
 553     type_register_static(&via_ac97_info);
 554     type_register_static(&via_mc97_info);
 555     type_register_static(&via_pm_info);
 556     type_register_static(&via_info);
 557 }
 558
 559 type_init(vt82c686b_register_types)