target-xtensa/overlay_tool.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
  29         a1, a2, a3, a4, a5, a6) \
  30     { .targno = (no), .type = (typ), .group = (grp) },
  31
  32 #ifndef XCHAL_HAVE_DIV32
  33 #define XCHAL_HAVE_DIV32 0
  34 #endif
  35
  36 #ifndef XCHAL_UNALIGNED_LOAD_HW
  37 #define XCHAL_UNALIGNED_LOAD_HW 0
  38 #endif
  39
  40 #ifndef XCHAL_HAVE_VECBASE
  41 #define XCHAL_HAVE_VECBASE 0
  42 #define XCHAL_VECBASE_RESET_VADDR 0
  43 #endif
  44
  45 #ifndef XCHAL_HW_MIN_VERSION
  46 #define XCHAL_HW_MIN_VERSION 0
  47 #endif
  48
  49 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
  50
  51 #define XTENSA_OPTIONS ( \
  52     XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
  53     XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
  54     XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
  55     XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
  56     XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
  57     XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
  58     XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
  59     XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
  60     XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
  61     XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
  62     XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
  63     XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
  64     XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
  65     XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
  66     XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
  67     XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
  68     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
  69     XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
  70         XTENSA_OPTION_ATOMCTL) | \
  71     /* Interrupts and exceptions */ \
  72     XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
  73     XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
  74     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
  75         XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
  76     XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
  77     XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
  78         XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
  79     XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
  80     /* Local memory, TODO */ \
  81     XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
  82     XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
  83             XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
  84     XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
  85     XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
  86             XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
  87     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
  88     /* Memory protection and translation */ \
  89     XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
  90             XTENSA_OPTION_REGION_PROTECTION) | \
  91     XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
  92             XTENSA_OPTION_REGION_TRANSLATION) | \
  93     XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
  94     XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
  95     /* Other, TODO */ \
  96     XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
  97     XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
  98     XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
  99     XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
 100     XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))
 101
 102 #ifndef XCHAL_WINDOW_OF4_VECOFS
 103 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 104 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 105 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 106 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 107 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 108 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 109 #endif
 110
 111 #if XCHAL_HAVE_WINDOWED
 112 #define WINDOW_VECTORS \
 113    [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
 114        XCHAL_WINDOW_VECTORS_VADDR, \
 115    [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
 116        XCHAL_WINDOW_VECTORS_VADDR, \
 117    [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
 118        XCHAL_WINDOW_VECTORS_VADDR, \
 119    [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
 120        XCHAL_WINDOW_VECTORS_VADDR, \
 121    [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
 122        XCHAL_WINDOW_VECTORS_VADDR, \
 123    [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
 124        XCHAL_WINDOW_VECTORS_VADDR,
 125 #else
 126 #define WINDOW_VECTORS
 127 #endif
 128
 129 #define EXCEPTION_VECTORS { \
 130         [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
 131         WINDOW_VECTORS \
 132         [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
 133         [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
 134         [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
 135         [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
 136     }
 137
 138 #define INTERRUPT_VECTORS { \
 139         0, \
 140         0, \
 141         XCHAL_INTLEVEL2_VECTOR_VADDR, \
 142         XCHAL_INTLEVEL3_VECTOR_VADDR, \
 143         XCHAL_INTLEVEL4_VECTOR_VADDR, \
 144         XCHAL_INTLEVEL5_VECTOR_VADDR, \
 145         XCHAL_INTLEVEL6_VECTOR_VADDR, \
 146         XCHAL_INTLEVEL7_VECTOR_VADDR, \
 147     }
 148
 149 #define LEVEL_MASKS { \
 150         [1] = XCHAL_INTLEVEL1_MASK, \
 151         [2] = XCHAL_INTLEVEL2_MASK, \
 152         [3] = XCHAL_INTLEVEL3_MASK, \
 153         [4] = XCHAL_INTLEVEL4_MASK, \
 154         [5] = XCHAL_INTLEVEL5_MASK, \
 155         [6] = XCHAL_INTLEVEL6_MASK, \
 156         [7] = XCHAL_INTLEVEL7_MASK, \
 157     }
 158
 159 #define INTTYPE_MASKS { \
 160         [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
 161         [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
 162         [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
 163     }
 164
 165 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
 166 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
 167 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
 168 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
 169 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
 170 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
 171 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
 172 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
 173 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
 174
 175
 176 #define INTERRUPT(i) { \
 177         .level = XCHAL_INT ## i ## _LEVEL, \
 178         .inttype = XCHAL_INT ## i ## _TYPE, \
 179     }
 180
 181 #define INTERRUPTS { \
 182         [0] = INTERRUPT(0), \
 183         [1] = INTERRUPT(1), \
 184         [2] = INTERRUPT(2), \
 185         [3] = INTERRUPT(3), \
 186         [4] = INTERRUPT(4), \
 187         [5] = INTERRUPT(5), \
 188         [6] = INTERRUPT(6), \
 189         [7] = INTERRUPT(7), \
 190         [8] = INTERRUPT(8), \
 191         [9] = INTERRUPT(9), \
 192         [10] = INTERRUPT(10), \
 193         [11] = INTERRUPT(11), \
 194         [12] = INTERRUPT(12), \
 195         [13] = INTERRUPT(13), \
 196         [14] = INTERRUPT(14), \
 197         [15] = INTERRUPT(15), \
 198         [16] = INTERRUPT(16), \
 199         [17] = INTERRUPT(17), \
 200         [18] = INTERRUPT(18), \
 201         [19] = INTERRUPT(19), \
 202         [20] = INTERRUPT(20), \
 203         [21] = INTERRUPT(21), \
 204         [22] = INTERRUPT(22), \
 205         [23] = INTERRUPT(23), \
 206         [24] = INTERRUPT(24), \
 207         [25] = INTERRUPT(25), \
 208         [26] = INTERRUPT(26), \
 209         [27] = INTERRUPT(27), \
 210         [28] = INTERRUPT(28), \
 211         [29] = INTERRUPT(29), \
 212         [30] = INTERRUPT(30), \
 213         [31] = INTERRUPT(31), \
 214     }
 215
 216 #define TIMERINTS { \
 217         [0] = XCHAL_TIMER0_INTERRUPT, \
 218         [1] = XCHAL_TIMER1_INTERRUPT, \
 219         [2] = XCHAL_TIMER2_INTERRUPT, \
 220     }
 221
 222 #define EXTINTS { \
 223         [0] = XCHAL_EXTINT0_NUM, \
 224         [1] = XCHAL_EXTINT1_NUM, \
 225         [2] = XCHAL_EXTINT2_NUM, \
 226         [3] = XCHAL_EXTINT3_NUM, \
 227         [4] = XCHAL_EXTINT4_NUM, \
 228         [5] = XCHAL_EXTINT5_NUM, \
 229         [6] = XCHAL_EXTINT6_NUM, \
 230         [7] = XCHAL_EXTINT7_NUM, \
 231         [8] = XCHAL_EXTINT8_NUM, \
 232         [9] = XCHAL_EXTINT9_NUM, \
 233         [10] = XCHAL_EXTINT10_NUM, \
 234         [11] = XCHAL_EXTINT11_NUM, \
 235         [12] = XCHAL_EXTINT12_NUM, \
 236         [13] = XCHAL_EXTINT13_NUM, \
 237         [14] = XCHAL_EXTINT14_NUM, \
 238         [15] = XCHAL_EXTINT15_NUM, \
 239         [16] = XCHAL_EXTINT16_NUM, \
 240         [17] = XCHAL_EXTINT17_NUM, \
 241         [18] = XCHAL_EXTINT18_NUM, \
 242         [19] = XCHAL_EXTINT19_NUM, \
 243         [20] = XCHAL_EXTINT20_NUM, \
 244         [21] = XCHAL_EXTINT21_NUM, \
 245         [22] = XCHAL_EXTINT22_NUM, \
 246         [23] = XCHAL_EXTINT23_NUM, \
 247         [24] = XCHAL_EXTINT24_NUM, \
 248         [25] = XCHAL_EXTINT25_NUM, \
 249         [26] = XCHAL_EXTINT26_NUM, \
 250         [27] = XCHAL_EXTINT27_NUM, \
 251         [28] = XCHAL_EXTINT28_NUM, \
 252         [29] = XCHAL_EXTINT29_NUM, \
 253         [30] = XCHAL_EXTINT30_NUM, \
 254         [31] = XCHAL_EXTINT31_NUM, \
 255     }
 256
 257 #define EXCEPTIONS_SECTION \
 258     .excm_level = XCHAL_EXCM_LEVEL, \
 259     .vecbase = XCHAL_VECBASE_RESET_VADDR, \
 260     .exception_vector = EXCEPTION_VECTORS
 261
 262 #define INTERRUPTS_SECTION \
 263     .ninterrupt = XCHAL_NUM_INTERRUPTS, \
 264     .nlevel = XCHAL_NUM_INTLEVELS, \
 265     .interrupt_vector = INTERRUPT_VECTORS, \
 266     .level_mask = LEVEL_MASKS, \
 267     .inttype_mask = INTTYPE_MASKS, \
 268     .interrupt = INTERRUPTS, \
 269     .nccompare = XCHAL_NUM_TIMERS, \
 270     .timerint = TIMERINTS, \
 271     .nextint = XCHAL_NUM_EXTINTERRUPTS, \
 272     .extint = EXTINTS
 273
 274 #if XCHAL_HAVE_PTP_MMU
 275
 276 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
 277         .nways = ways, \
 278         .way_size = { \
 279             (refill_way_size), (refill_way_size), \
 280             (refill_way_size), (refill_way_size), \
 281             4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
 282         }, \
 283         .varway56 = (way56), \
 284         .nrefillentries = (refill_way_size) * 4, \
 285     }
 286
 287 #define ITLB(varway56) \
 288     TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
 289
 290 #define DTLB(varway56) \
 291     TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
 292
 293 #define TLB_SECTION \
 294     .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
 295     .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
 296
 297 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
 298
 299 #define TLB_TEMPLATE { \
 300         .nways = 1, \
 301         .way_size = { \
 302             8, \
 303         } \
 304     }
 305
 306 #define TLB_SECTION \
 307     .itlb = TLB_TEMPLATE, \
 308     .dtlb = TLB_TEMPLATE
 309
 310 #endif
 311
 312 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
 313 #define REGISTER_CORE(core) \
 314     static void __attribute__((constructor)) register_core(void) \
 315     { \
 316         static XtensaConfigList node = { \
 317             .config = &core, \
 318         }; \
 319         xtensa_register_core(&node); \
 320     }
 321 #else
 322 #define REGISTER_CORE(core)
 323 #endif
 324
 325 #define DEBUG_SECTION \
 326     .debug_level = XCHAL_DEBUGLEVEL, \
 327     .nibreak = XCHAL_NUM_IBREAK, \
 328     .ndbreak = XCHAL_NUM_DBREAK
 329
 330 #define CONFIG_SECTION \
 331     .configid = { \
 332         XCHAL_HW_CONFIGID0, \
 333         XCHAL_HW_CONFIGID1, \
 334     }
 335
 336 #define DEFAULT_SECTIONS \
 337     .options = XTENSA_OPTIONS, \
 338     .nareg = XCHAL_NUM_AREGS, \
 339     .ndepc = (XCHAL_XEA_VERSION >= 2), \
 340     EXCEPTIONS_SECTION, \
 341     INTERRUPTS_SECTION, \
 342     TLB_SECTION, \
 343     DEBUG_SECTION, \
 344     CONFIG_SECTION
 345
 346
 347 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
 348 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
 349 #endif
 350 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
 351 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
 352 #endif
 353 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
 354 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
 355 #endif
 356 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
 357 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
 358 #endif
 359 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
 360 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
 361 #endif
 362 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
 363 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
 364 #endif
 365
 366
 367 #if XCHAL_NUM_INTERRUPTS <= 0
 368 #define XCHAL_INT0_LEVEL 0
 369 #define XCHAL_INT0_TYPE 0
 370 #endif
 371 #if XCHAL_NUM_INTERRUPTS <= 1
 372 #define XCHAL_INT1_LEVEL 0
 373 #define XCHAL_INT1_TYPE 0
 374 #endif
 375 #if XCHAL_NUM_INTERRUPTS <= 2
 376 #define XCHAL_INT2_LEVEL 0
 377 #define XCHAL_INT2_TYPE 0
 378 #endif
 379 #if XCHAL_NUM_INTERRUPTS <= 3
 380 #define XCHAL_INT3_LEVEL 0
 381 #define XCHAL_INT3_TYPE 0
 382 #endif
 383 #if XCHAL_NUM_INTERRUPTS <= 4
 384 #define XCHAL_INT4_LEVEL 0
 385 #define XCHAL_INT4_TYPE 0
 386 #endif
 387 #if XCHAL_NUM_INTERRUPTS <= 5
 388 #define XCHAL_INT5_LEVEL 0
 389 #define XCHAL_INT5_TYPE 0
 390 #endif
 391 #if XCHAL_NUM_INTERRUPTS <= 6
 392 #define XCHAL_INT6_LEVEL 0
 393 #define XCHAL_INT6_TYPE 0
 394 #endif
 395 #if XCHAL_NUM_INTERRUPTS <= 7
 396 #define XCHAL_INT7_LEVEL 0
 397 #define XCHAL_INT7_TYPE 0
 398 #endif
 399 #if XCHAL_NUM_INTERRUPTS <= 8
 400 #define XCHAL_INT8_LEVEL 0
 401 #define XCHAL_INT8_TYPE 0
 402 #endif
 403 #if XCHAL_NUM_INTERRUPTS <= 9
 404 #define XCHAL_INT9_LEVEL 0
 405 #define XCHAL_INT9_TYPE 0
 406 #endif
 407 #if XCHAL_NUM_INTERRUPTS <= 10
 408 #define XCHAL_INT10_LEVEL 0
 409 #define XCHAL_INT10_TYPE 0
 410 #endif
 411 #if XCHAL_NUM_INTERRUPTS <= 11
 412 #define XCHAL_INT11_LEVEL 0
 413 #define XCHAL_INT11_TYPE 0
 414 #endif
 415 #if XCHAL_NUM_INTERRUPTS <= 12
 416 #define XCHAL_INT12_LEVEL 0
 417 #define XCHAL_INT12_TYPE 0
 418 #endif
 419 #if XCHAL_NUM_INTERRUPTS <= 13
 420 #define XCHAL_INT13_LEVEL 0
 421 #define XCHAL_INT13_TYPE 0
 422 #endif
 423 #if XCHAL_NUM_INTERRUPTS <= 14
 424 #define XCHAL_INT14_LEVEL 0
 425 #define XCHAL_INT14_TYPE 0
 426 #endif
 427 #if XCHAL_NUM_INTERRUPTS <= 15
 428 #define XCHAL_INT15_LEVEL 0
 429 #define XCHAL_INT15_TYPE 0
 430 #endif
 431 #if XCHAL_NUM_INTERRUPTS <= 16
 432 #define XCHAL_INT16_LEVEL 0
 433 #define XCHAL_INT16_TYPE 0
 434 #endif
 435 #if XCHAL_NUM_INTERRUPTS <= 17
 436 #define XCHAL_INT17_LEVEL 0
 437 #define XCHAL_INT17_TYPE 0
 438 #endif
 439 #if XCHAL_NUM_INTERRUPTS <= 18
 440 #define XCHAL_INT18_LEVEL 0
 441 #define XCHAL_INT18_TYPE 0
 442 #endif
 443 #if XCHAL_NUM_INTERRUPTS <= 19
 444 #define XCHAL_INT19_LEVEL 0
 445 #define XCHAL_INT19_TYPE 0
 446 #endif
 447 #if XCHAL_NUM_INTERRUPTS <= 20
 448 #define XCHAL_INT20_LEVEL 0
 449 #define XCHAL_INT20_TYPE 0
 450 #endif
 451 #if XCHAL_NUM_INTERRUPTS <= 21
 452 #define XCHAL_INT21_LEVEL 0
 453 #define XCHAL_INT21_TYPE 0
 454 #endif
 455 #if XCHAL_NUM_INTERRUPTS <= 22
 456 #define XCHAL_INT22_LEVEL 0
 457 #define XCHAL_INT22_TYPE 0
 458 #endif
 459 #if XCHAL_NUM_INTERRUPTS <= 23
 460 #define XCHAL_INT23_LEVEL 0
 461 #define XCHAL_INT23_TYPE 0
 462 #endif
 463 #if XCHAL_NUM_INTERRUPTS <= 24
 464 #define XCHAL_INT24_LEVEL 0
 465 #define XCHAL_INT24_TYPE 0
 466 #endif
 467 #if XCHAL_NUM_INTERRUPTS <= 25
 468 #define XCHAL_INT25_LEVEL 0
 469 #define XCHAL_INT25_TYPE 0
 470 #endif
 471 #if XCHAL_NUM_INTERRUPTS <= 26
 472 #define XCHAL_INT26_LEVEL 0
 473 #define XCHAL_INT26_TYPE 0
 474 #endif
 475 #if XCHAL_NUM_INTERRUPTS <= 27
 476 #define XCHAL_INT27_LEVEL 0
 477 #define XCHAL_INT27_TYPE 0
 478 #endif
 479 #if XCHAL_NUM_INTERRUPTS <= 28
 480 #define XCHAL_INT28_LEVEL 0
 481 #define XCHAL_INT28_TYPE 0
 482 #endif
 483 #if XCHAL_NUM_INTERRUPTS <= 29
 484 #define XCHAL_INT29_LEVEL 0
 485 #define XCHAL_INT29_TYPE 0
 486 #endif
 487 #if XCHAL_NUM_INTERRUPTS <= 30
 488 #define XCHAL_INT30_LEVEL 0
 489 #define XCHAL_INT30_TYPE 0
 490 #endif
 491 #if XCHAL_NUM_INTERRUPTS <= 31
 492 #define XCHAL_INT31_LEVEL 0
 493 #define XCHAL_INT31_TYPE 0
 494 #endif
 495
 496
 497 #if XCHAL_NUM_EXTINTERRUPTS <= 0
 498 #define XCHAL_EXTINT0_NUM 0
 499 #endif
 500 #if XCHAL_NUM_EXTINTERRUPTS <= 1
 501 #define XCHAL_EXTINT1_NUM 0
 502 #endif
 503 #if XCHAL_NUM_EXTINTERRUPTS <= 2
 504 #define XCHAL_EXTINT2_NUM 0
 505 #endif
 506 #if XCHAL_NUM_EXTINTERRUPTS <= 3
 507 #define XCHAL_EXTINT3_NUM 0
 508 #endif
 509 #if XCHAL_NUM_EXTINTERRUPTS <= 4
 510 #define XCHAL_EXTINT4_NUM 0
 511 #endif
 512 #if XCHAL_NUM_EXTINTERRUPTS <= 5
 513 #define XCHAL_EXTINT5_NUM 0
 514 #endif
 515 #if XCHAL_NUM_EXTINTERRUPTS <= 6
 516 #define XCHAL_EXTINT6_NUM 0
 517 #endif
 518 #if XCHAL_NUM_EXTINTERRUPTS <= 7
 519 #define XCHAL_EXTINT7_NUM 0
 520 #endif
 521 #if XCHAL_NUM_EXTINTERRUPTS <= 8
 522 #define XCHAL_EXTINT8_NUM 0
 523 #endif
 524 #if XCHAL_NUM_EXTINTERRUPTS <= 9
 525 #define XCHAL_EXTINT9_NUM 0
 526 #endif
 527 #if XCHAL_NUM_EXTINTERRUPTS <= 10
 528 #define XCHAL_EXTINT10_NUM 0
 529 #endif
 530 #if XCHAL_NUM_EXTINTERRUPTS <= 11
 531 #define XCHAL_EXTINT11_NUM 0
 532 #endif
 533 #if XCHAL_NUM_EXTINTERRUPTS <= 12
 534 #define XCHAL_EXTINT12_NUM 0
 535 #endif
 536 #if XCHAL_NUM_EXTINTERRUPTS <= 13
 537 #define XCHAL_EXTINT13_NUM 0
 538 #endif
 539 #if XCHAL_NUM_EXTINTERRUPTS <= 14
 540 #define XCHAL_EXTINT14_NUM 0
 541 #endif
 542 #if XCHAL_NUM_EXTINTERRUPTS <= 15
 543 #define XCHAL_EXTINT15_NUM 0
 544 #endif
 545 #if XCHAL_NUM_EXTINTERRUPTS <= 16
 546 #define XCHAL_EXTINT16_NUM 0
 547 #endif
 548 #if XCHAL_NUM_EXTINTERRUPTS <= 17
 549 #define XCHAL_EXTINT17_NUM 0
 550 #endif
 551 #if XCHAL_NUM_EXTINTERRUPTS <= 18
 552 #define XCHAL_EXTINT18_NUM 0
 553 #endif
 554 #if XCHAL_NUM_EXTINTERRUPTS <= 19
 555 #define XCHAL_EXTINT19_NUM 0
 556 #endif
 557 #if XCHAL_NUM_EXTINTERRUPTS <= 20
 558 #define XCHAL_EXTINT20_NUM 0
 559 #endif
 560 #if XCHAL_NUM_EXTINTERRUPTS <= 21
 561 #define XCHAL_EXTINT21_NUM 0
 562 #endif
 563 #if XCHAL_NUM_EXTINTERRUPTS <= 22
 564 #define XCHAL_EXTINT22_NUM 0
 565 #endif
 566 #if XCHAL_NUM_EXTINTERRUPTS <= 23
 567 #define XCHAL_EXTINT23_NUM 0
 568 #endif
 569 #if XCHAL_NUM_EXTINTERRUPTS <= 24
 570 #define XCHAL_EXTINT24_NUM 0
 571 #endif
 572 #if XCHAL_NUM_EXTINTERRUPTS <= 25
 573 #define XCHAL_EXTINT25_NUM 0
 574 #endif
 575 #if XCHAL_NUM_EXTINTERRUPTS <= 26
 576 #define XCHAL_EXTINT26_NUM 0
 577 #endif
 578 #if XCHAL_NUM_EXTINTERRUPTS <= 27
 579 #define XCHAL_EXTINT27_NUM 0
 580 #endif
 581 #if XCHAL_NUM_EXTINTERRUPTS <= 28
 582 #define XCHAL_EXTINT28_NUM 0
 583 #endif
 584 #if XCHAL_NUM_EXTINTERRUPTS <= 29
 585 #define XCHAL_EXTINT29_NUM 0
 586 #endif
 587 #if XCHAL_NUM_EXTINTERRUPTS <= 30
 588 #define XCHAL_EXTINT30_NUM 0
 589 #endif
 590 #if XCHAL_NUM_EXTINTERRUPTS <= 31
 591 #define XCHAL_EXTINT31_NUM 0
 592 #endif
 593
 594
 595 #define XTHAL_TIMER_UNCONFIGURED 0