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seccomp: libseccomp version varying according to arch
[qemu/qmp-unstable.git] / target-cris / translate_v10.c
blobb742c4cd01ab5015a4e77df70db34f820d9e2236
1 /*
2 * CRISv10 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2010 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "crisv10-decode.h"
22
23 static const char *regnames_v10[] =
24 {
25 "$r0", "$r1", "$r2", "$r3",
26 "$r4", "$r5", "$r6", "$r7",
27 "$r8", "$r9", "$r10", "$r11",
28 "$r12", "$r13", "$sp", "$pc",
29 };
30
31 static const char *pregnames_v10[] =
32 {
33 "$bz", "$vr", "$p2", "$p3",
34 "$wz", "$ccr", "$p6-prefix", "$mof",
35 "$dz", "$ibr", "$irp", "$srp",
36 "$bar", "$dccr", "$brp", "$usp",
37 };
38
39 /* We need this table to handle preg-moves with implicit width. */
40 static int preg_sizes_v10[] = {
41 1, /* bz. */
42 1, /* vr. */
43 1, /* pid. */
44 1, /* srs. */
45 2, /* wz. */
46 2, 2, 4,
47 4, 4, 4, 4,
48 4, 4, 4, 4,
49 };
50
51 static inline int dec10_size(unsigned int size)
52 {
53 size++;
54 if (size == 3)
55 size++;
56 return size;
57 }
58
59 static inline void cris_illegal_insn(DisasContext *dc)
60 {
61 qemu_log("illegal insn at pc=%x\n", dc->pc);
62 t_gen_raise_exception(EXCP_BREAK);
63 }
64
65 static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
66 unsigned int size, int mem_index)
67 {
68 TCGLabel *l1 = gen_new_label();
69 TCGv taddr = tcg_temp_local_new();
70 TCGv tval = tcg_temp_local_new();
71 TCGv t1 = tcg_temp_local_new();
72 dc->postinc = 0;
73 cris_evaluate_flags(dc);
74
75 tcg_gen_mov_tl(taddr, addr);
76 tcg_gen_mov_tl(tval, val);
77
78 /* Store only if F flag isn't set */
79 tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
80 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
81 if (size == 1) {
82 tcg_gen_qemu_st8(tval, taddr, mem_index);
83 } else if (size == 2) {
84 tcg_gen_qemu_st16(tval, taddr, mem_index);
85 } else {
86 tcg_gen_qemu_st32(tval, taddr, mem_index);
87 }
88 gen_set_label(l1);
89 tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
90 tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
91 tcg_temp_free(t1);
92 tcg_temp_free(tval);
93 tcg_temp_free(taddr);
94 }
95
96 static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
97 unsigned int size)
98 {
99 int mem_index = cpu_mmu_index(&dc->cpu->env);
100
101 /* If we get a fault on a delayslot we must keep the jmp state in
102 the cpu-state to be able to re-execute the jmp. */
103 if (dc->delayed_branch == 1) {
104 cris_store_direct_jmp(dc);
105 }
106
107 /* Conditional writes. We only support the kind were X is known
108 at translation time. */
109 if (dc->flagx_known && dc->flags_x) {
110 gen_store_v10_conditional(dc, addr, val, size, mem_index);
111 return;
112 }
113
114 if (size == 1) {
115 tcg_gen_qemu_st8(val, addr, mem_index);
116 } else if (size == 2) {
117 tcg_gen_qemu_st16(val, addr, mem_index);
118 } else {
119 tcg_gen_qemu_st32(val, addr, mem_index);
120 }
121 }
122
123
124 /* Prefix flag and register are used to handle the more complex
125 addressing modes. */
126 static void cris_set_prefix(DisasContext *dc)
127 {
128 dc->clear_prefix = 0;
129 dc->tb_flags |= PFIX_FLAG;
130 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG);
131
132 /* prefix insns dont clear the x flag. */
133 dc->clear_x = 0;
134 cris_lock_irq(dc);
135 }
136
137 static void crisv10_prepare_memaddr(DisasContext *dc,
138 TCGv addr, unsigned int size)
139 {
140 if (dc->tb_flags & PFIX_FLAG) {
141 tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]);
142 } else {
143 tcg_gen_mov_tl(addr, cpu_R[dc->src]);
144 }
145 }
146
147 static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
148 {
149 unsigned int insn_len = 0;
150
151 if (dc->tb_flags & PFIX_FLAG) {
152 if (dc->mode == CRISV10_MODE_AUTOINC) {
153 tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]);
154 }
155 } else {
156 if (dc->mode == CRISV10_MODE_AUTOINC) {
157 if (dc->src == 15) {
158 insn_len += size & ~1;
159 } else {
160 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size);
161 }
162 }
163 }
164 return insn_len;
165 }
166
167 static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
168 int s_ext, int memsize, TCGv dst)
169 {
170 unsigned int rs;
171 uint32_t imm;
172 int is_imm;
173 int insn_len = 0;
174
175 rs = dc->src;
176 is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
177 LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
178 rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG);
179
180 /* Load [$rs] onto T1. */
181 if (is_imm) {
182 if (memsize != 4) {
183 if (s_ext) {
184 if (memsize == 1)
185 imm = cpu_ldsb_code(env, dc->pc + 2);
186 else
187 imm = cpu_ldsw_code(env, dc->pc + 2);
188 } else {
189 if (memsize == 1)
190 imm = cpu_ldub_code(env, dc->pc + 2);
191 else
192 imm = cpu_lduw_code(env, dc->pc + 2);
193 }
194 } else
195 imm = cpu_ldl_code(env, dc->pc + 2);
196
197 tcg_gen_movi_tl(dst, imm);
198
199 if (dc->mode == CRISV10_MODE_AUTOINC) {
200 insn_len += memsize;
201 if (memsize == 1)
202 insn_len++;
203 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len);
204 }
205 } else {
206 TCGv addr;
207
208 addr = tcg_temp_new();
209 cris_flush_cc_state(dc);
210 crisv10_prepare_memaddr(dc, addr, memsize);
211 gen_load(dc, dst, addr, memsize, 0);
212 if (s_ext)
213 t_gen_sext(dst, dst, memsize);
214 else
215 t_gen_zext(dst, dst, memsize);
216 insn_len += crisv10_post_memaddr(dc, memsize);
217 tcg_temp_free(addr);
218 }
219
220 if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
221 dc->dst = dc->src;
222 }
223 return insn_len;
224 }
225
226 static unsigned int dec10_quick_imm(DisasContext *dc)
227 {
228 int32_t imm, simm;
229 int op;
230
231 /* sign extend. */
232 imm = dc->ir & ((1 << 6) - 1);
233 simm = (int8_t) (imm << 2);
234 simm >>= 2;
235 switch (dc->opcode) {
236 case CRISV10_QIMM_BDAP_R0:
237 case CRISV10_QIMM_BDAP_R1:
238 case CRISV10_QIMM_BDAP_R2:
239 case CRISV10_QIMM_BDAP_R3:
240 simm = (int8_t)dc->ir;
241 LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
242 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
243 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
244 cris_set_prefix(dc);
245 if (dc->dst == 15) {
246 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
247 } else {
248 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
249 }
250 break;
251
252 case CRISV10_QIMM_MOVEQ:
253 LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
254
255 cris_cc_mask(dc, CC_MASK_NZVC);
256 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
257 cpu_R[dc->dst], tcg_const_tl(simm), 4);
258 break;
259 case CRISV10_QIMM_CMPQ:
260 LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
261
262 cris_cc_mask(dc, CC_MASK_NZVC);
263 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
264 cpu_R[dc->dst], tcg_const_tl(simm), 4);
265 break;
266 case CRISV10_QIMM_ADDQ:
267 LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
268
269 cris_cc_mask(dc, CC_MASK_NZVC);
270 cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
271 cpu_R[dc->dst], tcg_const_tl(imm), 4);
272 break;
273 case CRISV10_QIMM_ANDQ:
274 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
275
276 cris_cc_mask(dc, CC_MASK_NZVC);
277 cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
278 cpu_R[dc->dst], tcg_const_tl(simm), 4);
279 break;
280 case CRISV10_QIMM_ASHQ:
281 LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
282
283 cris_cc_mask(dc, CC_MASK_NZVC);
284 op = imm & (1 << 5);
285 imm &= 0x1f;
286 if (op) {
287 cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
288 cpu_R[dc->dst], tcg_const_tl(imm), 4);
289 } else {
290 /* BTST */
291 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
292 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
293 tcg_const_tl(imm), cpu_PR[PR_CCS]);
294 }
295 break;
296 case CRISV10_QIMM_LSHQ:
297 LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
298
299 op = CC_OP_LSL;
300 if (imm & (1 << 5)) {
301 op = CC_OP_LSR;
302 }
303 imm &= 0x1f;
304 cris_cc_mask(dc, CC_MASK_NZVC);
305 cris_alu(dc, op, cpu_R[dc->dst],
306 cpu_R[dc->dst], tcg_const_tl(imm), 4);
307 break;
308 case CRISV10_QIMM_SUBQ:
309 LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
310
311 cris_cc_mask(dc, CC_MASK_NZVC);
312 cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
313 cpu_R[dc->dst], tcg_const_tl(imm), 4);
314 break;
315 case CRISV10_QIMM_ORQ:
316 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
317
318 cris_cc_mask(dc, CC_MASK_NZVC);
319 cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
320 cpu_R[dc->dst], tcg_const_tl(simm), 4);
321 break;
322
323 case CRISV10_QIMM_BCC_R0:
324 case CRISV10_QIMM_BCC_R1:
325 case CRISV10_QIMM_BCC_R2:
326 case CRISV10_QIMM_BCC_R3:
327 imm = dc->ir & 0xff;
328 /* bit 0 is a sign bit. */
329 if (imm & 1) {
330 imm |= 0xffffff00; /* sign extend. */
331 imm &= ~1; /* get rid of the sign bit. */
332 }
333 imm += 2;
334 LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
335
336 cris_cc_mask(dc, 0);
337 cris_prepare_cc_branch(dc, imm, dc->cond);
338 break;
339
340 default:
341 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
342 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
343 cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n");
344 break;
345 }
346 return 2;
347 }
348
349 static unsigned int dec10_setclrf(DisasContext *dc)
350 {
351 uint32_t flags;
352 unsigned int set = ~dc->opcode & 1;
353
354 flags = EXTRACT_FIELD(dc->ir, 0, 3)
355 | (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
356 LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
357
358
359 if (flags & X_FLAG) {
360 dc->flagx_known = 1;
361 if (set)
362 dc->flags_x = X_FLAG;
363 else
364 dc->flags_x = 0;
365 }
366
367 cris_evaluate_flags (dc);
368 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
369 cris_update_cc_x(dc);
370 tcg_gen_movi_tl(cc_op, dc->cc_op);
371
372 if (set) {
373 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
374 } else {
375 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS],
376 ~(flags|F_FLAG_V10|P_FLAG_V10));
377 }
378
379 dc->flags_uptodate = 1;
380 dc->clear_x = 0;
381 cris_lock_irq(dc);
382 return 2;
383 }
384
385 static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
386 TCGv dd, TCGv ds, TCGv sd, TCGv ss)
387 {
388 if (sext) {
389 t_gen_sext(dd, sd, size);
390 t_gen_sext(ds, ss, size);
391 } else {
392 t_gen_zext(dd, sd, size);
393 t_gen_zext(ds, ss, size);
394 }
395 }
396
397 static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)
398 {
399 TCGv t[2];
400
401 t[0] = tcg_temp_new();
402 t[1] = tcg_temp_new();
403 dec10_reg_prep_sext(dc, size, sext,
404 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
405
406 if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) {
407 tcg_gen_andi_tl(t[1], t[1], 63);
408 }
409
410 assert(dc->dst != 15);
411 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
412 tcg_temp_free(t[0]);
413 tcg_temp_free(t[1]);
414 }
415
416 static void dec10_reg_bound(DisasContext *dc, int size)
417 {
418 TCGv t;
419
420 t = tcg_temp_local_new();
421 t_gen_zext(t, cpu_R[dc->src], size);
422 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
423 tcg_temp_free(t);
424 }
425
426 static void dec10_reg_mul(DisasContext *dc, int size, int sext)
427 {
428 int op = sext ? CC_OP_MULS : CC_OP_MULU;
429 TCGv t[2];
430
431 t[0] = tcg_temp_new();
432 t[1] = tcg_temp_new();
433 dec10_reg_prep_sext(dc, size, sext,
434 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
435
436 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);
437
438 tcg_temp_free(t[0]);
439 tcg_temp_free(t[1]);
440 }
441
442
443 static void dec10_reg_movs(DisasContext *dc)
444 {
445 int size = (dc->size & 1) + 1;
446 TCGv t;
447
448 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
449 cris_cc_mask(dc, CC_MASK_NZVC);
450
451 t = tcg_temp_new();
452 if (dc->ir & 32)
453 t_gen_sext(t, cpu_R[dc->src], size);
454 else
455 t_gen_zext(t, cpu_R[dc->src], size);
456
457 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
458 tcg_temp_free(t);
459 }
460
461 static void dec10_reg_alux(DisasContext *dc, int op)
462 {
463 int size = (dc->size & 1) + 1;
464 TCGv t;
465
466 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
467 cris_cc_mask(dc, CC_MASK_NZVC);
468
469 t = tcg_temp_new();
470 if (dc->ir & 32)
471 t_gen_sext(t, cpu_R[dc->src], size);
472 else
473 t_gen_zext(t, cpu_R[dc->src], size);
474
475 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
476 tcg_temp_free(t);
477 }
478
479 static void dec10_reg_mov_pr(DisasContext *dc)
480 {
481 LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
482 cris_lock_irq(dc);
483 if (dc->src == 15) {
484 tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]);
485 cris_prepare_jmp(dc, JMP_INDIRECT);
486 return;
487 }
488 if (dc->dst == PR_CCS) {
489 cris_evaluate_flags(dc);
490 }
491 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src],
492 cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]);
493 }
494
495 static void dec10_reg_abs(DisasContext *dc)
496 {
497 TCGv t0;
498
499 LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
500
501 assert(dc->dst != 15);
502 t0 = tcg_temp_new();
503 tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
504 tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
505 tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
506
507 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
508 tcg_temp_free(t0);
509 }
510
511 static void dec10_reg_swap(DisasContext *dc)
512 {
513 TCGv t0;
514
515 LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
516
517 cris_cc_mask(dc, CC_MASK_NZVC);
518 t0 = tcg_temp_new();
519 tcg_gen_mov_tl(t0, cpu_R[dc->src]);
520 if (dc->dst & 8)
521 tcg_gen_not_tl(t0, t0);
522 if (dc->dst & 4)
523 t_gen_swapw(t0, t0);
524 if (dc->dst & 2)
525 t_gen_swapb(t0, t0);
526 if (dc->dst & 1)
527 t_gen_swapr(t0, t0);
528 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
529 tcg_temp_free(t0);
530 }
531
532 static void dec10_reg_scc(DisasContext *dc)
533 {
534 int cond = dc->dst;
535
536 LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
537
538 if (cond != CC_A)
539 {
540 TCGLabel *l1 = gen_new_label();
541 gen_tst_cc (dc, cpu_R[dc->src], cond);
542 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->src], 0, l1);
543 tcg_gen_movi_tl(cpu_R[dc->src], 1);
544 gen_set_label(l1);
545 } else {
546 tcg_gen_movi_tl(cpu_R[dc->src], 1);
547 }
548
549 cris_cc_mask(dc, 0);
550 }
551
552 static unsigned int dec10_reg(DisasContext *dc)
553 {
554 TCGv t;
555 unsigned int insn_len = 2;
556 unsigned int size = dec10_size(dc->size);
557 unsigned int tmp;
558
559 if (dc->size != 3) {
560 switch (dc->opcode) {
561 case CRISV10_REG_MOVE_R:
562 LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
563 cris_cc_mask(dc, CC_MASK_NZVC);
564 dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
565 if (dc->dst == 15) {
566 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
567 cris_prepare_jmp(dc, JMP_INDIRECT);
568 dc->delayed_branch = 1;
569 }
570 break;
571 case CRISV10_REG_MOVX:
572 cris_cc_mask(dc, CC_MASK_NZVC);
573 dec10_reg_movs(dc);
574 break;
575 case CRISV10_REG_ADDX:
576 cris_cc_mask(dc, CC_MASK_NZVC);
577 dec10_reg_alux(dc, CC_OP_ADD);
578 break;
579 case CRISV10_REG_SUBX:
580 cris_cc_mask(dc, CC_MASK_NZVC);
581 dec10_reg_alux(dc, CC_OP_SUB);
582 break;
583 case CRISV10_REG_ADD:
584 LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
585 cris_cc_mask(dc, CC_MASK_NZVC);
586 dec10_reg_alu(dc, CC_OP_ADD, size, 0);
587 break;
588 case CRISV10_REG_SUB:
589 LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
590 cris_cc_mask(dc, CC_MASK_NZVC);
591 dec10_reg_alu(dc, CC_OP_SUB, size, 0);
592 break;
593 case CRISV10_REG_CMP:
594 LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
595 cris_cc_mask(dc, CC_MASK_NZVC);
596 dec10_reg_alu(dc, CC_OP_CMP, size, 0);
597 break;
598 case CRISV10_REG_BOUND:
599 LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
600 cris_cc_mask(dc, CC_MASK_NZVC);
601 dec10_reg_bound(dc, size);
602 break;
603 case CRISV10_REG_AND:
604 LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
605 cris_cc_mask(dc, CC_MASK_NZVC);
606 dec10_reg_alu(dc, CC_OP_AND, size, 0);
607 break;
608 case CRISV10_REG_ADDI:
609 if (dc->src == 15) {
610 /* nop. */
611 return 2;
612 }
613 t = tcg_temp_new();
614 LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
615 tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
616 tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
617 tcg_temp_free(t);
618 break;
619 case CRISV10_REG_LSL:
620 LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
621 cris_cc_mask(dc, CC_MASK_NZVC);
622 dec10_reg_alu(dc, CC_OP_LSL, size, 0);
623 break;
624 case CRISV10_REG_LSR:
625 LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
626 cris_cc_mask(dc, CC_MASK_NZVC);
627 dec10_reg_alu(dc, CC_OP_LSR, size, 0);
628 break;
629 case CRISV10_REG_ASR:
630 LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
631 cris_cc_mask(dc, CC_MASK_NZVC);
632 dec10_reg_alu(dc, CC_OP_ASR, size, 1);
633 break;
634 case CRISV10_REG_OR:
635 LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
636 cris_cc_mask(dc, CC_MASK_NZVC);
637 dec10_reg_alu(dc, CC_OP_OR, size, 0);
638 break;
639 case CRISV10_REG_NEG:
640 LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
641 cris_cc_mask(dc, CC_MASK_NZVC);
642 dec10_reg_alu(dc, CC_OP_NEG, size, 0);
643 break;
644 case CRISV10_REG_BIAP:
645 LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
646 dc->opcode, dc->src, dc->dst, size);
647 switch (size) {
648 case 4: tmp = 2; break;
649 case 2: tmp = 1; break;
650 case 1: tmp = 0; break;
651 default:
652 cpu_abort(CPU(dc->cpu), "Unhandled BIAP");
653 break;
654 }
655
656 t = tcg_temp_new();
657 tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp);
658 if (dc->src == 15) {
659 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1);
660 } else {
661 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
662 }
663 tcg_temp_free(t);
664 cris_set_prefix(dc);
665 break;
666
667 default:
668 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
669 dc->opcode, dc->src, dc->dst);
670 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
671 break;
672 }
673 } else {
674 switch (dc->opcode) {
675 case CRISV10_REG_MOVX:
676 cris_cc_mask(dc, CC_MASK_NZVC);
677 dec10_reg_movs(dc);
678 break;
679 case CRISV10_REG_ADDX:
680 cris_cc_mask(dc, CC_MASK_NZVC);
681 dec10_reg_alux(dc, CC_OP_ADD);
682 break;
683 case CRISV10_REG_SUBX:
684 cris_cc_mask(dc, CC_MASK_NZVC);
685 dec10_reg_alux(dc, CC_OP_SUB);
686 break;
687 case CRISV10_REG_MOVE_SPR_R:
688 cris_evaluate_flags(dc);
689 cris_cc_mask(dc, 0);
690 dec10_reg_mov_pr(dc);
691 break;
692 case CRISV10_REG_MOVE_R_SPR:
693 LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
694 cris_evaluate_flags(dc);
695 if (dc->src != 11) /* fast for srp. */
696 dc->cpustate_changed = 1;
697 t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]);
698 break;
699 case CRISV10_REG_SETF:
700 case CRISV10_REG_CLEARF:
701 dec10_setclrf(dc);
702 break;
703 case CRISV10_REG_SWAP:
704 dec10_reg_swap(dc);
705 break;
706 case CRISV10_REG_ABS:
707 cris_cc_mask(dc, CC_MASK_NZVC);
708 dec10_reg_abs(dc);
709 break;
710 case CRISV10_REG_LZ:
711 LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
712 cris_cc_mask(dc, CC_MASK_NZVC);
713 dec10_reg_alu(dc, CC_OP_LZ, 4, 0);
714 break;
715 case CRISV10_REG_XOR:
716 LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
717 cris_cc_mask(dc, CC_MASK_NZVC);
718 dec10_reg_alu(dc, CC_OP_XOR, 4, 0);
719 break;
720 case CRISV10_REG_BTST:
721 LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
722 cris_cc_mask(dc, CC_MASK_NZVC);
723 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
724 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
725 cpu_R[dc->src], cpu_PR[PR_CCS]);
726 break;
727 case CRISV10_REG_DSTEP:
728 LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
729 cris_cc_mask(dc, CC_MASK_NZVC);
730 cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst],
731 cpu_R[dc->dst], cpu_R[dc->src], 4);
732 break;
733 case CRISV10_REG_MSTEP:
734 LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
735 cris_evaluate_flags(dc);
736 cris_cc_mask(dc, CC_MASK_NZVC);
737 cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst],
738 cpu_R[dc->dst], cpu_R[dc->src], 4);
739 break;
740 case CRISV10_REG_SCC:
741 dec10_reg_scc(dc);
742 break;
743 default:
744 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
745 dc->opcode, dc->src, dc->dst);
746 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
747 break;
748 }
749 }
750 return insn_len;
751 }
752
753 static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
754 unsigned int size)
755 {
756 unsigned int insn_len = 2;
757 TCGv t;
758
759 LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__,
760 size, dc->src, dc->dst);
761
762 cris_cc_mask(dc, CC_MASK_NZVC);
763 t = tcg_temp_new();
764 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
765 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
766 if (dc->dst == 15) {
767 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
768 cris_prepare_jmp(dc, JMP_INDIRECT);
769 dc->delayed_branch = 1;
770 return insn_len;
771 }
772
773 tcg_temp_free(t);
774 return insn_len;
775 }
776
777 static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
778 {
779 unsigned int insn_len = 2;
780 TCGv addr;
781
782 LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
783 addr = tcg_temp_new();
784 crisv10_prepare_memaddr(dc, addr, size);
785 gen_store_v10(dc, addr, cpu_R[dc->dst], size);
786 insn_len += crisv10_post_memaddr(dc, size);
787
788 return insn_len;
789 }
790
791 static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
792 {
793 unsigned int insn_len = 2, rd = dc->dst;
794 TCGv t, addr;
795
796 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
797 cris_lock_irq(dc);
798
799 addr = tcg_temp_new();
800 t = tcg_temp_new();
801 insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
802 if (rd == 15) {
803 tcg_gen_mov_tl(env_btarget, t);
804 cris_prepare_jmp(dc, JMP_INDIRECT);
805 dc->delayed_branch = 1;
806 return insn_len;
807 }
808
809 tcg_gen_mov_tl(cpu_PR[rd], t);
810 dc->cpustate_changed = 1;
811 tcg_temp_free(addr);
812 tcg_temp_free(t);
813 return insn_len;
814 }
815
816 static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
817 {
818 unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst];
819 TCGv addr, t0;
820
821 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
822
823 addr = tcg_temp_new();
824 crisv10_prepare_memaddr(dc, addr, size);
825 if (dc->dst == PR_CCS) {
826 t0 = tcg_temp_new();
827 cris_evaluate_flags(dc);
828 tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
829 gen_store_v10(dc, addr, t0, size);
830 tcg_temp_free(t0);
831 } else {
832 gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
833 }
834 t0 = tcg_temp_new();
835 insn_len += crisv10_post_memaddr(dc, size);
836 cris_lock_irq(dc);
837
838 return insn_len;
839 }
840
841 static void dec10_movem_r_m(DisasContext *dc)
842 {
843 int i, pfix = dc->tb_flags & PFIX_FLAG;
844 TCGv addr, t0;
845
846 LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__,
847 dc->dst, dc->src, dc->postinc, dc->ir);
848
849 addr = tcg_temp_new();
850 t0 = tcg_temp_new();
851 crisv10_prepare_memaddr(dc, addr, 4);
852 tcg_gen_mov_tl(t0, addr);
853 for (i = dc->dst; i >= 0; i--) {
854 if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
855 gen_store_v10(dc, addr, t0, 4);
856 } else {
857 gen_store_v10(dc, addr, cpu_R[i], 4);
858 }
859 tcg_gen_addi_tl(addr, addr, 4);
860 }
861
862 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
863 tcg_gen_mov_tl(cpu_R[dc->src], t0);
864 }
865
866 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
867 tcg_gen_mov_tl(cpu_R[dc->src], addr);
868 }
869 tcg_temp_free(addr);
870 tcg_temp_free(t0);
871 }
872
873 static void dec10_movem_m_r(DisasContext *dc)
874 {
875 int i, pfix = dc->tb_flags & PFIX_FLAG;
876 TCGv addr, t0;
877
878 LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__,
879 dc->src, dc->dst, dc->postinc, dc->ir);
880
881 addr = tcg_temp_new();
882 t0 = tcg_temp_new();
883 crisv10_prepare_memaddr(dc, addr, 4);
884 tcg_gen_mov_tl(t0, addr);
885 for (i = dc->dst; i >= 0; i--) {
886 gen_load(dc, cpu_R[i], addr, 4, 0);
887 tcg_gen_addi_tl(addr, addr, 4);
888 }
889
890 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
891 tcg_gen_mov_tl(cpu_R[dc->src], t0);
892 }
893
894 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
895 tcg_gen_mov_tl(cpu_R[dc->src], addr);
896 }
897 tcg_temp_free(addr);
898 tcg_temp_free(t0);
899 }
900
901 static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
902 int op, unsigned int size)
903 {
904 int insn_len = 0;
905 int rd = dc->dst;
906 TCGv t[2];
907
908 cris_alu_m_alloc_temps(t);
909 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
910 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
911 if (dc->dst == 15) {
912 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
913 cris_prepare_jmp(dc, JMP_INDIRECT);
914 dc->delayed_branch = 1;
915 return insn_len;
916 }
917
918 cris_alu_m_free_temps(t);
919
920 return insn_len;
921 }
922
923 static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
924 unsigned int size)
925 {
926 int insn_len = 0;
927 int rd = dc->dst;
928 TCGv t;
929
930 t = tcg_temp_local_new();
931 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
932 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
933 if (dc->dst == 15) {
934 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
935 cris_prepare_jmp(dc, JMP_INDIRECT);
936 dc->delayed_branch = 1;
937 return insn_len;
938 }
939
940 tcg_temp_free(t);
941 return insn_len;
942 }
943
944 static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
945 {
946 unsigned int size = (dc->size & 1) ? 2 : 1;
947 unsigned int sx = !!(dc->size & 2);
948 int insn_len = 2;
949 int rd = dc->dst;
950 TCGv t;
951
952 LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
953
954 t = tcg_temp_new();
955
956 cris_cc_mask(dc, CC_MASK_NZVC);
957 insn_len += dec10_prep_move_m(env, dc, sx, size, t);
958 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
959 if (dc->dst == 15) {
960 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
961 cris_prepare_jmp(dc, JMP_INDIRECT);
962 dc->delayed_branch = 1;
963 return insn_len;
964 }
965
966 tcg_temp_free(t);
967 return insn_len;
968 }
969
970 static int dec10_dip(CPUCRISState *env, DisasContext *dc)
971 {
972 int insn_len = 2;
973 uint32_t imm;
974
975 LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
976 dc->pc, dc->opcode, dc->src, dc->dst);
977 if (dc->src == 15) {
978 imm = cpu_ldl_code(env, dc->pc + 2);
979 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
980 if (dc->postinc)
981 insn_len += 4;
982 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2);
983 } else {
984 gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0);
985 if (dc->postinc)
986 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
987 }
988
989 cris_set_prefix(dc);
990 return insn_len;
991 }
992
993 static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
994 {
995 int insn_len = 2;
996 int rd = dc->dst;
997
998 LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
999 dc->pc, dc->opcode, dc->src, dc->dst, size);
1000
1001 assert(dc->dst != 15);
1002 #if 0
1003 /* 8bit embedded offset? */
1004 if (!dc->postinc && (dc->ir & (1 << 11))) {
1005 int simm = dc->ir & 0xff;
1006
1007 /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
1008 /* sign extended. */
1009 simm = (int8_t)simm;
1010
1011 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
1012
1013 cris_set_prefix(dc);
1014 return insn_len;
1015 }
1016 #endif
1017 /* Now the rest of the modes are truly indirect. */
1018 insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
1019 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
1020 cris_set_prefix(dc);
1021 return insn_len;
1022 }
1023
1024 static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
1025 {
1026 unsigned int insn_len = 2;
1027 unsigned int size = dec10_size(dc->size);
1028 uint32_t imm;
1029 int32_t simm;
1030 TCGv t[2];
1031
1032 if (dc->size != 3) {
1033 switch (dc->opcode) {
1034 case CRISV10_IND_MOVE_M_R:
1035 return dec10_ind_move_m_r(env, dc, size);
1036 break;
1037 case CRISV10_IND_MOVE_R_M:
1038 return dec10_ind_move_r_m(dc, size);
1039 break;
1040 case CRISV10_IND_CMP:
1041 LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
1042 cris_cc_mask(dc, CC_MASK_NZVC);
1043 insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
1044 break;
1045 case CRISV10_IND_TEST:
1046 LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
1047
1048 cris_evaluate_flags(dc);
1049 cris_cc_mask(dc, CC_MASK_NZVC);
1050 cris_alu_m_alloc_temps(t);
1051 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
1052 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
1053 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
1054 t[0], tcg_const_tl(0), size);
1055 cris_alu_m_free_temps(t);
1056 break;
1057 case CRISV10_IND_ADD:
1058 LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
1059 cris_cc_mask(dc, CC_MASK_NZVC);
1060 insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
1061 break;
1062 case CRISV10_IND_SUB:
1063 LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
1064 cris_cc_mask(dc, CC_MASK_NZVC);
1065 insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
1066 break;
1067 case CRISV10_IND_BOUND:
1068 LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
1069 cris_cc_mask(dc, CC_MASK_NZVC);
1070 insn_len += dec10_ind_bound(env, dc, size);
1071 break;
1072 case CRISV10_IND_AND:
1073 LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
1074 cris_cc_mask(dc, CC_MASK_NZVC);
1075 insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
1076 break;
1077 case CRISV10_IND_OR:
1078 LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
1079 cris_cc_mask(dc, CC_MASK_NZVC);
1080 insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
1081 break;
1082 case CRISV10_IND_MOVX:
1083 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
1084 break;
1085 case CRISV10_IND_ADDX:
1086 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
1087 break;
1088 case CRISV10_IND_SUBX:
1089 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
1090 break;
1091 case CRISV10_IND_CMPX:
1092 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
1093 break;
1094 case CRISV10_IND_MUL:
1095 /* This is a reg insn coded in the mem indir space. */
1096 LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
1097 cris_cc_mask(dc, CC_MASK_NZVC);
1098 dec10_reg_mul(dc, size, dc->ir & (1 << 10));
1099 break;
1100 case CRISV10_IND_BDAP_M:
1101 insn_len = dec10_bdap_m(env, dc, size);
1102 break;
1103 default:
1104 LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
1105 dc->pc, size, dc->opcode, dc->src, dc->dst);
1106 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
1107 break;
1108 }
1109 return insn_len;
1110 }
1111
1112 switch (dc->opcode) {
1113 case CRISV10_IND_MOVE_M_SPR:
1114 insn_len = dec10_ind_move_m_pr(env, dc);
1115 break;
1116 case CRISV10_IND_MOVE_SPR_M:
1117 insn_len = dec10_ind_move_pr_m(dc);
1118 break;
1119 case CRISV10_IND_JUMP_M:
1120 if (dc->src == 15) {
1121 LOG_DIS("jump.%d %d r%d r%d direct\n", size,
1122 dc->opcode, dc->src, dc->dst);
1123 imm = cpu_ldl_code(env, dc->pc + 2);
1124 if (dc->mode == CRISV10_MODE_AUTOINC)
1125 insn_len += size;
1126
1127 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1128 dc->jmp_pc = imm;
1129 cris_prepare_jmp(dc, JMP_DIRECT);
1130 dc->delayed_branch--; /* v10 has no dslot here. */
1131 } else {
1132 if (dc->dst == 14) {
1133 LOG_DIS("break %d\n", dc->src);
1134 cris_evaluate_flags(dc);
1135 tcg_gen_movi_tl(env_pc, dc->pc + 2);
1136 t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2));
1137 t_gen_raise_exception(EXCP_BREAK);
1138 dc->is_jmp = DISAS_UPDATE;
1139 return insn_len;
1140 }
1141 LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
1142 dc->opcode, dc->src, dc->dst);
1143 t[0] = tcg_temp_new();
1144 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1145 crisv10_prepare_memaddr(dc, t[0], size);
1146 gen_load(dc, env_btarget, t[0], 4, 0);
1147 insn_len += crisv10_post_memaddr(dc, size);
1148 cris_prepare_jmp(dc, JMP_INDIRECT);
1149 dc->delayed_branch--; /* v10 has no dslot here. */
1150 tcg_temp_free(t[0]);
1151 }
1152 break;
1153
1154 case CRISV10_IND_MOVEM_R_M:
1155 LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
1156 dc->pc, dc->opcode, dc->dst, dc->src);
1157 dec10_movem_r_m(dc);
1158 break;
1159 case CRISV10_IND_MOVEM_M_R:
1160 LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
1161 dec10_movem_m_r(dc);
1162 break;
1163 case CRISV10_IND_JUMP_R:
1164 LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
1165 dc->pc, dc->opcode, dc->dst, dc->src);
1166 tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
1167 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1168 cris_prepare_jmp(dc, JMP_INDIRECT);
1169 dc->delayed_branch--; /* v10 has no dslot here. */
1170 break;
1171 case CRISV10_IND_MOVX:
1172 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
1173 break;
1174 case CRISV10_IND_ADDX:
1175 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
1176 break;
1177 case CRISV10_IND_SUBX:
1178 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
1179 break;
1180 case CRISV10_IND_CMPX:
1181 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
1182 break;
1183 case CRISV10_IND_DIP:
1184 insn_len = dec10_dip(env, dc);
1185 break;
1186 case CRISV10_IND_BCC_M:
1187
1188 cris_cc_mask(dc, 0);
1189 imm = cpu_ldsw_code(env, dc->pc + 2);
1190 simm = (int16_t)imm;
1191 simm += 4;
1192
1193 LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
1194 cris_prepare_cc_branch(dc, simm, dc->cond);
1195 insn_len = 4;
1196 break;
1197 default:
1198 LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
1199 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
1200 break;
1201 }
1202
1203 return insn_len;
1204 }
1205
1206 static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
1207 {
1208 unsigned int insn_len = 2;
1209
1210 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1211 tcg_gen_debug_insn_start(dc->pc);
1212
1213 /* Load a halfword onto the instruction register. */
1214 dc->ir = cpu_lduw_code(env, dc->pc);
1215
1216 /* Now decode it. */
1217 dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
1218 dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
1219 dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
1220 dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
1221 dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
1222 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
1223
1224 dc->clear_prefix = 1;
1225
1226 /* FIXME: What if this insn insn't 2 in length?? */
1227 if (dc->src == 15 || dc->dst == 15)
1228 tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
1229
1230 switch (dc->mode) {
1231 case CRISV10_MODE_QIMMEDIATE:
1232 insn_len = dec10_quick_imm(dc);
1233 break;
1234 case CRISV10_MODE_REG:
1235 insn_len = dec10_reg(dc);
1236 break;
1237 case CRISV10_MODE_AUTOINC:
1238 case CRISV10_MODE_INDIRECT:
1239 insn_len = dec10_ind(env, dc);
1240 break;
1241 }
1242
1243 if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
1244 dc->tb_flags &= ~PFIX_FLAG;
1245 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
1246 if (dc->tb_flags != dc->tb->flags) {
1247 dc->cpustate_changed = 1;
1248 }
1249 }
1250
1251 /* CRISv10 locks out interrupts on dslots. */
1252 if (dc->delayed_branch == 2) {
1253 cris_lock_irq(dc);
1254 }
1255 return insn_len;
1256 }
1257
1258 void cris_initialize_crisv10_tcg(void)
1259 {
1260 int i;
1261
1262 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1263 cc_x = tcg_global_mem_new(TCG_AREG0,
1264 offsetof(CPUCRISState, cc_x), "cc_x");
1265 cc_src = tcg_global_mem_new(TCG_AREG0,
1266 offsetof(CPUCRISState, cc_src), "cc_src");
1267 cc_dest = tcg_global_mem_new(TCG_AREG0,
1268 offsetof(CPUCRISState, cc_dest),
1269 "cc_dest");
1270 cc_result = tcg_global_mem_new(TCG_AREG0,
1271 offsetof(CPUCRISState, cc_result),
1272 "cc_result");
1273 cc_op = tcg_global_mem_new(TCG_AREG0,
1274 offsetof(CPUCRISState, cc_op), "cc_op");
1275 cc_size = tcg_global_mem_new(TCG_AREG0,
1276 offsetof(CPUCRISState, cc_size),
1277 "cc_size");
1278 cc_mask = tcg_global_mem_new(TCG_AREG0,
1279 offsetof(CPUCRISState, cc_mask),
1280 "cc_mask");
1281
1282 env_pc = tcg_global_mem_new(TCG_AREG0,
1283 offsetof(CPUCRISState, pc),
1284 "pc");
1285 env_btarget = tcg_global_mem_new(TCG_AREG0,
1286 offsetof(CPUCRISState, btarget),
1287 "btarget");
1288 env_btaken = tcg_global_mem_new(TCG_AREG0,
1289 offsetof(CPUCRISState, btaken),
1290 "btaken");
1291 for (i = 0; i < 16; i++) {
1292 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1293 offsetof(CPUCRISState, regs[i]),
1294 regnames_v10[i]);
1295 }
1296 for (i = 0; i < 16; i++) {
1297 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
1298 offsetof(CPUCRISState, pregs[i]),
1299 pregnames_v10[i]);
1300 }
1301 }
QEMU Monitor Protocol