disas/mips.c

   1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003
   4    Free Software Foundation, Inc.
   5    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "disas/bfd.h"
  23
  24 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
  25    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
  26    Free Software Foundation, Inc.
  27    Contributed by Ralph Campbell and OSF
  28    Commented and modified by Ian Lance Taylor, Cygnus Support
  29
  30 This file is part of GDB, GAS, and the GNU binutils.
  31
  32 GDB, GAS, and the GNU binutils are free software; you can redistribute
  33 them and/or modify them under the terms of the GNU General Public
  34 License as published by the Free Software Foundation; either version
  35 1, or (at your option) any later version.
  36
  37 GDB, GAS, and the GNU binutils are distributed in the hope that they
  38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  40 the GNU General Public License for more details.
  41
  42 You should have received a copy of the GNU General Public License
  43 along with this file; see the file COPYING.  If not,
  44 see <http://www.gnu.org/licenses/>.  */
  45
  46 /* These are bit masks and shift counts to use to access the various
  47    fields of an instruction.  To retrieve the X field of an
  48    instruction, use the expression
  49         (i >> OP_SH_X) & OP_MASK_X
  50    To set the same field (to j), use
  51         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  52
  53    Make sure you use fields that are appropriate for the instruction,
  54    of course.
  55
  56    The 'i' format uses OP, RS, RT and IMMEDIATE.
  57
  58    The 'j' format uses OP and TARGET.
  59
  60    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  61
  62    The 'b' format uses OP, RS, RT and DELTA.
  63
  64    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  65
  66    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  67
  68    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  69    breakpoint instruction are not defined; Kane says the breakpoint
  70    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  71    only use ten bits).  An optional two-operand form of break/sdbbp
  72    allows the lower ten bits to be set too, and MIPS32 and later
  73    architectures allow 20 bits to be set with a signal operand
  74    (using CODE20).
  75
  76    The syscall instruction uses CODE20.
  77
  78    The general coprocessor instructions use COPZ.  */
  79
  80 #define OP_MASK_OP              0x3f
  81 #define OP_SH_OP                26
  82 #define OP_MASK_RS              0x1f
  83 #define OP_SH_RS                21
  84 #define OP_MASK_FR              0x1f
  85 #define OP_SH_FR                21
  86 #define OP_MASK_FMT             0x1f
  87 #define OP_SH_FMT               21
  88 #define OP_MASK_BCC             0x7
  89 #define OP_SH_BCC               18
  90 #define OP_MASK_CODE            0x3ff
  91 #define OP_SH_CODE              16
  92 #define OP_MASK_CODE2           0x3ff
  93 #define OP_SH_CODE2             6
  94 #define OP_MASK_RT              0x1f
  95 #define OP_SH_RT                16
  96 #define OP_MASK_FT              0x1f
  97 #define OP_SH_FT                16
  98 #define OP_MASK_CACHE           0x1f
  99 #define OP_SH_CACHE             16
 100 #define OP_MASK_RD              0x1f
 101 #define OP_SH_RD                11
 102 #define OP_MASK_FS              0x1f
 103 #define OP_SH_FS                11
 104 #define OP_MASK_PREFX           0x1f
 105 #define OP_SH_PREFX             11
 106 #define OP_MASK_CCC             0x7
 107 #define OP_SH_CCC               8
 108 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
 109 #define OP_SH_CODE20            6
 110 #define OP_MASK_SHAMT           0x1f
 111 #define OP_SH_SHAMT             6
 112 #define OP_MASK_FD              0x1f
 113 #define OP_SH_FD                6
 114 #define OP_MASK_TARGET          0x3ffffff
 115 #define OP_SH_TARGET            0
 116 #define OP_MASK_COPZ            0x1ffffff
 117 #define OP_SH_COPZ              0
 118 #define OP_MASK_IMMEDIATE       0xffff
 119 #define OP_SH_IMMEDIATE         0
 120 #define OP_MASK_DELTA           0xffff
 121 #define OP_SH_DELTA             0
 122 #define OP_MASK_DELTA_R6        0x1ff
 123 #define OP_SH_DELTA_R6          7
 124 #define OP_MASK_FUNCT           0x3f
 125 #define OP_SH_FUNCT             0
 126 #define OP_MASK_SPEC            0x3f
 127 #define OP_SH_SPEC              0
 128 #define OP_SH_LOCC              8       /* FP condition code.  */
 129 #define OP_SH_HICC              18      /* FP condition code.  */
 130 #define OP_MASK_CC              0x7
 131 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 132 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 133 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 134 #define OP_MASK_COP1SPEC        0xf
 135 #define OP_MASK_COP1SCLR        0x4
 136 #define OP_MASK_COP1CMP         0x3
 137 #define OP_SH_COP1CMP           4
 138 #define OP_SH_FORMAT            21      /* FP short format field.  */
 139 #define OP_MASK_FORMAT          0x7
 140 #define OP_SH_TRUE              16
 141 #define OP_MASK_TRUE            0x1
 142 #define OP_SH_GE                17
 143 #define OP_MASK_GE              0x01
 144 #define OP_SH_UNSIGNED          16
 145 #define OP_MASK_UNSIGNED        0x1
 146 #define OP_SH_HINT              16
 147 #define OP_MASK_HINT            0x1f
 148 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 149 #define OP_MASK_MMI             0x3f
 150 #define OP_SH_MMISUB            6
 151 #define OP_MASK_MMISUB          0x1f
 152 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 153 #define OP_SH_PERFREG           1
 154 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 155 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 156 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 157 #define OP_MASK_CODE19          0x7ffff
 158 #define OP_SH_ALN               21
 159 #define OP_MASK_ALN             0x7
 160 #define OP_SH_VSEL              21
 161 #define OP_MASK_VSEL            0x1f
 162 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 163                                            but 0x8-0xf don't select bytes.  */
 164 #define OP_SH_VECBYTE           22
 165 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 166 #define OP_SH_VECALIGN          21
 167 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 168 #define OP_SH_INSMSB            11
 169 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 170 #define OP_SH_EXTMSBD           11
 171
 172 #define OP_OP_COP0              0x10
 173 #define OP_OP_COP1              0x11
 174 #define OP_OP_COP2              0x12
 175 #define OP_OP_COP3              0x13
 176 #define OP_OP_LWC1              0x31
 177 #define OP_OP_LWC2              0x32
 178 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 179 #define OP_OP_LDC1              0x35
 180 #define OP_OP_LDC2              0x36
 181 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 182 #define OP_OP_SWC1              0x39
 183 #define OP_OP_SWC2              0x3a
 184 #define OP_OP_SWC3              0x3b
 185 #define OP_OP_SDC1              0x3d
 186 #define OP_OP_SDC2              0x3e
 187 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 188
 189 /* MIPS DSP ASE */
 190 #define OP_SH_DSPACC            11
 191 #define OP_MASK_DSPACC          0x3
 192 #define OP_SH_DSPACC_S          21
 193 #define OP_MASK_DSPACC_S        0x3
 194 #define OP_SH_DSPSFT            20
 195 #define OP_MASK_DSPSFT          0x3f
 196 #define OP_SH_DSPSFT_7          19
 197 #define OP_MASK_DSPSFT_7        0x7f
 198 #define OP_SH_SA3               21
 199 #define OP_MASK_SA3             0x7
 200 #define OP_SH_SA4               21
 201 #define OP_MASK_SA4             0xf
 202 #define OP_SH_IMM8              16
 203 #define OP_MASK_IMM8            0xff
 204 #define OP_SH_IMM10             16
 205 #define OP_MASK_IMM10           0x3ff
 206 #define OP_SH_WRDSP             11
 207 #define OP_MASK_WRDSP           0x3f
 208 #define OP_SH_RDDSP             16
 209 #define OP_MASK_RDDSP           0x3f
 210 #define OP_SH_BP                11
 211 #define OP_MASK_BP              0x3
 212
 213 /* MIPS MT ASE */
 214 #define OP_SH_MT_U              5
 215 #define OP_MASK_MT_U            0x1
 216 #define OP_SH_MT_H              4
 217 #define OP_MASK_MT_H            0x1
 218 #define OP_SH_MTACC_T           18
 219 #define OP_MASK_MTACC_T         0x3
 220 #define OP_SH_MTACC_D           13
 221 #define OP_MASK_MTACC_D         0x3
 222
 223 /* MSA */
 224 #define OP_MASK_1BIT            0x1
 225 #define OP_SH_1BIT              16
 226 #define OP_MASK_2BIT            0x3
 227 #define OP_SH_2BIT              16
 228 #define OP_MASK_3BIT            0x7
 229 #define OP_SH_3BIT              16
 230 #define OP_MASK_4BIT            0xf
 231 #define OP_SH_4BIT              16
 232 #define OP_MASK_5BIT            0x1f
 233 #define OP_SH_5BIT              16
 234 #define OP_MASK_10BIT           0x3ff
 235 #define OP_SH_10BIT             11
 236 #define OP_MASK_MSACR11         0x1f
 237 #define OP_SH_MSACR11           11
 238 #define OP_MASK_MSACR6          0x1f
 239 #define OP_SH_MSACR6            6
 240 #define OP_MASK_GPR             0x1f
 241 #define OP_SH_GPR               6
 242 #define OP_MASK_1_TO_4          0x3
 243 #define OP_SH_1_TO_4            6
 244
 245 #define OP_OP_COP0              0x10
 246 #define OP_OP_COP1              0x11
 247 #define OP_OP_COP2              0x12
 248 #define OP_OP_COP3              0x13
 249 #define OP_OP_LWC1              0x31
 250 #define OP_OP_LWC2              0x32
 251 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 252 #define OP_OP_LDC1              0x35
 253 #define OP_OP_LDC2              0x36
 254 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 255 #define OP_OP_SWC1              0x39
 256 #define OP_OP_SWC2              0x3a
 257 #define OP_OP_SWC3              0x3b
 258 #define OP_OP_SDC1              0x3d
 259 #define OP_OP_SDC2              0x3e
 260 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 261
 262 /* Values in the 'VSEL' field.  */
 263 #define MDMX_FMTSEL_IMM_QH      0x1d
 264 #define MDMX_FMTSEL_IMM_OB      0x1e
 265 #define MDMX_FMTSEL_VEC_QH      0x15
 266 #define MDMX_FMTSEL_VEC_OB      0x16
 267
 268 /* UDI */
 269 #define OP_SH_UDI1              6
 270 #define OP_MASK_UDI1            0x1f
 271 #define OP_SH_UDI2              6
 272 #define OP_MASK_UDI2            0x3ff
 273 #define OP_SH_UDI3              6
 274 #define OP_MASK_UDI3            0x7fff
 275 #define OP_SH_UDI4              6
 276 #define OP_MASK_UDI4            0xfffff
 277 /* This structure holds information for a particular instruction.  */
 278
 279 struct mips_opcode
 280 {
 281   /* The name of the instruction.  */
 282   const char *name;
 283   /* A string describing the arguments for this instruction.  */
 284   const char *args;
 285   /* The basic opcode for the instruction.  When assembling, this
 286      opcode is modified by the arguments to produce the actual opcode
 287      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 288   unsigned long match;
 289   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 290      relevant portions of the opcode when disassembling.  If the
 291      actual opcode anded with the match field equals the opcode field,
 292      then we have found the correct instruction.  If pinfo is
 293      INSN_MACRO, then this field is the macro identifier.  */
 294   unsigned long mask;
 295   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 296      of bits describing the instruction, notably any relevant hazard
 297      information.  */
 298   unsigned long pinfo;
 299   /* A collection of additional bits describing the instruction. */
 300   unsigned long pinfo2;
 301   /* A collection of bits describing the instruction sets of which this
 302      instruction or macro is a member. */
 303   unsigned long membership;
 304 };
 305
 306 /* These are the characters which may appear in the args field of an
 307    instruction.  They appear in the order in which the fields appear
 308    when the instruction is used.  Commas and parentheses in the args
 309    string are ignored when assembling, and written into the output
 310    when disassembling.
 311
 312    Each of these characters corresponds to a mask field defined above.
 313
 314    "<" 5 bit shift amount (OP_*_SHAMT)
 315    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 316    "a" 26 bit target address (OP_*_TARGET)
 317    "b" 5 bit base register (OP_*_RS)
 318    "c" 10 bit breakpoint code (OP_*_CODE)
 319    "d" 5 bit destination register specifier (OP_*_RD)
 320    "h" 5 bit prefx hint (OP_*_PREFX)
 321    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 322    "j" 16 bit signed immediate (OP_*_DELTA)
 323    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 324        Also used for immediate operands in vr5400 vector insns.
 325    "o" 16 bit signed offset (OP_*_DELTA)
 326    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 327    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 328    "r" 5 bit same register used as both source and target (OP_*_RS)
 329    "s" 5 bit source register specifier (OP_*_RS)
 330    "t" 5 bit target register (OP_*_RT)
 331    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 332    "v" 5 bit same register used as both source and destination (OP_*_RS)
 333    "w" 5 bit same register used as both target and destination (OP_*_RT)
 334    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 335        (used by clo and clz)
 336    "C" 25 bit coprocessor function code (OP_*_COPZ)
 337    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 338    "J" 19 bit wait function code (OP_*_CODE19)
 339    "x" accept and ignore register name
 340    "z" must be zero register
 341    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 342    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 343         LSB (OP_*_SHAMT).
 344         Enforces: 0 <= pos < 32.
 345    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 346         Requires that "+A" or "+E" occur first to set position.
 347         Enforces: 0 < (pos+size) <= 32.
 348    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 349         Requires that "+A" or "+E" occur first to set position.
 350         Enforces: 0 < (pos+size) <= 32.
 351         (Also used by "dext" w/ different limits, but limits for
 352         that are checked by the M_DEXT macro.)
 353    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 354         Enforces: 32 <= pos < 64.
 355    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 356         Requires that "+A" or "+E" occur first to set position.
 357         Enforces: 32 < (pos+size) <= 64.
 358    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 359         Requires that "+A" or "+E" occur first to set position.
 360         Enforces: 32 < (pos+size) <= 64.
 361    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 362         Requires that "+A" or "+E" occur first to set position.
 363         Enforces: 32 < (pos+size) <= 64.
 364
 365    Floating point instructions:
 366    "D" 5 bit destination register (OP_*_FD)
 367    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 368    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 369    "S" 5 bit fs source 1 register (OP_*_FS)
 370    "T" 5 bit ft source 2 register (OP_*_FT)
 371    "R" 5 bit fr source 3 register (OP_*_FR)
 372    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 373    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 374
 375    Coprocessor instructions:
 376    "E" 5 bit target register (OP_*_RT)
 377    "G" 5 bit destination register (OP_*_RD)
 378    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 379    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 380    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 381    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 382    see also "k" above
 383    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 384         for pretty-printing in disassembly only.
 385
 386    Macro instructions:
 387    "A" General 32 bit expression
 388    "I" 32 bit immediate (value placed in imm_expr).
 389    "+I" 32 bit immediate (value placed in imm2_expr).
 390    "F" 64 bit floating point constant in .rdata
 391    "L" 64 bit floating point constant in .lit8
 392    "f" 32 bit floating point constant
 393    "l" 32 bit floating point constant in .lit4
 394
 395    MDMX instruction operands (note that while these use the FP register
 396    fields, they accept both $fN and $vN names for the registers):
 397    "O"  MDMX alignment offset (OP_*_ALN)
 398    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 399    "X"  MDMX destination register (OP_*_FD)
 400    "Y"  MDMX source register (OP_*_FS)
 401    "Z"  MDMX source register (OP_*_FT)
 402
 403    DSP ASE usage:
 404    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 405    "3" 3 bit unsigned immediate (OP_*_SA3)
 406    "4" 4 bit unsigned immediate (OP_*_SA4)
 407    "5" 8 bit unsigned immediate (OP_*_IMM8)
 408    "6" 5 bit unsigned immediate (OP_*_RS)
 409    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 410    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 411    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 412    "0" 6 bit signed immediate (OP_*_DSPSFT)
 413    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 414    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 415    "@" 10 bit signed immediate (OP_*_IMM10)
 416
 417    MT ASE usage:
 418    "!" 1 bit usermode flag (OP_*_MT_U)
 419    "$" 1 bit load high flag (OP_*_MT_H)
 420    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 421    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 422    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 423    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 424    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 425
 426    UDI immediates:
 427    "+1" UDI immediate bits 6-10
 428    "+2" UDI immediate bits 6-15
 429    "+3" UDI immediate bits 6-20
 430    "+4" UDI immediate bits 6-25
 431
 432    R6 immediates/displacements :
 433    (adding suffix to 'o' to avoid adding new characters)
 434    "+o"  9 bits immediate/displacement (shift = 7)
 435    "+o1" 18 bits immediate/displacement (shift = 0)
 436    "+o2" 19 bits immediate/displacement (shift = 0)
 437
 438    Other:
 439    "()" parens surrounding optional value
 440    ","  separates operands
 441    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 442    "+"  Start of extension sequence.
 443
 444    Characters used so far, for quick reference when adding more:
 445    "234567890"
 446    "%[]<>(),+:'@!$*&"
 447    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 448    "abcdefghijklopqrstuvwxz"
 449
 450    Extension character sequences used so far ("+" followed by the
 451    following), for quick reference when adding more:
 452    "1234"
 453    "ABCDEFGHIT"
 454    "t"
 455 */
 456
 457 /* These are the bits which may be set in the pinfo field of an
 458    instructions, if it is not equal to INSN_MACRO.  */
 459
 460 /* Modifies the general purpose register in OP_*_RD.  */
 461 #define INSN_WRITE_GPR_D            0x00000001
 462 /* Modifies the general purpose register in OP_*_RT.  */
 463 #define INSN_WRITE_GPR_T            0x00000002
 464 /* Modifies general purpose register 31.  */
 465 #define INSN_WRITE_GPR_31           0x00000004
 466 /* Modifies the floating point register in OP_*_FD.  */
 467 #define INSN_WRITE_FPR_D            0x00000008
 468 /* Modifies the floating point register in OP_*_FS.  */
 469 #define INSN_WRITE_FPR_S            0x00000010
 470 /* Modifies the floating point register in OP_*_FT.  */
 471 #define INSN_WRITE_FPR_T            0x00000020
 472 /* Reads the general purpose register in OP_*_RS.  */
 473 #define INSN_READ_GPR_S             0x00000040
 474 /* Reads the general purpose register in OP_*_RT.  */
 475 #define INSN_READ_GPR_T             0x00000080
 476 /* Reads the floating point register in OP_*_FS.  */
 477 #define INSN_READ_FPR_S             0x00000100
 478 /* Reads the floating point register in OP_*_FT.  */
 479 #define INSN_READ_FPR_T             0x00000200
 480 /* Reads the floating point register in OP_*_FR.  */
 481 #define INSN_READ_FPR_R             0x00000400
 482 /* Modifies coprocessor condition code.  */
 483 #define INSN_WRITE_COND_CODE        0x00000800
 484 /* Reads coprocessor condition code.  */
 485 #define INSN_READ_COND_CODE         0x00001000
 486 /* TLB operation.  */
 487 #define INSN_TLB                    0x00002000
 488 /* Reads coprocessor register other than floating point register.  */
 489 #define INSN_COP                    0x00004000
 490 /* Instruction loads value from memory, requiring delay.  */
 491 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 492 /* Instruction loads value from coprocessor, requiring delay.  */
 493 #define INSN_LOAD_COPROC_DELAY      0x00010000
 494 /* Instruction has unconditional branch delay slot.  */
 495 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 496 /* Instruction has conditional branch delay slot.  */
 497 #define INSN_COND_BRANCH_DELAY      0x00040000
 498 /* Conditional branch likely: if branch not taken, insn nullified.  */
 499 #define INSN_COND_BRANCH_LIKELY     0x00080000
 500 /* Moves to coprocessor register, requiring delay.  */
 501 #define INSN_COPROC_MOVE_DELAY      0x00100000
 502 /* Loads coprocessor register from memory, requiring delay.  */
 503 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 504 /* Reads the HI register.  */
 505 #define INSN_READ_HI                0x00400000
 506 /* Reads the LO register.  */
 507 #define INSN_READ_LO                0x00800000
 508 /* Modifies the HI register.  */
 509 #define INSN_WRITE_HI               0x01000000
 510 /* Modifies the LO register.  */
 511 #define INSN_WRITE_LO               0x02000000
 512 /* Takes a trap (easier to keep out of delay slot).  */
 513 #define INSN_TRAP                   0x04000000
 514 /* Instruction stores value into memory.  */
 515 #define INSN_STORE_MEMORY           0x08000000
 516 /* Instruction uses single precision floating point.  */
 517 #define FP_S                        0x10000000
 518 /* Instruction uses double precision floating point.  */
 519 #define FP_D                        0x20000000
 520 /* Instruction is part of the tx39's integer multiply family.    */
 521 #define INSN_MULT                   0x40000000
 522 /* Instruction synchronize shared memory.  */
 523 #define INSN_SYNC                   0x80000000
 524
 525 /* These are the bits which may be set in the pinfo2 field of an
 526    instruction. */
 527
 528 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 529 #define INSN2_ALIAS                 0x00000001
 530 /* Instruction reads MDMX accumulator. */
 531 #define INSN2_READ_MDMX_ACC         0x00000002
 532 /* Instruction writes MDMX accumulator. */
 533 #define INSN2_WRITE_MDMX_ACC        0x00000004
 534
 535 /* Reads the general purpose register in OP_*_RD.  */
 536 #define INSN2_READ_GPR_D    0x00000200
 537
 538 /* Instruction is actually a macro.  It should be ignored by the
 539    disassembler, and requires special treatment by the assembler.  */
 540 #define INSN_MACRO                  0xffffffff
 541
 542 /* Masks used to mark instructions to indicate which MIPS ISA level
 543    they were introduced in.  ISAs, as defined below, are logical
 544    ORs of these bits, indicating that they support the instructions
 545    defined at the given level.  */
 546
 547 #define INSN_ISA_MASK             0x00000fff
 548 #define INSN_ISA1                 0x00000001
 549 #define INSN_ISA2                 0x00000002
 550 #define INSN_ISA3                 0x00000004
 551 #define INSN_ISA4                 0x00000008
 552 #define INSN_ISA5                 0x00000010
 553 #define INSN_ISA32                0x00000020
 554 #define INSN_ISA64                0x00000040
 555 #define INSN_ISA32R2              0x00000080
 556 #define INSN_ISA64R2              0x00000100
 557 #define INSN_ISA32R6              0x00000200
 558 #define INSN_ISA64R6              0x00000400
 559
 560 /* Masks used for MIPS-defined ASEs.  */
 561 #define INSN_ASE_MASK             0x0000f000
 562
 563 /* DSP ASE */
 564 #define INSN_DSP                  0x00001000
 565 #define INSN_DSP64                0x00002000
 566 /* MIPS 16 ASE */
 567 #define INSN_MIPS16               0x00004000
 568 /* MIPS-3D ASE */
 569 #define INSN_MIPS3D               0x00008000
 570
 571 /* Chip specific instructions.  These are bitmasks.  */
 572
 573 /* MIPS R4650 instruction.  */
 574 #define INSN_4650                 0x00010000
 575 /* LSI R4010 instruction.  */
 576 #define INSN_4010                 0x00020000
 577 /* NEC VR4100 instruction.  */
 578 #define INSN_4100                 0x00040000
 579 /* Toshiba R3900 instruction.  */
 580 #define INSN_3900                 0x00080000
 581 /* MIPS R10000 instruction.  */
 582 #define INSN_10000                0x00100000
 583 /* Broadcom SB-1 instruction.  */
 584 #define INSN_SB1                  0x00200000
 585 /* NEC VR4111/VR4181 instruction.  */
 586 #define INSN_4111                 0x00400000
 587 /* NEC VR4120 instruction.  */
 588 #define INSN_4120                 0x00800000
 589 /* NEC VR5400 instruction.  */
 590 #define INSN_5400                 0x01000000
 591 /* NEC VR5500 instruction.  */
 592 #define INSN_5500                 0x02000000
 593
 594 /* MDMX ASE */
 595 #define INSN_MDMX                 0x00000000    /* Deprecated */
 596
 597 /* MIPS MSA Extension */
 598 #define INSN_MSA                  0x04000000
 599 #define INSN_MSA64                0x04000000
 600
 601 /* MT ASE */
 602 #define INSN_MT                   0x08000000
 603 /* SmartMIPS ASE  */
 604 #define INSN_SMARTMIPS            0x10000000
 605 /* DSP R2 ASE  */
 606 #define INSN_DSPR2                0x20000000
 607
 608 /* ST Microelectronics Loongson 2E.  */
 609 #define INSN_LOONGSON_2E          0x40000000
 610 /* ST Microelectronics Loongson 2F.  */
 611 #define INSN_LOONGSON_2F          0x80000000
 612
 613 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 614
 615 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 616 #define       ISA_MIPS1       (INSN_ISA1)
 617 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 618 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 619 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 620 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 621
 622 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 623 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 624
 625 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 626 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 627
 628 #define       ISA_MIPS32R6    (ISA_MIPS32R2 | INSN_ISA32R6)
 629 #define       ISA_MIPS64R6    (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
 630
 631 /* CPU defines, use instead of hardcoding processor number. Keep this
 632    in sync with bfd/archures.c in order for machine selection to work.  */
 633 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 634 #define CPU_R3000       3000
 635 #define CPU_R3900       3900
 636 #define CPU_R4000       4000
 637 #define CPU_R4010       4010
 638 #define CPU_VR4100      4100
 639 #define CPU_R4111       4111
 640 #define CPU_VR4120      4120
 641 #define CPU_R4300       4300
 642 #define CPU_R4400       4400
 643 #define CPU_R4600       4600
 644 #define CPU_R4650       4650
 645 #define CPU_R5000       5000
 646 #define CPU_VR5400      5400
 647 #define CPU_VR5500      5500
 648 #define CPU_R6000       6000
 649 #define CPU_RM7000      7000
 650 #define CPU_R8000       8000
 651 #define CPU_R10000      10000
 652 #define CPU_R12000      12000
 653 #define CPU_MIPS16      16
 654 #define CPU_MIPS32      32
 655 #define CPU_MIPS32R2    33
 656 #define CPU_MIPS5       5
 657 #define CPU_MIPS64      64
 658 #define CPU_MIPS64R2    65
 659 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 660
 661 /* Test for membership in an ISA including chip specific ISAs.  INSN
 662    is pointer to an element of the opcode table; ISA is the specified
 663    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 664    test, or zero if no CPU specific ISA test is desired.  */
 665
 666 #if 0
 667 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 668     (((insn)->membership & isa) != 0                                    \
 669      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 670      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 671      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 672      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 673      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 674      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 675      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 676          && ((insn)->membership & INSN_10000) != 0)                     \
 677      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 678      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 679      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 680      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 681      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 682      || 0)      /* Please keep this term for easier source merging.  */
 683 #else
 684 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
 685     (1 != 0)
 686 #endif
 687
 688 /* This is a list of macro expanded instructions.
 689
 690    _I appended means immediate
 691    _A appended means address
 692    _AB appended means address with base register
 693    _D appended means 64 bit floating point constant
 694    _S appended means 32 bit floating point constant.  */
 695
 696 enum
 697 {
 698   M_ABS,
 699   M_ADD_I,
 700   M_ADDU_I,
 701   M_AND_I,
 702   M_BALIGN,
 703   M_BEQ,
 704   M_BEQ_I,
 705   M_BEQL_I,
 706   M_BGE,
 707   M_BGEL,
 708   M_BGE_I,
 709   M_BGEL_I,
 710   M_BGEU,
 711   M_BGEUL,
 712   M_BGEU_I,
 713   M_BGEUL_I,
 714   M_BGT,
 715   M_BGTL,
 716   M_BGT_I,
 717   M_BGTL_I,
 718   M_BGTU,
 719   M_BGTUL,
 720   M_BGTU_I,
 721   M_BGTUL_I,
 722   M_BLE,
 723   M_BLEL,
 724   M_BLE_I,
 725   M_BLEL_I,
 726   M_BLEU,
 727   M_BLEUL,
 728   M_BLEU_I,
 729   M_BLEUL_I,
 730   M_BLT,
 731   M_BLTL,
 732   M_BLT_I,
 733   M_BLTL_I,
 734   M_BLTU,
 735   M_BLTUL,
 736   M_BLTU_I,
 737   M_BLTUL_I,
 738   M_BNE,
 739   M_BNE_I,
 740   M_BNEL_I,
 741   M_CACHE_AB,
 742   M_DABS,
 743   M_DADD_I,
 744   M_DADDU_I,
 745   M_DDIV_3,
 746   M_DDIV_3I,
 747   M_DDIVU_3,
 748   M_DDIVU_3I,
 749   M_DEXT,
 750   M_DINS,
 751   M_DIV_3,
 752   M_DIV_3I,
 753   M_DIVU_3,
 754   M_DIVU_3I,
 755   M_DLA_AB,
 756   M_DLCA_AB,
 757   M_DLI,
 758   M_DMUL,
 759   M_DMUL_I,
 760   M_DMULO,
 761   M_DMULO_I,
 762   M_DMULOU,
 763   M_DMULOU_I,
 764   M_DREM_3,
 765   M_DREM_3I,
 766   M_DREMU_3,
 767   M_DREMU_3I,
 768   M_DSUB_I,
 769   M_DSUBU_I,
 770   M_DSUBU_I_2,
 771   M_J_A,
 772   M_JAL_1,
 773   M_JAL_2,
 774   M_JAL_A,
 775   M_L_DOB,
 776   M_L_DAB,
 777   M_LA_AB,
 778   M_LB_A,
 779   M_LB_AB,
 780   M_LBU_A,
 781   M_LBU_AB,
 782   M_LCA_AB,
 783   M_LD_A,
 784   M_LD_OB,
 785   M_LD_AB,
 786   M_LDC1_AB,
 787   M_LDC2_AB,
 788   M_LDC3_AB,
 789   M_LDL_AB,
 790   M_LDR_AB,
 791   M_LH_A,
 792   M_LH_AB,
 793   M_LHU_A,
 794   M_LHU_AB,
 795   M_LI,
 796   M_LI_D,
 797   M_LI_DD,
 798   M_LI_S,
 799   M_LI_SS,
 800   M_LL_AB,
 801   M_LLD_AB,
 802   M_LS_A,
 803   M_LW_A,
 804   M_LW_AB,
 805   M_LWC0_A,
 806   M_LWC0_AB,
 807   M_LWC1_A,
 808   M_LWC1_AB,
 809   M_LWC2_A,
 810   M_LWC2_AB,
 811   M_LWC3_A,
 812   M_LWC3_AB,
 813   M_LWL_A,
 814   M_LWL_AB,
 815   M_LWR_A,
 816   M_LWR_AB,
 817   M_LWU_AB,
 818   M_MOVE,
 819   M_MUL,
 820   M_MUL_I,
 821   M_MULO,
 822   M_MULO_I,
 823   M_MULOU,
 824   M_MULOU_I,
 825   M_NOR_I,
 826   M_OR_I,
 827   M_REM_3,
 828   M_REM_3I,
 829   M_REMU_3,
 830   M_REMU_3I,
 831   M_DROL,
 832   M_ROL,
 833   M_DROL_I,
 834   M_ROL_I,
 835   M_DROR,
 836   M_ROR,
 837   M_DROR_I,
 838   M_ROR_I,
 839   M_S_DA,
 840   M_S_DOB,
 841   M_S_DAB,
 842   M_S_S,
 843   M_SC_AB,
 844   M_SCD_AB,
 845   M_SD_A,
 846   M_SD_OB,
 847   M_SD_AB,
 848   M_SDC1_AB,
 849   M_SDC2_AB,
 850   M_SDC3_AB,
 851   M_SDL_AB,
 852   M_SDR_AB,
 853   M_SEQ,
 854   M_SEQ_I,
 855   M_SGE,
 856   M_SGE_I,
 857   M_SGEU,
 858   M_SGEU_I,
 859   M_SGT,
 860   M_SGT_I,
 861   M_SGTU,
 862   M_SGTU_I,
 863   M_SLE,
 864   M_SLE_I,
 865   M_SLEU,
 866   M_SLEU_I,
 867   M_SLT_I,
 868   M_SLTU_I,
 869   M_SNE,
 870   M_SNE_I,
 871   M_SB_A,
 872   M_SB_AB,
 873   M_SH_A,
 874   M_SH_AB,
 875   M_SW_A,
 876   M_SW_AB,
 877   M_SWC0_A,
 878   M_SWC0_AB,
 879   M_SWC1_A,
 880   M_SWC1_AB,
 881   M_SWC2_A,
 882   M_SWC2_AB,
 883   M_SWC3_A,
 884   M_SWC3_AB,
 885   M_SWL_A,
 886   M_SWL_AB,
 887   M_SWR_A,
 888   M_SWR_AB,
 889   M_SUB_I,
 890   M_SUBU_I,
 891   M_SUBU_I_2,
 892   M_TEQ_I,
 893   M_TGE_I,
 894   M_TGEU_I,
 895   M_TLT_I,
 896   M_TLTU_I,
 897   M_TNE_I,
 898   M_TRUNCWD,
 899   M_TRUNCWS,
 900   M_ULD,
 901   M_ULD_A,
 902   M_ULH,
 903   M_ULH_A,
 904   M_ULHU,
 905   M_ULHU_A,
 906   M_ULW,
 907   M_ULW_A,
 908   M_USH,
 909   M_USH_A,
 910   M_USW,
 911   M_USW_A,
 912   M_USD,
 913   M_USD_A,
 914   M_XOR_I,
 915   M_COP0,
 916   M_COP1,
 917   M_COP2,
 918   M_COP3,
 919   M_NUM_MACROS
 920 };
 921
 922
 923 /* The order of overloaded instructions matters.  Label arguments and
 924    register arguments look the same. Instructions that can have either
 925    for arguments must apear in the correct order in this table for the
 926    assembler to pick the right one. In other words, entries with
 927    immediate operands must apear after the same instruction with
 928    registers.
 929
 930    Many instructions are short hand for other instructions (i.e., The
 931    jal <register> instruction is short for jalr <register>).  */
 932
 933 extern const struct mips_opcode mips_builtin_opcodes[];
 934 extern const int bfd_mips_num_builtin_opcodes;
 935 extern struct mips_opcode *mips_opcodes;
 936 extern int bfd_mips_num_opcodes;
 937 #define NUMOPCODES bfd_mips_num_opcodes
 938
 939 \f
 940 /* The rest of this file adds definitions for the mips16 TinyRISC
 941    processor.  */
 942
 943 /* These are the bitmasks and shift counts used for the different
 944    fields in the instruction formats.  Other than OP, no masks are
 945    provided for the fixed portions of an instruction, since they are
 946    not needed.
 947
 948    The I format uses IMM11.
 949
 950    The RI format uses RX and IMM8.
 951
 952    The RR format uses RX, and RY.
 953
 954    The RRI format uses RX, RY, and IMM5.
 955
 956    The RRR format uses RX, RY, and RZ.
 957
 958    The RRI_A format uses RX, RY, and IMM4.
 959
 960    The SHIFT format uses RX, RY, and SHAMT.
 961
 962    The I8 format uses IMM8.
 963
 964    The I8_MOVR32 format uses RY and REGR32.
 965
 966    The IR_MOV32R format uses REG32R and MOV32Z.
 967
 968    The I64 format uses IMM8.
 969
 970    The RI64 format uses RY and IMM5.
 971    */
 972
 973 #define MIPS16OP_MASK_OP        0x1f
 974 #define MIPS16OP_SH_OP          11
 975 #define MIPS16OP_MASK_IMM11     0x7ff
 976 #define MIPS16OP_SH_IMM11       0
 977 #define MIPS16OP_MASK_RX        0x7
 978 #define MIPS16OP_SH_RX          8
 979 #define MIPS16OP_MASK_IMM8      0xff
 980 #define MIPS16OP_SH_IMM8        0
 981 #define MIPS16OP_MASK_RY        0x7
 982 #define MIPS16OP_SH_RY          5
 983 #define MIPS16OP_MASK_IMM5      0x1f
 984 #define MIPS16OP_SH_IMM5        0
 985 #define MIPS16OP_MASK_RZ        0x7
 986 #define MIPS16OP_SH_RZ          2
 987 #define MIPS16OP_MASK_IMM4      0xf
 988 #define MIPS16OP_SH_IMM4        0
 989 #define MIPS16OP_MASK_REGR32    0x1f
 990 #define MIPS16OP_SH_REGR32      0
 991 #define MIPS16OP_MASK_REG32R    0x1f
 992 #define MIPS16OP_SH_REG32R      3
 993 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 994 #define MIPS16OP_MASK_MOVE32Z   0x7
 995 #define MIPS16OP_SH_MOVE32Z     0
 996 #define MIPS16OP_MASK_IMM6      0x3f
 997 #define MIPS16OP_SH_IMM6        5
 998
 999 /* These are the characters which may appears in the args field of an
1000    instruction.  They appear in the order in which the fields appear
1001    when the instruction is used.  Commas and parentheses in the args
1002    string are ignored when assembling, and written into the output
1003    when disassembling.
1004
1005    "y" 3 bit register (MIPS16OP_*_RY)
1006    "x" 3 bit register (MIPS16OP_*_RX)
1007    "z" 3 bit register (MIPS16OP_*_RZ)
1008    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1009    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1010    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1011    "0" zero register ($0)
1012    "S" stack pointer ($sp or $29)
1013    "P" program counter
1014    "R" return address register ($ra or $31)
1015    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1016    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1017    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1018    "a" 26 bit jump address
1019    "e" 11 bit extension value
1020    "l" register list for entry instruction
1021    "L" register list for exit instruction
1022
1023    The remaining codes may be extended.  Except as otherwise noted,
1024    the full extended operand is a 16 bit signed value.
1025    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1026    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1027    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1028    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1029    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1030    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1031    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1032    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1033    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1034    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1035    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1036    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1037    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1038    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1039    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1040    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1041    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1042    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1043    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1044    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1045    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1046    */
1047
1048 /* Save/restore encoding for the args field when all 4 registers are
1049    either saved as arguments or saved/restored as statics.  */
1050 #define MIPS16_ALL_ARGS    0xe
1051 #define MIPS16_ALL_STATICS 0xb
1052
1053 /* For the mips16, we use the same opcode table format and a few of
1054    the same flags.  However, most of the flags are different.  */
1055
1056 /* Modifies the register in MIPS16OP_*_RX.  */
1057 #define MIPS16_INSN_WRITE_X                 0x00000001
1058 /* Modifies the register in MIPS16OP_*_RY.  */
1059 #define MIPS16_INSN_WRITE_Y                 0x00000002
1060 /* Modifies the register in MIPS16OP_*_RZ.  */
1061 #define MIPS16_INSN_WRITE_Z                 0x00000004
1062 /* Modifies the T ($24) register.  */
1063 #define MIPS16_INSN_WRITE_T                 0x00000008
1064 /* Modifies the SP ($29) register.  */
1065 #define MIPS16_INSN_WRITE_SP                0x00000010
1066 /* Modifies the RA ($31) register.  */
1067 #define MIPS16_INSN_WRITE_31                0x00000020
1068 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1069 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1070 /* Reads the register in MIPS16OP_*_RX.  */
1071 #define MIPS16_INSN_READ_X                  0x00000080
1072 /* Reads the register in MIPS16OP_*_RY.  */
1073 #define MIPS16_INSN_READ_Y                  0x00000100
1074 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1075 #define MIPS16_INSN_READ_Z                  0x00000200
1076 /* Reads the T ($24) register.  */
1077 #define MIPS16_INSN_READ_T                  0x00000400
1078 /* Reads the SP ($29) register.  */
1079 #define MIPS16_INSN_READ_SP                 0x00000800
1080 /* Reads the RA ($31) register.  */
1081 #define MIPS16_INSN_READ_31                 0x00001000
1082 /* Reads the program counter.  */
1083 #define MIPS16_INSN_READ_PC                 0x00002000
1084 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1085 #define MIPS16_INSN_READ_GPR_X              0x00004000
1086 /* Is a branch insn. */
1087 #define MIPS16_INSN_BRANCH                  0x00010000
1088
1089 /* The following flags have the same value for the mips16 opcode
1090    table:
1091    INSN_UNCOND_BRANCH_DELAY
1092    INSN_COND_BRANCH_DELAY
1093    INSN_COND_BRANCH_LIKELY (never used)
1094    INSN_READ_HI
1095    INSN_READ_LO
1096    INSN_WRITE_HI
1097    INSN_WRITE_LO
1098    INSN_TRAP
1099    INSN_ISA3
1100    */
1101
1102 extern const struct mips_opcode mips16_opcodes[];
1103 extern const int bfd_mips16_num_opcodes;
1104
1105 /* Short hand so the lines aren't too long.  */
1106
1107 #define LDD     INSN_LOAD_MEMORY_DELAY
1108 #define LCD     INSN_LOAD_COPROC_DELAY
1109 #define UBD     INSN_UNCOND_BRANCH_DELAY
1110 #define CBD     INSN_COND_BRANCH_DELAY
1111 #define COD     INSN_COPROC_MOVE_DELAY
1112 #define CLD     INSN_COPROC_MEMORY_DELAY
1113 #define CBL     INSN_COND_BRANCH_LIKELY
1114 #define TRAP    INSN_TRAP
1115 #define SM      INSN_STORE_MEMORY
1116
1117 #define WR_d    INSN_WRITE_GPR_D
1118 #define WR_t    INSN_WRITE_GPR_T
1119 #define WR_31   INSN_WRITE_GPR_31
1120 #define WR_D    INSN_WRITE_FPR_D
1121 #define WR_T    INSN_WRITE_FPR_T
1122 #define WR_S    INSN_WRITE_FPR_S
1123 #define RD_s    INSN_READ_GPR_S
1124 #define RD_b    INSN_READ_GPR_S
1125 #define RD_t    INSN_READ_GPR_T
1126 #define RD_S    INSN_READ_FPR_S
1127 #define RD_T    INSN_READ_FPR_T
1128 #define RD_R    INSN_READ_FPR_R
1129 #define WR_CC   INSN_WRITE_COND_CODE
1130 #define RD_CC   INSN_READ_COND_CODE
1131 #define RD_C0   INSN_COP
1132 #define RD_C1   INSN_COP
1133 #define RD_C2   INSN_COP
1134 #define RD_C3   INSN_COP
1135 #define WR_C0   INSN_COP
1136 #define WR_C1   INSN_COP
1137 #define WR_C2   INSN_COP
1138 #define WR_C3   INSN_COP
1139
1140 #define WR_HI   INSN_WRITE_HI
1141 #define RD_HI   INSN_READ_HI
1142 #define MOD_HI  WR_HI|RD_HI
1143
1144 #define WR_LO   INSN_WRITE_LO
1145 #define RD_LO   INSN_READ_LO
1146 #define MOD_LO  WR_LO|RD_LO
1147
1148 #define WR_HILO WR_HI|WR_LO
1149 #define RD_HILO RD_HI|RD_LO
1150 #define MOD_HILO WR_HILO|RD_HILO
1151
1152 #define IS_M    INSN_MULT
1153
1154 #define WR_MACC INSN2_WRITE_MDMX_ACC
1155 #define RD_MACC INSN2_READ_MDMX_ACC
1156
1157 #define I1      INSN_ISA1
1158 #define I2      INSN_ISA2
1159 #define I3      INSN_ISA3
1160 #define I4      INSN_ISA4
1161 #define I5      INSN_ISA5
1162 #define I32     INSN_ISA32
1163 #define I64     INSN_ISA64
1164 #define I33     INSN_ISA32R2
1165 #define I65     INSN_ISA64R2
1166 #define I32R6   INSN_ISA32R6
1167 #define I64R6   INSN_ISA64R6
1168
1169 /* MIPS64 MIPS-3D ASE support.  */
1170 #define I16     INSN_MIPS16
1171
1172 /* MIPS32 SmartMIPS ASE support.  */
1173 #define SMT     INSN_SMARTMIPS
1174
1175 /* MIPS64 MIPS-3D ASE support.  */
1176 #define M3D     INSN_MIPS3D
1177
1178 /* MIPS64 MDMX ASE support.  */
1179 #define MX      INSN_MDMX
1180
1181 #define IL2E    (INSN_LOONGSON_2E)
1182 #define IL2F    (INSN_LOONGSON_2F)
1183
1184 #define P3      INSN_4650
1185 #define L1      INSN_4010
1186 #define V1      (INSN_4100 | INSN_4111 | INSN_4120)
1187 #define T3      INSN_3900
1188 #define M1      INSN_10000
1189 #define SB1     INSN_SB1
1190 #define N411    INSN_4111
1191 #define N412    INSN_4120
1192 #define N5      (INSN_5400 | INSN_5500)
1193 #define N54     INSN_5400
1194 #define N55     INSN_5500
1195
1196 #define G1      (T3             \
1197                  )
1198
1199 #define G2      (T3             \
1200                  )
1201
1202 #define G3      (I4             \
1203                  )
1204
1205 /* MIPS DSP ASE support.
1206    NOTE:
1207    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1208    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1209    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1210    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1211    (RD_HILO) attributes, such that HILO dependencies are maintained
1212    conservatively.
1213
1214    2. For some mul. instructions that use integer registers as destinations
1215    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1216
1217    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1218    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1219    certain fields of the DSP control register.  For simplicity, we decide not
1220    to track dependencies of these fields.
1221    However, "bposge32" is a branch instruction that depends on the "pos"
1222    field.  In order to make sure that GAS does not reorder DSP instructions
1223    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1224    attribute to those instructions that write the "pos" field.  */
1225
1226 #define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */
1227 #define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
1228 #define MOD_a   WR_a|RD_a
1229 #define DSP_VOLA        INSN_TRAP
1230 #define D32     INSN_DSP
1231 #define D33     INSN_DSPR2
1232 #define D64     INSN_DSP64
1233
1234 /* MIPS MT ASE support.  */
1235 #define MT32    INSN_MT
1236
1237 /* MSA */
1238 #define MSA     INSN_MSA
1239 #define MSA64   INSN_MSA64
1240 #define WR_VD   INSN_WRITE_FPR_D    /* Reuse INSN_WRITE_FPR_D */
1241 #define RD_VD   WR_VD               /* Reuse WR_VD */
1242 #define RD_VT   INSN_READ_FPR_T     /* Reuse INSN_READ_FPR_T */
1243 #define RD_VS   INSN_READ_FPR_S     /* Reuse INSN_READ_FPR_S */
1244 #define RD_d    INSN2_READ_GPR_D    /* Reuse INSN2_READ_GPR_D */
1245
1246 #define RD_rd6  0
1247
1248 /* The order of overloaded instructions matters.  Label arguments and
1249    register arguments look the same. Instructions that can have either
1250    for arguments must apear in the correct order in this table for the
1251    assembler to pick the right one. In other words, entries with
1252    immediate operands must apear after the same instruction with
1253    registers.
1254
1255    Because of the lookup algorithm used, entries with the same opcode
1256    name must be contiguous.
1257
1258    Many instructions are short hand for other instructions (i.e., The
1259    jal <register> instruction is short for jalr <register>).  */
1260
1261 const struct mips_opcode mips_builtin_opcodes[] =
1262 {
1263 /* These instructions appear first so that the disassembler will find
1264    them first.  The assemblers uses a hash table based on the
1265    instruction name anyhow.  */
1266 /* name,    args,       match,      mask,       pinfo,                  membership */
1267 {"lwpc",    "s,+o2",    0xec080000, 0xfc180000, WR_d,                 0, I32R6},
1268 {"lwupc",   "s,+o2",    0xec100000, 0xfc180000, WR_d,                 0, I64R6},
1269 {"ldpc",    "s,+o1",    0xec180000, 0xfc1c0000, WR_d,                 0, I64R6},
1270 {"addiupc", "s,+o2",    0xec000000, 0xfc180000, WR_d,                 0, I32R6},
1271 {"auipc",   "s,u",      0xec1e0000, 0xfc1f0000, WR_d,                 0, I32R6},
1272 {"aluipc",  "s,u",      0xec1f0000, 0xfc1f0000, WR_d,                 0, I32R6},
1273 {"daui",    "s,t,u",    0x74000000, 0xfc000000, RD_s|WR_t,            0, I64R6},
1274 {"dahi",    "s,u",      0x04060000, 0xfc1f0000, RD_s,                 0, I64R6},
1275 {"dati",    "s,u",      0x041e0000, 0xfc1f0000, RD_s,                 0, I64R6},
1276 {"lsa",     "d,s,t",    0x00000005, 0xfc00073f, WR_d|RD_s|RD_t,       0, I32R6},
1277 {"dlsa",    "d,s,t",    0x00000015, 0xfc00073f, WR_d|RD_s|RD_t,       0, I64R6},
1278 {"clz",     "U,s",      0x00000050, 0xfc1f07ff, WR_d|RD_s,            0, I32R6},
1279 {"clo",     "U,s",      0x00000051, 0xfc1f07ff, WR_d|RD_s,            0, I32R6},
1280 {"dclz",    "U,s",      0x00000052, 0xfc1f07ff, WR_d|RD_s,            0, I64R6},
1281 {"dclo",    "U,s",      0x00000053, 0xfc1f07ff, WR_d|RD_s,            0, I64R6},
1282 {"sdbbp",   "B",        0x0000000e, 0xfc00003f, TRAP,                 0, I32R6},
1283 {"mul",     "d,s,t",    0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1284 {"muh",     "d,s,t",    0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1285 {"mulu",    "d,s,t",    0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1286 {"muhu",    "d,s,t",    0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1287 {"div",     "d,s,t",    0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1288 {"mod",     "d,s,t",    0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1289 {"divu",    "d,s,t",    0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1290 {"modu",    "d,s,t",    0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1291 {"dmul",    "d,s,t",    0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1292 {"dmuh",    "d,s,t",    0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1293 {"dmulu",   "d,s,t",    0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1294 {"dmuhu",   "d,s,t",    0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1295 {"ddiv",    "d,s,t",    0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1296 {"dmod",    "d,s,t",    0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1297 {"ddivu",   "d,s,t",    0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1298 {"dmodu",   "d,s,t",    0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1299 {"ll",      "t,o(b)",   0x7c000036, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1300 {"sc",      "t,o(b)",   0x7c000026, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1301 {"lld",     "t,o(b)",   0x7c000037, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1302 {"scd",     "t,o(b)",   0x7c000027, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1303 {"pref",    "h,o(b)",   0x7c000035, 0xfc00007f, RD_b,                 0, I32R6},
1304 {"cache",   "k,o(b)",   0x7c000025, 0xfc00007f, RD_b,                 0, I32R6},
1305 {"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1306 {"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1307 {"maddf.s", "D,S,T",    0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1308 {"maddf.d", "D,S,T",    0x46200018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1309 {"msubf.s", "D,S,T",    0x46000019, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1310 {"msubf.d", "D,S,T",    0x46200019, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1311 {"max.s",   "D,S,T",    0x4600001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1312 {"max.d",   "D,S,T",    0x4620001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1313 {"maxa.s",  "D,S,T",    0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1314 {"maxa.d",  "D,S,T",    0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1315 {"rint.s",  "D,S",      0x4600001a, 0xffff003f, WR_D|RD_S|FP_S,       0, I32R6},
1316 {"rint.d",  "D,S",      0x4620001a, 0xffff003f, WR_D|RD_S|FP_D,       0, I32R6},
1317 {"class.s", "D,S",      0x4600001b, 0xffff003f, WR_D|RD_S|FP_S,       0, I32R6},
1318 {"class.d", "D,S",      0x4620001b, 0xffff003f, WR_D|RD_S|FP_D,       0, I32R6},
1319 {"min.s",   "D,S,T",    0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1320 {"min.d",   "D,S,T",    0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1321 {"mina.s",  "D,S,T",    0x4600001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1322 {"mina.d",  "D,S,T",    0x4620001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1323 {"sel.s",   "D,S,T",    0x46000010, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1324 {"sel.d",   "D,S,T",    0x46200010, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1325 {"seleqz.s", "D,S,T",   0x46000014, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1326 {"seleqz.d", "D,S,T",   0x46200014, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1327 {"selnez.s", "D,S,T",   0x46000017, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1328 {"selnez.d", "D,S,T",   0x46200017, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1329 {"align",   "d,v,t",    0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t,       0, I32R6},
1330 {"dalign",  "d,v,t",    0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t,       0, I64R6},
1331 {"bitswap", "d,w",      0x7c000020, 0xffe007ff, WR_d|RD_t,            0, I32R6},
1332 {"dbitswap","d,w",      0x7c000024, 0xffe007ff, WR_d|RD_t,            0, I64R6},
1333 {"balc",    "+p",       0xe8000000, 0xfc000000, UBD|WR_31,            0, I32R6},
1334 {"bc",      "+p",       0xc8000000, 0xfc000000, UBD|WR_31,            0, I32R6},
1335 {"jic",     "t,o",      0xd8000000, 0xffe00000, UBD|RD_t,             0, I32R6},
1336 {"beqzc",   "s,+p",     0xd8000000, 0xfc000000, CBD|RD_s,             0, I32R6},
1337 {"jialc",   "t,o",      0xf8000000, 0xffe00000, UBD|RD_t,             0, I32R6},
1338 {"bnezc",   "s,+p",     0xf8000000, 0xfc000000, CBD|RD_s,             0, I32R6},
1339 {"beqzalc", "s,t,p",    0x20000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1340 {"bovc",    "s,t,p",    0x20000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1341 {"beqc",    "s,t,p",    0x20000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1342 {"bnezalc", "s,t,p",    0x60000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1343 {"bnvc",    "s,t,p",    0x60000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1344 {"bnec",    "s,t,p",    0x60000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1345 {"blezc",   "s,t,p",    0x58000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1346 {"bgezc",   "s,t,p",    0x58000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1347 {"bgec",    "s,t,p",    0x58000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1348 {"bgtzc",   "s,t,p",    0x5c000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1349 {"bltzc",   "s,t,p",    0x5c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1350 {"bltc",    "s,t,p",    0x5c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1351 {"blezalc", "s,t,p",    0x18000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1352 {"bgezalc", "s,t,p",    0x18000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1353 {"bgeuc",   "s,t,p",    0x18000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1354 {"bgtzalc", "s,t,p",    0x1c000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1355 {"bltzalc", "s,t,p",    0x1c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1356 {"bltuc",   "s,t,p",    0x1c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1357 {"nal",     "p",        0x04100000, 0xffff0000, WR_31,                0, I32R6},
1358 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,            0, I32R6},
1359 {"bc1eqz",  "T,p",      0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D,   0, I32R6},
1360 {"bc1nez",  "T,p",      0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D,   0, I32R6},
1361 {"bc2eqz",  "E,p",      0x49200000, 0xffe00000, CBD|RD_C2,            0, I32R6},
1362 {"bc2nez",  "E,p",      0x49a00000, 0xffe00000, CBD|RD_C2,            0, I32R6},
1363 {"cmp.af.s",   "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1364 {"cmp.un.s",   "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1365 {"cmp.eq.s",   "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1366 {"cmp.ueq.s",  "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1367 {"cmp.lt.s",   "D,S,T", 0x46800004, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1368 {"cmp.ult.s",  "D,S,T", 0x46800005, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1369 {"cmp.le.s",   "D,S,T", 0x46800006, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1370 {"cmp.ule.s",  "D,S,T", 0x46800007, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1371 {"cmp.saf.s",  "D,S,T", 0x46800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1372 {"cmp.sun.s",  "D,S,T", 0x46800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1373 {"cmp.seq.s",  "D,S,T", 0x4680000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1374 {"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1375 {"cmp.slt.s",  "D,S,T", 0x4680000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1376 {"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1377 {"cmp.sle.s",  "D,S,T", 0x4680000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1378 {"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1379 {"cmp.or.s",   "D,S,T", 0x46800011, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1380 {"cmp.une.s",  "D,S,T", 0x46800012, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1381 {"cmp.ne.s",   "D,S,T", 0x46800013, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1382 {"cmp.sor.s",  "D,S,T", 0x46800019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1383 {"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1384 {"cmp.sne.s",  "D,S,T", 0x4680001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1385 {"cmp.af.d",   "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1386 {"cmp.un.d",   "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1387 {"cmp.eq.d",   "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1388 {"cmp.ueq.d",  "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1389 {"cmp.lt.d",   "D,S,T", 0x46a00004, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1390 {"cmp.ult.d",  "D,S,T", 0x46a00005, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1391 {"cmp.le.d",   "D,S,T", 0x46a00006, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1392 {"cmp.ule.d",  "D,S,T", 0x46a00007, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1393 {"cmp.saf.d",  "D,S,T", 0x46a00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1394 {"cmp.sun.d",  "D,S,T", 0x46a00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1395 {"cmp.seq.d",  "D,S,T", 0x46a0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1396 {"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1397 {"cmp.slt.d",  "D,S,T", 0x46a0000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1398 {"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1399 {"cmp.sle.d",  "D,S,T", 0x46a0000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1400 {"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1401 {"cmp.or.d",   "D,S,T", 0x46a00011, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1402 {"cmp.une.d",  "D,S,T", 0x46a00012, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1403 {"cmp.ne.d",   "D,S,T", 0x46a00013, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1404 {"cmp.sor.d",  "D,S,T", 0x46a00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1405 {"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1406 {"cmp.sne.d",  "D,S,T", 0x46a0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1407
1408 /* MSA */
1409 {"sll.b",   "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1410 {"sll.h",   "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1411 {"sll.w",   "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1412 {"sll.d",   "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1413 {"slli.b",  "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1414 {"slli.h",  "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1415 {"slli.w",  "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1416 {"slli.d",  "+d,+e,'",  0x78000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1417 {"sra.b",   "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1418 {"sra.h",   "+d,+e,+f", 0x78a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1419 {"sra.w",   "+d,+e,+f", 0x78c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1420 {"sra.d",   "+d,+e,+f", 0x78e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1421 {"srai.b",  "+d,+e,+7", 0x78f00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1422 {"srai.h",  "+d,+e,+8", 0x78e00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1423 {"srai.w",  "+d,+e,+9", 0x78c00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1424 {"srai.d",  "+d,+e,'",  0x78800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1425 {"srl.b",   "+d,+e,+f", 0x7900000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1426 {"srl.h",   "+d,+e,+f", 0x7920000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1427 {"srl.w",   "+d,+e,+f", 0x7940000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1428 {"srl.d",   "+d,+e,+f", 0x7960000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1429 {"srli.b",  "+d,+e,+7", 0x79700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1430 {"srli.h",  "+d,+e,+8", 0x79600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1431 {"srli.w",  "+d,+e,+9", 0x79400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1432 {"srli.d",  "+d,+e,'",  0x79000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1433 {"bclr.b",  "+d,+e,+f", 0x7980000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1434 {"bclr.h",  "+d,+e,+f", 0x79a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1435 {"bclr.w",  "+d,+e,+f", 0x79c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1436 {"bclr.d",  "+d,+e,+f", 0x79e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1437 {"bclri.b", "+d,+e,+7", 0x79f00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1438 {"bclri.h", "+d,+e,+8", 0x79e00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1439 {"bclri.w", "+d,+e,+9", 0x79c00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1440 {"bclri.d", "+d,+e,'",  0x79800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1441 {"bset.b",  "+d,+e,+f", 0x7a00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1442 {"bset.h",  "+d,+e,+f", 0x7a20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1443 {"bset.w",  "+d,+e,+f", 0x7a40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1444 {"bset.d",  "+d,+e,+f", 0x7a60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1445 {"bseti.b", "+d,+e,+7", 0x7a700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1446 {"bseti.h", "+d,+e,+8", 0x7a600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1447 {"bseti.w", "+d,+e,+9", 0x7a400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1448 {"bseti.d", "+d,+e,'",  0x7a000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1449 {"bneg.b",  "+d,+e,+f", 0x7a80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1450 {"bneg.h",  "+d,+e,+f", 0x7aa0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1451 {"bneg.w",  "+d,+e,+f", 0x7ac0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1452 {"bneg.d",  "+d,+e,+f", 0x7ae0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1453 {"bnegi.b", "+d,+e,+7", 0x7af00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1454 {"bnegi.h", "+d,+e,+8", 0x7ae00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1455 {"bnegi.w", "+d,+e,+9", 0x7ac00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1456 {"bnegi.d", "+d,+e,'",  0x7a800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1457 {"binsl.b", "+d,+e,+f", 0x7b00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1458 {"binsl.h", "+d,+e,+f", 0x7b20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1459 {"binsl.w", "+d,+e,+f", 0x7b40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1460 {"binsl.d", "+d,+e,+f", 0x7b60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1461 {"binsli.b", "+d,+e,+7", 0x7b700009, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1462 {"binsli.h", "+d,+e,+8", 0x7b600009, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1463 {"binsli.w", "+d,+e,+9", 0x7b400009, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1464 {"binsli.d", "+d,+e,'",  0x7b000009, 0xffc0003f, WR_VD|RD_VS,       0, MSA},
1465 {"binsr.b", "+d,+e,+f", 0x7b80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1466 {"binsr.h", "+d,+e,+f", 0x7ba0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1467 {"binsr.w", "+d,+e,+f", 0x7bc0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1468 {"binsr.d", "+d,+e,+f", 0x7be0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1469 {"binsri.b", "+d,+e,+7", 0x7bf00009, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1470 {"binsri.h", "+d,+e,+8", 0x7be00009, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1471 {"binsri.w", "+d,+e,+9", 0x7bc00009, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1472 {"binsri.d", "+d,+e,'",  0x7b800009, 0xffc0003f, WR_VD|RD_VS,       0, MSA},
1473 {"addv.b",  "+d,+e,+f", 0x7800000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1474 {"addv.h",  "+d,+e,+f", 0x7820000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1475 {"addv.w",  "+d,+e,+f", 0x7840000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1476 {"addv.d",  "+d,+e,+f", 0x7860000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1477 {"addvi.b", "+d,+e,k",  0x78000006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1478 {"addvi.h", "+d,+e,k",  0x78200006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1479 {"addvi.w", "+d,+e,k",  0x78400006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1480 {"addvi.d", "+d,+e,k",  0x78600006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1481 {"subv.b",  "+d,+e,+f", 0x7880000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1482 {"subv.h",  "+d,+e,+f", 0x78a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1483 {"subv.w",  "+d,+e,+f", 0x78c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1484 {"subv.d",  "+d,+e,+f", 0x78e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1485 {"subvi.b", "+d,+e,k",  0x78800006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1486 {"subvi.h", "+d,+e,k",  0x78a00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1487 {"subvi.w", "+d,+e,k",  0x78c00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1488 {"subvi.d", "+d,+e,k",  0x78e00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1489 {"max_s.b", "+d,+e,+f", 0x7900000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1490 {"max_s.h", "+d,+e,+f", 0x7920000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1491 {"max_s.w", "+d,+e,+f", 0x7940000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1492 {"max_s.d", "+d,+e,+f", 0x7960000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1493 {"maxi_s.b", "+d,+e,+5", 0x79000006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1494 {"maxi_s.h", "+d,+e,+5", 0x79200006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1495 {"maxi_s.w", "+d,+e,+5", 0x79400006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1496 {"maxi_s.d", "+d,+e,+5", 0x79600006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1497 {"max_u.b", "+d,+e,+f", 0x7980000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1498 {"max_u.h", "+d,+e,+f", 0x79a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1499 {"max_u.w", "+d,+e,+f", 0x79c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1500 {"max_u.d", "+d,+e,+f", 0x79e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1501 {"maxi_u.b", "+d,+e,k",  0x79800006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1502 {"maxi_u.h", "+d,+e,k",  0x79a00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1503 {"maxi_u.w", "+d,+e,k",  0x79c00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1504 {"maxi_u.d", "+d,+e,k",  0x79e00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1505 {"min_s.b", "+d,+e,+f", 0x7a00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1506 {"min_s.h", "+d,+e,+f", 0x7a20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1507 {"min_s.w", "+d,+e,+f", 0x7a40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1508 {"min_s.d", "+d,+e,+f", 0x7a60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1509 {"mini_s.b", "+d,+e,+5", 0x7a000006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1510 {"mini_s.h", "+d,+e,+5", 0x7a200006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1511 {"mini_s.w", "+d,+e,+5", 0x7a400006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1512 {"mini_s.d", "+d,+e,+5", 0x7a600006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1513 {"min_u.b", "+d,+e,+f", 0x7a80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1514 {"min_u.h", "+d,+e,+f", 0x7aa0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1515 {"min_u.w", "+d,+e,+f", 0x7ac0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1516 {"min_u.d", "+d,+e,+f", 0x7ae0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1517 {"mini_u.b", "+d,+e,k",  0x7a800006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1518 {"mini_u.h", "+d,+e,k",  0x7aa00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1519 {"mini_u.w", "+d,+e,k",  0x7ac00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1520 {"mini_u.d", "+d,+e,k",  0x7ae00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1521 {"max_a.b", "+d,+e,+f", 0x7b00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1522 {"max_a.h", "+d,+e,+f", 0x7b20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1523 {"max_a.w", "+d,+e,+f", 0x7b40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1524 {"max_a.d", "+d,+e,+f", 0x7b60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1525 {"min_a.b", "+d,+e,+f", 0x7b80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1526 {"min_a.h", "+d,+e,+f", 0x7ba0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1527 {"min_a.w", "+d,+e,+f", 0x7bc0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1528 {"min_a.d", "+d,+e,+f", 0x7be0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1529 {"ceq.b",   "+d,+e,+f", 0x7800000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1530 {"ceq.h",   "+d,+e,+f", 0x7820000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1531 {"ceq.w",   "+d,+e,+f", 0x7840000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1532 {"ceq.d",   "+d,+e,+f", 0x7860000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1533 {"ceqi.b",  "+d,+e,+5", 0x78000007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1534 {"ceqi.h",  "+d,+e,+5", 0x78200007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1535 {"ceqi.w",  "+d,+e,+5", 0x78400007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1536 {"ceqi.d",  "+d,+e,+5", 0x78600007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1537 {"clt_s.b", "+d,+e,+f", 0x7900000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1538 {"clt_s.h", "+d,+e,+f", 0x7920000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1539 {"clt_s.w", "+d,+e,+f", 0x7940000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1540 {"clt_s.d", "+d,+e,+f", 0x7960000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1541 {"clti_s.b", "+d,+e,+5", 0x79000007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1542 {"clti_s.h", "+d,+e,+5", 0x79200007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1543 {"clti_s.w", "+d,+e,+5", 0x79400007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1544 {"clti_s.d", "+d,+e,+5", 0x79600007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1545 {"clt_u.b", "+d,+e,+f", 0x7980000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1546 {"clt_u.h", "+d,+e,+f", 0x79a0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1547 {"clt_u.w", "+d,+e,+f", 0x79c0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1548 {"clt_u.d", "+d,+e,+f", 0x79e0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1549 {"clti_u.b", "+d,+e,k",  0x79800007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1550 {"clti_u.h", "+d,+e,k",  0x79a00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1551 {"clti_u.w", "+d,+e,k",  0x79c00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1552 {"clti_u.d", "+d,+e,k",  0x79e00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1553 {"cle_s.b", "+d,+e,+f", 0x7a00000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1554 {"cle_s.h", "+d,+e,+f", 0x7a20000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1555 {"cle_s.w", "+d,+e,+f", 0x7a40000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1556 {"cle_s.d", "+d,+e,+f", 0x7a60000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1557 {"clei_s.b", "+d,+e,+5", 0x7a000007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1558 {"clei_s.h", "+d,+e,+5", 0x7a200007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1559 {"clei_s.w", "+d,+e,+5", 0x7a400007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1560 {"clei_s.d", "+d,+e,+5", 0x7a600007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1561 {"cle_u.b", "+d,+e,+f", 0x7a80000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1562 {"cle_u.h", "+d,+e,+f", 0x7aa0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1563 {"cle_u.w", "+d,+e,+f", 0x7ac0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1564 {"cle_u.d", "+d,+e,+f", 0x7ae0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1565 {"clei_u.b", "+d,+e,k",  0x7a800007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1566 {"clei_u.h", "+d,+e,k",  0x7aa00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1567 {"clei_u.w", "+d,+e,k",  0x7ac00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1568 {"clei_u.d", "+d,+e,k",  0x7ae00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1569 {"ld.b",    "+d,+^(d)", 0x78000020, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1570 {"ld.h",    "+d,+#(d)", 0x78000021, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1571 {"ld.w",    "+d,+$(d)", 0x78000022, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1572 {"ld.d",    "+d,+%(d)", 0x78000023, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1573 {"st.b",    "+d,+^(d)", 0x78000024, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1574 {"st.h",    "+d,+#(d)", 0x78000025, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1575 {"st.w",    "+d,+$(d)", 0x78000026, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1576 {"st.d",    "+d,+%(d)", 0x78000027, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1577 {"sat_s.b", "+d,+e,+7", 0x7870000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1578 {"sat_s.h", "+d,+e,+8", 0x7860000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1579 {"sat_s.w", "+d,+e,+9", 0x7840000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1580 {"sat_s.d", "+d,+e,'",  0x7800000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1581 {"sat_u.b", "+d,+e,+7", 0x78f0000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1582 {"sat_u.h", "+d,+e,+8", 0x78e0000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1583 {"sat_u.w", "+d,+e,+9", 0x78c0000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1584 {"sat_u.d", "+d,+e,'",  0x7880000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1585 {"add_a.b", "+d,+e,+f", 0x78000010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1586 {"add_a.h", "+d,+e,+f", 0x78200010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1587 {"add_a.w", "+d,+e,+f", 0x78400010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1588 {"add_a.d", "+d,+e,+f", 0x78600010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1589 {"adds_a.b", "+d,+e,+f", 0x78800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1590 {"adds_a.h", "+d,+e,+f", 0x78a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1591 {"adds_a.w", "+d,+e,+f", 0x78c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1592 {"adds_a.d", "+d,+e,+f", 0x78e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1593 {"adds_s.b", "+d,+e,+f", 0x79000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1594 {"adds_s.h", "+d,+e,+f", 0x79200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1595 {"adds_s.w", "+d,+e,+f", 0x79400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1596 {"adds_s.d", "+d,+e,+f", 0x79600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1597 {"adds_u.b", "+d,+e,+f", 0x79800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1598 {"adds_u.h", "+d,+e,+f", 0x79a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1599 {"adds_u.w", "+d,+e,+f", 0x79c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1600 {"adds_u.d", "+d,+e,+f", 0x79e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1601 {"ave_s.b", "+d,+e,+f", 0x7a000010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1602 {"ave_s.h", "+d,+e,+f", 0x7a200010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1603 {"ave_s.w", "+d,+e,+f", 0x7a400010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1604 {"ave_s.d", "+d,+e,+f", 0x7a600010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1605 {"ave_u.b", "+d,+e,+f", 0x7a800010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1606 {"ave_u.h", "+d,+e,+f", 0x7aa00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1607 {"ave_u.w", "+d,+e,+f", 0x7ac00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1608 {"ave_u.d", "+d,+e,+f", 0x7ae00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1609 {"aver_s.b", "+d,+e,+f", 0x7b000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1610 {"aver_s.h", "+d,+e,+f", 0x7b200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1611 {"aver_s.w", "+d,+e,+f", 0x7b400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1612 {"aver_s.d", "+d,+e,+f", 0x7b600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1613 {"aver_u.b", "+d,+e,+f", 0x7b800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1614 {"aver_u.h", "+d,+e,+f", 0x7ba00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1615 {"aver_u.w", "+d,+e,+f", 0x7bc00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1616 {"aver_u.d", "+d,+e,+f", 0x7be00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1617 {"subs_s.b", "+d,+e,+f", 0x78000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1618 {"subs_s.h", "+d,+e,+f", 0x78200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1619 {"subs_s.w", "+d,+e,+f", 0x78400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1620 {"subs_s.d", "+d,+e,+f", 0x78600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1621 {"subs_u.b", "+d,+e,+f", 0x78800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1622 {"subs_u.h", "+d,+e,+f", 0x78a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1623 {"subs_u.w", "+d,+e,+f", 0x78c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1624 {"subs_u.d", "+d,+e,+f", 0x78e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1625 {"subsus_u.b", "+d,+e,+f", 0x79000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1626 {"subsus_u.h", "+d,+e,+f", 0x79200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1627 {"subsus_u.w", "+d,+e,+f", 0x79400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1628 {"subsus_u.d", "+d,+e,+f", 0x79600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1629 {"subsuu_s.b", "+d,+e,+f", 0x79800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1630 {"subsuu_s.h", "+d,+e,+f", 0x79a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1631 {"subsuu_s.w", "+d,+e,+f", 0x79c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1632 {"subsuu_s.d", "+d,+e,+f", 0x79e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1633 {"asub_s.b", "+d,+e,+f", 0x7a000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1634 {"asub_s.h", "+d,+e,+f", 0x7a200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1635 {"asub_s.w", "+d,+e,+f", 0x7a400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1636 {"asub_s.d", "+d,+e,+f", 0x7a600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1637 {"asub_u.b", "+d,+e,+f", 0x7a800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1638 {"asub_u.h", "+d,+e,+f", 0x7aa00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1639 {"asub_u.w", "+d,+e,+f", 0x7ac00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1640 {"asub_u.d", "+d,+e,+f", 0x7ae00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1641 {"mulv.b",  "+d,+e,+f", 0x78000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1642 {"mulv.h",  "+d,+e,+f", 0x78200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1643 {"mulv.w",  "+d,+e,+f", 0x78400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1644 {"mulv.d",  "+d,+e,+f", 0x78600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1645 {"maddv.b", "+d,+e,+f", 0x78800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1646 {"maddv.h", "+d,+e,+f", 0x78a00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1647 {"maddv.w", "+d,+e,+f", 0x78c00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1648 {"maddv.d", "+d,+e,+f", 0x78e00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1649 {"msubv.b", "+d,+e,+f", 0x79000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1650 {"msubv.h", "+d,+e,+f", 0x79200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1651 {"msubv.w", "+d,+e,+f", 0x79400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1652 {"msubv.d", "+d,+e,+f", 0x79600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1653 {"div_s.b", "+d,+e,+f", 0x7a000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1654 {"div_s.h", "+d,+e,+f", 0x7a200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1655 {"div_s.w", "+d,+e,+f", 0x7a400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1656 {"div_s.d", "+d,+e,+f", 0x7a600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1657 {"div_u.b", "+d,+e,+f", 0x7a800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1658 {"div_u.h", "+d,+e,+f", 0x7aa00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1659 {"div_u.w", "+d,+e,+f", 0x7ac00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1660 {"div_u.d", "+d,+e,+f", 0x7ae00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1661 {"mod_s.b", "+d,+e,+f", 0x7b000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1662 {"mod_s.h", "+d,+e,+f", 0x7b200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1663 {"mod_s.w", "+d,+e,+f", 0x7b400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1664 {"mod_s.d", "+d,+e,+f", 0x7b600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1665 {"mod_u.b", "+d,+e,+f", 0x7b800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1666 {"mod_u.h", "+d,+e,+f", 0x7ba00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1667 {"mod_u.w", "+d,+e,+f", 0x7bc00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1668 {"mod_u.d", "+d,+e,+f", 0x7be00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1669 {"dotp_s.h", "+d,+e,+f", 0x78200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1670 {"dotp_s.w", "+d,+e,+f", 0x78400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1671 {"dotp_s.d", "+d,+e,+f", 0x78600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1672 {"dotp_u.h", "+d,+e,+f", 0x78a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1673 {"dotp_u.w", "+d,+e,+f", 0x78c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1674 {"dotp_u.d", "+d,+e,+f", 0x78e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1675 {"dpadd_s.h", "+d,+e,+f", 0x79200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1676 {"dpadd_s.w", "+d,+e,+f", 0x79400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1677 {"dpadd_s.d", "+d,+e,+f", 0x79600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1678 {"dpadd_u.h", "+d,+e,+f", 0x79a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1679 {"dpadd_u.w", "+d,+e,+f", 0x79c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1680 {"dpadd_u.d", "+d,+e,+f", 0x79e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1681 {"dpsub_s.h", "+d,+e,+f", 0x7a200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1682 {"dpsub_s.w", "+d,+e,+f", 0x7a400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1683 {"dpsub_s.d", "+d,+e,+f", 0x7a600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1684 {"dpsub_u.h", "+d,+e,+f", 0x7aa00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1685 {"dpsub_u.w", "+d,+e,+f", 0x7ac00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1686 {"dpsub_u.d", "+d,+e,+f", 0x7ae00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1687 {"sld.b",   "+d,+e[t]", 0x78000014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1688 {"sld.h",   "+d,+e[t]", 0x78200014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1689 {"sld.w",   "+d,+e[t]", 0x78400014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1690 {"sld.d",   "+d,+e[t]", 0x78600014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1691 {"sldi.b",  "+d,+e[+9]", 0x78000019, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1692 {"sldi.h",  "+d,+e[+8]", 0x78200019, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1693 {"sldi.w",  "+d,+e[+7]", 0x78300019, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1694 {"sldi.d",  "+d,+e[+6]", 0x78380019, 0xfffc003f, WR_VD|RD_VS,       0, MSA},
1695 {"splat.b", "+d,+e[t]", 0x78800014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1696 {"splat.h", "+d,+e[t]", 0x78a00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1697 {"splat.w", "+d,+e[t]", 0x78c00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1698 {"splat.d", "+d,+e[t]", 0x78e00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1699 {"splati.b", "+d,+e[+9]", 0x78400019, 0xffe0003f, WR_VD|RD_VS,      0, MSA},
1700 {"splati.h", "+d,+e[+8]", 0x78600019, 0xfff0003f, WR_VD|RD_VS,      0, MSA},
1701 {"splati.w", "+d,+e[+7]", 0x78700019, 0xfff8003f, WR_VD|RD_VS,      0, MSA},
1702 {"splati.d", "+d,+e[+6]", 0x78780019, 0xfffc003f, WR_VD|RD_VS,      0, MSA},
1703 {"pckev.b", "+d,+e,+f", 0x79000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1704 {"pckev.h", "+d,+e,+f", 0x79200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1705 {"pckev.w", "+d,+e,+f", 0x79400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1706 {"pckev.d", "+d,+e,+f", 0x79600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1707 {"pckod.b", "+d,+e,+f", 0x79800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1708 {"pckod.h", "+d,+e,+f", 0x79a00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1709 {"pckod.w", "+d,+e,+f", 0x79c00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1710 {"pckod.d", "+d,+e,+f", 0x79e00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1711 {"ilvl.b",  "+d,+e,+f", 0x7a000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1712 {"ilvl.h",  "+d,+e,+f", 0x7a200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1713 {"ilvl.w",  "+d,+e,+f", 0x7a400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1714 {"ilvl.d",  "+d,+e,+f", 0x7a600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1715 {"ilvr.b",  "+d,+e,+f", 0x7a800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1716 {"ilvr.h",  "+d,+e,+f", 0x7aa00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1717 {"ilvr.w",  "+d,+e,+f", 0x7ac00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1718 {"ilvr.d",  "+d,+e,+f", 0x7ae00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1719 {"ilvev.b", "+d,+e,+f", 0x7b000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1720 {"ilvev.h", "+d,+e,+f", 0x7b200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1721 {"ilvev.w", "+d,+e,+f", 0x7b400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1722 {"ilvev.d", "+d,+e,+f", 0x7b600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1723 {"ilvod.b", "+d,+e,+f", 0x7b800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1724 {"ilvod.h", "+d,+e,+f", 0x7ba00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1725 {"ilvod.w", "+d,+e,+f", 0x7bc00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1726 {"ilvod.d", "+d,+e,+f", 0x7be00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1727 {"vshf.b",  "+d,+e,+f", 0x78000015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1728 {"vshf.h",  "+d,+e,+f", 0x78200015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1729 {"vshf.w",  "+d,+e,+f", 0x78400015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1730 {"vshf.d",  "+d,+e,+f", 0x78600015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1731 {"srar.b",  "+d,+e,+f", 0x78800015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1732 {"srar.h",  "+d,+e,+f", 0x78a00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1733 {"srar.w",  "+d,+e,+f", 0x78c00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1734 {"srar.d",  "+d,+e,+f", 0x78e00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1735 {"srari.b", "+d,+e,+7", 0x7970000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1736 {"srari.h", "+d,+e,+8", 0x7960000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1737 {"srari.w", "+d,+e,+9", 0x7940000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1738 {"srari.d", "+d,+e,'",  0x7900000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1739 {"srlr.b",  "+d,+e,+f", 0x79000015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1740 {"srlr.h",  "+d,+e,+f", 0x79200015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1741 {"srlr.w",  "+d,+e,+f", 0x79400015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1742 {"srlr.d",  "+d,+e,+f", 0x79600015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1743 {"srlri.b", "+d,+e,+7", 0x79f0000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1744 {"srlri.h", "+d,+e,+8", 0x79e0000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1745 {"srlri.w", "+d,+e,+9", 0x79c0000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1746 {"srlri.d", "+d,+e,'",  0x7980000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1747 {"hadd_s.h", "+d,+e,+f", 0x7a200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1748 {"hadd_s.w", "+d,+e,+f", 0x7a400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1749 {"hadd_s.d", "+d,+e,+f", 0x7a600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1750 {"hadd_u.h", "+d,+e,+f", 0x7aa00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1751 {"hadd_u.w", "+d,+e,+f", 0x7ac00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1752 {"hadd_u.d", "+d,+e,+f", 0x7ae00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1753 {"hsub_s.h", "+d,+e,+f", 0x7b200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1754 {"hsub_s.w", "+d,+e,+f", 0x7b400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1755 {"hsub_s.d", "+d,+e,+f", 0x7b600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1756 {"hsub_u.h", "+d,+e,+f", 0x7ba00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1757 {"hsub_u.w", "+d,+e,+f", 0x7bc00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1758 {"hsub_u.d", "+d,+e,+f", 0x7be00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1759 {"and.v",   "+d,+e,+f", 0x7800001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1760 {"andi.b",  "+d,+e,5",  0x78000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1761 {"or.v",    "+d,+e,+f", 0x7820001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1762 {"ori.b",   "+d,+e,5",  0x79000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1763 {"nor.v",   "+d,+e,+f", 0x7840001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1764 {"nori.b",  "+d,+e,5",  0x7a000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1765 {"xor.v",   "+d,+e,+f", 0x7860001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1766 {"xori.b",  "+d,+e,5",  0x7b000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1767 {"bmnz.v",  "+d,+e,+f", 0x7880001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1768 {"bmnzi.b", "+d,+e,5",  0x78000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1769 {"bmz.v",   "+d,+e,+f", 0x78a0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1770 {"bmzi.b",  "+d,+e,5",  0x79000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1771 {"bsel.v",  "+d,+e,+f", 0x78c0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1772 {"bseli.b", "+d,+e,5",  0x7a000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1773 {"shf.b",   "+d,+e,5",  0x78000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1774 {"shf.h",   "+d,+e,5",  0x79000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1775 {"shf.w",   "+d,+e,5",  0x7a000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1776 {"bnz.v",    "+f,p",    0x45e00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1777 {"bz.v",    "+f,p",     0x45600000, 0xffe00000, CBD|RD_VT,          0, MSA},
1778 {"fill.b",  "+d,d",     0x7b00001e, 0xffff003f, WR_VD,           RD_d, MSA},
1779 {"fill.h",  "+d,d",     0x7b01001e, 0xffff003f, WR_VD,           RD_d, MSA},
1780 {"fill.w",  "+d,d",     0x7b02001e, 0xffff003f, WR_VD,           RD_d, MSA},
1781 {"fill.d",  "+d,d",     0x7b03001e, 0xffff003f, WR_VD,           RD_d, MSA64},
1782 {"pcnt.b",  "+d,+e",    0x7b04001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1783 {"pcnt.h",  "+d,+e",    0x7b05001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1784 {"pcnt.w",  "+d,+e",    0x7b06001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1785 {"pcnt.d",  "+d,+e",    0x7b07001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1786 {"nloc.b",  "+d,+e",    0x7b08001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1787 {"nloc.h",  "+d,+e",    0x7b09001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1788 {"nloc.w",  "+d,+e",    0x7b0a001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1789 {"nloc.d",  "+d,+e",    0x7b0b001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1790 {"nlzc.b",  "+d,+e",    0x7b0c001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1791 {"nlzc.h",  "+d,+e",    0x7b0d001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1792 {"nlzc.w",  "+d,+e",    0x7b0e001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1793 {"nlzc.d",  "+d,+e",    0x7b0f001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1794 {"copy_s.b", "+i,+e[+9]", 0x78800019, 0xffe0003f, RD_VS,       RD_rd6, MSA},
1795 {"copy_s.h", "+i,+e[+8]", 0x78a00019, 0xfff0003f, RD_VS,       RD_rd6, MSA},
1796 {"copy_s.w", "+i,+e[+7]", 0x78b00019, 0xfff8003f, RD_VS,       RD_rd6, MSA},
1797 {"copy_s.d", "+i,+e[+6]", 0x78b80019, 0xfffc003f, RD_VS,       RD_rd6, MSA64},
1798 {"copy_u.b", "+i,+e[+9]", 0x78c00019, 0xffe0003f, RD_VS,       RD_rd6, MSA},
1799 {"copy_u.h", "+i,+e[+8]", 0x78e00019, 0xfff0003f, RD_VS,       RD_rd6, MSA},
1800 {"copy_u.w", "+i,+e[+7]", 0x78f00019, 0xfff8003f, RD_VS,       RD_rd6, MSA},
1801 {"copy_u.d", "+i,+e[+6]", 0x78f80019, 0xfffc003f, RD_VS,       RD_rd6, MSA64},
1802 {"insert.b", "+d[+9],d", 0x79000019, 0xffe0003f, WR_VD|RD_VD,    RD_d, MSA},
1803 {"insert.h", "+d[+8],d", 0x79200019, 0xfff0003f, WR_VD|RD_VD,    RD_d, MSA},
1804 {"insert.w", "+d[+7],d", 0x79300019, 0xfff8003f, WR_VD|RD_VD,    RD_d, MSA},
1805 {"insert.d", "+d[+6],d", 0x79380019, 0xfffc003f, WR_VD|RD_VD,    RD_d, MSA64},
1806 {"insve.b", "+d[+9],+e[+~]", 0x79400019, 0xffe0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1807 {"insve.h", "+d[+8],+e[+~]", 0x79600019, 0xfff0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1808 {"insve.w", "+d[+7],+e[+~]", 0x79700019, 0xfff8003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1809 {"insve.d", "+d[+6],+e[+~]", 0x79780019, 0xfffc003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1810 {"bnz.b",    "+f,p",    0x47800000, 0xffe00000, CBD|RD_VT,          0, MSA},
1811 {"bnz.h",    "+f,p",    0x47a00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1812 {"bnz.w",    "+f,p",    0x47c00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1813 {"bnz.d",    "+f,p",    0x47e00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1814 {"bz.b",    "+f,p",     0x47000000, 0xffe00000, CBD|RD_VT,          0, MSA},
1815 {"bz.h",    "+f,p",     0x47200000, 0xffe00000, CBD|RD_VT,          0, MSA},
1816 {"bz.w",    "+f,p",     0x47400000, 0xffe00000, CBD|RD_VT,          0, MSA},
1817 {"bz.d",    "+f,p",     0x47600000, 0xffe00000, CBD|RD_VT,          0, MSA},
1818 {"ldi.b",   "+d,+0",    0x7b000007, 0xffe0003f, WR_VD,              0, MSA},
1819 {"ldi.h",   "+d,+0",    0x7b200007, 0xffe0003f, WR_VD,              0, MSA},
1820 {"ldi.w",   "+d,+0",    0x7b400007, 0xffe0003f, WR_VD,              0, MSA},
1821 {"ldi.d",   "+d,+0",    0x7b600007, 0xffe0003f, WR_VD,              0, MSA},
1822 {"fcaf.w",  "+d,+e,+f", 0x7800001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1823 {"fcaf.d",  "+d,+e,+f", 0x7820001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1824 {"fcun.w",  "+d,+e,+f", 0x7840001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1825 {"fcun.d",  "+d,+e,+f", 0x7860001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1826 {"fceq.w",  "+d,+e,+f", 0x7880001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1827 {"fceq.d",  "+d,+e,+f", 0x78a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1828 {"fcueq.w", "+d,+e,+f", 0x78c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1829 {"fcueq.d", "+d,+e,+f", 0x78e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1830 {"fclt.w",  "+d,+e,+f", 0x7900001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1831 {"fclt.d",  "+d,+e,+f", 0x7920001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1832 {"fcult.w", "+d,+e,+f", 0x7940001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1833 {"fcult.d", "+d,+e,+f", 0x7960001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1834 {"fcle.w",  "+d,+e,+f", 0x7980001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1835 {"fcle.d",  "+d,+e,+f", 0x79a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1836 {"fcule.w", "+d,+e,+f", 0x79c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1837 {"fcule.d", "+d,+e,+f", 0x79e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1838 {"fsaf.w",  "+d,+e,+f", 0x7a00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1839 {"fsaf.d",  "+d,+e,+f", 0x7a20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1840 {"fsun.w",  "+d,+e,+f", 0x7a40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1841 {"fsun.d",  "+d,+e,+f", 0x7a60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1842 {"fseq.w",  "+d,+e,+f", 0x7a80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1843 {"fseq.d",  "+d,+e,+f", 0x7aa0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1844 {"fsueq.w", "+d,+e,+f", 0x7ac0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1845 {"fsueq.d", "+d,+e,+f", 0x7ae0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1846 {"fslt.w",  "+d,+e,+f", 0x7b00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1847 {"fslt.d",  "+d,+e,+f", 0x7b20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1848 {"fsult.w", "+d,+e,+f", 0x7b40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1849 {"fsult.d", "+d,+e,+f", 0x7b60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1850 {"fsle.w",  "+d,+e,+f", 0x7b80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1851 {"fsle.d",  "+d,+e,+f", 0x7ba0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1852 {"fsule.w", "+d,+e,+f", 0x7bc0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1853 {"fsule.d", "+d,+e,+f", 0x7be0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1854 {"fadd.w",  "+d,+e,+f", 0x7800001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1855 {"fadd.d",  "+d,+e,+f", 0x7820001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1856 {"fsub.w",  "+d,+e,+f", 0x7840001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1857 {"fsub.d",  "+d,+e,+f", 0x7860001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1858 {"fmul.w",  "+d,+e,+f", 0x7880001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1859 {"fmul.d",  "+d,+e,+f", 0x78a0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1860 {"fdiv.w",  "+d,+e,+f", 0x78c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1861 {"fdiv.d",  "+d,+e,+f", 0x78e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1862 {"fmadd.w", "+d,+e,+f", 0x7900001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1863 {"fmadd.d", "+d,+e,+f", 0x7920001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1864 {"fmsub.w", "+d,+e,+f", 0x7940001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1865 {"fmsub.d", "+d,+e,+f", 0x7960001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1866 {"fexp2.w", "+d,+e,+f", 0x79c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1867 {"fexp2.d", "+d,+e,+f", 0x79e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1868 {"fexdo.h", "+d,+e,+f", 0x7a00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1869 {"fexdo.w", "+d,+e,+f", 0x7a20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1870 {"ftq.h",   "+d,+e,+f", 0x7a80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1871 {"ftq.w",   "+d,+e,+f", 0x7aa0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1872 {"fmin.w",  "+d,+e,+f", 0x7b00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1873 {"fmin.d",  "+d,+e,+f", 0x7b20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1874 {"fmin_a.w", "+d,+e,+f", 0x7b40001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1875 {"fmin_a.d", "+d,+e,+f", 0x7b60001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1876 {"fmax.w",  "+d,+e,+f", 0x7b80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1877 {"fmax.d",  "+d,+e,+f", 0x7ba0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1878 {"fmax_a.w", "+d,+e,+f", 0x7bc0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1879 {"fmax_a.d", "+d,+e,+f", 0x7be0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1880 {"fcor.w",  "+d,+e,+f", 0x7840001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1881 {"fcor.d",  "+d,+e,+f", 0x7860001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1882 {"fcune.w", "+d,+e,+f", 0x7880001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1883 {"fcune.d", "+d,+e,+f", 0x78a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1884 {"fcne.w",  "+d,+e,+f", 0x78c0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1885 {"fcne.d",  "+d,+e,+f", 0x78e0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1886 {"mul_q.h", "+d,+e,+f", 0x7900001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1887 {"mul_q.w", "+d,+e,+f", 0x7920001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1888 {"madd_q.h", "+d,+e,+f", 0x7940001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1889 {"madd_q.w", "+d,+e,+f", 0x7960001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1890 {"msub_q.h", "+d,+e,+f", 0x7980001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1891 {"msub_q.w", "+d,+e,+f", 0x79a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1892 {"fsor.w",  "+d,+e,+f", 0x7a40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1893 {"fsor.d",  "+d,+e,+f", 0x7a60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1894 {"fsune.w", "+d,+e,+f", 0x7a80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1895 {"fsune.d", "+d,+e,+f", 0x7aa0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1896 {"fsne.w",  "+d,+e,+f", 0x7ac0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1897 {"fsne.d",  "+d,+e,+f", 0x7ae0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1898 {"mulr_q.h", "+d,+e,+f", 0x7b00001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1899 {"mulr_q.w", "+d,+e,+f", 0x7b20001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1900 {"maddr_q.h", "+d,+e,+f", 0x7b40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1901 {"maddr_q.w", "+d,+e,+f", 0x7b60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1902 {"msubr_q.h", "+d,+e,+f", 0x7b80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1903 {"msubr_q.w", "+d,+e,+f", 0x7ba0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1904 {"fclass.w", "+d,+e",    0x7b20001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1905 {"fclass.d", "+d,+e",    0x7b21001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1906 {"fsqrt.w", "+d,+e",    0x7b26001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1907 {"fsqrt.d", "+d,+e",    0x7b27001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1908 {"frsqrt.w", "+d,+e",    0x7b28001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1909 {"frsqrt.d", "+d,+e",    0x7b29001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1910 {"frcp.w",  "+d,+e",    0x7b2a001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1911 {"frcp.d",  "+d,+e",    0x7b2b001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1912 {"frint.w", "+d,+e",    0x7b2c001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1913 {"frint.d", "+d,+e",    0x7b2d001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1914 {"flog2.w", "+d,+e",    0x7b2e001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1915 {"flog2.d", "+d,+e",    0x7b2f001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1916 {"fexupl.w", "+d,+e",    0x7b30001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1917 {"fexupl.d", "+d,+e",    0x7b31001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1918 {"fexupr.w", "+d,+e",    0x7b32001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1919 {"fexupr.d", "+d,+e",    0x7b33001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1920 {"ffql.w",  "+d,+e",    0x7b34001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1921 {"ffql.d",  "+d,+e",    0x7b35001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1922 {"ffqr.w",  "+d,+e",    0x7b36001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1923 {"ffqr.d",  "+d,+e",    0x7b37001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1924 {"ftint_s.w", "+d,+e",   0x7b38001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1925 {"ftint_s.d", "+d,+e",   0x7b39001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1926 {"ftint_u.w", "+d,+e",   0x7b3a001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1927 {"ftint_u.d", "+d,+e",   0x7b3b001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1928 {"ffint_s.w", "+d,+e",   0x7b3c001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1929 {"ffint_s.d", "+d,+e",   0x7b3d001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1930 {"ffint_u.w", "+d,+e",   0x7b3e001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1931 {"ffint_u.d", "+d,+e",   0x7b3f001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1932 {"ftrunc_s.w", "+d,+e",  0x7b40001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1933 {"ftrunc_s.d", "+d,+e",  0x7b41001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1934 {"ftrunc_u.w", "+d,+e",  0x7b42001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1935 {"ftrunc_u.d", "+d,+e",  0x7b43001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1936 {"ctcmsa",  "+h,d",     0x783e0019, 0xffff003f, COD,             RD_d, MSA},
1937 {"cfcmsa",  "+i,+g",    0x787e0019, 0xffff003f, COD,                0, MSA},
1938 {"move.v",  "+d,+e",    0x78be0019, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1939 {"lsa",     "d,v,t,+@", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t,     0, MSA},
1940 {"dlsa",    "d,v,t,+@", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t,     0, MSA64},
1941
1942 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,              I4|I32|G3       },
1943 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
1944 {"nop",     "",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1      }, /* sll */
1945 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I32|N55 }, /* sll */
1946 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I33     }, /* sll */
1947 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */
1948 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
1949 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO,             0,              I1      },
1950 {"move",    "d,s",      0,    (int) M_MOVE,     INSN_MACRO,             0,              I1      },
1951 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */
1952 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */
1953 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */
1954 {"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */
1955 {"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */
1956 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/
1957
1958 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
1959 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1960 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1961 {"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1962 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1963 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
1964 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1965 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1966 {"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1967 {"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1968 {"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1969 {"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1970 {"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1971 {"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1972 {"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1973 {"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1974 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1975 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1976 {"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1977 {"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1978 {"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1979 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1980 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
1981 {"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1982 {"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
1983 {"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1984 {"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1985 {"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
1986 {"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
1987 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1988 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
1989 {"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1990 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1991 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1992 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1993 {"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1994 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1995 /* b is at the top of the table.  */
1996 /* bal is at the top of the table.  */
1997 /* bc0[tf]l? are at the bottom of the table.  */
1998 {"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1999 {"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2000 {"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2001 {"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2002 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
2003 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
2004 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
2005 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
2006 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
2007 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
2008 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
2009 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
2010 /* bc2* are at the bottom of the table.  */
2011 /* bc3* are at the bottom of the table.  */
2012 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2013 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2014 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
2015 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1      },
2016 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
2017 {"beql",    "s,I,p",    0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3   },
2018 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO,             0,              I1      },
2019 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO,             0,              I1      },
2020 {"bgel",    "s,t,p",    0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3   },
2021 {"bgel",    "s,I,p",    0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3   },
2022 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO,             0,              I1      },
2023 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO,             0,              I1      },
2024 {"bgeul",   "s,t,p",    0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3   },
2025 {"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3   },
2026 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2027 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2028 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
2029 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
2030 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO,             0,              I1      },
2031 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO,             0,              I1      },
2032 {"bgtl",    "s,t,p",    0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3   },
2033 {"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3   },
2034 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO,             0,              I1      },
2035 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO,             0,              I1      },
2036 {"bgtul",   "s,t,p",    0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3   },
2037 {"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3   },
2038 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2039 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2040 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO,             0,              I1      },
2041 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO,             0,              I1      },
2042 {"blel",    "s,t,p",    0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3   },
2043 {"blel",    "s,I,p",    0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3   },
2044 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO,             0,              I1      },
2045 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO,             0,              I1      },
2046 {"bleul",   "s,t,p",    0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3   },
2047 {"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3   },
2048 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2049 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2050 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO,             0,              I1      },
2051 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO,             0,              I1      },
2052 {"bltl",    "s,t,p",    0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3   },
2053 {"bltl",    "s,I,p",    0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3   },
2054 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO,             0,              I1      },
2055 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO,             0,              I1      },
2056 {"bltul",   "s,t,p",    0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3   },
2057 {"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3   },
2058 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2059 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2060 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
2061 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
2062 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2063 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2064 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
2065 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1      },
2066 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
2067 {"bnel",    "s,I,p",    0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3   },
2068 {"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,              I1      },
2069 {"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
2070 {"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
2071 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2072 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2073 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2074 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2075 {"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2076 {"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2077 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2078 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2079 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2080 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2081 {"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2082 {"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2083 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2084 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2085 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2086 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2087 {"c.eq.ob", "Y,Q",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2088 {"c.eq.ob", "S,T",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2089 {"c.eq.ob", "S,T[e]",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2090 {"c.eq.ob", "S,k",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2091 {"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2092 {"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2093 {"c.eq.qh", "Y,Q",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2094 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2095 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2096 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2097 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2098 {"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2099 {"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2100 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2101 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2102 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2103 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2104 {"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2105 {"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2106 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2107 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2108 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2109 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2110 {"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2111 {"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2112 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2113 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2114 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2115 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2116 {"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2117 {"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2118 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2119 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2120 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2121 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2122 {"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2123 {"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2124 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2125 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2126 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2127 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2128 {"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2129 {"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2130 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2131 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2132 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2133 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2134 {"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2135 {"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2136 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2137 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2138 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2139 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2140 {"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2141 {"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2142 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2143 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2144 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2145 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2146 {"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2147 {"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2148 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2149 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2150 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2151 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2152 {"c.lt.ob", "Y,Q",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2153 {"c.lt.ob", "S,T",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2154 {"c.lt.ob", "S,T[e]",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2155 {"c.lt.ob", "S,k",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2156 {"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2157 {"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2158 {"c.lt.qh", "Y,Q",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2159 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2160 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2161 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2162 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2163 {"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2164 {"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2165 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2166 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2167 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2168 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2169 {"c.le.ob", "Y,Q",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2170 {"c.le.ob", "S,T",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2171 {"c.le.ob", "S,T[e]",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2172 {"c.le.ob", "S,k",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2173 {"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2174 {"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2175 {"c.le.qh", "Y,Q",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2176 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2177 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2178 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2179 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2180 {"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2181 {"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2182 {"cabs.eq.d",  "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2183 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2184 {"cabs.eq.s",  "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2185 {"cabs.f.d",   "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2186 {"cabs.f.ps",  "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2187 {"cabs.f.s",   "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2188 {"cabs.le.d",  "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2189 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2190 {"cabs.le.s",  "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2191 {"cabs.lt.d",  "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2192 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2193 {"cabs.lt.s",  "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2194 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2195 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2196 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2197 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2198 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2199 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2200 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2201 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2202 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2203 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2204 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2205 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2206 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2207 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2208 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2209 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2210 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2211 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2212 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2213 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2214 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2215 {"cabs.sf.d",  "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2216 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2217 {"cabs.sf.s",  "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2218 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2219 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2220 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2221 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2222 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2223 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2224 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2225 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2226 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2227 {"cabs.un.d",  "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2228 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2229 {"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2230 /* CW4010 instructions which are aliases for the cache instruction.  */
2231 {"flushi",  "",         0xbc010000, 0xffffffff, 0,                      0,              L1      },
2232 {"flushd",  "",         0xbc020000, 0xffffffff, 0,                      0,              L1      },
2233 {"flushid", "",         0xbc030000, 0xffffffff, 0,                      0,              L1      },
2234 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,              L1      },
2235 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,              I3|I32|T3},
2236 {"cache",   "k,A(b)",   0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3|I32|T3},
2237 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2238 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2239 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2240 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2241 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
2242 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
2243 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
2244 /* cfc2 is at the bottom of the table.  */
2245 /* cfc3 is at the bottom of the table.  */
2246 {"cftc1",   "d,E",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
2247 {"cftc1",   "d,T",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
2248 {"cftc2",   "d,E",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2249 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
2250 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
2251 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2252 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
2253 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
2254 /* ctc2 is at the bottom of the table.  */
2255 /* ctc3 is at the bottom of the table.  */
2256 {"cttc1",   "t,g",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
2257 {"cttc1",   "t,S",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
2258 {"cttc2",   "t,g",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
2259 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2260 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2261 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2262 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2263 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2264 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2265 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2266 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2267 {"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
2268 {"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
2269 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2270 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2271 {"cvt.ps.pw", "D,S",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
2272 {"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5|I33  },
2273 {"cvt.pw.ps", "D,S",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
2274 {"dabs",    "d,v",      0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
2275 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2276 {"dadd",    "t,r,I",    0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
2277 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
2278 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
2279 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2280 {"daddu",   "t,r,I",    0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3      },
2281 {"dbreak",  "",         0x7000003f, 0xffffffff, 0,                      0,              N5      },
2282 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
2283 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
2284 /* dctr and dctw are used on the r5000.  */
2285 {"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   0,              I3      },
2286 {"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   0,              I3      },
2287 {"deret",   "",         0x4200001f, 0xffffffff, 0,                      0,              I32|G2  },
2288 {"dext",    "t,r,I,+I", 0,    (int) M_DEXT,     INSN_MACRO,             0,              I65     },
2289 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2290 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2291 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2292 /* For ddiv, see the comments about div.  */
2293 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2294 {"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3      },
2295 {"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3      },
2296 /* For ddivu, see the comments about div.  */
2297 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2298 {"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
2299 {"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
2300 {"di",      "",         0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
2301 {"di",      "t",        0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
2302 {"dins",    "t,r,I,+I", 0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
2303 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2304 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2305 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2306 /* The MIPS assembler treats the div opcode with two operands as
2307    though the first operand appeared twice (the first operand is both
2308    a source and a destination).  To get the div machine instruction,
2309    you must use an explicit destination of $0.  */
2310 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2311 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2312 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1      },
2313 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1      },
2314 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2315 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2316 {"div.ps",  "D,V,T",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2317 /* For divu, see the comments about div.  */
2318 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2319 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2320 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1      },
2321 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1      },
2322 {"dla",     "t,A(b)",   0,    (int) M_DLA_AB,   INSN_MACRO,             0,              I3      },
2323 {"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,  INSN_MACRO,             0,              I3      },
2324 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   0,              I3      }, /* addiu */
2325 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   0,              I3      }, /* ori */
2326 {"dli",     "t,I",      0,    (int) M_DLI,      INSN_MACRO,             0,              I3      },
2327 {"dmacc",   "d,s,t",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2328 {"dmacchi", "d,s,t",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2329 {"dmacchis", "d,s,t",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2330 {"dmacchiu", "d,s,t",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2331 {"dmacchius", "d,s,t",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2332 {"dmaccs",  "d,s,t",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2333 {"dmaccu",  "d,s,t",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2334 {"dmaccus", "d,s,t",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2335 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,              N411    },
2336 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
2337 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
2338 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
2339 {"dmt",     "",         0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
2340 {"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2341 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
2342 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
2343 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
2344 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
2345 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
2346 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
2347 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
2348 /* dmfc2 is at the bottom of the table.  */
2349 /* dmtc2 is at the bottom of the table.  */
2350 /* dmfc3 is at the bottom of the table.  */
2351 /* dmtc3 is at the bottom of the table.  */
2352 {"dmul",    "d,v,t",    0,    (int) M_DMUL,     INSN_MACRO,             0,              I3      },
2353 {"dmul",    "d,v,I",    0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3      },
2354 {"dmulo",   "d,v,t",    0,    (int) M_DMULO,    INSN_MACRO,             0,              I3      },
2355 {"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3      },
2356 {"dmulou",  "d,v,t",    0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3      },
2357 {"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3      },
2358 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2359 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2360 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
2361 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
2362 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2363 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
2364 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
2365 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2366 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
2367 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
2368 {"dret",    "",         0x7000003e, 0xffffffff, 0,                      0,              N5      },
2369 {"drol",    "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
2370 {"drol",    "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
2371 {"dror",    "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I3      },
2372 {"dror",    "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I3      },
2373 {"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
2374 {"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I65  },
2375 {"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
2376 {"drotl",   "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I65     },
2377 {"drotl",   "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I65     },
2378 {"drotr",   "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I65     },
2379 {"drotr",   "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I65     },
2380 {"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I65     },
2381 {"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              I65     },
2382 {"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,              0,              I65     },
2383 {"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,              0,              I65     },
2384 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2385 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2386 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
2387 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
2388 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2389 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2390 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2391 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
2392 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
2393 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2394 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2395 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2396 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
2397 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
2398 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2399 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2400 {"dsub",    "d,v,I",    0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
2401 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2402 {"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
2403 {"dvpe",    "",         0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
2404 {"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2405 {"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
2406 {"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
2407 {"emt",     "",         0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
2408 {"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2409 {"eret",    "",         0x42000018, 0xffffffff, 0,                      0,              I3|I32  },
2410 {"evpe",    "",         0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
2411 {"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2412 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,             0,              I33     },
2413 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2414 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2415 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2416 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2417 {"hibernate","",        0x42000023, 0xffffffff, 0,                      0,              V1      },
2418 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,             0,              I33     },
2419 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      },
2420 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
2421    the same hazard barrier effect.  */
2422 {"jr.hb",   "s",        0x00000408, 0xfc1fffff, UBD|RD_s,               0,              I32     },
2423 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      }, /* jr */
2424 /* SVR4 PIC code requires special handling for j, so it must be a
2425    macro.  */
2426 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO,             0,              I1      },
2427 /* This form of j is used by the disassembler and internally by the
2428    assembler, but will never match user input (because the line above
2429    will match first).  */
2430 {"j",       "a",        0x08000000, 0xfc000000, UBD,                    0,              I1      },
2431 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I1      },
2432 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I1      },
2433 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
2434    with the same hazard barrier effect.  */
2435 {"jalr.hb", "s",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I32     },
2436 {"jalr.hb", "d,s",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I32     },
2437 /* SVR4 PIC code requires special handling for jal, so it must be a
2438    macro.  */
2439 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO,             0,              I1      },
2440 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO,             0,              I1      },
2441 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO,             0,              I1      },
2442 /* This form of jal is used by the disassembler and internally by the
2443    assembler, but will never match user input (because the line above
2444    will match first).  */
2445 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              0,              I1      },
2446 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              0,              I16     },
2447 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1      },
2448 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2449 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1      },
2450 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2451 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1      },
2452 {"lca",     "t,A(b)",   0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1      },
2453 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,              I3      },
2454 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO,             0,              I1      },
2455 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1      },
2456 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
2457 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
2458 {"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
2459 {"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
2460 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
2461 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO,             0,              I1      },
2462 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO,             0,              I1      },
2463 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
2464 {"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
2465 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
2466 {"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2      },
2467 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
2468 {"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
2469 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
2470 {"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
2471 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
2472 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2473 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
2474 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2475 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
2476 /* li is at the start of the table.  */
2477 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO,             0,              I1      },
2478 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO,             0,              I1      },
2479 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO,             0,              I1      },
2480 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO,             0,              I1      },
2481 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      },
2482 {"ll",      "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2      },
2483 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
2484 {"lld",     "t,A(b)",   0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3      },
2485 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   0,              I1      },
2486 {"aui",     "s,t,u",    0x3c000000, 0xfc000000, RD_s|WR_t,            0, I32R6},
2487 {"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5|I33|N55},
2488 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2489 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
2490 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2491 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
2492 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
2493 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
2494 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2495 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2496 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
2497 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2498 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2499 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
2500 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2501 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1      },
2502 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2503 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
2504 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
2505 {"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2      }, /* as lwl */
2506 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2507 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
2508 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
2509 {"flush",   "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2      }, /* as lwr */
2510 {"fork",    "d,s,t",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
2511 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
2512 {"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
2513 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
2514 {"lwxs",    "d,t(b)",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
2515 {"macc",    "d,s,t",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2516 {"macc",    "d,s,t",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2517 {"maccs",   "d,s,t",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2518 {"macchi",  "d,s,t",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2519 {"macchi",  "d,s,t",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2520 {"macchis", "d,s,t",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2521 {"macchiu", "d,s,t",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2522 {"macchiu", "d,s,t",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2523 {"macchius","d,s,t",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2524 {"maccu",   "d,s,t",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2525 {"maccu",   "d,s,t",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2526 {"maccus",  "d,s,t",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2527 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
2528 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
2529 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
2530 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
2531 {"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5|I33  },
2532 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
2533 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
2534 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
2535 {"madd",    "7,s,t",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
2536 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2537 {"maddp",   "s,t",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         SMT     },
2538 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
2539 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
2540 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
2541 {"maddu",   "7,s,t",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
2542 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2543 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              N411    },
2544 {"max.ob",  "X,Y,Q",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2545 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2546 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2547 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2548 {"max.qh",  "X,Y,Q",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2549 {"mfpc",    "t,P",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
2550 {"mfps",    "t,P",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
2551 {"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2552 {"mftacx",  "d,*",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2553 {"mftc0",   "d,+t",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2554 {"mftc0",   "d,+T",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2555 {"mftc0",   "d,E,H",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2556 {"mftc1",   "d,T",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
2557 {"mftc1",   "d,E",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
2558 {"mftc2",   "d,E",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2559 {"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
2560 {"mftgpr",  "d,t",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
2561 {"mfthc1",  "d,T",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
2562 {"mfthc1",  "d,E",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
2563 {"mfthc2",  "d,E",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2564 {"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2565 {"mfthi",   "d,*",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2566 {"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2567 {"mftlo",   "d,*",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2568 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,             0,              MT32    },
2569 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
2570 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
2571 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
2572 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
2573 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
2574 {"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
2575 {"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
2576 /* mfc2 is at the bottom of the table.  */
2577 /* mfhc2 is at the bottom of the table.  */
2578 /* mfc3 is at the bottom of the table.  */
2579 {"mfdr",    "t,G",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,              N5      },
2580 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             0,              I1      },
2581 {"mfhi",    "d,9",      0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              D32     },
2582 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
2583 {"mflo",    "d,9",      0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
2584 {"mflhxu",  "d",        0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
2585 {"min.ob",  "X,Y,Q",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2586 {"min.ob",  "D,S,T",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2587 {"min.ob",  "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2588 {"min.ob",  "D,S,k",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2589 {"min.qh",  "X,Y,Q",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2590 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
2591 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2592 {"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
2593 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
2594 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
2595 {"movf.l",  "D,S,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2596 {"movf.l",  "X,Y,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2597 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
2598 {"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
2599 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
2600 {"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
2601 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
2602 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2603 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2604 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
2605 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
2606 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
2607 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
2608 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2609 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2610 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
2611 {"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
2612 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
2613 {"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
2614 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
2615 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2616 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2617 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
2618 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
2619 {"msac",    "d,s,t",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2620 {"msacu",   "d,s,t",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2621 {"msachi",  "d,s,t",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2622 {"msachiu", "d,s,t",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2623 /* move is at the top of the table.  */
2624 {"msgn.qh", "X,Y,Q",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2625 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2626 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2627 {"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2628 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
2629 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
2630 {"msub",    "7,s,t",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2631 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
2632 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
2633 {"msubu",   "7,s,t",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2634 {"mtpc",    "t,P",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
2635 {"mtps",    "t,P",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
2636 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
2637 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
2638 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
2639 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
2640 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
2641 {"mthc1",   "t,S",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
2642 {"mthc1",   "t,G",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
2643 /* mtc2 is at the bottom of the table.  */
2644 /* mthc2 is at the bottom of the table.  */
2645 /* mtc3 is at the bottom of the table.  */
2646 {"mtdr",    "t,G",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,              N5      },
2647 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,              I1      },
2648 {"mthi",    "s,7",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              D32     },
2649 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
2650 {"mtlo",    "s,7",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
2651 {"mtlhx",   "s",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
2652 {"mttc0",   "t,G",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2653 {"mttc0",   "t,+D",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2654 {"mttc0",   "t,G,H",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2655 {"mttc1",   "t,S",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
2656 {"mttc1",   "t,G",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
2657 {"mttc2",   "t,g",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
2658 {"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2659 {"mttacx",  "t,&",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2660 {"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
2661 {"mttgpr",  "t,d",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
2662 {"mtthc1",  "t,S",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
2663 {"mtthc1",  "t,G",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
2664 {"mtthc2",  "t,g",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
2665 {"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2666 {"mtthi",   "t,&",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2667 {"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2668 {"mttlo",   "t,&",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2669 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,             0,              MT32    },
2670 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2671 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2672 {"mul.ob",  "X,Y,Q",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2673 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2674 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2675 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2676 {"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2677 {"mul.qh",  "X,Y,Q",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2678 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              I32|P3|N55},
2679 {"mul",     "d,s,t",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
2680 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO,             0,              I1      },
2681 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
2682 {"mula.ob", "Y,Q",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2683 {"mula.ob", "S,T",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2684 {"mula.ob", "S,T[e]",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2685 {"mula.ob", "S,k",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2686 {"mula.qh", "Y,Q",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2687 {"mulhi",   "d,s,t",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2688 {"mulhiu",  "d,s,t",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2689 {"mull.ob", "Y,Q",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2690 {"mull.ob", "S,T",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2691 {"mull.ob", "S,T[e]",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2692 {"mull.ob", "S,k",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2693 {"mull.qh", "Y,Q",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2694 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO,             0,              I1      },
2695 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1      },
2696 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
2697 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
2698 {"mulr.ps", "D,S,T",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2699 {"muls",    "d,s,t",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2700 {"mulsu",   "d,s,t",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2701 {"mulshi",  "d,s,t",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2702 {"mulshiu", "d,s,t",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2703 {"muls.ob", "Y,Q",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2704 {"muls.ob", "S,T",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2705 {"muls.ob", "S,T[e]",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2706 {"muls.ob", "S,k",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2707 {"muls.qh", "Y,Q",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2708 {"mulsl.ob", "Y,Q",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2709 {"mulsl.ob", "S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2710 {"mulsl.ob", "S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2711 {"mulsl.ob", "S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2712 {"mulsl.qh", "Y,Q",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2713 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
2714 {"mult",    "7,s,t",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2715 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2716 {"multp",   "s,t",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
2717 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
2718 {"multu",   "7,s,t",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2719 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2720 {"mulu",    "d,s,t",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2721 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
2722 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
2723 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
2724 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2725 {"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
2726 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2727 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2728 {"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2729 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2730 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2731 {"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2732 /* nop is at the start of the table.  */
2733 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2734 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
2735 {"nor.ob",  "X,Y,Q",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2736 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2737 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2738 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2739 {"nor.qh",  "X,Y,Q",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2740 {"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
2741 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2742 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
2743 {"or.ob",   "X,Y,Q",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2744 {"or.ob",   "D,S,T",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2745 {"or.ob",   "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2746 {"or.ob",   "D,S,k",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2747 {"or.qh",   "X,Y,Q",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2748 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2749 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2750 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
2751 {"pavg.ob", "X,Y,Q",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2752 {"pickf.ob", "X,Y,Q",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2753 {"pickf.ob", "D,S,T",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2754 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2755 {"pickf.ob", "D,S,k",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2756 {"pickf.qh", "X,Y,Q",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2757 {"pickt.ob", "X,Y,Q",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2758 {"pickt.ob", "D,S,T",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2759 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2760 {"pickt.ob", "D,S,k",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2761 {"pickt.qh", "X,Y,Q",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2762 {"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2763 {"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2764   /* pref and prefx are at the start of the table.  */
2765 {"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2766 {"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2767 {"pperm",   "s,t",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
2768 {"rach.ob", "X",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2769 {"rach.ob", "D",        0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
2770 {"rach.qh", "X",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2771 {"racl.ob", "X",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2772 {"racl.ob", "D",        0x4800003f, 0xfffff83f, WR_D,                   0,              N54     },
2773 {"racl.qh", "X",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2774 {"racm.ob", "X",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2775 {"racm.ob", "D",        0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
2776 {"racm.qh", "X",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2777 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2778 {"recip.ps","D,S",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2779 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2780 {"recip1.d",  "D,S",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2781 {"recip1.ps", "D,S",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2782 {"recip1.s",  "D,S",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2783 {"recip2.d",  "D,S,T",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2784 {"recip2.ps", "D,S,T",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2785 {"recip2.s",  "D,S,T",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2786 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2787 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO,             0,              I1      },
2788 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1      },
2789 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2790 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1      },
2791 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1      },
2792 {"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,                   0,              I33     },
2793 {"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,                   0,              I33     },
2794 {"rfe",     "",         0x42000010, 0xffffffff, 0,                      0,              I1|T3   },
2795 {"rnas.qh", "X,Q",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2796 {"rnau.ob", "X,Q",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2797 {"rnau.qh", "X,Q",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2798 {"rnes.qh", "X,Q",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2799 {"rneu.ob", "X,Q",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2800 {"rneu.qh", "X,Q",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2801 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I1      },
2802 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1      },
2803 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I1      },
2804 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1      },
2805 {"ror",     "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33|SMT },
2806 {"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33|SMT },
2807 {"rotl",    "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I33|SMT },
2808 {"rotl",    "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|SMT },
2809 {"rotr",    "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
2810 {"rotr",    "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
2811 {"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
2812 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2813 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2814 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2815 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2816 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2817 {"rsqrt.ps","D,S",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2818 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2819 {"rsqrt1.d",  "D,S",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2820 {"rsqrt1.ps", "D,S",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2821 {"rsqrt1.s",  "D,S",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2822 {"rsqrt2.d",  "D,S,T",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2823 {"rsqrt2.ps", "D,S,T",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2824 {"rsqrt2.s",  "D,S,T",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2825 {"rzs.qh",  "X,Q",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2826 {"rzu.ob",  "X,Q",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2827 {"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,              N54     },
2828 {"rzu.qh",  "X,Q",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2829 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2830 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1      },
2831 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2      },
2832 {"sc",      "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2      },
2833 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3      },
2834 {"scd",     "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3      },
2835 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2836 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO,             0,              I1      },
2837 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1      },
2838 {"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   0,              G2      },
2839 {"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   0,              G2      },
2840 {"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   0,              G2      },
2841 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,              I32     },
2842 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,              I32     },
2843 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2844 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2845 {"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2846 {"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2847 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
2848 {"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
2849 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
2850 {"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
2851 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2852 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO,             0,              I1      },
2853 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO,             0,              I1      },
2854 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2855 {"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
2856 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2857 {"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
2858 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,              I4|I33  },
2859 {"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2860 {"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2861 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2862 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2863 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
2864 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
2865 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
2866 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
2867 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
2868 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO,             0,              I1      },
2869 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO,             0,              I1      },
2870 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO,             0,              I1      },
2871 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO,             0,              I1      },
2872 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO,             0,              I1      },
2873 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2874 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO,             0,              I1      },
2875 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2876 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2877 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2878 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2879 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2880 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2881 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2882 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2883 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2884 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2885 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2886 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2887 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2888 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2889 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
2890 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
2891 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
2892 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
2893 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2894 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
2895 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2896 {"sll.ob",  "X,Y,Q",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2897 {"sll.ob",  "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2898 {"sll.ob",  "D,S,k",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2899 {"sll.qh",  "X,Y,Q",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2900 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2901 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
2902 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2903 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2904 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2905 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
2906 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
2907 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
2908 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
2909 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2910 {"sqrt.ps", "D,S",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2911 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2912 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
2913 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2914 {"sra.qh",  "X,Y,Q",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2915 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2916 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
2917 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2918 {"srl.ob",  "X,Y,Q",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2919 {"srl.ob",  "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2920 {"srl.ob",  "D,S,k",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2921 {"srl.qh",  "X,Y,Q",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2922 /* ssnop is at the start of the table.  */
2923 {"standby", "",         0x42000021, 0xffffffff, 0,                      0,              V1      },
2924 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2925 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
2926 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2927 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2928 {"sub.ob",  "X,Y,Q",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2929 {"sub.ob",  "D,S,T",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2930 {"sub.ob",  "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2931 {"sub.ob",  "D,S,k",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2932 {"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2933 {"sub.qh",  "X,Y,Q",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2934 {"suba.ob", "Y,Q",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2935 {"suba.qh", "Y,Q",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2936 {"subl.ob", "Y,Q",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2937 {"subl.qh", "Y,Q",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2938 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2939 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
2940 {"suspend", "",         0x42000022, 0xffffffff, 0,                      0,              V1      },
2941 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      0,              I5|I33|N55},
2942 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2943 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1      },
2944 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
2945 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
2946 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2947 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2948 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2949 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2950 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
2951 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2952 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
2953 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
2954 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
2955 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1      },
2956 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2957 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
2958 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2959 {"scache",  "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2      }, /* as swl */
2960 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2961 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
2962 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2963 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2      }, /* as swr */
2964 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0,              I4|I33  },
2965 {"sync",    "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
2966 {"sync.p",  "",         0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
2967 {"sync.l",  "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
2968 {"synci",   "o(b)",     0x041f0000, 0xfc1f0000, SM|RD_b,                0,              I33     },
2969 {"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   0,              I1      },
2970 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   0,              I1      },
2971 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2972 {"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2973 {"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2974 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* teqi */
2975 {"teq",     "s,I",      0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2      },
2976 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2977 {"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2978 {"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2979 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgei */
2980 {"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2      },
2981 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2982 {"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2983 {"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2984 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
2985 {"tgeu",    "s,I",      0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },
2986 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,              I1      },
2987 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,              I1      },
2988 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,              I1      },
2989 {"tlbinv",  "",         0x42000003, 0xffffffff, INSN_TLB,             0, I32  },
2990 {"tlbinvf", "",         0x42000004, 0xffffffff, INSN_TLB,             0, I32  },
2991 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,              I1      },
2992 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2993 {"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2994 {"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2995 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tlti */
2996 {"tlt",     "s,I",      0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2      },
2997 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2998 {"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2999 {"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
3000 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tltiu */
3001 {"tltu",    "s,I",      0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2      },
3002 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
3003 {"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
3004 {"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
3005 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
3006 {"tne",     "s,I",      0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
3007 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
3008 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
3009 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
3010 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
3011 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
3012 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
3013 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
3014 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO,             0,              I1      },
3015 {"uld",     "t,o(b)",   0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
3016 {"uld",     "t,A(b)",   0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
3017 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
3018 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO,             0,              I1      },
3019 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO,             0,              I1      },
3020 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO,             0,              I1      },
3021 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO,             0,              I1      },
3022 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO,             0,              I1      },
3023 {"usd",     "t,o(b)",   0,    (int) M_USD,      INSN_MACRO,             0,              I3      },
3024 {"usd",     "t,A(b)",   0,    (int) M_USD_A,    INSN_MACRO,             0,              I3      },
3025 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO,             0,              I1      },
3026 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO,             0,              I1      },
3027 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO,             0,              I1      },
3028 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO,             0,              I1      },
3029 {"wach.ob", "Y",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
3030 {"wach.ob", "S",        0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
3031 {"wach.qh", "Y",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
3032 {"wacl.ob", "Y,Z",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
3033 {"wacl.ob", "S,T",      0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
3034 {"wacl.qh", "Y,Z",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
3035 {"wait",    "",         0x42000020, 0xffffffff, TRAP,                   0,              I3|I32  },
3036 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   0,              I32|N55 },
3037 {"waiti",   "",         0x42000020, 0xffffffff, TRAP,                   0,              L1      },
3038 {"wrpgpr",  "d,w",      0x41c00000, 0xffe007ff, RD_t,                   0,              I33     },
3039 {"wsbh",    "d,w",      0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
3040 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
3041 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
3042 {"xor.ob",  "X,Y,Q",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
3043 {"xor.ob",  "D,S,T",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
3044 {"xor.ob",  "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
3045 {"xor.ob",  "D,S,k",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
3046 {"xor.qh",  "X,Y,Q",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
3047 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
3048 {"yield",   "s",        0x7c000009, 0xfc1fffff, TRAP|RD_s,              0,              MT32    },
3049 {"yield",   "d,s",      0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,         0,              MT32    },
3050
3051 /* User Defined Instruction.  */
3052 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3053 {"udi0",     "s,t,+2",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3054 {"udi0",     "s,+3",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3055 {"udi0",     "+4",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3056 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3057 {"udi1",     "s,t,+2",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3058 {"udi1",     "s,+3",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3059 {"udi1",     "+4",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3060 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3061 {"udi2",     "s,t,+2",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3062 {"udi2",     "s,+3",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3063 {"udi2",     "+4",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3064 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3065 {"udi3",     "s,t,+2",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3066 {"udi3",     "s,+3",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3067 {"udi3",     "+4",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3068 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3069 {"udi4",     "s,t,+2",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3070 {"udi4",     "s,+3",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3071 {"udi4",     "+4",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3072 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3073 {"udi5",     "s,t,+2",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3074 {"udi5",     "s,+3",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3075 {"udi5",     "+4",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3076 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3077 {"udi6",     "s,t,+2",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3078 {"udi6",     "s,+3",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3079 {"udi6",     "+4",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3080 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3081 {"udi7",     "s,t,+2",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3082 {"udi7",     "s,+3",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3083 {"udi7",     "+4",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3084 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3085 {"udi8",     "s,t,+2",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3086 {"udi8",     "s,+3",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3087 {"udi8",     "+4",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3088 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3089 {"udi9",      "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3090 {"udi9",     "s,+3",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3091 {"udi9",     "+4",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3092 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3093 {"udi10",    "s,t,+2",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3094 {"udi10",    "s,+3",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3095 {"udi10",    "+4",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3096 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3097 {"udi11",    "s,t,+2",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3098 {"udi11",    "s,+3",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3099 {"udi11",    "+4",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3100 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3101 {"udi12",    "s,t,+2",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3102 {"udi12",    "s,+3",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3103 {"udi12",    "+4",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3104 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3105 {"udi13",    "s,t,+2",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3106 {"udi13",    "s,+3",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3107 {"udi13",    "+4",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3108 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3109 {"udi14",    "s,t,+2",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3110 {"udi14",    "s,+3",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3111 {"udi14",    "+4",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3112 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3113 {"udi15",    "s,t,+2",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3114 {"udi15",    "s,+3",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3115 {"udi15",    "+4",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3116
3117 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
3118    instructions so they are here for the latters to take precedence.  */
3119 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3120 {"bc2f",    "N,p",      0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32     },
3121 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3122 {"bc2fl",   "N,p",      0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32     },
3123 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3124 {"bc2t",    "N,p",      0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32     },
3125 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3126 {"bc2tl",   "N,p",      0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
3127 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
3128 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
3129 {"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
3130 {"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
3131 {"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
3132 {"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
3133 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
3134 {"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
3135 {"mfhc2",   "t,G",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
3136 {"mfhc2",   "t,G,H",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33     },
3137 {"mfhc2",   "t,i",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33     },
3138 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1      },
3139 {"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32     },
3140 {"mthc2",   "t,G",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3141 {"mthc2",   "t,G,H",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3142 {"mthc2",   "t,i",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3143
3144 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
3145    instructions, so they are here for the latters to take precedence.  */
3146 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3147 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3148 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3149 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3150 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
3151 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
3152 {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3      },
3153 {"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3      },
3154 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
3155 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32     },
3156 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
3157 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32     },
3158
3159 /* No hazard protection on coprocessor instructions--they shouldn't
3160    change the state of the processor and if they do it's up to the
3161    user to put in nops as necessary.  These are at the end so that the
3162    disassembler recognizes more specific versions first.  */
3163 {"c0",      "C",        0x42000000, 0xfe000000, 0,                      0,              I1      },
3164 {"c1",      "C",        0x46000000, 0xfe000000, 0,                      0,              I1      },
3165 {"c2",      "C",        0x4a000000, 0xfe000000, 0,                      0,              I1      },
3166 {"c3",      "C",        0x4e000000, 0xfe000000, 0,                      0,              I1      },
3167 {"cop0",     "C",       0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
3168 {"cop1",     "C",       0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
3169 {"cop2",     "C",       0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
3170 {"cop3",     "C",       0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
3171   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
3172      4010 any more, so move this insn out of the way.  If the object
3173      format gave us more info, we could do this right.  */
3174 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              0,              L1      },
3175 /* MIPS DSP ASE */
3176 {"absq_s.ph", "d,t",    0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3177 {"absq_s.pw", "d,t",    0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3178 {"absq_s.qh", "d,t",    0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3179 {"absq_s.w", "d,t",     0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3180 {"addq.ph", "d,s,t",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3181 {"addq.pw", "d,s,t",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3182 {"addq.qh", "d,s,t",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3183 {"addq_s.ph", "d,s,t",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3184 {"addq_s.pw", "d,s,t",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3185 {"addq_s.qh", "d,s,t",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3186 {"addq_s.w", "d,s,t",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3187 {"addsc",   "d,s,t",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3188 {"addu.ob", "d,s,t",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3189 {"addu.qb", "d,s,t",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3190 {"addu_s.ob", "d,s,t",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3191 {"addu_s.qb", "d,s,t",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3192 {"addwc",   "d,s,t",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3193 {"bitrev",  "d,t",      0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3194 {"bposge32", "p",       0x041c0000, 0xffff0000, CBD,                    0,              D32     },
3195 {"bposge64", "p",       0x041d0000, 0xffff0000, CBD,                    0,              D64     },
3196 {"cmp.eq.ph", "s,t",    0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3197 {"cmp.eq.pw", "s,t",    0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3198 {"cmp.eq.qh", "s,t",    0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3199 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3200 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3201 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3202 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3203 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3204 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3205 {"cmp.le.ph", "s,t",    0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3206 {"cmp.le.pw", "s,t",    0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3207 {"cmp.le.qh", "s,t",    0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3208 {"cmp.lt.ph", "s,t",    0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3209 {"cmp.lt.pw", "s,t",    0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3210 {"cmp.lt.qh", "s,t",    0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3211 {"cmpu.eq.ob", "s,t",   0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3212 {"cmpu.eq.qb", "s,t",   0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3213 {"cmpu.le.ob", "s,t",   0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3214 {"cmpu.le.qb", "s,t",   0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3215 {"cmpu.lt.ob", "s,t",   0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3216 {"cmpu.lt.qb", "s,t",   0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3217 {"dextpdp", "t,7,6",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D64     },
3218 {"dextpdpv", "t,7,s",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D64     },
3219 {"dextp",   "t,7,6",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3220 {"dextpv",  "t,7,s",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3221 {"dextr.l", "t,7,6",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3222 {"dextr_r.l", "t,7,6",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3223 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3224 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3225 {"dextr_r.w", "t,7,6",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3226 {"dextr_s.h", "t,7,6",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3227 {"dextrv.l", "t,7,s",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3228 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3229 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
3230 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
3231 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3232 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3233 {"dextrv.w", "t,7,s",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3234 {"dextr.w", "t,7,6",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3235 {"dinsv",   "t,s",      0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              D64     },
3236 {"dmadd",   "7,s,t",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3237 {"dmaddu",  "7,s,t",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3238 {"dmsub",   "7,s,t",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3239 {"dmsubu",  "7,s,t",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3240 {"dmthlip", "s,7",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D64     },
3241 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3242 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3243 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3244 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3245 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3246 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3247 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3248 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3249 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3250 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3251 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3252 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3253 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3254 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3255 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3256 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3257 {"dshilo",  "7,:",      0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              D64     },
3258 {"dshilov", "7,s",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              D64     },
3259 {"extpdp",  "t,7,6",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
3260 {"extpdpv", "t,7,s",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
3261 {"extp",    "t,7,6",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3262 {"extpv",   "t,7,s",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3263 {"extr_rs.w", "t,7,6",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3264 {"extr_r.w", "t,7,6",   0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3265 {"extr_s.h", "t,7,6",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3266 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3267 {"extrv_r.w", "t,7,s",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3268 {"extrv_s.h", "t,7,s",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3269 {"extrv.w", "t,7,s",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3270 {"extr.w",  "t,7,6",    0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3271 {"insv",    "t,s",      0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
3272 {"lbux",    "d,t(b)",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3273 {"ldx",     "d,t(b)",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D64     },
3274 {"lhx",     "d,t(b)",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3275 {"lwx",     "d,t(b)",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3276 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
3277 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
3278 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3279 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3280 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3281 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3282 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3283 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3284 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3285 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3286 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3287 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3288 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3289 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3290 {"modsub",  "d,s,t",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3291 {"mthlip",  "s,7",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
3292 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3293 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3294 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
3295 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
3296 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
3297 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
3298 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3299 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3300 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
3301 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D64     },
3302 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3303 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
3304 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3305 {"packrl.ph", "d,s,t",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3306 {"packrl.pw", "d,s,t",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3307 {"pick.ob", "d,s,t",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3308 {"pick.ph", "d,s,t",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3309 {"pick.pw", "d,s,t",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3310 {"pick.qb", "d,s,t",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3311 {"pick.qh", "d,s,t",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3312 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3313 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3314 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3315 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3316 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3317 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3318 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,           0,              D32     },
3319 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3320 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,           0,              D32     },
3321 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3322 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,           0,              D64     },
3323 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3324 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
3325 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3326 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3327 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3328 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3329 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,             0,              D32     },
3330 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3331 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,             0,              D32     },
3332 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3333 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3334 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3335 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3336 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
3337 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3338 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3339 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
3340 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
3341 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,     0,              D32     },
3342 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
3343 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
3344 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
3345 {"raddu.l.ob", "d,s",   0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              D64     },
3346 {"raddu.w.qb", "d,s",   0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              D32     },
3347 {"rddsp",   "d",        0x7fff04b8, 0xffff07ff, WR_d,                   0,              D32     },
3348 {"rddsp",   "d,'",      0x7c0004b8, 0xffc007ff, WR_d,                   0,              D32     },
3349 {"repl.ob", "d,5",      0x7c000096, 0xff0007ff, WR_d,                   0,              D64     },
3350 {"repl.ph", "d,@",      0x7c000292, 0xfc0007ff, WR_d,                   0,              D32     },
3351 {"repl.pw", "d,@",      0x7c000496, 0xfc0007ff, WR_d,                   0,              D64     },
3352 {"repl.qb", "d,5",      0x7c000092, 0xff0007ff, WR_d,                   0,              D32     },
3353 {"repl.qh", "d,@",      0x7c000296, 0xfc0007ff, WR_d,                   0,              D64     },
3354 {"replv.ob", "d,t",     0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3355 {"replv.ph", "d,t",     0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3356 {"replv.pw", "d,t",     0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3357 {"replv.qb", "d,t",     0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3358 {"replv.qh", "d,t",     0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3359 {"shilo",   "7,0",      0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              D32     },
3360 {"shilov",  "7,s",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              D32     },
3361 {"shll.ob", "d,t,3",    0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              D64     },
3362 {"shll.ph", "d,t,4",    0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3363 {"shll.pw", "d,t,6",    0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3364 {"shll.qb", "d,t,3",    0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              D32     },
3365 {"shll.qh", "d,t,4",    0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3366 {"shll_s.ph", "d,t,4",  0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3367 {"shll_s.pw", "d,t,6",  0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3368 {"shll_s.qh", "d,t,4",  0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3369 {"shll_s.w", "d,t,6",   0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
3370 {"shllv.ob", "d,t,s",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3371 {"shllv.ph", "d,t,s",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3372 {"shllv.pw", "d,t,s",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3373 {"shllv.qb", "d,t,s",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3374 {"shllv.qh", "d,t,s",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3375 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3376 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3377 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3378 {"shllv_s.w", "d,t,s",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3379 {"shra.ph", "d,t,4",    0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3380 {"shra.pw", "d,t,6",    0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3381 {"shra.qh", "d,t,4",    0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3382 {"shra_r.ph", "d,t,4",  0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3383 {"shra_r.pw", "d,t,6",  0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3384 {"shra_r.qh", "d,t,4",  0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3385 {"shra_r.w", "d,t,6",   0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
3386 {"shrav.ph", "d,t,s",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3387 {"shrav.pw", "d,t,s",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3388 {"shrav.qh", "d,t,s",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3389 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3390 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3391 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3392 {"shrav_r.w", "d,t,s",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3393 {"shrl.ob", "d,t,3",    0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              D64     },
3394 {"shrl.qb", "d,t,3",    0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              D32     },
3395 {"shrlv.ob", "d,t,s",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3396 {"shrlv.qb", "d,t,s",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3397 {"subq.ph", "d,s,t",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3398 {"subq.pw", "d,s,t",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3399 {"subq.qh", "d,s,t",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3400 {"subq_s.ph", "d,s,t",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3401 {"subq_s.pw", "d,s,t",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3402 {"subq_s.qh", "d,s,t",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3403 {"subq_s.w", "d,s,t",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3404 {"subu.ob", "d,s,t",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3405 {"subu.qb", "d,s,t",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3406 {"subu_s.ob", "d,s,t",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3407 {"subu_s.qb", "d,s,t",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3408 {"wrdsp",   "s",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              D32     },
3409 {"wrdsp",   "s,8",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              D32     },
3410 /* MIPS DSP ASE Rev2 */
3411 {"absq_s.qb", "d,t",    0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33     },
3412 {"addu.ph", "d,s,t",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3413 {"addu_s.ph", "d,s,t",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3414 {"adduh.qb", "d,s,t",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3415 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3416 {"append",  "t,s,h",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
3417 {"balign",  "t,s,I",    0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
3418 {"balign",  "t,s,2",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33     },
3419 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3420 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3421 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3422 {"dpa.w.ph", "7,s,t",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3423 {"dps.w.ph", "7,s,t",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3424 {"mul.ph",  "d,s,t",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3425 {"mul_s.ph", "d,s,t",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3426 {"mulq_rs.w", "d,s,t",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3427 {"mulq_s.ph", "d,s,t",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3428 {"mulq_s.w", "d,s,t",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3429 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3430 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33     },
3431 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33     },
3432 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33     },
3433 {"prepend", "t,s,h",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
3434 {"shra.qb", "d,t,3",    0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33     },
3435 {"shra_r.qb", "d,t,3",  0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33     },
3436 {"shrav.qb", "d,t,s",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3437 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3438 {"shrl.ph", "d,t,4",    0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33     },
3439 {"shrlv.ph", "d,t,s",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3440 {"subu.ph", "d,s,t",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3441 {"subu_s.ph", "d,s,t",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3442 {"subuh.qb", "d,s,t",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3443 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3444 {"addqh.ph", "d,s,t",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3445 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3446 {"addqh.w", "d,s,t",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3447 {"addqh_r.w", "d,s,t",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3448 {"subqh.ph", "d,s,t",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3449 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3450 {"subqh.w", "d,s,t",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3451 {"subqh_r.w", "d,s,t",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3452 {"dpax.w.ph", "7,s,t",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3453 {"dpsx.w.ph", "7,s,t",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3454 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
3455 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
3456 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
3457 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
3458 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
3459 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3460 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3461 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3462 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3463 /* ST Microelectronics Loongson-2E and -2F.  */
3464 {"mult.g",      "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3465 {"mult.g",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3466 {"multu.g",     "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3467 {"multu.g",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3468 {"dmult.g",     "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3469 {"dmult.g",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3470 {"dmultu.g",    "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3471 {"dmultu.g",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3472 {"div.g",       "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3473 {"div.g",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3474 {"divu.g",      "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3475 {"divu.g",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3476 {"ddiv.g",      "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3477 {"ddiv.g",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3478 {"ddivu.g",     "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3479 {"ddivu.g",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3480 {"mod.g",       "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3481 {"mod.g",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3482 {"modu.g",      "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3483 {"modu.g",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3484 {"dmod.g",      "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3485 {"dmod.g",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3486 {"dmodu.g",     "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3487 {"dmodu.g",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3488 };
3489
3490 #define MIPS_NUM_OPCODES \
3491         ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
3492 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
3493
3494 /* const removed from the following to allow for dynamic extensions to the
3495  * built-in instruction set. */
3496 struct mips_opcode *mips_opcodes =
3497   (struct mips_opcode *) mips_builtin_opcodes;
3498 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
3499 #undef MIPS_NUM_OPCODES
3500
3501 /* Mips instructions are at maximum this many bytes long.  */
3502 #define INSNLEN 4
3503
3504 \f
3505 /* FIXME: These should be shared with gdb somehow.  */
3506
3507 struct mips_cp0sel_name
3508 {
3509   unsigned int cp0reg;
3510   unsigned int sel;
3511   const char * const name;
3512 };
3513
3514 #if 0
3515 /* The mips16 registers.  */
3516 static const unsigned int mips16_to_32_reg_map[] =
3517 {
3518   16, 17, 2, 3, 4, 5, 6, 7
3519 };
3520
3521 #define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
3522 #endif
3523
3524 static const char * const mips_gpr_names_numeric[32] =
3525 {
3526   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3527   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3528   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3529   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3530 };
3531
3532 static const char * const mips_gpr_names_oldabi[32] =
3533 {
3534   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
3535   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
3536   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
3537   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
3538 };
3539
3540 static const char * const mips_gpr_names_newabi[32] =
3541 {
3542   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
3543   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
3544   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
3545   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
3546 };
3547
3548 static const char * const mips_fpr_names_numeric[32] =
3549 {
3550   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
3551   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
3552   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
3553   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
3554 };
3555
3556 static const char * const mips_fpr_names_32[32] =
3557 {
3558   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
3559   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
3560   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
3561   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
3562 };
3563
3564 static const char * const mips_fpr_names_n32[32] =
3565 {
3566   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
3567   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
3568   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
3569   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
3570 };
3571
3572 static const char * const mips_fpr_names_64[32] =
3573 {
3574   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
3575   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
3576   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
3577   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
3578 };
3579
3580 static const char * const mips_wr_names[32] = {
3581   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",
3582   "w8",  "w9",  "w10", "w11", "w12", "w13", "w14", "w15",
3583   "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3584   "w24", "w25", "w26", "w27", "w28", "w29", "w30", "w31"
3585 };
3586
3587 static const char * const mips_cp0_names_numeric[32] =
3588 {
3589   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3590   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3591   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3592   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3593 };
3594
3595 static const char * const mips_cp0_names_mips3264[32] =
3596 {
3597   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3598   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3599   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3600   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3601   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3602   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3603   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
3604   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
3605 };
3606
3607 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
3608 {
3609   {  4, 1, "c0_contextconfig"   },
3610   {  0, 1, "c0_mvpcontrol"      },
3611   {  0, 2, "c0_mvpconf0"        },
3612   {  0, 3, "c0_mvpconf1"        },
3613   {  1, 1, "c0_vpecontrol"      },
3614   {  1, 2, "c0_vpeconf0"        },
3615   {  1, 3, "c0_vpeconf1"        },
3616   {  1, 4, "c0_yqmask"          },
3617   {  1, 5, "c0_vpeschedule"     },
3618   {  1, 6, "c0_vpeschefback"    },
3619   {  2, 1, "c0_tcstatus"        },
3620   {  2, 2, "c0_tcbind"          },
3621   {  2, 3, "c0_tcrestart"       },
3622   {  2, 4, "c0_tchalt"          },
3623   {  2, 5, "c0_tccontext"       },
3624   {  2, 6, "c0_tcschedule"      },
3625   {  2, 7, "c0_tcschefback"     },
3626   {  5, 1, "c0_pagegrain"       },
3627   {  6, 1, "c0_srsconf0"        },
3628   {  6, 2, "c0_srsconf1"        },
3629   {  6, 3, "c0_srsconf2"        },
3630   {  6, 4, "c0_srsconf3"        },
3631   {  6, 5, "c0_srsconf4"        },
3632   { 12, 1, "c0_intctl"          },
3633   { 12, 2, "c0_srsctl"          },
3634   { 12, 3, "c0_srsmap"          },
3635   { 15, 1, "c0_ebase"           },
3636   { 16, 1, "c0_config1"         },
3637   { 16, 2, "c0_config2"         },
3638   { 16, 3, "c0_config3"         },
3639   { 18, 1, "c0_watchlo,1"       },
3640   { 18, 2, "c0_watchlo,2"       },
3641   { 18, 3, "c0_watchlo,3"       },
3642   { 18, 4, "c0_watchlo,4"       },
3643   { 18, 5, "c0_watchlo,5"       },
3644   { 18, 6, "c0_watchlo,6"       },
3645   { 18, 7, "c0_watchlo,7"       },
3646   { 19, 1, "c0_watchhi,1"       },
3647   { 19, 2, "c0_watchhi,2"       },
3648   { 19, 3, "c0_watchhi,3"       },
3649   { 19, 4, "c0_watchhi,4"       },
3650   { 19, 5, "c0_watchhi,5"       },
3651   { 19, 6, "c0_watchhi,6"       },
3652   { 19, 7, "c0_watchhi,7"       },
3653   { 23, 1, "c0_tracecontrol"    },
3654   { 23, 2, "c0_tracecontrol2"   },
3655   { 23, 3, "c0_usertracedata"   },
3656   { 23, 4, "c0_tracebpc"        },
3657   { 25, 1, "c0_perfcnt,1"       },
3658   { 25, 2, "c0_perfcnt,2"       },
3659   { 25, 3, "c0_perfcnt,3"       },
3660   { 25, 4, "c0_perfcnt,4"       },
3661   { 25, 5, "c0_perfcnt,5"       },
3662   { 25, 6, "c0_perfcnt,6"       },
3663   { 25, 7, "c0_perfcnt,7"       },
3664   { 27, 1, "c0_cacheerr,1"      },
3665   { 27, 2, "c0_cacheerr,2"      },
3666   { 27, 3, "c0_cacheerr,3"      },
3667   { 28, 1, "c0_datalo"          },
3668   { 28, 2, "c0_taglo1"          },
3669   { 28, 3, "c0_datalo1"         },
3670   { 28, 4, "c0_taglo2"          },
3671   { 28, 5, "c0_datalo2"         },
3672   { 28, 6, "c0_taglo3"          },
3673   { 28, 7, "c0_datalo3"         },
3674   { 29, 1, "c0_datahi"          },
3675   { 29, 2, "c0_taghi1"          },
3676   { 29, 3, "c0_datahi1"         },
3677   { 29, 4, "c0_taghi2"          },
3678   { 29, 5, "c0_datahi2"         },
3679   { 29, 6, "c0_taghi3"          },
3680   { 29, 7, "c0_datahi3"         },
3681 };
3682
3683 static const char * const mips_cp0_names_mips3264r2[32] =
3684 {
3685   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3686   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
3687   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3688   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3689   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3690   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3691   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
3692   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
3693 };
3694
3695 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
3696 {
3697   {  4, 1, "c0_contextconfig"   },
3698   {  5, 1, "c0_pagegrain"       },
3699   { 12, 1, "c0_intctl"          },
3700   { 12, 2, "c0_srsctl"          },
3701   { 12, 3, "c0_srsmap"          },
3702   { 15, 1, "c0_ebase"           },
3703   { 16, 1, "c0_config1"         },
3704   { 16, 2, "c0_config2"         },
3705   { 16, 3, "c0_config3"         },
3706   { 18, 1, "c0_watchlo,1"       },
3707   { 18, 2, "c0_watchlo,2"       },
3708   { 18, 3, "c0_watchlo,3"       },
3709   { 18, 4, "c0_watchlo,4"       },
3710   { 18, 5, "c0_watchlo,5"       },
3711   { 18, 6, "c0_watchlo,6"       },
3712   { 18, 7, "c0_watchlo,7"       },
3713   { 19, 1, "c0_watchhi,1"       },
3714   { 19, 2, "c0_watchhi,2"       },
3715   { 19, 3, "c0_watchhi,3"       },
3716   { 19, 4, "c0_watchhi,4"       },
3717   { 19, 5, "c0_watchhi,5"       },
3718   { 19, 6, "c0_watchhi,6"       },
3719   { 19, 7, "c0_watchhi,7"       },
3720   { 23, 1, "c0_tracecontrol"    },
3721   { 23, 2, "c0_tracecontrol2"   },
3722   { 23, 3, "c0_usertracedata"   },
3723   { 23, 4, "c0_tracebpc"        },
3724   { 25, 1, "c0_perfcnt,1"       },
3725   { 25, 2, "c0_perfcnt,2"       },
3726   { 25, 3, "c0_perfcnt,3"       },
3727   { 25, 4, "c0_perfcnt,4"       },
3728   { 25, 5, "c0_perfcnt,5"       },
3729   { 25, 6, "c0_perfcnt,6"       },
3730   { 25, 7, "c0_perfcnt,7"       },
3731   { 27, 1, "c0_cacheerr,1"      },
3732   { 27, 2, "c0_cacheerr,2"      },
3733   { 27, 3, "c0_cacheerr,3"      },
3734   { 28, 1, "c0_datalo"          },
3735   { 28, 2, "c0_taglo1"          },
3736   { 28, 3, "c0_datalo1"         },
3737   { 28, 4, "c0_taglo2"          },
3738   { 28, 5, "c0_datalo2"         },
3739   { 28, 6, "c0_taglo3"          },
3740   { 28, 7, "c0_datalo3"         },
3741   { 29, 1, "c0_datahi"          },
3742   { 29, 2, "c0_taghi1"          },
3743   { 29, 3, "c0_datahi1"         },
3744   { 29, 4, "c0_taghi2"          },
3745   { 29, 5, "c0_datahi2"         },
3746   { 29, 6, "c0_taghi3"          },
3747   { 29, 7, "c0_datahi3"         },
3748 };
3749
3750 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
3751 static const char * const mips_cp0_names_sb1[32] =
3752 {
3753   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3754   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3755   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3756   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3757   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3758   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3759   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
3760   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
3761 };
3762
3763 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3764 {
3765   { 16, 1, "c0_config1"         },
3766   { 18, 1, "c0_watchlo,1"       },
3767   { 19, 1, "c0_watchhi,1"       },
3768   { 22, 0, "c0_perftrace"       },
3769   { 23, 3, "c0_edebug"          },
3770   { 25, 1, "c0_perfcnt,1"       },
3771   { 25, 2, "c0_perfcnt,2"       },
3772   { 25, 3, "c0_perfcnt,3"       },
3773   { 25, 4, "c0_perfcnt,4"       },
3774   { 25, 5, "c0_perfcnt,5"       },
3775   { 25, 6, "c0_perfcnt,6"       },
3776   { 25, 7, "c0_perfcnt,7"       },
3777   { 26, 1, "c0_buserr_pa"       },
3778   { 27, 1, "c0_cacheerr_d"      },
3779   { 27, 3, "c0_cacheerr_d_pa"   },
3780   { 28, 1, "c0_datalo_i"        },
3781   { 28, 2, "c0_taglo_d"         },
3782   { 28, 3, "c0_datalo_d"        },
3783   { 29, 1, "c0_datahi_i"        },
3784   { 29, 2, "c0_taghi_d"         },
3785   { 29, 3, "c0_datahi_d"        },
3786 };
3787
3788 static const char * const mips_hwr_names_numeric[32] =
3789 {
3790   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3791   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3792   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3793   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3794 };
3795
3796 static const char * const mips_hwr_names_mips3264r2[32] =
3797 {
3798   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
3799   "$4",          "$5",            "$6",           "$7",
3800   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3801   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3802   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3803 };
3804
3805 static const char * const mips_msa_control_names_mips3264r2[32] = {
3806   "MSAIR", "MSACSR", "$2", "$3",  "$4",   "$5",   "$6",   "$7",
3807   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3808   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3809   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3810 };
3811
3812 struct mips_abi_choice
3813 {
3814   const char *name;
3815   const char * const *gpr_names;
3816   const char * const *fpr_names;
3817 };
3818
3819 static struct mips_abi_choice mips_abi_choices[] =
3820 {
3821   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3822   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3823   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3824   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3825 };
3826
3827 struct mips_arch_choice
3828 {
3829   const char *name;
3830   int bfd_mach_valid;
3831   unsigned long bfd_mach;
3832   int processor;
3833   int isa;
3834   const char * const *cp0_names;
3835   const struct mips_cp0sel_name *cp0sel_names;
3836   unsigned int cp0sel_names_len;
3837   const char * const *hwr_names;
3838 };
3839
3840 #define bfd_mach_mips3000              3000
3841 #define bfd_mach_mips3900              3900
3842 #define bfd_mach_mips4000              4000
3843 #define bfd_mach_mips4010              4010
3844 #define bfd_mach_mips4100              4100
3845 #define bfd_mach_mips4111              4111
3846 #define bfd_mach_mips4120              4120
3847 #define bfd_mach_mips4300              4300
3848 #define bfd_mach_mips4400              4400
3849 #define bfd_mach_mips4600              4600
3850 #define bfd_mach_mips4650              4650
3851 #define bfd_mach_mips5000              5000
3852 #define bfd_mach_mips5400              5400
3853 #define bfd_mach_mips5500              5500
3854 #define bfd_mach_mips6000              6000
3855 #define bfd_mach_mips7000              7000
3856 #define bfd_mach_mips8000              8000
3857 #define bfd_mach_mips9000              9000
3858 #define bfd_mach_mips10000             10000
3859 #define bfd_mach_mips12000             12000
3860 #define bfd_mach_mips16                16
3861 #define bfd_mach_mips5                 5
3862 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
3863 #define bfd_mach_mipsisa32             32
3864 #define bfd_mach_mipsisa32r2           33
3865 #define bfd_mach_mipsisa64             64
3866 #define bfd_mach_mipsisa64r2           65
3867
3868 static const struct mips_arch_choice mips_arch_choices[] =
3869 {
3870   { "numeric",  0, 0, 0, 0,
3871     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3872
3873   { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3874     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3875   { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3876     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3877   { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3878     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3879   { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3880     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3881   { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3882     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3883   { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3884     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3885   { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3886     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3887   { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3888     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3889   { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3890     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3891   { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3892     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3893   { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3894     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3895   { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3896     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3897   { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3898     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3899   { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3900     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3901   { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3902     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3903   { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3904     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3905   { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3906     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3907   { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3908     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3909   { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3910     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3911   { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3912     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3913   { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3914     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3915
3916   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3917      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
3918      _MIPS32 Architecture For Programmers Volume I: Introduction to the
3919      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3920      page 1.  */
3921   { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
3922     ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3923     mips_cp0_names_mips3264,
3924     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3925     mips_hwr_names_numeric },
3926
3927   { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3928     (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3929      | INSN_MIPS3D | INSN_MT | INSN_MSA),
3930     mips_cp0_names_mips3264r2,
3931     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3932     mips_hwr_names_mips3264r2 },
3933
3934   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
3935   { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
3936     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3937     mips_cp0_names_mips3264,
3938     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3939     mips_hwr_names_numeric },
3940
3941   { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3942     (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3943      | INSN_DSP64 | INSN_MT | INSN_MDMX),
3944     mips_cp0_names_mips3264r2,
3945     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3946     mips_hwr_names_mips3264r2 },
3947
3948   { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
3949     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3950     mips_cp0_names_sb1,
3951     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3952     mips_hwr_names_numeric },
3953
3954   /* This entry, mips16, is here only for ISA/processor selection; do
3955      not print its name.  */
3956   { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3957     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3958 };
3959
3960 /* ISA and processor type to disassemble for, and register names to use.
3961    set_default_mips_dis_options and parse_mips_dis_options fill in these
3962    values.  */
3963 static int mips_processor;
3964 static int mips_isa;
3965 static const char * const *mips_gpr_names;
3966 static const char * const *mips_fpr_names;
3967 static const char * const *mips_cp0_names;
3968 static const struct mips_cp0sel_name *mips_cp0sel_names;
3969 static int mips_cp0sel_names_len;
3970 static const char * const *mips_hwr_names;
3971
3972 /* Other options */
3973 static int no_aliases;  /* If set disassemble as most general inst.  */
3974 \f
3975 static const struct mips_abi_choice *
3976 choose_abi_by_name (const char *name, unsigned int namelen)
3977 {
3978   const struct mips_abi_choice *c;
3979   unsigned int i;
3980
3981   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3982     if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3983         && strlen (mips_abi_choices[i].name) == namelen)
3984       c = &mips_abi_choices[i];
3985
3986   return c;
3987 }
3988
3989 static const struct mips_arch_choice *
3990 choose_arch_by_name (const char *name, unsigned int namelen)
3991 {
3992   const struct mips_arch_choice *c = NULL;
3993   unsigned int i;
3994
3995   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3996     if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3997         && strlen (mips_arch_choices[i].name) == namelen)
3998       c = &mips_arch_choices[i];
3999
4000   return c;
4001 }
4002
4003 static const struct mips_arch_choice *
4004 choose_arch_by_number (unsigned long mach)
4005 {
4006   static unsigned long hint_bfd_mach;
4007   static const struct mips_arch_choice *hint_arch_choice;
4008   const struct mips_arch_choice *c;
4009   unsigned int i;
4010
4011   /* We optimize this because even if the user specifies no
4012      flags, this will be done for every instruction!  */
4013   if (hint_bfd_mach == mach
4014       && hint_arch_choice != NULL
4015       && hint_arch_choice->bfd_mach == hint_bfd_mach)
4016     return hint_arch_choice;
4017
4018   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
4019     {
4020       if (mips_arch_choices[i].bfd_mach_valid
4021           && mips_arch_choices[i].bfd_mach == mach)
4022         {
4023           c = &mips_arch_choices[i];
4024           hint_bfd_mach = mach;
4025           hint_arch_choice = c;
4026         }
4027     }
4028   return c;
4029 }
4030
4031 static void
4032 set_default_mips_dis_options (struct disassemble_info *info)
4033 {
4034   const struct mips_arch_choice *chosen_arch;
4035
4036   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
4037      and numeric FPR, CP0 register, and HWR names.  */
4038   mips_isa = ISA_MIPS3;
4039   mips_processor =  CPU_R3000;
4040   mips_gpr_names = mips_gpr_names_oldabi;
4041   mips_fpr_names = mips_fpr_names_numeric;
4042   mips_cp0_names = mips_cp0_names_numeric;
4043   mips_cp0sel_names = NULL;
4044   mips_cp0sel_names_len = 0;
4045   mips_hwr_names = mips_hwr_names_numeric;
4046   no_aliases = 0;
4047
4048   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
4049 #if 0
4050   if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
4051     {
4052       Elf_Internal_Ehdr *header;
4053
4054       header = elf_elfheader (info->section->owner);
4055       if (is_newabi (header))
4056         mips_gpr_names = mips_gpr_names_newabi;
4057     }
4058 #endif
4059
4060   /* Set ISA, architecture, and cp0 register names as best we can.  */
4061 #if !defined(SYMTAB_AVAILABLE) && 0
4062   /* This is running out on a target machine, not in a host tool.
4063      FIXME: Where does mips_target_info come from?  */
4064   target_processor = mips_target_info.processor;
4065   mips_isa = mips_target_info.isa;
4066 #else
4067   chosen_arch = choose_arch_by_number (info->mach);
4068   if (chosen_arch != NULL)
4069     {
4070       mips_processor = chosen_arch->processor;
4071       mips_isa = chosen_arch->isa;
4072       mips_cp0_names = chosen_arch->cp0_names;
4073       mips_cp0sel_names = chosen_arch->cp0sel_names;
4074       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4075       mips_hwr_names = chosen_arch->hwr_names;
4076     }
4077 #endif
4078 }
4079
4080 static void
4081 parse_mips_dis_option (const char *option, unsigned int len)
4082 {
4083   unsigned int i, optionlen, vallen;
4084   const char *val;
4085   const struct mips_abi_choice *chosen_abi;
4086   const struct mips_arch_choice *chosen_arch;
4087
4088   /* Look for the = that delimits the end of the option name.  */
4089   for (i = 0; i < len; i++)
4090     {
4091       if (option[i] == '=')
4092         break;
4093     }
4094   if (i == 0)           /* Invalid option: no name before '='.  */
4095     return;
4096   if (i == len)         /* Invalid option: no '='.  */
4097     return;
4098   if (i == (len - 1))   /* Invalid option: no value after '='.  */
4099     return;
4100
4101   optionlen = i;
4102   val = option + (optionlen + 1);
4103   vallen = len - (optionlen + 1);
4104
4105   if (strncmp("gpr-names", option, optionlen) == 0
4106       && strlen("gpr-names") == optionlen)
4107     {
4108       chosen_abi = choose_abi_by_name (val, vallen);
4109       if (chosen_abi != NULL)
4110         mips_gpr_names = chosen_abi->gpr_names;
4111       return;
4112     }
4113
4114   if (strncmp("fpr-names", option, optionlen) == 0
4115       && strlen("fpr-names") == optionlen)
4116     {
4117       chosen_abi = choose_abi_by_name (val, vallen);
4118       if (chosen_abi != NULL)
4119         mips_fpr_names = chosen_abi->fpr_names;
4120       return;
4121     }
4122
4123   if (strncmp("cp0-names", option, optionlen) == 0
4124       && strlen("cp0-names") == optionlen)
4125     {
4126       chosen_arch = choose_arch_by_name (val, vallen);
4127       if (chosen_arch != NULL)
4128         {
4129           mips_cp0_names = chosen_arch->cp0_names;
4130           mips_cp0sel_names = chosen_arch->cp0sel_names;
4131           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4132         }
4133       return;
4134     }
4135
4136   if (strncmp("hwr-names", option, optionlen) == 0
4137       && strlen("hwr-names") == optionlen)
4138     {
4139       chosen_arch = choose_arch_by_name (val, vallen);
4140       if (chosen_arch != NULL)
4141         mips_hwr_names = chosen_arch->hwr_names;
4142       return;
4143     }
4144
4145   if (strncmp("reg-names", option, optionlen) == 0
4146       && strlen("reg-names") == optionlen)
4147     {
4148       /* We check both ABI and ARCH here unconditionally, so
4149          that "numeric" will do the desirable thing: select
4150          numeric register names for all registers.  Other than
4151          that, a given name probably won't match both.  */
4152       chosen_abi = choose_abi_by_name (val, vallen);
4153       if (chosen_abi != NULL)
4154         {
4155           mips_gpr_names = chosen_abi->gpr_names;
4156           mips_fpr_names = chosen_abi->fpr_names;
4157         }
4158       chosen_arch = choose_arch_by_name (val, vallen);
4159       if (chosen_arch != NULL)
4160         {
4161           mips_cp0_names = chosen_arch->cp0_names;
4162           mips_cp0sel_names = chosen_arch->cp0sel_names;
4163           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4164           mips_hwr_names = chosen_arch->hwr_names;
4165         }
4166       return;
4167     }
4168
4169   /* Invalid option.  */
4170 }
4171
4172 static void
4173 parse_mips_dis_options (const char *options)
4174 {
4175   const char *option_end;
4176
4177   if (options == NULL)
4178     return;
4179
4180   while (*options != '\0')
4181     {
4182       /* Skip empty options.  */
4183       if (*options == ',')
4184         {
4185           options++;
4186           continue;
4187         }
4188
4189       /* We know that *options is neither NUL or a comma.  */
4190       option_end = options + 1;
4191       while (*option_end != ',' && *option_end != '\0')
4192         option_end++;
4193
4194       parse_mips_dis_option (options, option_end - options);
4195
4196       /* Go on to the next one.  If option_end points to a comma, it
4197          will be skipped above.  */
4198       options = option_end;
4199     }
4200 }
4201
4202 static const struct mips_cp0sel_name *
4203 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
4204                          unsigned int len,
4205                          unsigned int cp0reg,
4206                          unsigned int sel)
4207 {
4208   unsigned int i;
4209
4210   for (i = 0; i < len; i++)
4211     if (names[i].cp0reg == cp0reg && names[i].sel == sel)
4212       return &names[i];
4213   return NULL;
4214 }
4215 \f
4216 /* Print insn arguments for 32/64-bit code.  */
4217
4218 static void
4219 print_insn_args (const char *d,
4220                  register unsigned long int l,
4221                  bfd_vma pc,
4222                  struct disassemble_info *info,
4223                  const struct mips_opcode *opp)
4224 {
4225   int op, delta;
4226   unsigned int lsb, msb, msbd;
4227
4228   lsb = 0;
4229
4230   for (; *d != '\0'; d++)
4231     {
4232       switch (*d)
4233         {
4234         case ',':
4235         case '(':
4236         case ')':
4237         case '[':
4238         case ']':
4239           (*info->fprintf_func) (info->stream, "%c", *d);
4240           break;
4241
4242         case '+':
4243           /* Extension character; switch for second char.  */
4244           d++;
4245           switch (*d)
4246             {
4247             case '\0':
4248               /* xgettext:c-format */
4249               (*info->fprintf_func) (info->stream,
4250                                      _("# internal error, incomplete extension sequence (+)"));
4251               return;
4252
4253             case 'A':
4254               lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
4255               (*info->fprintf_func) (info->stream, "0x%x", lsb);
4256               break;
4257
4258             case 'B':
4259               msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
4260               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4261               break;
4262
4263             case '1':
4264               (*info->fprintf_func) (info->stream, "0x%lx",
4265                                      (l >> OP_SH_UDI1) & OP_MASK_UDI1);
4266               break;
4267
4268             case '2':
4269               (*info->fprintf_func) (info->stream, "0x%lx",
4270                                      (l >> OP_SH_UDI2) & OP_MASK_UDI2);
4271               break;
4272
4273             case '3':
4274               (*info->fprintf_func) (info->stream, "0x%lx",
4275                                      (l >> OP_SH_UDI3) & OP_MASK_UDI3);
4276               break;
4277
4278             case '4':
4279               (*info->fprintf_func) (info->stream, "0x%lx",
4280                                      (l >> OP_SH_UDI4) & OP_MASK_UDI4);
4281               break;
4282
4283         case '5': /* 5-bit signed immediate in bit 16 */
4284             delta = ((l >> OP_SH_RT) & OP_MASK_RT);
4285             if (delta & 0x10) { /* test sign bit */
4286                 delta |= ~OP_MASK_RT;
4287             }
4288             (*info->fprintf_func) (info->stream, "%d", delta);
4289             break;
4290
4291         case '6':
4292             (*info->fprintf_func) (info->stream, "0x%lx",
4293                     (l >> OP_SH_2BIT) & OP_MASK_2BIT);
4294             break;
4295
4296         case '7':
4297             (*info->fprintf_func) (info->stream, "0x%lx",
4298                     (l >> OP_SH_3BIT) & OP_MASK_3BIT);
4299             break;
4300
4301         case '8':
4302             (*info->fprintf_func) (info->stream, "0x%lx",
4303                     (l >> OP_SH_4BIT) & OP_MASK_4BIT);
4304             break;
4305
4306         case '9':
4307             (*info->fprintf_func) (info->stream, "0x%lx",
4308                     (l >> OP_SH_5BIT) & OP_MASK_5BIT);
4309             break;
4310
4311         case ':':
4312             (*info->fprintf_func) (info->stream, "0x%lx",
4313                     (l >> OP_SH_1BIT) & OP_MASK_1BIT);
4314             break;
4315
4316         case '!': /* 10-bit pc-relative target in bit 11 */
4317             delta = ((l >> OP_SH_10BIT) & OP_MASK_10BIT);
4318             if (delta & 0x200) { /* test sign bit */
4319                 delta |= ~OP_MASK_10BIT;
4320             }
4321             info->target = (delta << 2) + pc + INSNLEN;
4322             (*info->print_address_func) (info->target, info);
4323             break;
4324
4325         case '~':
4326             (*info->fprintf_func) (info->stream, "0");
4327             break;
4328
4329         case '@':
4330             (*info->fprintf_func) (info->stream, "0x%lx",
4331                     ((l >> OP_SH_1_TO_4) & OP_MASK_1_TO_4)+1);
4332             break;
4333
4334         case '^': /* 10-bit signed immediate << 0 in bit 16 */
4335             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4336             if (delta & 0x200) { /* test sign bit */
4337                 delta |= ~OP_MASK_IMM10;
4338             }
4339             (*info->fprintf_func) (info->stream, "%d", delta);
4340             break;
4341
4342         case '#': /* 10-bit signed immediate << 1 in bit 16 */
4343             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4344             if (delta & 0x200) { /* test sign bit */
4345                 delta |= ~OP_MASK_IMM10;
4346             }
4347             (*info->fprintf_func) (info->stream, "%d", delta << 1);
4348             break;
4349
4350         case '$': /* 10-bit signed immediate << 2 in bit 16 */
4351             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4352             if (delta & 0x200) { /* test sign bit */
4353                 delta |= ~OP_MASK_IMM10;
4354             }
4355             (*info->fprintf_func) (info->stream, "%d", delta << 2);
4356             break;
4357
4358         case '%': /* 10-bit signed immediate << 3 in bit 16 */
4359             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4360             if (delta & 0x200) { /* test sign bit */
4361                 delta |= ~OP_MASK_IMM10;
4362             }
4363             (*info->fprintf_func) (info->stream, "%d", delta << 3);
4364             break;
4365
4366             case 'C':
4367             case 'H':
4368               msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
4369               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4370               break;
4371
4372             case 'D':
4373               {
4374                 const struct mips_cp0sel_name *n;
4375                 unsigned int cp0reg, sel;
4376
4377                 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
4378                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4379
4380                 /* CP0 register including 'sel' code for mtcN (et al.), to be
4381                    printed textually if known.  If not known, print both
4382                    CP0 register name and sel numerically since CP0 register
4383                    with sel 0 may have a name unrelated to register being
4384                    printed.  */
4385                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4386                                             mips_cp0sel_names_len, cp0reg, sel);
4387                 if (n != NULL)
4388                   (*info->fprintf_func) (info->stream, "%s", n->name);
4389                 else
4390                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4391                 break;
4392               }
4393
4394             case 'E':
4395               lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
4396               (*info->fprintf_func) (info->stream, "0x%x", lsb);
4397               break;
4398
4399             case 'F':
4400               msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
4401               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4402               break;
4403
4404             case 'G':
4405               msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
4406               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4407               break;
4408
4409             case 'o':
4410                 switch (*(d+1)) {
4411                 case '1':
4412                     d++;
4413                     delta = l & ((1 << 18) - 1);
4414                     if (delta & 0x20000) {
4415                         delta |= ~0x1ffff;
4416                     }
4417                     break;
4418                 case '2':
4419                     d++;
4420                     delta = l & ((1 << 19) - 1);
4421                     if (delta & 0x40000) {
4422                         delta |= ~0x3ffff;
4423                     }
4424                     break;
4425                 default:
4426                     delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
4427                     if (delta & 0x8000) {
4428                         delta |= ~0xffff;
4429                     }
4430                 }
4431
4432                 (*info->fprintf_func) (info->stream, "%d", delta);
4433                 break;
4434
4435             case 'p':
4436                 /* Sign extend the displacement with 26 bits.  */
4437                 delta = (l >> OP_SH_DELTA) & OP_MASK_TARGET;
4438                 if (delta & 0x2000000) {
4439                     delta |= ~0x3FFFFFF;
4440                 }
4441                 info->target = (delta << 2) + pc + INSNLEN;
4442                 (*info->print_address_func) (info->target, info);
4443                 break;
4444
4445             case 't': /* Coprocessor 0 reg name */
4446               (*info->fprintf_func) (info->stream, "%s",
4447                                      mips_cp0_names[(l >> OP_SH_RT) &
4448                                                      OP_MASK_RT]);
4449               break;
4450
4451             case 'T': /* Coprocessor 0 reg name */
4452               {
4453                 const struct mips_cp0sel_name *n;
4454                 unsigned int cp0reg, sel;
4455
4456                 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
4457                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4458
4459                 /* CP0 register including 'sel' code for mftc0, to be
4460                    printed textually if known.  If not known, print both
4461                    CP0 register name and sel numerically since CP0 register
4462                    with sel 0 may have a name unrelated to register being
4463                    printed.  */
4464                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4465                                             mips_cp0sel_names_len, cp0reg, sel);
4466                 if (n != NULL)
4467                   (*info->fprintf_func) (info->stream, "%s", n->name);
4468                 else
4469                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4470                 break;
4471               }
4472
4473         case 'd':
4474             (*info->fprintf_func) (info->stream, "%s",
4475                     mips_wr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4476             break;
4477
4478         case 'e':
4479             (*info->fprintf_func) (info->stream, "%s",
4480                     mips_wr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4481             break;
4482
4483         case 'f':
4484             (*info->fprintf_func) (info->stream, "%s",
4485                     mips_wr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4486             break;
4487
4488         case 'g':
4489             (*info->fprintf_func) (info->stream, "%s",
4490                     mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR11)
4491                                                       & OP_MASK_MSACR11]);
4492             break;
4493
4494         case 'h':
4495             (*info->fprintf_func) (info->stream, "%s",
4496                     mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR6)
4497                                                       & OP_MASK_MSACR6]);
4498             break;
4499
4500         case 'i':
4501             (*info->fprintf_func) (info->stream, "%s",
4502                     mips_gpr_names[(l >> OP_SH_GPR) & OP_MASK_GPR]);
4503             break;
4504
4505             default:
4506               /* xgettext:c-format */
4507               (*info->fprintf_func) (info->stream,
4508                                      _("# internal error, undefined extension sequence (+%c)"),
4509                                      *d);
4510               return;
4511             }
4512           break;
4513
4514         case '2':
4515           (*info->fprintf_func) (info->stream, "0x%lx",
4516                                  (l >> OP_SH_BP) & OP_MASK_BP);
4517           break;
4518
4519         case '3':
4520           (*info->fprintf_func) (info->stream, "0x%lx",
4521                                  (l >> OP_SH_SA3) & OP_MASK_SA3);
4522           break;
4523
4524         case '4':
4525           (*info->fprintf_func) (info->stream, "0x%lx",
4526                                  (l >> OP_SH_SA4) & OP_MASK_SA4);
4527           break;
4528
4529         case '5':
4530           (*info->fprintf_func) (info->stream, "0x%lx",
4531                                  (l >> OP_SH_IMM8) & OP_MASK_IMM8);
4532           break;
4533
4534         case '6':
4535           (*info->fprintf_func) (info->stream, "0x%lx",
4536                                  (l >> OP_SH_RS) & OP_MASK_RS);
4537           break;
4538
4539         case '7':
4540           (*info->fprintf_func) (info->stream, "$ac%ld",
4541                                  (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
4542           break;
4543
4544         case '8':
4545           (*info->fprintf_func) (info->stream, "0x%lx",
4546                                  (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
4547           break;
4548
4549         case '9':
4550           (*info->fprintf_func) (info->stream, "$ac%ld",
4551                                  (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
4552           break;
4553
4554         case '0': /* dsp 6-bit signed immediate in bit 20 */
4555           delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
4556           if (delta & 0x20) /* test sign bit */
4557             delta |= ~OP_MASK_DSPSFT;
4558           (*info->fprintf_func) (info->stream, "%d", delta);
4559           break;
4560
4561         case ':': /* dsp 7-bit signed immediate in bit 19 */
4562           delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
4563           if (delta & 0x40) /* test sign bit */
4564             delta |= ~OP_MASK_DSPSFT_7;
4565           (*info->fprintf_func) (info->stream, "%d", delta);
4566           break;
4567
4568         case '\'':
4569           (*info->fprintf_func) (info->stream, "0x%lx",
4570                                  (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
4571           break;
4572
4573         case '@': /* dsp 10-bit signed immediate in bit 16 */
4574           delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4575           if (delta & 0x200) /* test sign bit */
4576             delta |= ~OP_MASK_IMM10;
4577           (*info->fprintf_func) (info->stream, "%d", delta);
4578           break;
4579
4580         case '!':
4581           (*info->fprintf_func) (info->stream, "%ld",
4582                                  (l >> OP_SH_MT_U) & OP_MASK_MT_U);
4583           break;
4584
4585         case '$':
4586           (*info->fprintf_func) (info->stream, "%ld",
4587                                  (l >> OP_SH_MT_H) & OP_MASK_MT_H);
4588           break;
4589
4590         case '*':
4591           (*info->fprintf_func) (info->stream, "$ac%ld",
4592                                  (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
4593           break;
4594
4595         case '&':
4596           (*info->fprintf_func) (info->stream, "$ac%ld",
4597                                  (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
4598           break;
4599
4600         case 'g':
4601           /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
4602           (*info->fprintf_func) (info->stream, "$%ld",
4603                                  (l >> OP_SH_RD) & OP_MASK_RD);
4604           break;
4605
4606         case 's':
4607         case 'b':
4608         case 'r':
4609         case 'v':
4610           (*info->fprintf_func) (info->stream, "%s",
4611                                  mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
4612           break;
4613
4614         case 't':
4615         case 'w':
4616           (*info->fprintf_func) (info->stream, "%s",
4617                                  mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4618           break;
4619
4620         case 'i':
4621         case 'u':
4622           (*info->fprintf_func) (info->stream, "0x%lx",
4623                                  (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
4624           break;
4625
4626         case 'j': /* Same as i, but sign-extended.  */
4627         case 'o':
4628             delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4629
4630           if (delta & 0x8000)
4631             delta |= ~0xffff;
4632           (*info->fprintf_func) (info->stream, "%d",
4633                                  delta);
4634           break;
4635
4636         case 'h':
4637           (*info->fprintf_func) (info->stream, "0x%x",
4638                                  (unsigned int) ((l >> OP_SH_PREFX)
4639                                                  & OP_MASK_PREFX));
4640           break;
4641
4642         case 'k':
4643           (*info->fprintf_func) (info->stream, "0x%x",
4644                                  (unsigned int) ((l >> OP_SH_CACHE)
4645                                                  & OP_MASK_CACHE));
4646           break;
4647
4648         case 'a':
4649           info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
4650                           | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
4651           /* For gdb disassembler, force odd address on jalx.  */
4652           if (info->flavour == bfd_target_unknown_flavour
4653               && strcmp (opp->name, "jalx") == 0)
4654             info->target |= 1;
4655           (*info->print_address_func) (info->target, info);
4656           break;
4657
4658         case 'p':
4659           /* Sign extend the displacement.  */
4660           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4661           if (delta & 0x8000)
4662             delta |= ~0xffff;
4663           info->target = (delta << 2) + pc + INSNLEN;
4664           (*info->print_address_func) (info->target, info);
4665           break;
4666
4667         case 'd':
4668           (*info->fprintf_func) (info->stream, "%s",
4669                                  mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4670           break;
4671
4672         case 'U':
4673           {
4674             /* First check for both rd and rt being equal.  */
4675             unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
4676             if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
4677               (*info->fprintf_func) (info->stream, "%s",
4678                                      mips_gpr_names[reg]);
4679             else
4680               {
4681                 /* If one is zero use the other.  */
4682                 if (reg == 0)
4683                   (*info->fprintf_func) (info->stream, "%s",
4684                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4685                 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
4686                   (*info->fprintf_func) (info->stream, "%s",
4687                                          mips_gpr_names[reg]);
4688                 else /* Bogus, result depends on processor.  */
4689                   (*info->fprintf_func) (info->stream, "%s or %s",
4690                                          mips_gpr_names[reg],
4691                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4692               }
4693           }
4694           break;
4695
4696         case 'z':
4697           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4698           break;
4699
4700         case '<':
4701           (*info->fprintf_func) (info->stream, "0x%lx",
4702                                  (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
4703           break;
4704
4705         case 'c':
4706           (*info->fprintf_func) (info->stream, "0x%lx",
4707                                  (l >> OP_SH_CODE) & OP_MASK_CODE);
4708           break;
4709
4710         case 'q':
4711           (*info->fprintf_func) (info->stream, "0x%lx",
4712                                  (l >> OP_SH_CODE2) & OP_MASK_CODE2);
4713           break;
4714
4715         case 'C':
4716           (*info->fprintf_func) (info->stream, "0x%lx",
4717                                  (l >> OP_SH_COPZ) & OP_MASK_COPZ);
4718           break;
4719
4720         case 'B':
4721           (*info->fprintf_func) (info->stream, "0x%lx",
4722
4723                                  (l >> OP_SH_CODE20) & OP_MASK_CODE20);
4724           break;
4725
4726         case 'J':
4727           (*info->fprintf_func) (info->stream, "0x%lx",
4728                                  (l >> OP_SH_CODE19) & OP_MASK_CODE19);
4729           break;
4730
4731         case 'S':
4732         case 'V':
4733           (*info->fprintf_func) (info->stream, "%s",
4734                                  mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4735           break;
4736
4737         case 'T':
4738         case 'W':
4739           (*info->fprintf_func) (info->stream, "%s",
4740                                  mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4741           break;
4742
4743         case 'D':
4744           (*info->fprintf_func) (info->stream, "%s",
4745                                  mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4746           break;
4747
4748         case 'R':
4749           (*info->fprintf_func) (info->stream, "%s",
4750                                  mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
4751           break;
4752
4753         case 'E':
4754           /* Coprocessor register for lwcN instructions, et al.
4755
4756              Note that there is no load/store cp0 instructions, and
4757              that FPU (cp1) instructions disassemble this field using
4758              'T' format.  Therefore, until we gain understanding of
4759              cp2 register names, we can simply print the register
4760              numbers.  */
4761           (*info->fprintf_func) (info->stream, "$%ld",
4762                                  (l >> OP_SH_RT) & OP_MASK_RT);
4763           break;
4764
4765         case 'G':
4766           /* Coprocessor register for mtcN instructions, et al.  Note
4767              that FPU (cp1) instructions disassemble this field using
4768              'S' format.  Therefore, we only need to worry about cp0,
4769              cp2, and cp3.  */
4770           op = (l >> OP_SH_OP) & OP_MASK_OP;
4771           if (op == OP_OP_COP0)
4772             (*info->fprintf_func) (info->stream, "%s",
4773                                    mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4774           else
4775             (*info->fprintf_func) (info->stream, "$%ld",
4776                                    (l >> OP_SH_RD) & OP_MASK_RD);
4777           break;
4778
4779         case 'K':
4780           (*info->fprintf_func) (info->stream, "%s",
4781                                  mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4782           break;
4783
4784         case 'N':
4785           (*info->fprintf_func) (info->stream,
4786                                  ((opp->pinfo & (FP_D | FP_S)) != 0
4787                                   ? "$fcc%ld" : "$cc%ld"),
4788                                  (l >> OP_SH_BCC) & OP_MASK_BCC);
4789           break;
4790
4791         case 'M':
4792           (*info->fprintf_func) (info->stream, "$fcc%ld",
4793                                  (l >> OP_SH_CCC) & OP_MASK_CCC);
4794           break;
4795
4796         case 'P':
4797           (*info->fprintf_func) (info->stream, "%ld",
4798                                  (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
4799           break;
4800
4801         case 'e':
4802           (*info->fprintf_func) (info->stream, "%ld",
4803                                  (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
4804           break;
4805
4806         case '%':
4807           (*info->fprintf_func) (info->stream, "%ld",
4808                                  (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
4809           break;
4810
4811         case 'H':
4812           (*info->fprintf_func) (info->stream, "%ld",
4813                                  (l >> OP_SH_SEL) & OP_MASK_SEL);
4814           break;
4815
4816         case 'O':
4817           (*info->fprintf_func) (info->stream, "%ld",
4818                                  (l >> OP_SH_ALN) & OP_MASK_ALN);
4819           break;
4820
4821         case 'Q':
4822           {
4823             unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
4824
4825             if ((vsel & 0x10) == 0)
4826               {
4827                 int fmt;
4828
4829                 vsel &= 0x0f;
4830                 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
4831                   if ((vsel & 1) == 0)
4832                     break;
4833                 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
4834                                        (l >> OP_SH_FT) & OP_MASK_FT,
4835                                        vsel >> 1);
4836               }
4837             else if ((vsel & 0x08) == 0)
4838               {
4839                 (*info->fprintf_func) (info->stream, "$v%ld",
4840                                        (l >> OP_SH_FT) & OP_MASK_FT);
4841               }
4842             else
4843               {
4844                 (*info->fprintf_func) (info->stream, "0x%lx",
4845                                        (l >> OP_SH_FT) & OP_MASK_FT);
4846               }
4847           }
4848           break;
4849
4850         case 'X':
4851           (*info->fprintf_func) (info->stream, "$v%ld",
4852                                  (l >> OP_SH_FD) & OP_MASK_FD);
4853           break;
4854
4855         case 'Y':
4856           (*info->fprintf_func) (info->stream, "$v%ld",
4857                                  (l >> OP_SH_FS) & OP_MASK_FS);
4858           break;
4859
4860         case 'Z':
4861           (*info->fprintf_func) (info->stream, "$v%ld",
4862                                  (l >> OP_SH_FT) & OP_MASK_FT);
4863           break;
4864
4865         default:
4866           /* xgettext:c-format */
4867           (*info->fprintf_func) (info->stream,
4868                                  _("# internal error, undefined modifier(%c)"),
4869                                  *d);
4870           return;
4871         }
4872     }
4873 }
4874 \f
4875 /* Check if the object uses NewABI conventions.  */
4876 #if 0
4877 static int
4878 is_newabi (header)
4879      Elf_Internal_Ehdr *header;
4880 {
4881   /* There are no old-style ABIs which use 64-bit ELF.  */
4882   if (header->e_ident[EI_CLASS] == ELFCLASS64)
4883     return 1;
4884
4885   /* If a 32-bit ELF file, n32 is a new-style ABI.  */
4886   if ((header->e_flags & EF_MIPS_ABI2) != 0)
4887     return 1;
4888
4889   return 0;
4890 }
4891 #endif
4892 \f
4893 /* Print the mips instruction at address MEMADDR in debugged memory,
4894    on using INFO.  Returns length of the instruction, in bytes, which is
4895    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
4896    this is little-endian code.  */
4897
4898 static int
4899 print_insn_mips (bfd_vma memaddr,
4900                  unsigned long int word,
4901                  struct disassemble_info *info)
4902 {
4903   const struct mips_opcode *op;
4904   static bfd_boolean init = 0;
4905   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4906
4907   /* Build a hash table to shorten the search time.  */
4908   if (! init)
4909     {
4910       unsigned int i;
4911
4912       for (i = 0; i <= OP_MASK_OP; i++)
4913         {
4914           for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4915             {
4916               if (op->pinfo == INSN_MACRO
4917                   || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
4918                 continue;
4919               if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4920                 {
4921                   mips_hash[i] = op;
4922                   break;
4923                 }
4924             }
4925         }
4926
4927       init = 1;
4928     }
4929
4930   info->bytes_per_chunk = INSNLEN;
4931   info->display_endian = info->endian;
4932   info->insn_info_valid = 1;
4933   info->branch_delay_insns = 0;
4934   info->data_size = 0;
4935   info->insn_type = dis_nonbranch;
4936   info->target = 0;
4937   info->target2 = 0;
4938
4939   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4940   if (op != NULL)
4941     {
4942       for (; op < &mips_opcodes[NUMOPCODES]; op++)
4943         {
4944           if (op->pinfo != INSN_MACRO
4945               && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4946               && (word & op->mask) == op->match)
4947             {
4948               const char *d;
4949
4950               /* We always allow to disassemble the jalx instruction.  */
4951               if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4952                   && strcmp (op->name, "jalx"))
4953                 continue;
4954
4955               if (strcmp(op->name, "bovc") == 0
4956                   || strcmp(op->name, "bnvc") == 0) {
4957                   if (((word >> OP_SH_RS) & OP_MASK_RS) <
4958                       ((word >> OP_SH_RT) & OP_MASK_RT)) {
4959                       continue;
4960                   }
4961               }
4962               if (strcmp(op->name, "bgezc") == 0
4963                   || strcmp(op->name, "bltzc") == 0
4964                   || strcmp(op->name, "bgezalc") == 0
4965                   || strcmp(op->name, "bltzalc") == 0) {
4966                   if (((word >> OP_SH_RS) & OP_MASK_RS) !=
4967                       ((word >> OP_SH_RT) & OP_MASK_RT)) {
4968                       continue;
4969                   }
4970               }
4971
4972               /* Figure out instruction type and branch delay information.  */
4973               if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4974                 {
4975                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4976                     info->insn_type = dis_jsr;
4977                   else
4978                     info->insn_type = dis_branch;
4979                   info->branch_delay_insns = 1;
4980                 }
4981               else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4982                                      | INSN_COND_BRANCH_LIKELY)) != 0)
4983                 {
4984                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4985                     info->insn_type = dis_condjsr;
4986                   else
4987                     info->insn_type = dis_condbranch;
4988                   info->branch_delay_insns = 1;
4989                 }
4990               else if ((op->pinfo & (INSN_STORE_MEMORY
4991                                      | INSN_LOAD_MEMORY_DELAY)) != 0)
4992                 info->insn_type = dis_dref;
4993
4994               (*info->fprintf_func) (info->stream, "%s", op->name);
4995
4996               d = op->args;
4997               if (d != NULL && *d != '\0')
4998                 {
4999                   (*info->fprintf_func) (info->stream, "\t");
5000                   print_insn_args (d, word, memaddr, info, op);
5001                 }
5002
5003               return INSNLEN;
5004             }
5005         }
5006     }
5007
5008   /* Handle undefined instructions.  */
5009   info->insn_type = dis_noninsn;
5010   (*info->fprintf_func) (info->stream, "0x%lx", word);
5011   return INSNLEN;
5012 }
5013 \f
5014 /* In an environment where we do not know the symbol type of the
5015    instruction we are forced to assume that the low order bit of the
5016    instructions' address may mark it as a mips16 instruction.  If we
5017    are single stepping, or the pc is within the disassembled function,
5018    this works.  Otherwise, we need a clue.  Sometimes.  */
5019
5020 static int
5021 _print_insn_mips (bfd_vma memaddr,
5022                   struct disassemble_info *info,
5023                   enum bfd_endian endianness)
5024 {
5025   bfd_byte buffer[INSNLEN];
5026   int status;
5027
5028   set_default_mips_dis_options (info);
5029   parse_mips_dis_options (info->disassembler_options);
5030
5031 #if 0
5032 #if 1
5033   /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
5034   /* Only a few tools will work this way.  */
5035   if (memaddr & 0x01)
5036     return print_insn_mips16 (memaddr, info);
5037 #endif
5038
5039 #if SYMTAB_AVAILABLE
5040   if (info->mach == bfd_mach_mips16
5041       || (info->flavour == bfd_target_elf_flavour
5042           && info->symbols != NULL
5043           && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
5044               == STO_MIPS16)))
5045     return print_insn_mips16 (memaddr, info);
5046 #endif
5047 #endif
5048
5049   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
5050   if (status == 0)
5051     {
5052       unsigned long insn;
5053
5054       if (endianness == BFD_ENDIAN_BIG)
5055         insn = (unsigned long) bfd_getb32 (buffer);
5056       else
5057         insn = (unsigned long) bfd_getl32 (buffer);
5058
5059       return print_insn_mips (memaddr, insn, info);
5060     }
5061   else
5062     {
5063       (*info->memory_error_func) (status, memaddr, info);
5064       return -1;
5065     }
5066 }
5067
5068 int
5069 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
5070 {
5071   return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
5072 }
5073
5074 int
5075 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
5076 {
5077   return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
5078 }
5079 \f
5080 /* Disassemble mips16 instructions.  */
5081 #if 0
5082 static int
5083 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
5084 {
5085   int status;
5086   bfd_byte buffer[2];
5087   int length;
5088   int insn;
5089   bfd_boolean use_extend;
5090   int extend = 0;
5091   const struct mips_opcode *op, *opend;
5092
5093   info->bytes_per_chunk = 2;
5094   info->display_endian = info->endian;
5095   info->insn_info_valid = 1;
5096   info->branch_delay_insns = 0;
5097   info->data_size = 0;
5098   info->insn_type = dis_nonbranch;
5099   info->target = 0;
5100   info->target2 = 0;
5101
5102   status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5103   if (status != 0)
5104     {
5105       (*info->memory_error_func) (status, memaddr, info);
5106       return -1;
5107     }
5108
5109   length = 2;
5110
5111   if (info->endian == BFD_ENDIAN_BIG)
5112     insn = bfd_getb16 (buffer);
5113   else
5114     insn = bfd_getl16 (buffer);
5115
5116   /* Handle the extend opcode specially.  */
5117   use_extend = FALSE;
5118   if ((insn & 0xf800) == 0xf000)
5119     {
5120       use_extend = TRUE;
5121       extend = insn & 0x7ff;
5122
5123       memaddr += 2;
5124
5125       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5126       if (status != 0)
5127         {
5128           (*info->fprintf_func) (info->stream, "extend 0x%x",
5129                                  (unsigned int) extend);
5130           (*info->memory_error_func) (status, memaddr, info);
5131           return -1;
5132         }
5133
5134       if (info->endian == BFD_ENDIAN_BIG)
5135         insn = bfd_getb16 (buffer);
5136       else
5137         insn = bfd_getl16 (buffer);
5138
5139       /* Check for an extend opcode followed by an extend opcode.  */
5140       if ((insn & 0xf800) == 0xf000)
5141         {
5142           (*info->fprintf_func) (info->stream, "extend 0x%x",
5143                                  (unsigned int) extend);
5144           info->insn_type = dis_noninsn;
5145           return length;
5146         }
5147
5148       length += 2;
5149     }
5150
5151   /* FIXME: Should probably use a hash table on the major opcode here.  */
5152
5153   opend = mips16_opcodes + bfd_mips16_num_opcodes;
5154   for (op = mips16_opcodes; op < opend; op++)
5155     {
5156       if (op->pinfo != INSN_MACRO
5157           && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
5158           && (insn & op->mask) == op->match)
5159         {
5160           const char *s;
5161
5162           if (strchr (op->args, 'a') != NULL)
5163             {
5164               if (use_extend)
5165                 {
5166                   (*info->fprintf_func) (info->stream, "extend 0x%x",
5167                                          (unsigned int) extend);
5168                   info->insn_type = dis_noninsn;
5169                   return length - 2;
5170                 }
5171
5172               use_extend = FALSE;
5173
5174               memaddr += 2;
5175
5176               status = (*info->read_memory_func) (memaddr, buffer, 2,
5177                                                   info);
5178               if (status == 0)
5179                 {
5180                   use_extend = TRUE;
5181                   if (info->endian == BFD_ENDIAN_BIG)
5182                     extend = bfd_getb16 (buffer);
5183                   else
5184                     extend = bfd_getl16 (buffer);
5185                   length += 2;
5186                 }
5187             }
5188
5189           (*info->fprintf_func) (info->stream, "%s", op->name);
5190           if (op->args[0] != '\0')
5191             (*info->fprintf_func) (info->stream, "\t");
5192
5193           for (s = op->args; *s != '\0'; s++)
5194             {
5195               if (*s == ','
5196                   && s[1] == 'w'
5197                   && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
5198                       == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
5199                 {
5200                   /* Skip the register and the comma.  */
5201                   ++s;
5202                   continue;
5203                 }
5204               if (*s == ','
5205                   && s[1] == 'v'
5206                   && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
5207                       == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
5208                 {
5209                   /* Skip the register and the comma.  */
5210                   ++s;
5211                   continue;
5212                 }
5213               print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
5214                                      info);
5215             }
5216
5217           if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
5218             {
5219               info->branch_delay_insns = 1;
5220               if (info->insn_type != dis_jsr)
5221                 info->insn_type = dis_branch;
5222             }
5223
5224           return length;
5225         }
5226     }
5227
5228   if (use_extend)
5229     (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
5230   (*info->fprintf_func) (info->stream, "0x%x", insn);
5231   info->insn_type = dis_noninsn;
5232
5233   return length;
5234 }
5235
5236 /* Disassemble an operand for a mips16 instruction.  */
5237
5238 static void
5239 print_mips16_insn_arg (char type,
5240                        const struct mips_opcode *op,
5241                        int l,
5242                        bfd_boolean use_extend,
5243                        int extend,
5244                        bfd_vma memaddr,
5245                        struct disassemble_info *info)
5246 {
5247   switch (type)
5248     {
5249     case ',':
5250     case '(':
5251     case ')':
5252       (*info->fprintf_func) (info->stream, "%c", type);
5253       break;
5254
5255     case 'y':
5256     case 'w':
5257       (*info->fprintf_func) (info->stream, "%s",
5258                              mips16_reg_names(((l >> MIPS16OP_SH_RY)
5259                                                & MIPS16OP_MASK_RY)));
5260       break;
5261
5262     case 'x':
5263     case 'v':
5264       (*info->fprintf_func) (info->stream, "%s",
5265                              mips16_reg_names(((l >> MIPS16OP_SH_RX)
5266                                                & MIPS16OP_MASK_RX)));
5267       break;
5268
5269     case 'z':
5270       (*info->fprintf_func) (info->stream, "%s",
5271                              mips16_reg_names(((l >> MIPS16OP_SH_RZ)
5272                                                & MIPS16OP_MASK_RZ)));
5273       break;
5274
5275     case 'Z':
5276       (*info->fprintf_func) (info->stream, "%s",
5277                              mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
5278                                                & MIPS16OP_MASK_MOVE32Z)));
5279       break;
5280
5281     case '0':
5282       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
5283       break;
5284
5285     case 'S':
5286       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
5287       break;
5288
5289     case 'P':
5290       (*info->fprintf_func) (info->stream, "$pc");
5291       break;
5292
5293     case 'R':
5294       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
5295       break;
5296
5297     case 'X':
5298       (*info->fprintf_func) (info->stream, "%s",
5299                              mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
5300                                             & MIPS16OP_MASK_REGR32)]);
5301       break;
5302
5303     case 'Y':
5304       (*info->fprintf_func) (info->stream, "%s",
5305                              mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
5306       break;
5307
5308     case '<':
5309     case '>':
5310     case '[':
5311     case ']':
5312     case '4':
5313     case '5':
5314     case 'H':
5315     case 'W':
5316     case 'D':
5317     case 'j':
5318     case '6':
5319     case '8':
5320     case 'V':
5321     case 'C':
5322     case 'U':
5323     case 'k':
5324     case 'K':
5325     case 'p':
5326     case 'q':
5327     case 'A':
5328     case 'B':
5329     case 'E':
5330       {
5331         int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
5332
5333         shift = 0;
5334         signedp = 0;
5335         extbits = 16;
5336         pcrel = 0;
5337         extu = 0;
5338         branch = 0;
5339         switch (type)
5340           {
5341           case '<':
5342             nbits = 3;
5343             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5344             extbits = 5;
5345             extu = 1;
5346             break;
5347           case '>':
5348             nbits = 3;
5349             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5350             extbits = 5;
5351             extu = 1;
5352             break;
5353           case '[':
5354             nbits = 3;
5355             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5356             extbits = 6;
5357             extu = 1;
5358             break;
5359           case ']':
5360             nbits = 3;
5361             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5362             extbits = 6;
5363             extu = 1;
5364             break;
5365           case '4':
5366             nbits = 4;
5367             immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
5368             signedp = 1;
5369             extbits = 15;
5370             break;
5371           case '5':
5372             nbits = 5;
5373             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5374             info->insn_type = dis_dref;
5375             info->data_size = 1;
5376             break;
5377           case 'H':
5378             nbits = 5;
5379             shift = 1;
5380             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5381             info->insn_type = dis_dref;
5382             info->data_size = 2;
5383             break;
5384           case 'W':
5385             nbits = 5;
5386             shift = 2;
5387             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5388             if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
5389                 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
5390               {
5391                 info->insn_type = dis_dref;
5392                 info->data_size = 4;
5393               }
5394             break;
5395           case 'D':
5396             nbits = 5;
5397             shift = 3;
5398             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5399             info->insn_type = dis_dref;
5400             info->data_size = 8;
5401             break;
5402           case 'j':
5403             nbits = 5;
5404             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5405             signedp = 1;
5406             break;
5407           case '6':
5408             nbits = 6;
5409             immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5410             break;
5411           case '8':
5412             nbits = 8;
5413             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5414             break;
5415           case 'V':
5416             nbits = 8;
5417             shift = 2;
5418             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5419             /* FIXME: This might be lw, or it might be addiu to $sp or
5420                $pc.  We assume it's load.  */
5421             info->insn_type = dis_dref;
5422             info->data_size = 4;
5423             break;
5424           case 'C':
5425             nbits = 8;
5426             shift = 3;
5427             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5428             info->insn_type = dis_dref;
5429             info->data_size = 8;
5430             break;
5431           case 'U':
5432             nbits = 8;
5433             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5434             extu = 1;
5435             break;
5436           case 'k':
5437             nbits = 8;
5438             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5439             signedp = 1;
5440             break;
5441           case 'K':
5442             nbits = 8;
5443             shift = 3;
5444             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5445             signedp = 1;
5446             break;
5447           case 'p':
5448             nbits = 8;
5449             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5450             signedp = 1;
5451             pcrel = 1;
5452             branch = 1;
5453             info->insn_type = dis_condbranch;
5454             break;
5455           case 'q':
5456             nbits = 11;
5457             immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
5458             signedp = 1;
5459             pcrel = 1;
5460             branch = 1;
5461             info->insn_type = dis_branch;
5462             break;
5463           case 'A':
5464             nbits = 8;
5465             shift = 2;
5466             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5467             pcrel = 1;
5468             /* FIXME: This can be lw or la.  We assume it is lw.  */
5469             info->insn_type = dis_dref;
5470             info->data_size = 4;
5471             break;
5472           case 'B':
5473             nbits = 5;
5474             shift = 3;
5475             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5476             pcrel = 1;
5477             info->insn_type = dis_dref;
5478             info->data_size = 8;
5479             break;
5480           case 'E':
5481             nbits = 5;
5482             shift = 2;
5483             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5484             pcrel = 1;
5485             break;
5486           default:
5487             abort ();
5488           }
5489
5490         if (! use_extend)
5491           {
5492             if (signedp && immed >= (1 << (nbits - 1)))
5493               immed -= 1 << nbits;
5494             immed <<= shift;
5495             if ((type == '<' || type == '>' || type == '[' || type == ']')
5496                 && immed == 0)
5497               immed = 8;
5498           }
5499         else
5500           {
5501             if (extbits == 16)
5502               immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
5503             else if (extbits == 15)
5504               immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
5505             else
5506               immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
5507             immed &= (1 << extbits) - 1;
5508             if (! extu && immed >= (1 << (extbits - 1)))
5509               immed -= 1 << extbits;
5510           }
5511
5512         if (! pcrel)
5513           (*info->fprintf_func) (info->stream, "%d", immed);
5514         else
5515           {
5516             bfd_vma baseaddr;
5517
5518             if (branch)
5519               {
5520                 immed *= 2;
5521                 baseaddr = memaddr + 2;
5522               }
5523             else if (use_extend)
5524               baseaddr = memaddr - 2;
5525             else
5526               {
5527                 int status;
5528                 bfd_byte buffer[2];
5529
5530                 baseaddr = memaddr;
5531
5532                 /* If this instruction is in the delay slot of a jr
5533                    instruction, the base address is the address of the
5534                    jr instruction.  If it is in the delay slot of jalr
5535                    instruction, the base address is the address of the
5536                    jalr instruction.  This test is unreliable: we have
5537                    no way of knowing whether the previous word is
5538                    instruction or data.  */
5539                 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
5540                                                     info);
5541                 if (status == 0
5542                     && (((info->endian == BFD_ENDIAN_BIG
5543                           ? bfd_getb16 (buffer)
5544                           : bfd_getl16 (buffer))
5545                          & 0xf800) == 0x1800))
5546                   baseaddr = memaddr - 4;
5547                 else
5548                   {
5549                     status = (*info->read_memory_func) (memaddr - 2, buffer,
5550                                                         2, info);
5551                     if (status == 0
5552                         && (((info->endian == BFD_ENDIAN_BIG
5553                               ? bfd_getb16 (buffer)
5554                               : bfd_getl16 (buffer))
5555                              & 0xf81f) == 0xe800))
5556                       baseaddr = memaddr - 2;
5557                   }
5558               }
5559             info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
5560             if (pcrel && branch
5561                 && info->flavour == bfd_target_unknown_flavour)
5562               /* For gdb disassembler, maintain odd address.  */
5563               info->target |= 1;
5564             (*info->print_address_func) (info->target, info);
5565           }
5566       }
5567       break;
5568
5569     case 'a':
5570       {
5571         int jalx = l & 0x400;
5572
5573         if (! use_extend)
5574           extend = 0;
5575         l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
5576         if (!jalx && info->flavour == bfd_target_unknown_flavour)
5577           /* For gdb disassembler, maintain odd address.  */
5578           l |= 1;
5579       }
5580       info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
5581       (*info->print_address_func) (info->target, info);
5582       info->insn_type = dis_jsr;
5583       info->branch_delay_insns = 1;
5584       break;
5585
5586     case 'l':
5587     case 'L':
5588       {
5589         int need_comma, amask, smask;
5590
5591         need_comma = 0;
5592
5593         l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5594
5595         amask = (l >> 3) & 7;
5596
5597         if (amask > 0 && amask < 5)
5598           {
5599             (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5600             if (amask > 1)
5601               (*info->fprintf_func) (info->stream, "-%s",
5602                                      mips_gpr_names[amask + 3]);
5603             need_comma = 1;
5604           }
5605
5606         smask = (l >> 1) & 3;
5607         if (smask == 3)
5608           {
5609             (*info->fprintf_func) (info->stream, "%s??",
5610                                    need_comma ? "," : "");
5611             need_comma = 1;
5612           }
5613         else if (smask > 0)
5614           {
5615             (*info->fprintf_func) (info->stream, "%s%s",
5616                                    need_comma ? "," : "",
5617                                    mips_gpr_names[16]);
5618             if (smask > 1)
5619               (*info->fprintf_func) (info->stream, "-%s",
5620                                      mips_gpr_names[smask + 15]);
5621             need_comma = 1;
5622           }
5623
5624         if (l & 1)
5625           {
5626             (*info->fprintf_func) (info->stream, "%s%s",
5627                                    need_comma ? "," : "",
5628                                    mips_gpr_names[31]);
5629             need_comma = 1;
5630           }
5631
5632         if (amask == 5 || amask == 6)
5633           {
5634             (*info->fprintf_func) (info->stream, "%s$f0",
5635                                    need_comma ? "," : "");
5636             if (amask == 6)
5637               (*info->fprintf_func) (info->stream, "-$f1");
5638           }
5639       }
5640       break;
5641
5642     case 'm':
5643     case 'M':
5644       /* MIPS16e save/restore.  */
5645       {
5646       int need_comma = 0;
5647       int amask, args, statics;
5648       int nsreg, smask;
5649       int framesz;
5650       int i, j;
5651
5652       l = l & 0x7f;
5653       if (use_extend)
5654         l |= extend << 16;
5655
5656       amask = (l >> 16) & 0xf;
5657       if (amask == MIPS16_ALL_ARGS)
5658         {
5659           args = 4;
5660           statics = 0;
5661         }
5662       else if (amask == MIPS16_ALL_STATICS)
5663         {
5664           args = 0;
5665           statics = 4;
5666         }
5667       else
5668         {
5669           args = amask >> 2;
5670           statics = amask & 3;
5671         }
5672
5673       if (args > 0) {
5674           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5675           if (args > 1)
5676             (*info->fprintf_func) (info->stream, "-%s",
5677                                    mips_gpr_names[4 + args - 1]);
5678           need_comma = 1;
5679       }
5680
5681       framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
5682       if (framesz == 0 && !use_extend)
5683         framesz = 128;
5684
5685       (*info->fprintf_func) (info->stream, "%s%d",
5686                              need_comma ? "," : "",
5687                              framesz);
5688
5689       if (l & 0x40)                   /* $ra */
5690         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
5691
5692       nsreg = (l >> 24) & 0x7;
5693       smask = 0;
5694       if (l & 0x20)                   /* $s0 */
5695         smask |= 1 << 0;
5696       if (l & 0x10)                   /* $s1 */
5697         smask |= 1 << 1;
5698       if (nsreg > 0)                  /* $s2-$s8 */
5699         smask |= ((1 << nsreg) - 1) << 2;
5700
5701       /* Find first set static reg bit.  */
5702       for (i = 0; i < 9; i++)
5703         {
5704           if (smask & (1 << i))
5705             {
5706               (*info->fprintf_func) (info->stream, ",%s",
5707                                      mips_gpr_names[i == 8 ? 30 : (16 + i)]);
5708               /* Skip over string of set bits.  */
5709               for (j = i; smask & (2 << j); j++)
5710                 continue;
5711               if (j > i)
5712                 (*info->fprintf_func) (info->stream, "-%s",
5713                                        mips_gpr_names[j == 8 ? 30 : (16 + j)]);
5714               i = j + 1;
5715             }
5716         }
5717
5718       /* Statics $ax - $a3.  */
5719       if (statics == 1)
5720         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
5721       else if (statics > 0)
5722         (*info->fprintf_func) (info->stream, ",%s-%s",
5723                                mips_gpr_names[7 - statics + 1],
5724                                mips_gpr_names[7]);
5725       }
5726       break;
5727
5728     default:
5729       /* xgettext:c-format */
5730       (*info->fprintf_func)
5731         (info->stream,
5732          _("# internal disassembler error, unrecognised modifier (%c)"),
5733          type);
5734       abort ();
5735     }
5736 }
5737
5738 void
5739 print_mips_disassembler_options (FILE *stream)
5740 {
5741   unsigned int i;
5742
5743   fprintf (stream, _("\n\
5744 The following MIPS specific disassembler options are supported for use\n\
5745 with the -M switch (multiple options should be separated by commas):\n"));
5746
5747   fprintf (stream, _("\n\
5748   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
5749                            Default: based on binary being disassembled.\n"));
5750
5751   fprintf (stream, _("\n\
5752   fpr-names=ABI            Print FPR names according to specified ABI.\n\
5753                            Default: numeric.\n"));
5754
5755   fprintf (stream, _("\n\
5756   cp0-names=ARCH           Print CP0 register names according to\n\
5757                            specified architecture.\n\
5758                            Default: based on binary being disassembled.\n"));
5759
5760   fprintf (stream, _("\n\
5761   hwr-names=ARCH           Print HWR names according to specified\n\
5762                            architecture.\n\
5763                            Default: based on binary being disassembled.\n"));
5764
5765   fprintf (stream, _("\n\
5766   reg-names=ABI            Print GPR and FPR names according to\n\
5767                            specified ABI.\n"));
5768
5769   fprintf (stream, _("\n\
5770   reg-names=ARCH           Print CP0 register and HWR names according to\n\
5771                            specified architecture.\n"));
5772
5773   fprintf (stream, _("\n\
5774   For the options above, the following values are supported for \"ABI\":\n\
5775    "));
5776   for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
5777     fprintf (stream, " %s", mips_abi_choices[i].name);
5778   fprintf (stream, _("\n"));
5779
5780   fprintf (stream, _("\n\
5781   For the options above, The following values are supported for \"ARCH\":\n\
5782    "));
5783   for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
5784     if (*mips_arch_choices[i].name != '\0')
5785       fprintf (stream, " %s", mips_arch_choices[i].name);
5786   fprintf (stream, _("\n"));
5787
5788   fprintf (stream, _("\n"));
5789 }
5790 #endif