target-i386/misc_helper.c

   1 /*
   2  *  x86 misc helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/ioport.h"
  22 #include "helper.h"
  23
  24 #if !defined(CONFIG_USER_ONLY)
  25 #include "exec/softmmu_exec.h"
  26 #endif /* !defined(CONFIG_USER_ONLY) */
  27
  28 /* check if Port I/O is allowed in TSS */
  29 static inline void check_io(CPUX86State *env, int addr, int size)
  30 {
  31     int io_offset, val, mask;
  32
  33     /* TSS must be a valid 32 bit one */
  34     if (!(env->tr.flags & DESC_P_MASK) ||
  35         ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
  36         env->tr.limit < 103) {
  37         goto fail;
  38     }
  39     io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
  40     io_offset += (addr >> 3);
  41     /* Note: the check needs two bytes */
  42     if ((io_offset + 1) > env->tr.limit) {
  43         goto fail;
  44     }
  45     val = cpu_lduw_kernel(env, env->tr.base + io_offset);
  46     val >>= (addr & 7);
  47     mask = (1 << size) - 1;
  48     /* all bits must be zero to allow the I/O */
  49     if ((val & mask) != 0) {
  50     fail:
  51         raise_exception_err(env, EXCP0D_GPF, 0);
  52     }
  53 }
  54
  55 void helper_check_iob(CPUX86State *env, uint32_t t0)
  56 {
  57     check_io(env, t0, 1);
  58 }
  59
  60 void helper_check_iow(CPUX86State *env, uint32_t t0)
  61 {
  62     check_io(env, t0, 2);
  63 }
  64
  65 void helper_check_iol(CPUX86State *env, uint32_t t0)
  66 {
  67     check_io(env, t0, 4);
  68 }
  69
  70 void helper_outb(uint32_t port, uint32_t data)
  71 {
  72     cpu_outb(port, data & 0xff);
  73 }
  74
  75 target_ulong helper_inb(uint32_t port)
  76 {
  77     return cpu_inb(port);
  78 }
  79
  80 void helper_outw(uint32_t port, uint32_t data)
  81 {
  82     cpu_outw(port, data & 0xffff);
  83 }
  84
  85 target_ulong helper_inw(uint32_t port)
  86 {
  87     return cpu_inw(port);
  88 }
  89
  90 void helper_outl(uint32_t port, uint32_t data)
  91 {
  92     cpu_outl(port, data);
  93 }
  94
  95 target_ulong helper_inl(uint32_t port)
  96 {
  97     return cpu_inl(port);
  98 }
  99
 100 void helper_into(CPUX86State *env, int next_eip_addend)
 101 {
 102     int eflags;
 103
 104     eflags = cpu_cc_compute_all(env, CC_OP);
 105     if (eflags & CC_O) {
 106         raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
 107     }
 108 }
 109
 110 void helper_single_step(CPUX86State *env)
 111 {
 112 #ifndef CONFIG_USER_ONLY
 113     check_hw_breakpoints(env, true);
 114     env->dr[6] |= DR6_BS;
 115 #endif
 116     raise_exception(env, EXCP01_DB);
 117 }
 118
 119 void helper_cpuid(CPUX86State *env)
 120 {
 121     uint32_t eax, ebx, ecx, edx;
 122
 123     cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
 124
 125     cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
 126                   &eax, &ebx, &ecx, &edx);
 127     env->regs[R_EAX] = eax;
 128     env->regs[R_EBX] = ebx;
 129     env->regs[R_ECX] = ecx;
 130     env->regs[R_EDX] = edx;
 131 }
 132
 133 #if defined(CONFIG_USER_ONLY)
 134 target_ulong helper_read_crN(CPUX86State *env, int reg)
 135 {
 136     return 0;
 137 }
 138
 139 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
 140 {
 141 }
 142
 143 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
 144 {
 145 }
 146 #else
 147 target_ulong helper_read_crN(CPUX86State *env, int reg)
 148 {
 149     target_ulong val;
 150
 151     cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
 152     switch (reg) {
 153     default:
 154         val = env->cr[reg];
 155         break;
 156     case 8:
 157         if (!(env->hflags2 & HF2_VINTR_MASK)) {
 158             val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
 159         } else {
 160             val = env->v_tpr;
 161         }
 162         break;
 163     }
 164     return val;
 165 }
 166
 167 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
 168 {
 169     cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
 170     switch (reg) {
 171     case 0:
 172         cpu_x86_update_cr0(env, t0);
 173         break;
 174     case 3:
 175         cpu_x86_update_cr3(env, t0);
 176         break;
 177     case 4:
 178         cpu_x86_update_cr4(env, t0);
 179         break;
 180     case 8:
 181         if (!(env->hflags2 & HF2_VINTR_MASK)) {
 182             cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
 183         }
 184         env->v_tpr = t0 & 0x0f;
 185         break;
 186     default:
 187         env->cr[reg] = t0;
 188         break;
 189     }
 190 }
 191
 192 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
 193 {
 194     int i;
 195
 196     if (reg < 4) {
 197         hw_breakpoint_remove(env, reg);
 198         env->dr[reg] = t0;
 199         hw_breakpoint_insert(env, reg);
 200     } else if (reg == 7) {
 201         for (i = 0; i < DR7_MAX_BP; i++) {
 202             hw_breakpoint_remove(env, i);
 203         }
 204         env->dr[7] = t0;
 205         for (i = 0; i < DR7_MAX_BP; i++) {
 206             hw_breakpoint_insert(env, i);
 207         }
 208     } else {
 209         env->dr[reg] = t0;
 210     }
 211 }
 212 #endif
 213
 214 void helper_lmsw(CPUX86State *env, target_ulong t0)
 215 {
 216     /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
 217        if already set to one. */
 218     t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
 219     helper_write_crN(env, 0, t0);
 220 }
 221
 222 void helper_invlpg(CPUX86State *env, target_ulong addr)
 223 {
 224     X86CPU *cpu = x86_env_get_cpu(env);
 225
 226     cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
 227     tlb_flush_page(CPU(cpu), addr);
 228 }
 229
 230 void helper_rdtsc(CPUX86State *env)
 231 {
 232     uint64_t val;
 233
 234     if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
 235         raise_exception(env, EXCP0D_GPF);
 236     }
 237     cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
 238
 239     val = cpu_get_tsc(env) + env->tsc_offset;
 240     env->regs[R_EAX] = (uint32_t)(val);
 241     env->regs[R_EDX] = (uint32_t)(val >> 32);
 242 }
 243
 244 void helper_rdtscp(CPUX86State *env)
 245 {
 246     helper_rdtsc(env);
 247     env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
 248 }
 249
 250 void helper_rdpmc(CPUX86State *env)
 251 {
 252     if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
 253         raise_exception(env, EXCP0D_GPF);
 254     }
 255     cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
 256
 257     /* currently unimplemented */
 258     qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
 259     raise_exception_err(env, EXCP06_ILLOP, 0);
 260 }
 261
 262 #if defined(CONFIG_USER_ONLY)
 263 void helper_wrmsr(CPUX86State *env)
 264 {
 265 }
 266
 267 void helper_rdmsr(CPUX86State *env)
 268 {
 269 }
 270 #else
 271 void helper_wrmsr(CPUX86State *env)
 272 {
 273     uint64_t val;
 274
 275     cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
 276
 277     val = ((uint32_t)env->regs[R_EAX]) |
 278         ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
 279
 280     switch ((uint32_t)env->regs[R_ECX]) {
 281     case MSR_IA32_SYSENTER_CS:
 282         env->sysenter_cs = val & 0xffff;
 283         break;
 284     case MSR_IA32_SYSENTER_ESP:
 285         env->sysenter_esp = val;
 286         break;
 287     case MSR_IA32_SYSENTER_EIP:
 288         env->sysenter_eip = val;
 289         break;
 290     case MSR_IA32_APICBASE:
 291         cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
 292         break;
 293     case MSR_EFER:
 294         {
 295             uint64_t update_mask;
 296
 297             update_mask = 0;
 298             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
 299                 update_mask |= MSR_EFER_SCE;
 300             }
 301             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
 302                 update_mask |= MSR_EFER_LME;
 303             }
 304             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
 305                 update_mask |= MSR_EFER_FFXSR;
 306             }
 307             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
 308                 update_mask |= MSR_EFER_NXE;
 309             }
 310             if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
 311                 update_mask |= MSR_EFER_SVME;
 312             }
 313             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
 314                 update_mask |= MSR_EFER_FFXSR;
 315             }
 316             cpu_load_efer(env, (env->efer & ~update_mask) |
 317                           (val & update_mask));
 318         }
 319         break;
 320     case MSR_STAR:
 321         env->star = val;
 322         break;
 323     case MSR_PAT:
 324         env->pat = val;
 325         break;
 326     case MSR_VM_HSAVE_PA:
 327         env->vm_hsave = val;
 328         break;
 329 #ifdef TARGET_X86_64
 330     case MSR_LSTAR:
 331         env->lstar = val;
 332         break;
 333     case MSR_CSTAR:
 334         env->cstar = val;
 335         break;
 336     case MSR_FMASK:
 337         env->fmask = val;
 338         break;
 339     case MSR_FSBASE:
 340         env->segs[R_FS].base = val;
 341         break;
 342     case MSR_GSBASE:
 343         env->segs[R_GS].base = val;
 344         break;
 345     case MSR_KERNELGSBASE:
 346         env->kernelgsbase = val;
 347         break;
 348 #endif
 349     case MSR_MTRRphysBase(0):
 350     case MSR_MTRRphysBase(1):
 351     case MSR_MTRRphysBase(2):
 352     case MSR_MTRRphysBase(3):
 353     case MSR_MTRRphysBase(4):
 354     case MSR_MTRRphysBase(5):
 355     case MSR_MTRRphysBase(6):
 356     case MSR_MTRRphysBase(7):
 357         env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 358                        MSR_MTRRphysBase(0)) / 2].base = val;
 359         break;
 360     case MSR_MTRRphysMask(0):
 361     case MSR_MTRRphysMask(1):
 362     case MSR_MTRRphysMask(2):
 363     case MSR_MTRRphysMask(3):
 364     case MSR_MTRRphysMask(4):
 365     case MSR_MTRRphysMask(5):
 366     case MSR_MTRRphysMask(6):
 367     case MSR_MTRRphysMask(7):
 368         env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 369                        MSR_MTRRphysMask(0)) / 2].mask = val;
 370         break;
 371     case MSR_MTRRfix64K_00000:
 372         env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 373                         MSR_MTRRfix64K_00000] = val;
 374         break;
 375     case MSR_MTRRfix16K_80000:
 376     case MSR_MTRRfix16K_A0000:
 377         env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 378                         MSR_MTRRfix16K_80000 + 1] = val;
 379         break;
 380     case MSR_MTRRfix4K_C0000:
 381     case MSR_MTRRfix4K_C8000:
 382     case MSR_MTRRfix4K_D0000:
 383     case MSR_MTRRfix4K_D8000:
 384     case MSR_MTRRfix4K_E0000:
 385     case MSR_MTRRfix4K_E8000:
 386     case MSR_MTRRfix4K_F0000:
 387     case MSR_MTRRfix4K_F8000:
 388         env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 389                         MSR_MTRRfix4K_C0000 + 3] = val;
 390         break;
 391     case MSR_MTRRdefType:
 392         env->mtrr_deftype = val;
 393         break;
 394     case MSR_MCG_STATUS:
 395         env->mcg_status = val;
 396         break;
 397     case MSR_MCG_CTL:
 398         if ((env->mcg_cap & MCG_CTL_P)
 399             && (val == 0 || val == ~(uint64_t)0)) {
 400             env->mcg_ctl = val;
 401         }
 402         break;
 403     case MSR_TSC_AUX:
 404         env->tsc_aux = val;
 405         break;
 406     case MSR_IA32_MISC_ENABLE:
 407         env->msr_ia32_misc_enable = val;
 408         break;
 409     default:
 410         if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
 411             && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
 412             (4 * env->mcg_cap & 0xff)) {
 413             uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
 414             if ((offset & 0x3) != 0
 415                 || (val == 0 || val == ~(uint64_t)0)) {
 416                 env->mce_banks[offset] = val;
 417             }
 418             break;
 419         }
 420         /* XXX: exception? */
 421         break;
 422     }
 423 }
 424
 425 void helper_rdmsr(CPUX86State *env)
 426 {
 427     uint64_t val;
 428
 429     cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
 430
 431     switch ((uint32_t)env->regs[R_ECX]) {
 432     case MSR_IA32_SYSENTER_CS:
 433         val = env->sysenter_cs;
 434         break;
 435     case MSR_IA32_SYSENTER_ESP:
 436         val = env->sysenter_esp;
 437         break;
 438     case MSR_IA32_SYSENTER_EIP:
 439         val = env->sysenter_eip;
 440         break;
 441     case MSR_IA32_APICBASE:
 442         val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
 443         break;
 444     case MSR_EFER:
 445         val = env->efer;
 446         break;
 447     case MSR_STAR:
 448         val = env->star;
 449         break;
 450     case MSR_PAT:
 451         val = env->pat;
 452         break;
 453     case MSR_VM_HSAVE_PA:
 454         val = env->vm_hsave;
 455         break;
 456     case MSR_IA32_PERF_STATUS:
 457         /* tsc_increment_by_tick */
 458         val = 1000ULL;
 459         /* CPU multiplier */
 460         val |= (((uint64_t)4ULL) << 40);
 461         break;
 462 #ifdef TARGET_X86_64
 463     case MSR_LSTAR:
 464         val = env->lstar;
 465         break;
 466     case MSR_CSTAR:
 467         val = env->cstar;
 468         break;
 469     case MSR_FMASK:
 470         val = env->fmask;
 471         break;
 472     case MSR_FSBASE:
 473         val = env->segs[R_FS].base;
 474         break;
 475     case MSR_GSBASE:
 476         val = env->segs[R_GS].base;
 477         break;
 478     case MSR_KERNELGSBASE:
 479         val = env->kernelgsbase;
 480         break;
 481     case MSR_TSC_AUX:
 482         val = env->tsc_aux;
 483         break;
 484 #endif
 485     case MSR_MTRRphysBase(0):
 486     case MSR_MTRRphysBase(1):
 487     case MSR_MTRRphysBase(2):
 488     case MSR_MTRRphysBase(3):
 489     case MSR_MTRRphysBase(4):
 490     case MSR_MTRRphysBase(5):
 491     case MSR_MTRRphysBase(6):
 492     case MSR_MTRRphysBase(7):
 493         val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 494                              MSR_MTRRphysBase(0)) / 2].base;
 495         break;
 496     case MSR_MTRRphysMask(0):
 497     case MSR_MTRRphysMask(1):
 498     case MSR_MTRRphysMask(2):
 499     case MSR_MTRRphysMask(3):
 500     case MSR_MTRRphysMask(4):
 501     case MSR_MTRRphysMask(5):
 502     case MSR_MTRRphysMask(6):
 503     case MSR_MTRRphysMask(7):
 504         val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 505                              MSR_MTRRphysMask(0)) / 2].mask;
 506         break;
 507     case MSR_MTRRfix64K_00000:
 508         val = env->mtrr_fixed[0];
 509         break;
 510     case MSR_MTRRfix16K_80000:
 511     case MSR_MTRRfix16K_A0000:
 512         val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 513                               MSR_MTRRfix16K_80000 + 1];
 514         break;
 515     case MSR_MTRRfix4K_C0000:
 516     case MSR_MTRRfix4K_C8000:
 517     case MSR_MTRRfix4K_D0000:
 518     case MSR_MTRRfix4K_D8000:
 519     case MSR_MTRRfix4K_E0000:
 520     case MSR_MTRRfix4K_E8000:
 521     case MSR_MTRRfix4K_F0000:
 522     case MSR_MTRRfix4K_F8000:
 523         val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 524                               MSR_MTRRfix4K_C0000 + 3];
 525         break;
 526     case MSR_MTRRdefType:
 527         val = env->mtrr_deftype;
 528         break;
 529     case MSR_MTRRcap:
 530         if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
 531             val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
 532                 MSR_MTRRcap_WC_SUPPORTED;
 533         } else {
 534             /* XXX: exception? */
 535             val = 0;
 536         }
 537         break;
 538     case MSR_MCG_CAP:
 539         val = env->mcg_cap;
 540         break;
 541     case MSR_MCG_CTL:
 542         if (env->mcg_cap & MCG_CTL_P) {
 543             val = env->mcg_ctl;
 544         } else {
 545             val = 0;
 546         }
 547         break;
 548     case MSR_MCG_STATUS:
 549         val = env->mcg_status;
 550         break;
 551     case MSR_IA32_MISC_ENABLE:
 552         val = env->msr_ia32_misc_enable;
 553         break;
 554     default:
 555         if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
 556             && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
 557             (4 * env->mcg_cap & 0xff)) {
 558             uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
 559             val = env->mce_banks[offset];
 560             break;
 561         }
 562         /* XXX: exception? */
 563         val = 0;
 564         break;
 565     }
 566     env->regs[R_EAX] = (uint32_t)(val);
 567     env->regs[R_EDX] = (uint32_t)(val >> 32);
 568 }
 569 #endif
 570
 571 static void do_pause(X86CPU *cpu)
 572 {
 573     CPUState *cs = CPU(cpu);
 574
 575     /* Just let another CPU run.  */
 576     cs->exception_index = EXCP_INTERRUPT;
 577     cpu_loop_exit(cs);
 578 }
 579
 580 static void do_hlt(X86CPU *cpu)
 581 {
 582     CPUState *cs = CPU(cpu);
 583     CPUX86State *env = &cpu->env;
 584
 585     env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
 586     cs->halted = 1;
 587     cs->exception_index = EXCP_HLT;
 588     cpu_loop_exit(cs);
 589 }
 590
 591 void helper_hlt(CPUX86State *env, int next_eip_addend)
 592 {
 593     X86CPU *cpu = x86_env_get_cpu(env);
 594
 595     cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
 596     env->eip += next_eip_addend;
 597
 598     do_hlt(cpu);
 599 }
 600
 601 void helper_monitor(CPUX86State *env, target_ulong ptr)
 602 {
 603     if ((uint32_t)env->regs[R_ECX] != 0) {
 604         raise_exception(env, EXCP0D_GPF);
 605     }
 606     /* XXX: store address? */
 607     cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
 608 }
 609
 610 void helper_mwait(CPUX86State *env, int next_eip_addend)
 611 {
 612     CPUState *cs;
 613     X86CPU *cpu;
 614
 615     if ((uint32_t)env->regs[R_ECX] != 0) {
 616         raise_exception(env, EXCP0D_GPF);
 617     }
 618     cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
 619     env->eip += next_eip_addend;
 620
 621     cpu = x86_env_get_cpu(env);
 622     cs = CPU(cpu);
 623     /* XXX: not complete but not completely erroneous */
 624     if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
 625         do_pause(cpu);
 626     } else {
 627         do_hlt(cpu);
 628     }
 629 }
 630
 631 void helper_pause(CPUX86State *env, int next_eip_addend)
 632 {
 633     X86CPU *cpu = x86_env_get_cpu(env);
 634
 635     cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0);
 636     env->eip += next_eip_addend;
 637
 638     do_pause(cpu);
 639 }
 640
 641 void helper_debug(CPUX86State *env)
 642 {
 643     CPUState *cs = CPU(x86_env_get_cpu(env));
 644
 645     cs->exception_index = EXCP_DEBUG;
 646     cpu_loop_exit(cs);
 647 }