target-s390x/ioinst.c

   1 /*
   2  * I/O instructions for S/390
   3  *
   4  * Copyright 2012, 2015 IBM Corp.
   5  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or (at
   8  * your option) any later version. See the COPYING file in the top-level
   9  * directory.
  10  */
  11
  12 #include <sys/types.h>
  13
  14 #include "cpu.h"
  15 #include "ioinst.h"
  16 #include "trace.h"
  17 #include "hw/s390x/s390-pci-bus.h"
  18
  19 int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
  20                                  int *schid)
  21 {
  22     if (!IOINST_SCHID_ONE(value)) {
  23         return -EINVAL;
  24     }
  25     if (!IOINST_SCHID_M(value)) {
  26         if (IOINST_SCHID_CSSID(value)) {
  27             return -EINVAL;
  28         }
  29         *cssid = 0;
  30         *m = 0;
  31     } else {
  32         *cssid = IOINST_SCHID_CSSID(value);
  33         *m = 1;
  34     }
  35     *ssid = IOINST_SCHID_SSID(value);
  36     *schid = IOINST_SCHID_NR(value);
  37     return 0;
  38 }
  39
  40 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1)
  41 {
  42     int cssid, ssid, schid, m;
  43     SubchDev *sch;
  44     int ret = -ENODEV;
  45     int cc;
  46
  47     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  48         program_interrupt(&cpu->env, PGM_OPERAND, 2);
  49         return;
  50     }
  51     trace_ioinst_sch_id("xsch", cssid, ssid, schid);
  52     sch = css_find_subch(m, cssid, ssid, schid);
  53     if (sch && css_subch_visible(sch)) {
  54         ret = css_do_xsch(sch);
  55     }
  56     switch (ret) {
  57     case -ENODEV:
  58         cc = 3;
  59         break;
  60     case -EBUSY:
  61         cc = 2;
  62         break;
  63     case 0:
  64         cc = 0;
  65         break;
  66     default:
  67         cc = 1;
  68         break;
  69     }
  70     setcc(cpu, cc);
  71 }
  72
  73 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1)
  74 {
  75     int cssid, ssid, schid, m;
  76     SubchDev *sch;
  77     int ret = -ENODEV;
  78     int cc;
  79
  80     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  81         program_interrupt(&cpu->env, PGM_OPERAND, 2);
  82         return;
  83     }
  84     trace_ioinst_sch_id("csch", cssid, ssid, schid);
  85     sch = css_find_subch(m, cssid, ssid, schid);
  86     if (sch && css_subch_visible(sch)) {
  87         ret = css_do_csch(sch);
  88     }
  89     if (ret == -ENODEV) {
  90         cc = 3;
  91     } else {
  92         cc = 0;
  93     }
  94     setcc(cpu, cc);
  95 }
  96
  97 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1)
  98 {
  99     int cssid, ssid, schid, m;
 100     SubchDev *sch;
 101     int ret = -ENODEV;
 102     int cc;
 103
 104     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 105         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 106         return;
 107     }
 108     trace_ioinst_sch_id("hsch", cssid, ssid, schid);
 109     sch = css_find_subch(m, cssid, ssid, schid);
 110     if (sch && css_subch_visible(sch)) {
 111         ret = css_do_hsch(sch);
 112     }
 113     switch (ret) {
 114     case -ENODEV:
 115         cc = 3;
 116         break;
 117     case -EBUSY:
 118         cc = 2;
 119         break;
 120     case 0:
 121         cc = 0;
 122         break;
 123     default:
 124         cc = 1;
 125         break;
 126     }
 127     setcc(cpu, cc);
 128 }
 129
 130 static int ioinst_schib_valid(SCHIB *schib)
 131 {
 132     if ((schib->pmcw.flags & PMCW_FLAGS_MASK_INVALID) ||
 133         (schib->pmcw.chars & PMCW_CHARS_MASK_INVALID)) {
 134         return 0;
 135     }
 136     /* Disallow extended measurements for now. */
 137     if (schib->pmcw.chars & PMCW_CHARS_MASK_XMWME) {
 138         return 0;
 139     }
 140     return 1;
 141 }
 142
 143 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 144 {
 145     int cssid, ssid, schid, m;
 146     SubchDev *sch;
 147     SCHIB schib;
 148     uint64_t addr;
 149     int ret = -ENODEV;
 150     int cc;
 151     CPUS390XState *env = &cpu->env;
 152
 153     addr = decode_basedisp_s(env, ipb);
 154     if (addr & 3) {
 155         program_interrupt(env, PGM_SPECIFICATION, 2);
 156         return;
 157     }
 158     if (s390_cpu_virt_mem_read(cpu, addr, &schib, sizeof(schib))) {
 159         return;
 160     }
 161     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 162         !ioinst_schib_valid(&schib)) {
 163         program_interrupt(env, PGM_OPERAND, 2);
 164         return;
 165     }
 166     trace_ioinst_sch_id("msch", cssid, ssid, schid);
 167     sch = css_find_subch(m, cssid, ssid, schid);
 168     if (sch && css_subch_visible(sch)) {
 169         ret = css_do_msch(sch, &schib);
 170     }
 171     switch (ret) {
 172     case -ENODEV:
 173         cc = 3;
 174         break;
 175     case -EBUSY:
 176         cc = 2;
 177         break;
 178     case 0:
 179         cc = 0;
 180         break;
 181     default:
 182         cc = 1;
 183         break;
 184     }
 185     setcc(cpu, cc);
 186 }
 187
 188 static void copy_orb_from_guest(ORB *dest, const ORB *src)
 189 {
 190     dest->intparm = be32_to_cpu(src->intparm);
 191     dest->ctrl0 = be16_to_cpu(src->ctrl0);
 192     dest->lpm = src->lpm;
 193     dest->ctrl1 = src->ctrl1;
 194     dest->cpa = be32_to_cpu(src->cpa);
 195 }
 196
 197 static int ioinst_orb_valid(ORB *orb)
 198 {
 199     if ((orb->ctrl0 & ORB_CTRL0_MASK_INVALID) ||
 200         (orb->ctrl1 & ORB_CTRL1_MASK_INVALID)) {
 201         return 0;
 202     }
 203     if ((orb->cpa & HIGH_ORDER_BIT) != 0) {
 204         return 0;
 205     }
 206     return 1;
 207 }
 208
 209 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 210 {
 211     int cssid, ssid, schid, m;
 212     SubchDev *sch;
 213     ORB orig_orb, orb;
 214     uint64_t addr;
 215     int ret = -ENODEV;
 216     int cc;
 217     CPUS390XState *env = &cpu->env;
 218
 219     addr = decode_basedisp_s(env, ipb);
 220     if (addr & 3) {
 221         program_interrupt(env, PGM_SPECIFICATION, 2);
 222         return;
 223     }
 224     if (s390_cpu_virt_mem_read(cpu, addr, &orig_orb, sizeof(orb))) {
 225         return;
 226     }
 227     copy_orb_from_guest(&orb, &orig_orb);
 228     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 229         !ioinst_orb_valid(&orb)) {
 230         program_interrupt(env, PGM_OPERAND, 2);
 231         return;
 232     }
 233     trace_ioinst_sch_id("ssch", cssid, ssid, schid);
 234     sch = css_find_subch(m, cssid, ssid, schid);
 235     if (sch && css_subch_visible(sch)) {
 236         ret = css_do_ssch(sch, &orb);
 237     }
 238     switch (ret) {
 239     case -ENODEV:
 240         cc = 3;
 241         break;
 242     case -EBUSY:
 243         cc = 2;
 244         break;
 245     case 0:
 246         cc = 0;
 247         break;
 248     default:
 249         cc = 1;
 250         break;
 251     }
 252     setcc(cpu, cc);
 253 }
 254
 255 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb)
 256 {
 257     CRW crw;
 258     uint64_t addr;
 259     int cc;
 260     CPUS390XState *env = &cpu->env;
 261
 262     addr = decode_basedisp_s(env, ipb);
 263     if (addr & 3) {
 264         program_interrupt(env, PGM_SPECIFICATION, 2);
 265         return;
 266     }
 267
 268     cc = css_do_stcrw(&crw);
 269     /* 0 - crw stored, 1 - zeroes stored */
 270
 271     if (s390_cpu_virt_mem_write(cpu, addr, &crw, sizeof(crw)) == 0) {
 272         setcc(cpu, cc);
 273     } else if (cc == 0) {
 274         /* Write failed: requeue CRW since STCRW is a suppressing instruction */
 275         css_undo_stcrw(&crw);
 276     }
 277 }
 278
 279 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 280 {
 281     int cssid, ssid, schid, m;
 282     SubchDev *sch;
 283     uint64_t addr;
 284     int cc;
 285     SCHIB schib;
 286     CPUS390XState *env = &cpu->env;
 287
 288     addr = decode_basedisp_s(env, ipb);
 289     if (addr & 3) {
 290         program_interrupt(env, PGM_SPECIFICATION, 2);
 291         return;
 292     }
 293
 294     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 295         /*
 296          * As operand exceptions have a lower priority than access exceptions,
 297          * we check whether the memory area is writeable (injecting the
 298          * access execption if it is not) first.
 299          */
 300         if (!s390_cpu_virt_mem_check_write(cpu, addr, sizeof(schib))) {
 301             program_interrupt(env, PGM_OPERAND, 2);
 302         }
 303         return;
 304     }
 305     trace_ioinst_sch_id("stsch", cssid, ssid, schid);
 306     sch = css_find_subch(m, cssid, ssid, schid);
 307     if (sch) {
 308         if (css_subch_visible(sch)) {
 309             css_do_stsch(sch, &schib);
 310             cc = 0;
 311         } else {
 312             /* Indicate no more subchannels in this css/ss */
 313             cc = 3;
 314         }
 315     } else {
 316         if (css_schid_final(m, cssid, ssid, schid)) {
 317             cc = 3; /* No more subchannels in this css/ss */
 318         } else {
 319             /* Store an empty schib. */
 320             memset(&schib, 0, sizeof(schib));
 321             cc = 0;
 322         }
 323     }
 324     if (cc != 3) {
 325         if (s390_cpu_virt_mem_write(cpu, addr, &schib, sizeof(schib)) != 0) {
 326             return;
 327         }
 328     } else {
 329         /* Access exceptions have a higher priority than cc3 */
 330         if (s390_cpu_virt_mem_check_write(cpu, addr, sizeof(schib)) != 0) {
 331             return;
 332         }
 333     }
 334     setcc(cpu, cc);
 335 }
 336
 337 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 338 {
 339     CPUS390XState *env = &cpu->env;
 340     int cssid, ssid, schid, m;
 341     SubchDev *sch;
 342     IRB irb;
 343     uint64_t addr;
 344     int cc, irb_len;
 345
 346     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 347         program_interrupt(env, PGM_OPERAND, 2);
 348         return -EIO;
 349     }
 350     trace_ioinst_sch_id("tsch", cssid, ssid, schid);
 351     addr = decode_basedisp_s(env, ipb);
 352     if (addr & 3) {
 353         program_interrupt(env, PGM_SPECIFICATION, 2);
 354         return -EIO;
 355     }
 356
 357     sch = css_find_subch(m, cssid, ssid, schid);
 358     if (sch && css_subch_visible(sch)) {
 359         cc = css_do_tsch_get_irb(sch, &irb, &irb_len);
 360     } else {
 361         cc = 3;
 362     }
 363     /* 0 - status pending, 1 - not status pending, 3 - not operational */
 364     if (cc != 3) {
 365         if (s390_cpu_virt_mem_write(cpu, addr, &irb, irb_len) != 0) {
 366             return -EFAULT;
 367         }
 368         css_do_tsch_update_subch(sch);
 369     } else {
 370         irb_len = sizeof(irb) - sizeof(irb.emw);
 371         /* Access exceptions have a higher priority than cc3 */
 372         if (s390_cpu_virt_mem_check_write(cpu, addr, irb_len) != 0) {
 373             return -EFAULT;
 374         }
 375     }
 376
 377     setcc(cpu, cc);
 378     return 0;
 379 }
 380
 381 typedef struct ChscReq {
 382     uint16_t len;
 383     uint16_t command;
 384     uint32_t param0;
 385     uint32_t param1;
 386     uint32_t param2;
 387 } QEMU_PACKED ChscReq;
 388
 389 typedef struct ChscResp {
 390     uint16_t len;
 391     uint16_t code;
 392     uint32_t param;
 393     char data[0];
 394 } QEMU_PACKED ChscResp;
 395
 396 #define CHSC_MIN_RESP_LEN 0x0008
 397
 398 #define CHSC_SCPD 0x0002
 399 #define CHSC_SCSC 0x0010
 400 #define CHSC_SDA  0x0031
 401 #define CHSC_SEI  0x000e
 402
 403 #define CHSC_SCPD_0_M 0x20000000
 404 #define CHSC_SCPD_0_C 0x10000000
 405 #define CHSC_SCPD_0_FMT 0x0f000000
 406 #define CHSC_SCPD_0_CSSID 0x00ff0000
 407 #define CHSC_SCPD_0_RFMT 0x00000f00
 408 #define CHSC_SCPD_0_RES 0xc000f000
 409 #define CHSC_SCPD_1_RES 0xffffff00
 410 #define CHSC_SCPD_01_CHPID 0x000000ff
 411 static void ioinst_handle_chsc_scpd(ChscReq *req, ChscResp *res)
 412 {
 413     uint16_t len = be16_to_cpu(req->len);
 414     uint32_t param0 = be32_to_cpu(req->param0);
 415     uint32_t param1 = be32_to_cpu(req->param1);
 416     uint16_t resp_code;
 417     int rfmt;
 418     uint16_t cssid;
 419     uint8_t f_chpid, l_chpid;
 420     int desc_size;
 421     int m;
 422
 423     rfmt = (param0 & CHSC_SCPD_0_RFMT) >> 8;
 424     if ((rfmt == 0) ||  (rfmt == 1)) {
 425         rfmt = !!(param0 & CHSC_SCPD_0_C);
 426     }
 427     if ((len != 0x0010) || (param0 & CHSC_SCPD_0_RES) ||
 428         (param1 & CHSC_SCPD_1_RES) || req->param2) {
 429         resp_code = 0x0003;
 430         goto out_err;
 431     }
 432     if (param0 & CHSC_SCPD_0_FMT) {
 433         resp_code = 0x0007;
 434         goto out_err;
 435     }
 436     cssid = (param0 & CHSC_SCPD_0_CSSID) >> 16;
 437     m = param0 & CHSC_SCPD_0_M;
 438     if (cssid != 0) {
 439         if (!m || !css_present(cssid)) {
 440             resp_code = 0x0008;
 441             goto out_err;
 442         }
 443     }
 444     f_chpid = param0 & CHSC_SCPD_01_CHPID;
 445     l_chpid = param1 & CHSC_SCPD_01_CHPID;
 446     if (l_chpid < f_chpid) {
 447         resp_code = 0x0003;
 448         goto out_err;
 449     }
 450     /* css_collect_chp_desc() is endian-aware */
 451     desc_size = css_collect_chp_desc(m, cssid, f_chpid, l_chpid, rfmt,
 452                                      &res->data);
 453     res->code = cpu_to_be16(0x0001);
 454     res->len = cpu_to_be16(8 + desc_size);
 455     res->param = cpu_to_be32(rfmt);
 456     return;
 457
 458   out_err:
 459     res->code = cpu_to_be16(resp_code);
 460     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 461     res->param = cpu_to_be32(rfmt);
 462 }
 463
 464 #define CHSC_SCSC_0_M 0x20000000
 465 #define CHSC_SCSC_0_FMT 0x000f0000
 466 #define CHSC_SCSC_0_CSSID 0x0000ff00
 467 #define CHSC_SCSC_0_RES 0xdff000ff
 468 static void ioinst_handle_chsc_scsc(ChscReq *req, ChscResp *res)
 469 {
 470     uint16_t len = be16_to_cpu(req->len);
 471     uint32_t param0 = be32_to_cpu(req->param0);
 472     uint8_t cssid;
 473     uint16_t resp_code;
 474     uint32_t general_chars[510];
 475     uint32_t chsc_chars[508];
 476
 477     if (len != 0x0010) {
 478         resp_code = 0x0003;
 479         goto out_err;
 480     }
 481
 482     if (param0 & CHSC_SCSC_0_FMT) {
 483         resp_code = 0x0007;
 484         goto out_err;
 485     }
 486     cssid = (param0 & CHSC_SCSC_0_CSSID) >> 8;
 487     if (cssid != 0) {
 488         if (!(param0 & CHSC_SCSC_0_M) || !css_present(cssid)) {
 489             resp_code = 0x0008;
 490             goto out_err;
 491         }
 492     }
 493     if ((param0 & CHSC_SCSC_0_RES) || req->param1 || req->param2) {
 494         resp_code = 0x0003;
 495         goto out_err;
 496     }
 497     res->code = cpu_to_be16(0x0001);
 498     res->len = cpu_to_be16(4080);
 499     res->param = 0;
 500
 501     memset(general_chars, 0, sizeof(general_chars));
 502     memset(chsc_chars, 0, sizeof(chsc_chars));
 503
 504     general_chars[0] = cpu_to_be32(0x03000000);
 505     general_chars[1] = cpu_to_be32(0x00059000);
 506
 507     chsc_chars[0] = cpu_to_be32(0x40000000);
 508     chsc_chars[3] = cpu_to_be32(0x00040000);
 509
 510     memcpy(res->data, general_chars, sizeof(general_chars));
 511     memcpy(res->data + sizeof(general_chars), chsc_chars, sizeof(chsc_chars));
 512     return;
 513
 514   out_err:
 515     res->code = cpu_to_be16(resp_code);
 516     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 517     res->param = 0;
 518 }
 519
 520 #define CHSC_SDA_0_FMT 0x0f000000
 521 #define CHSC_SDA_0_OC 0x0000ffff
 522 #define CHSC_SDA_0_RES 0xf0ff0000
 523 #define CHSC_SDA_OC_MCSSE 0x0
 524 #define CHSC_SDA_OC_MSS 0x2
 525 static void ioinst_handle_chsc_sda(ChscReq *req, ChscResp *res)
 526 {
 527     uint16_t resp_code = 0x0001;
 528     uint16_t len = be16_to_cpu(req->len);
 529     uint32_t param0 = be32_to_cpu(req->param0);
 530     uint16_t oc;
 531     int ret;
 532
 533     if ((len != 0x0400) || (param0 & CHSC_SDA_0_RES)) {
 534         resp_code = 0x0003;
 535         goto out;
 536     }
 537
 538     if (param0 & CHSC_SDA_0_FMT) {
 539         resp_code = 0x0007;
 540         goto out;
 541     }
 542
 543     oc = param0 & CHSC_SDA_0_OC;
 544     switch (oc) {
 545     case CHSC_SDA_OC_MCSSE:
 546         ret = css_enable_mcsse();
 547         if (ret == -EINVAL) {
 548             resp_code = 0x0101;
 549             goto out;
 550         }
 551         break;
 552     case CHSC_SDA_OC_MSS:
 553         ret = css_enable_mss();
 554         if (ret == -EINVAL) {
 555             resp_code = 0x0101;
 556             goto out;
 557         }
 558         break;
 559     default:
 560         resp_code = 0x0003;
 561         goto out;
 562     }
 563
 564 out:
 565     res->code = cpu_to_be16(resp_code);
 566     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 567     res->param = 0;
 568 }
 569
 570 static int chsc_sei_nt0_get_event(void *res)
 571 {
 572     /* no events yet */
 573     return 1;
 574 }
 575
 576 static int chsc_sei_nt0_have_event(void)
 577 {
 578     /* no events yet */
 579     return 0;
 580 }
 581
 582 #define CHSC_SEI_NT0    (1ULL << 63)
 583 #define CHSC_SEI_NT2    (1ULL << 61)
 584 static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)
 585 {
 586     uint64_t selection_mask = ldq_p(&req->param1);
 587     uint8_t *res_flags = (uint8_t *)res->data;
 588     int have_event = 0;
 589     int have_more = 0;
 590
 591     /* regarding architecture nt0 can not be masked */
 592     have_event = !chsc_sei_nt0_get_event(res);
 593     have_more = chsc_sei_nt0_have_event();
 594
 595     if (selection_mask & CHSC_SEI_NT2) {
 596         if (!have_event) {
 597             have_event = !chsc_sei_nt2_get_event(res);
 598         }
 599
 600         if (!have_more) {
 601             have_more = chsc_sei_nt2_have_event();
 602         }
 603     }
 604
 605     if (have_event) {
 606         res->code = cpu_to_be16(0x0001);
 607         if (have_more) {
 608             (*res_flags) |= 0x80;
 609         } else {
 610             (*res_flags) &= ~0x80;
 611         }
 612     } else {
 613         res->code = cpu_to_be16(0x0004);
 614     }
 615 }
 616
 617 static void ioinst_handle_chsc_unimplemented(ChscResp *res)
 618 {
 619     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 620     res->code = cpu_to_be16(0x0004);
 621     res->param = 0;
 622 }
 623
 624 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb)
 625 {
 626     ChscReq *req;
 627     ChscResp *res;
 628     uint64_t addr;
 629     int reg;
 630     uint16_t len;
 631     uint16_t command;
 632     CPUS390XState *env = &cpu->env;
 633     uint8_t buf[TARGET_PAGE_SIZE];
 634
 635     trace_ioinst("chsc");
 636     reg = (ipb >> 20) & 0x00f;
 637     addr = env->regs[reg];
 638     /* Page boundary? */
 639     if (addr & 0xfff) {
 640         program_interrupt(env, PGM_SPECIFICATION, 2);
 641         return;
 642     }
 643     /*
 644      * Reading sizeof(ChscReq) bytes is currently enough for all of our
 645      * present CHSC sub-handlers ... if we ever need more, we should take
 646      * care of req->len here first.
 647      */
 648     if (s390_cpu_virt_mem_read(cpu, addr, buf, sizeof(ChscReq))) {
 649         return;
 650     }
 651     req = (ChscReq *)buf;
 652     len = be16_to_cpu(req->len);
 653     /* Length field valid? */
 654     if ((len < 16) || (len > 4088) || (len & 7)) {
 655         program_interrupt(env, PGM_OPERAND, 2);
 656         return;
 657     }
 658     memset((char *)req + len, 0, TARGET_PAGE_SIZE - len);
 659     res = (void *)((char *)req + len);
 660     command = be16_to_cpu(req->command);
 661     trace_ioinst_chsc_cmd(command, len);
 662     switch (command) {
 663     case CHSC_SCSC:
 664         ioinst_handle_chsc_scsc(req, res);
 665         break;
 666     case CHSC_SCPD:
 667         ioinst_handle_chsc_scpd(req, res);
 668         break;
 669     case CHSC_SDA:
 670         ioinst_handle_chsc_sda(req, res);
 671         break;
 672     case CHSC_SEI:
 673         ioinst_handle_chsc_sei(req, res);
 674         break;
 675     default:
 676         ioinst_handle_chsc_unimplemented(res);
 677         break;
 678     }
 679
 680     if (!s390_cpu_virt_mem_write(cpu, addr + len, res, be16_to_cpu(res->len))) {
 681         setcc(cpu, 0);    /* Command execution complete */
 682     }
 683 }
 684
 685 int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb)
 686 {
 687     CPUS390XState *env = &cpu->env;
 688     uint64_t addr;
 689     int lowcore;
 690     IOIntCode int_code;
 691     hwaddr len;
 692     int ret;
 693
 694     trace_ioinst("tpi");
 695     addr = decode_basedisp_s(env, ipb);
 696     if (addr & 3) {
 697         program_interrupt(env, PGM_SPECIFICATION, 2);
 698         return -EIO;
 699     }
 700
 701     lowcore = addr ? 0 : 1;
 702     len = lowcore ? 8 /* two words */ : 12 /* three words */;
 703     ret = css_do_tpi(&int_code, lowcore);
 704     if (ret == 1) {
 705         s390_cpu_virt_mem_write(cpu, lowcore ? 184 : addr, &int_code, len);
 706     }
 707     return ret;
 708 }
 709
 710 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
 711 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
 712 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
 713 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
 714
 715 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
 716                         uint32_t ipb)
 717 {
 718     uint8_t mbk;
 719     int update;
 720     int dct;
 721     CPUS390XState *env = &cpu->env;
 722
 723     trace_ioinst("schm");
 724
 725     if (SCHM_REG1_RES(reg1)) {
 726         program_interrupt(env, PGM_OPERAND, 2);
 727         return;
 728     }
 729
 730     mbk = SCHM_REG1_MBK(reg1);
 731     update = SCHM_REG1_UPD(reg1);
 732     dct = SCHM_REG1_DCT(reg1);
 733
 734     if (update && (reg2 & 0x000000000000001f)) {
 735         program_interrupt(env, PGM_OPERAND, 2);
 736         return;
 737     }
 738
 739     css_do_schm(mbk, update, dct, update ? reg2 : 0);
 740 }
 741
 742 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1)
 743 {
 744     int cssid, ssid, schid, m;
 745     SubchDev *sch;
 746     int ret = -ENODEV;
 747     int cc;
 748
 749     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 750         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 751         return;
 752     }
 753     trace_ioinst_sch_id("rsch", cssid, ssid, schid);
 754     sch = css_find_subch(m, cssid, ssid, schid);
 755     if (sch && css_subch_visible(sch)) {
 756         ret = css_do_rsch(sch);
 757     }
 758     switch (ret) {
 759     case -ENODEV:
 760         cc = 3;
 761         break;
 762     case -EINVAL:
 763         cc = 2;
 764         break;
 765     case 0:
 766         cc = 0;
 767         break;
 768     default:
 769         cc = 1;
 770         break;
 771     }
 772     setcc(cpu, cc);
 773 }
 774
 775 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
 776 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
 777 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
 778 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1)
 779 {
 780     int cc;
 781     uint8_t cssid;
 782     uint8_t chpid;
 783     int ret;
 784     CPUS390XState *env = &cpu->env;
 785
 786     if (RCHP_REG1_RES(reg1)) {
 787         program_interrupt(env, PGM_OPERAND, 2);
 788         return;
 789     }
 790
 791     cssid = RCHP_REG1_CSSID(reg1);
 792     chpid = RCHP_REG1_CHPID(reg1);
 793
 794     trace_ioinst_chp_id("rchp", cssid, chpid);
 795
 796     ret = css_do_rchp(cssid, chpid);
 797
 798     switch (ret) {
 799     case -ENODEV:
 800         cc = 3;
 801         break;
 802     case -EBUSY:
 803         cc = 2;
 804         break;
 805     case 0:
 806         cc = 0;
 807         break;
 808     default:
 809         /* Invalid channel subsystem. */
 810         program_interrupt(env, PGM_OPERAND, 2);
 811         return;
 812     }
 813     setcc(cpu, cc);
 814 }
 815
 816 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
 817 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1)
 818 {
 819     /* We do not provide address limit checking, so let's suppress it. */
 820     if (SAL_REG1_INVALID(reg1) || reg1 & 0x000000000000ffff) {
 821         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 822     }
 823 }