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Rename variables and rearrange code to please gcc -Wshadow checks
[qemu/qemu_0_9_1_stable.git] / vl.h
blob4a072a90a97f9344d464cd1407e78c3643cb99e7
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef MIN
97 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
98 #endif
99 #ifndef MAX
100 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
101 #endif
102
103 /* cutils.c */
104 void pstrcpy(char *buf, int buf_size, const char *str);
105 char *pstrcat(char *buf, int buf_size, const char *s);
106 int strstart(const char *str, const char *val, const char **ptr);
107 int stristart(const char *str, const char *val, const char **ptr);
108
109 /* vl.c */
110 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
111
112 void hw_error(const char *fmt, ...);
113
114 extern const char *bios_dir;
115
116 extern int vm_running;
117 extern const char *qemu_name;
118
119 typedef struct vm_change_state_entry VMChangeStateEntry;
120 typedef void VMChangeStateHandler(void *opaque, int running);
121 typedef void VMStopHandler(void *opaque, int reason);
122
123 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
124 void *opaque);
125 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
126
127 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
128 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
129
130 void vm_start(void);
131 void vm_stop(int reason);
132
133 typedef void QEMUResetHandler(void *opaque);
134
135 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
136 void qemu_system_reset_request(void);
137 void qemu_system_shutdown_request(void);
138 void qemu_system_powerdown_request(void);
139 #if !defined(TARGET_SPARC)
140 // Please implement a power failure function to signal the OS
141 #define qemu_system_powerdown() do{}while(0)
142 #else
143 void qemu_system_powerdown(void);
144 #endif
145
146 void main_loop_wait(int timeout);
147
148 extern int ram_size;
149 extern int bios_size;
150 extern int rtc_utc;
151 extern int cirrus_vga_enabled;
152 extern int vmsvga_enabled;
153 extern int graphic_width;
154 extern int graphic_height;
155 extern int graphic_depth;
156 extern const char *keyboard_layout;
157 extern int kqemu_allowed;
158 extern int win2k_install_hack;
159 extern int alt_grab;
160 extern int usb_enabled;
161 extern int smp_cpus;
162 extern int cursor_hide;
163 extern int graphic_rotate;
164 extern int no_quit;
165 extern int semihosting_enabled;
166 extern int autostart;
167 extern const char *bootp_filename;
168
169 #define MAX_OPTION_ROMS 16
170 extern const char *option_rom[MAX_OPTION_ROMS];
171 extern int nb_option_roms;
172
173 #ifdef TARGET_SPARC
174 #define MAX_PROM_ENVS 128
175 extern const char *prom_envs[MAX_PROM_ENVS];
176 extern unsigned int nb_prom_envs;
177 #endif
178
179 /* XXX: make it dynamic */
180 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
181 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
182 #define BIOS_SIZE ((512 + 32) * 1024)
183 #elif defined(TARGET_MIPS)
184 #define BIOS_SIZE (4 * 1024 * 1024)
185 #endif
186
187 /* keyboard/mouse support */
188
189 #define MOUSE_EVENT_LBUTTON 0x01
190 #define MOUSE_EVENT_RBUTTON 0x02
191 #define MOUSE_EVENT_MBUTTON 0x04
192
193 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
194 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
195
196 typedef struct QEMUPutMouseEntry {
197 QEMUPutMouseEvent *qemu_put_mouse_event;
198 void *qemu_put_mouse_event_opaque;
199 int qemu_put_mouse_event_absolute;
200 char *qemu_put_mouse_event_name;
201
202 /* used internally by qemu for handling mice */
203 struct QEMUPutMouseEntry *next;
204 } QEMUPutMouseEntry;
205
206 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
207 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
208 void *opaque, int absolute,
209 const char *name);
210 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
211
212 void kbd_put_keycode(int keycode);
213 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
214 int kbd_mouse_is_absolute(void);
215
216 void do_info_mice(void);
217 void do_mouse_set(int index);
218
219 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
220 constants) */
221 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
222 #define QEMU_KEY_BACKSPACE 0x007f
223 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
224 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
225 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
226 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
227 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
228 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
229 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
230 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
231 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
232
233 #define QEMU_KEY_CTRL_UP 0xe400
234 #define QEMU_KEY_CTRL_DOWN 0xe401
235 #define QEMU_KEY_CTRL_LEFT 0xe402
236 #define QEMU_KEY_CTRL_RIGHT 0xe403
237 #define QEMU_KEY_CTRL_HOME 0xe404
238 #define QEMU_KEY_CTRL_END 0xe405
239 #define QEMU_KEY_CTRL_PAGEUP 0xe406
240 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
241
242 void kbd_put_keysym(int keysym);
243
244 /* async I/O support */
245
246 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
247 typedef int IOCanRWHandler(void *opaque);
248 typedef void IOHandler(void *opaque);
249
250 int qemu_set_fd_handler2(int fd,
251 IOCanRWHandler *fd_read_poll,
252 IOHandler *fd_read,
253 IOHandler *fd_write,
254 void *opaque);
255 int qemu_set_fd_handler(int fd,
256 IOHandler *fd_read,
257 IOHandler *fd_write,
258 void *opaque);
259
260 /* Polling handling */
261
262 /* return TRUE if no sleep should be done afterwards */
263 typedef int PollingFunc(void *opaque);
264
265 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
266 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
267
268 #ifdef _WIN32
269 /* Wait objects handling */
270 typedef void WaitObjectFunc(void *opaque);
271
272 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
273 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
274 #endif
275
276 typedef struct QEMUBH QEMUBH;
277
278 /* character device */
279
280 #define CHR_EVENT_BREAK 0 /* serial break char */
281 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
282 #define CHR_EVENT_RESET 2 /* new connection established */
283
284
285 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
286 typedef struct {
287 int speed;
288 int parity;
289 int data_bits;
290 int stop_bits;
291 } QEMUSerialSetParams;
292
293 #define CHR_IOCTL_SERIAL_SET_BREAK 2
294
295 #define CHR_IOCTL_PP_READ_DATA 3
296 #define CHR_IOCTL_PP_WRITE_DATA 4
297 #define CHR_IOCTL_PP_READ_CONTROL 5
298 #define CHR_IOCTL_PP_WRITE_CONTROL 6
299 #define CHR_IOCTL_PP_READ_STATUS 7
300 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
301 #define CHR_IOCTL_PP_EPP_READ 9
302 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
303 #define CHR_IOCTL_PP_EPP_WRITE 11
304
305 typedef void IOEventHandler(void *opaque, int event);
306
307 typedef struct CharDriverState {
308 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
309 void (*chr_update_read_handler)(struct CharDriverState *s);
310 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
311 IOEventHandler *chr_event;
312 IOCanRWHandler *chr_can_read;
313 IOReadHandler *chr_read;
314 void *handler_opaque;
315 void (*chr_send_event)(struct CharDriverState *chr, int event);
316 void (*chr_close)(struct CharDriverState *chr);
317 void *opaque;
318 int focus;
319 QEMUBH *bh;
320 } CharDriverState;
321
322 CharDriverState *qemu_chr_open(const char *filename);
323 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
324 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
325 void qemu_chr_send_event(CharDriverState *s, int event);
326 void qemu_chr_add_handlers(CharDriverState *s,
327 IOCanRWHandler *fd_can_read,
328 IOReadHandler *fd_read,
329 IOEventHandler *fd_event,
330 void *opaque);
331 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
332 void qemu_chr_reset(CharDriverState *s);
333 int qemu_chr_can_read(CharDriverState *s);
334 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
335
336 /* consoles */
337
338 typedef struct DisplayState DisplayState;
339 typedef struct TextConsole TextConsole;
340
341 typedef void (*vga_hw_update_ptr)(void *);
342 typedef void (*vga_hw_invalidate_ptr)(void *);
343 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
344
345 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
346 vga_hw_invalidate_ptr invalidate,
347 vga_hw_screen_dump_ptr screen_dump,
348 void *opaque);
349 void vga_hw_update(void);
350 void vga_hw_invalidate(void);
351 void vga_hw_screen_dump(const char *filename);
352
353 int is_graphic_console(void);
354 CharDriverState *text_console_init(DisplayState *ds);
355 void console_select(unsigned int index);
356
357 /* serial ports */
358
359 #define MAX_SERIAL_PORTS 4
360
361 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
362
363 /* parallel ports */
364
365 #define MAX_PARALLEL_PORTS 3
366
367 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
368
369 struct ParallelIOArg {
370 void *buffer;
371 int count;
372 };
373
374 /* VLANs support */
375
376 typedef struct VLANClientState VLANClientState;
377
378 struct VLANClientState {
379 IOReadHandler *fd_read;
380 /* Packets may still be sent if this returns zero. It's used to
381 rate-limit the slirp code. */
382 IOCanRWHandler *fd_can_read;
383 void *opaque;
384 struct VLANClientState *next;
385 struct VLANState *vlan;
386 char info_str[256];
387 };
388
389 typedef struct VLANState {
390 int id;
391 VLANClientState *first_client;
392 struct VLANState *next;
393 unsigned int nb_guest_devs, nb_host_devs;
394 } VLANState;
395
396 VLANState *qemu_find_vlan(int id);
397 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
398 IOReadHandler *fd_read,
399 IOCanRWHandler *fd_can_read,
400 void *opaque);
401 int qemu_can_send_packet(VLANClientState *vc);
402 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
403 void qemu_handler_true(void *opaque);
404
405 void do_info_network(void);
406
407 /* TAP win32 */
408 int tap_win32_init(VLANState *vlan, const char *ifname);
409
410 /* NIC info */
411
412 #define MAX_NICS 8
413
414 typedef struct NICInfo {
415 uint8_t macaddr[6];
416 const char *model;
417 VLANState *vlan;
418 } NICInfo;
419
420 extern int nb_nics;
421 extern NICInfo nd_table[MAX_NICS];
422
423 /* timers */
424
425 typedef struct QEMUClock QEMUClock;
426 typedef struct QEMUTimer QEMUTimer;
427 typedef void QEMUTimerCB(void *opaque);
428
429 /* The real time clock should be used only for stuff which does not
430 change the virtual machine state, as it is run even if the virtual
431 machine is stopped. The real time clock has a frequency of 1000
432 Hz. */
433 extern QEMUClock *rt_clock;
434
435 /* The virtual clock is only run during the emulation. It is stopped
436 when the virtual machine is stopped. Virtual timers use a high
437 precision clock, usually cpu cycles (use ticks_per_sec). */
438 extern QEMUClock *vm_clock;
439
440 int64_t qemu_get_clock(QEMUClock *clock);
441
442 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
443 void qemu_free_timer(QEMUTimer *ts);
444 void qemu_del_timer(QEMUTimer *ts);
445 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
446 int qemu_timer_pending(QEMUTimer *ts);
447
448 extern int64_t ticks_per_sec;
449 extern int pit_min_timer_count;
450
451 int64_t cpu_get_ticks(void);
452 void cpu_enable_ticks(void);
453 void cpu_disable_ticks(void);
454
455 /* VM Load/Save */
456
457 typedef struct QEMUFile QEMUFile;
458
459 QEMUFile *qemu_fopen(const char *filename, const char *mode);
460 void qemu_fflush(QEMUFile *f);
461 void qemu_fclose(QEMUFile *f);
462 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
463 void qemu_put_byte(QEMUFile *f, int v);
464 void qemu_put_be16(QEMUFile *f, unsigned int v);
465 void qemu_put_be32(QEMUFile *f, unsigned int v);
466 void qemu_put_be64(QEMUFile *f, uint64_t v);
467 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
468 int qemu_get_byte(QEMUFile *f);
469 unsigned int qemu_get_be16(QEMUFile *f);
470 unsigned int qemu_get_be32(QEMUFile *f);
471 uint64_t qemu_get_be64(QEMUFile *f);
472
473 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
474 {
475 qemu_put_be64(f, *pv);
476 }
477
478 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
479 {
480 qemu_put_be32(f, *pv);
481 }
482
483 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
484 {
485 qemu_put_be16(f, *pv);
486 }
487
488 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
489 {
490 qemu_put_byte(f, *pv);
491 }
492
493 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
494 {
495 *pv = qemu_get_be64(f);
496 }
497
498 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
499 {
500 *pv = qemu_get_be32(f);
501 }
502
503 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
504 {
505 *pv = qemu_get_be16(f);
506 }
507
508 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
509 {
510 *pv = qemu_get_byte(f);
511 }
512
513 #if TARGET_LONG_BITS == 64
514 #define qemu_put_betl qemu_put_be64
515 #define qemu_get_betl qemu_get_be64
516 #define qemu_put_betls qemu_put_be64s
517 #define qemu_get_betls qemu_get_be64s
518 #else
519 #define qemu_put_betl qemu_put_be32
520 #define qemu_get_betl qemu_get_be32
521 #define qemu_put_betls qemu_put_be32s
522 #define qemu_get_betls qemu_get_be32s
523 #endif
524
525 int64_t qemu_ftell(QEMUFile *f);
526 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
527
528 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
529 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
530
531 int register_savevm(const char *idstr,
532 int instance_id,
533 int version_id,
534 SaveStateHandler *save_state,
535 LoadStateHandler *load_state,
536 void *opaque);
537 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
538 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
539
540 void cpu_save(QEMUFile *f, void *opaque);
541 int cpu_load(QEMUFile *f, void *opaque, int version_id);
542
543 void do_savevm(const char *name);
544 void do_loadvm(const char *name);
545 void do_delvm(const char *name);
546 void do_info_snapshots(void);
547
548 /* bottom halves */
549 typedef void QEMUBHFunc(void *opaque);
550
551 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
552 void qemu_bh_schedule(QEMUBH *bh);
553 void qemu_bh_cancel(QEMUBH *bh);
554 void qemu_bh_delete(QEMUBH *bh);
555 int qemu_bh_poll(void);
556
557 /* block.c */
558 typedef struct BlockDriverState BlockDriverState;
559 typedef struct BlockDriver BlockDriver;
560
561 extern BlockDriver bdrv_raw;
562 extern BlockDriver bdrv_host_device;
563 extern BlockDriver bdrv_cow;
564 extern BlockDriver bdrv_qcow;
565 extern BlockDriver bdrv_vmdk;
566 extern BlockDriver bdrv_cloop;
567 extern BlockDriver bdrv_dmg;
568 extern BlockDriver bdrv_bochs;
569 extern BlockDriver bdrv_vpc;
570 extern BlockDriver bdrv_vvfat;
571 extern BlockDriver bdrv_qcow2;
572
573 typedef struct BlockDriverInfo {
574 /* in bytes, 0 if irrelevant */
575 int cluster_size;
576 /* offset at which the VM state can be saved (0 if not possible) */
577 int64_t vm_state_offset;
578 } BlockDriverInfo;
579
580 typedef struct QEMUSnapshotInfo {
581 char id_str[128]; /* unique snapshot id */
582 /* the following fields are informative. They are not needed for
583 the consistency of the snapshot */
584 char name[256]; /* user choosen name */
585 uint32_t vm_state_size; /* VM state info size */
586 uint32_t date_sec; /* UTC date of the snapshot */
587 uint32_t date_nsec;
588 uint64_t vm_clock_nsec; /* VM clock relative to boot */
589 } QEMUSnapshotInfo;
590
591 #define BDRV_O_RDONLY 0x0000
592 #define BDRV_O_RDWR 0x0002
593 #define BDRV_O_ACCESS 0x0003
594 #define BDRV_O_CREAT 0x0004 /* create an empty file */
595 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
596 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
597 use a disk image format on top of
598 it (default for
599 bdrv_file_open()) */
600
601 void bdrv_init(void);
602 BlockDriver *bdrv_find_format(const char *format_name);
603 int bdrv_create(BlockDriver *drv,
604 const char *filename, int64_t size_in_sectors,
605 const char *backing_file, int flags);
606 BlockDriverState *bdrv_new(const char *device_name);
607 void bdrv_delete(BlockDriverState *bs);
608 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
609 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
610 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
611 BlockDriver *drv);
612 void bdrv_close(BlockDriverState *bs);
613 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
614 uint8_t *buf, int nb_sectors);
615 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
616 const uint8_t *buf, int nb_sectors);
617 int bdrv_pread(BlockDriverState *bs, int64_t offset,
618 void *buf, int count);
619 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
620 const void *buf, int count);
621 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
622 int64_t bdrv_getlength(BlockDriverState *bs);
623 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
624 int bdrv_commit(BlockDriverState *bs);
625 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
626 /* async block I/O */
627 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
628 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
629
630 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
631 uint8_t *buf, int nb_sectors,
632 BlockDriverCompletionFunc *cb, void *opaque);
633 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
634 const uint8_t *buf, int nb_sectors,
635 BlockDriverCompletionFunc *cb, void *opaque);
636 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
637
638 void qemu_aio_init(void);
639 void qemu_aio_poll(void);
640 void qemu_aio_flush(void);
641 void qemu_aio_wait_start(void);
642 void qemu_aio_wait(void);
643 void qemu_aio_wait_end(void);
644
645 int qemu_key_check(BlockDriverState *bs, const char *name);
646
647 /* Ensure contents are flushed to disk. */
648 void bdrv_flush(BlockDriverState *bs);
649
650 #define BDRV_TYPE_HD 0
651 #define BDRV_TYPE_CDROM 1
652 #define BDRV_TYPE_FLOPPY 2
653 #define BIOS_ATA_TRANSLATION_AUTO 0
654 #define BIOS_ATA_TRANSLATION_NONE 1
655 #define BIOS_ATA_TRANSLATION_LBA 2
656 #define BIOS_ATA_TRANSLATION_LARGE 3
657 #define BIOS_ATA_TRANSLATION_RECHS 4
658
659 void bdrv_set_geometry_hint(BlockDriverState *bs,
660 int cyls, int heads, int secs);
661 void bdrv_set_type_hint(BlockDriverState *bs, int type);
662 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
663 void bdrv_get_geometry_hint(BlockDriverState *bs,
664 int *pcyls, int *pheads, int *psecs);
665 int bdrv_get_type_hint(BlockDriverState *bs);
666 int bdrv_get_translation_hint(BlockDriverState *bs);
667 int bdrv_is_removable(BlockDriverState *bs);
668 int bdrv_is_read_only(BlockDriverState *bs);
669 int bdrv_is_inserted(BlockDriverState *bs);
670 int bdrv_media_changed(BlockDriverState *bs);
671 int bdrv_is_locked(BlockDriverState *bs);
672 void bdrv_set_locked(BlockDriverState *bs, int locked);
673 void bdrv_eject(BlockDriverState *bs, int eject_flag);
674 void bdrv_set_change_cb(BlockDriverState *bs,
675 void (*change_cb)(void *opaque), void *opaque);
676 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
677 void bdrv_info(void);
678 BlockDriverState *bdrv_find(const char *name);
679 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
680 int bdrv_is_encrypted(BlockDriverState *bs);
681 int bdrv_set_key(BlockDriverState *bs, const char *key);
682 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
683 void *opaque);
684 const char *bdrv_get_device_name(BlockDriverState *bs);
685 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
686 const uint8_t *buf, int nb_sectors);
687 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
688
689 void bdrv_get_backing_filename(BlockDriverState *bs,
690 char *filename, int filename_size);
691 int bdrv_snapshot_create(BlockDriverState *bs,
692 QEMUSnapshotInfo *sn_info);
693 int bdrv_snapshot_goto(BlockDriverState *bs,
694 const char *snapshot_id);
695 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
696 int bdrv_snapshot_list(BlockDriverState *bs,
697 QEMUSnapshotInfo **psn_info);
698 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
699
700 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
701 int path_is_absolute(const char *path);
702 void path_combine(char *dest, int dest_size,
703 const char *base_path,
704 const char *filename);
705
706 #ifndef QEMU_TOOL
707
708 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
709 int boot_device,
710 DisplayState *ds, const char **fd_filename, int snapshot,
711 const char *kernel_filename, const char *kernel_cmdline,
712 const char *initrd_filename, const char *cpu_model);
713
714 typedef struct QEMUMachine {
715 const char *name;
716 const char *desc;
717 QEMUMachineInitFunc *init;
718 struct QEMUMachine *next;
719 } QEMUMachine;
720
721 int qemu_register_machine(QEMUMachine *m);
722
723 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
724
725 #if defined(TARGET_PPC)
726 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
727 #endif
728
729 #if defined(TARGET_MIPS)
730 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
731 #endif
732
733 #include "hw/irq.h"
734
735 /* ISA bus */
736
737 extern target_phys_addr_t isa_mem_base;
738
739 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
740 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
741
742 int register_ioport_read(int start, int length, int size,
743 IOPortReadFunc *func, void *opaque);
744 int register_ioport_write(int start, int length, int size,
745 IOPortWriteFunc *func, void *opaque);
746 void isa_unassign_ioport(int start, int length);
747
748 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
749
750 /* PCI bus */
751
752 extern target_phys_addr_t pci_mem_base;
753
754 typedef struct PCIBus PCIBus;
755 typedef struct PCIDevice PCIDevice;
756
757 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
758 uint32_t address, uint32_t data, int len);
759 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
760 uint32_t address, int len);
761 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
762 uint32_t addr, uint32_t size, int type);
763
764 #define PCI_ADDRESS_SPACE_MEM 0x00
765 #define PCI_ADDRESS_SPACE_IO 0x01
766 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
767
768 typedef struct PCIIORegion {
769 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
770 uint32_t size;
771 uint8_t type;
772 PCIMapIORegionFunc *map_func;
773 } PCIIORegion;
774
775 #define PCI_ROM_SLOT 6
776 #define PCI_NUM_REGIONS 7
777
778 #define PCI_DEVICES_MAX 64
779
780 #define PCI_VENDOR_ID 0x00 /* 16 bits */
781 #define PCI_DEVICE_ID 0x02 /* 16 bits */
782 #define PCI_COMMAND 0x04 /* 16 bits */
783 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
784 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
785 #define PCI_CLASS_DEVICE 0x0a /* Device class */
786 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
787 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
788 #define PCI_MIN_GNT 0x3e /* 8 bits */
789 #define PCI_MAX_LAT 0x3f /* 8 bits */
790
791 struct PCIDevice {
792 /* PCI config space */
793 uint8_t config[256];
794
795 /* the following fields are read only */
796 PCIBus *bus;
797 int devfn;
798 char name[64];
799 PCIIORegion io_regions[PCI_NUM_REGIONS];
800
801 /* do not access the following fields */
802 PCIConfigReadFunc *config_read;
803 PCIConfigWriteFunc *config_write;
804 /* ??? This is a PC-specific hack, and should be removed. */
805 int irq_index;
806
807 /* IRQ objects for the INTA-INTD pins. */
808 qemu_irq *irq;
809
810 /* Current IRQ levels. Used internally by the generic PCI code. */
811 int irq_state[4];
812 };
813
814 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
815 int instance_size, int devfn,
816 PCIConfigReadFunc *config_read,
817 PCIConfigWriteFunc *config_write);
818
819 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
820 uint32_t size, int type,
821 PCIMapIORegionFunc *map_func);
822
823 uint32_t pci_default_read_config(PCIDevice *d,
824 uint32_t address, int len);
825 void pci_default_write_config(PCIDevice *d,
826 uint32_t address, uint32_t val, int len);
827 void pci_device_save(PCIDevice *s, QEMUFile *f);
828 int pci_device_load(PCIDevice *s, QEMUFile *f);
829
830 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
831 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
832 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
833 qemu_irq *pic, int devfn_min, int nirq);
834
835 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
836 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
837 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
838 int pci_bus_num(PCIBus *s);
839 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
840
841 void pci_info(void);
842 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
843 pci_map_irq_fn map_irq, const char *name);
844
845 /* prep_pci.c */
846 PCIBus *pci_prep_init(qemu_irq *pic);
847
848 /* grackle_pci.c */
849 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
850
851 /* unin_pci.c */
852 PCIBus *pci_pmac_init(qemu_irq *pic);
853
854 /* apb_pci.c */
855 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
856 qemu_irq *pic);
857
858 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
859
860 /* piix_pci.c */
861 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
862 void i440fx_set_smm(PCIDevice *d, int val);
863 int piix3_init(PCIBus *bus, int devfn);
864 void i440fx_init_memory_mappings(PCIDevice *d);
865
866 int piix4_init(PCIBus *bus, int devfn);
867
868 /* openpic.c */
869 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
870 enum {
871 OPENPIC_OUTPUT_INT = 0, /* IRQ */
872 OPENPIC_OUTPUT_CINT, /* critical IRQ */
873 OPENPIC_OUTPUT_MCK, /* Machine check event */
874 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
875 OPENPIC_OUTPUT_RESET, /* Core reset event */
876 OPENPIC_OUTPUT_NB,
877 };
878 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
879 qemu_irq **irqs, qemu_irq irq_out);
880
881 /* heathrow_pic.c */
882 qemu_irq *heathrow_pic_init(int *pmem_index);
883
884 /* gt64xxx.c */
885 PCIBus *pci_gt64120_init(qemu_irq *pic);
886
887 #ifdef HAS_AUDIO
888 struct soundhw {
889 const char *name;
890 const char *descr;
891 int enabled;
892 int isa;
893 union {
894 int (*init_isa) (AudioState *s, qemu_irq *pic);
895 int (*init_pci) (PCIBus *bus, AudioState *s);
896 } init;
897 };
898
899 extern struct soundhw soundhw[];
900 #endif
901
902 /* vga.c */
903
904 #ifndef TARGET_SPARC
905 #define VGA_RAM_SIZE (8192 * 1024)
906 #else
907 #define VGA_RAM_SIZE (9 * 1024 * 1024)
908 #endif
909
910 struct DisplayState {
911 uint8_t *data;
912 int linesize;
913 int depth;
914 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
915 int width;
916 int height;
917 void *opaque;
918 QEMUTimer *gui_timer;
919
920 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
921 void (*dpy_resize)(struct DisplayState *s, int w, int h);
922 void (*dpy_refresh)(struct DisplayState *s);
923 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
924 int dst_x, int dst_y, int w, int h);
925 void (*dpy_fill)(struct DisplayState *s, int x, int y,
926 int w, int h, uint32_t c);
927 void (*mouse_set)(int x, int y, int on);
928 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
929 uint8_t *image, uint8_t *mask);
930 };
931
932 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
933 {
934 s->dpy_update(s, x, y, w, h);
935 }
936
937 static inline void dpy_resize(DisplayState *s, int w, int h)
938 {
939 s->dpy_resize(s, w, h);
940 }
941
942 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
943 unsigned long vga_ram_offset, int vga_ram_size);
944 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
945 unsigned long vga_ram_offset, int vga_ram_size,
946 unsigned long vga_bios_offset, int vga_bios_size);
947 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
948 unsigned long vga_ram_offset, int vga_ram_size,
949 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
950 int it_shift);
951
952 /* cirrus_vga.c */
953 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
954 unsigned long vga_ram_offset, int vga_ram_size);
955 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
956 unsigned long vga_ram_offset, int vga_ram_size);
957
958 /* vmware_vga.c */
959 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
960 unsigned long vga_ram_offset, int vga_ram_size);
961
962 /* sdl.c */
963 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
964
965 /* cocoa.m */
966 void cocoa_display_init(DisplayState *ds, int full_screen);
967
968 /* vnc.c */
969 void vnc_display_init(DisplayState *ds, const char *display);
970 void do_info_vnc(void);
971
972 /* x_keymap.c */
973 extern uint8_t _translate_keycode(const int key);
974
975 /* ide.c */
976 #define MAX_DISKS 4
977
978 extern BlockDriverState *bs_table[MAX_DISKS + 1];
979 extern BlockDriverState *sd_bdrv;
980 extern BlockDriverState *mtd_bdrv;
981
982 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
983 BlockDriverState *hd0, BlockDriverState *hd1);
984 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
985 int secondary_ide_enabled);
986 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
987 qemu_irq *pic);
988 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
989 qemu_irq *pic);
990 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
991
992 /* cdrom.c */
993 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
994 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
995
996 /* ds1225y.c */
997 typedef struct ds1225y_t ds1225y_t;
998 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
999
1000 /* es1370.c */
1001 int es1370_init (PCIBus *bus, AudioState *s);
1002
1003 /* sb16.c */
1004 int SB16_init (AudioState *s, qemu_irq *pic);
1005
1006 /* adlib.c */
1007 int Adlib_init (AudioState *s, qemu_irq *pic);
1008
1009 /* gus.c */
1010 int GUS_init (AudioState *s, qemu_irq *pic);
1011
1012 /* dma.c */
1013 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1014 int DMA_get_channel_mode (int nchan);
1015 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1016 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1017 void DMA_hold_DREQ (int nchan);
1018 void DMA_release_DREQ (int nchan);
1019 void DMA_schedule(int nchan);
1020 void DMA_run (void);
1021 void DMA_init (int high_page_enable);
1022 void DMA_register_channel (int nchan,
1023 DMA_transfer_handler transfer_handler,
1024 void *opaque);
1025 /* fdc.c */
1026 #define MAX_FD 2
1027 extern BlockDriverState *fd_table[MAX_FD];
1028
1029 typedef struct fdctrl_t fdctrl_t;
1030
1031 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1032 target_phys_addr_t io_base,
1033 BlockDriverState **fds);
1034 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1035
1036 /* eepro100.c */
1037
1038 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1039 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1040 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1041
1042 /* ne2000.c */
1043
1044 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1045 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1046
1047 /* rtl8139.c */
1048
1049 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1050
1051 /* pcnet.c */
1052
1053 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1054 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1055 qemu_irq irq);
1056
1057 /* vmmouse.c */
1058 void *vmmouse_init(void *m);
1059
1060 /* pckbd.c */
1061
1062 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1063 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1064 target_phys_addr_t base, int it_shift);
1065
1066 /* mc146818rtc.c */
1067
1068 typedef struct RTCState RTCState;
1069
1070 RTCState *rtc_init(int base, qemu_irq irq);
1071 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1072 void rtc_set_memory(RTCState *s, int addr, int val);
1073 void rtc_set_date(RTCState *s, const struct tm *tm);
1074
1075 /* serial.c */
1076
1077 typedef struct SerialState SerialState;
1078 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1079 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1080 qemu_irq irq, CharDriverState *chr,
1081 int ioregister);
1082 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1083 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1084 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1085 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1086 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1087 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1088
1089 /* parallel.c */
1090
1091 typedef struct ParallelState ParallelState;
1092 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1093 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1094
1095 /* i8259.c */
1096
1097 typedef struct PicState2 PicState2;
1098 extern PicState2 *isa_pic;
1099 void pic_set_irq(int irq, int level);
1100 void pic_set_irq_new(void *opaque, int irq, int level);
1101 qemu_irq *i8259_init(qemu_irq parent_irq);
1102 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1103 void *alt_irq_opaque);
1104 int pic_read_irq(PicState2 *s);
1105 void pic_update_irq(PicState2 *s);
1106 uint32_t pic_intack_read(PicState2 *s);
1107 void pic_info(void);
1108 void irq_info(void);
1109
1110 /* APIC */
1111 typedef struct IOAPICState IOAPICState;
1112
1113 int apic_init(CPUState *env);
1114 int apic_get_interrupt(CPUState *env);
1115 IOAPICState *ioapic_init(void);
1116 void ioapic_set_irq(void *opaque, int vector, int level);
1117
1118 /* i8254.c */
1119
1120 #define PIT_FREQ 1193182
1121
1122 typedef struct PITState PITState;
1123
1124 PITState *pit_init(int base, qemu_irq irq);
1125 void pit_set_gate(PITState *pit, int channel, int val);
1126 int pit_get_gate(PITState *pit, int channel);
1127 int pit_get_initial_count(PITState *pit, int channel);
1128 int pit_get_mode(PITState *pit, int channel);
1129 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1130
1131 /* jazz_led.c */
1132 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1133
1134 /* pcspk.c */
1135 void pcspk_init(PITState *);
1136 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1137
1138 #include "hw/i2c.h"
1139
1140 #include "hw/smbus.h"
1141
1142 /* acpi.c */
1143 extern int acpi_enabled;
1144 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1145 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1146 void acpi_bios_init(void);
1147
1148 /* pc.c */
1149 extern QEMUMachine pc_machine;
1150 extern QEMUMachine isapc_machine;
1151 extern int fd_bootchk;
1152
1153 void ioport_set_a20(int enable);
1154 int ioport_get_a20(void);
1155
1156 /* ppc.c */
1157 extern QEMUMachine prep_machine;
1158 extern QEMUMachine core99_machine;
1159 extern QEMUMachine heathrow_machine;
1160 extern QEMUMachine ref405ep_machine;
1161 extern QEMUMachine taihu_machine;
1162
1163 /* mips_r4k.c */
1164 extern QEMUMachine mips_machine;
1165
1166 /* mips_malta.c */
1167 extern QEMUMachine mips_malta_machine;
1168
1169 /* mips_int.c */
1170 extern void cpu_mips_irq_init_cpu(CPUState *env);
1171
1172 /* mips_pica61.c */
1173 extern QEMUMachine mips_pica61_machine;
1174
1175 /* mips_timer.c */
1176 extern void cpu_mips_clock_init(CPUState *);
1177 extern void cpu_mips_irqctrl_init (void);
1178
1179 /* shix.c */
1180 extern QEMUMachine shix_machine;
1181
1182 #ifdef TARGET_PPC
1183 /* PowerPC hardware exceptions management helpers */
1184 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1185 typedef struct clk_setup_t clk_setup_t;
1186 struct clk_setup_t {
1187 clk_setup_cb cb;
1188 void *opaque;
1189 };
1190 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1191 {
1192 if (clk->cb != NULL)
1193 (*clk->cb)(clk->opaque, freq);
1194 }
1195
1196 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1197 /* Embedded PowerPC DCR management */
1198 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1199 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1200 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1201 int (*dcr_write_error)(int dcrn));
1202 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1203 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1204 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1205 /* Embedded PowerPC reset */
1206 void ppc40x_core_reset (CPUState *env);
1207 void ppc40x_chip_reset (CPUState *env);
1208 void ppc40x_system_reset (CPUState *env);
1209 #endif
1210 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1211
1212 extern CPUWriteMemoryFunc *PPC_io_write[];
1213 extern CPUReadMemoryFunc *PPC_io_read[];
1214 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1215
1216 /* sun4m.c */
1217 extern QEMUMachine ss5_machine, ss10_machine;
1218
1219 /* iommu.c */
1220 void *iommu_init(target_phys_addr_t addr);
1221 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1222 uint8_t *buf, int len, int is_write);
1223 static inline void sparc_iommu_memory_read(void *opaque,
1224 target_phys_addr_t addr,
1225 uint8_t *buf, int len)
1226 {
1227 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1228 }
1229
1230 static inline void sparc_iommu_memory_write(void *opaque,
1231 target_phys_addr_t addr,
1232 uint8_t *buf, int len)
1233 {
1234 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1235 }
1236
1237 /* tcx.c */
1238 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1239 unsigned long vram_offset, int vram_size, int width, int height,
1240 int depth);
1241
1242 /* slavio_intctl.c */
1243 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1244 const uint32_t *intbit_to_level,
1245 qemu_irq **irq, qemu_irq **cpu_irq,
1246 qemu_irq **parent_irq, unsigned int cputimer);
1247 void slavio_pic_info(void *opaque);
1248 void slavio_irq_info(void *opaque);
1249
1250 /* loader.c */
1251 int get_image_size(const char *filename);
1252 int load_image(const char *filename, uint8_t *addr);
1253 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1254 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1255 int load_aout(const char *filename, uint8_t *addr);
1256 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1257
1258 /* slavio_timer.c */
1259 void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1260
1261 /* slavio_serial.c */
1262 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1263 CharDriverState *chr1, CharDriverState *chr2);
1264 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1265
1266 /* slavio_misc.c */
1267 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1268 qemu_irq irq);
1269 void slavio_set_power_fail(void *opaque, int power_failing);
1270
1271 /* esp.c */
1272 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1273 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1274 void *dma_opaque, qemu_irq irq);
1275
1276 /* sparc32_dma.c */
1277 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1278 void *iommu, qemu_irq **dev_irq);
1279 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1280 uint8_t *buf, int len, int do_bswap);
1281 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1282 uint8_t *buf, int len, int do_bswap);
1283 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1284 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1285 void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
1286 void *dev_opaque);
1287
1288 /* cs4231.c */
1289 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1290
1291 /* sun4u.c */
1292 extern QEMUMachine sun4u_machine;
1293
1294 /* NVRAM helpers */
1295 #include "hw/m48t59.h"
1296
1297 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1298 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1299 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1300 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1301 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1302 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1303 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1304 const unsigned char *str, uint32_t max);
1305 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1306 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1307 uint32_t start, uint32_t count);
1308 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1309 const unsigned char *arch,
1310 uint32_t RAM_size, int boot_device,
1311 uint32_t kernel_image, uint32_t kernel_size,
1312 const char *cmdline,
1313 uint32_t initrd_image, uint32_t initrd_size,
1314 uint32_t NVRAM_image,
1315 int width, int height, int depth);
1316
1317 /* adb.c */
1318
1319 #define MAX_ADB_DEVICES 16
1320
1321 #define ADB_MAX_OUT_LEN 16
1322
1323 typedef struct ADBDevice ADBDevice;
1324
1325 /* buf = NULL means polling */
1326 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1327 const uint8_t *buf, int len);
1328 typedef int ADBDeviceReset(ADBDevice *d);
1329
1330 struct ADBDevice {
1331 struct ADBBusState *bus;
1332 int devaddr;
1333 int handler;
1334 ADBDeviceRequest *devreq;
1335 ADBDeviceReset *devreset;
1336 void *opaque;
1337 };
1338
1339 typedef struct ADBBusState {
1340 ADBDevice devices[MAX_ADB_DEVICES];
1341 int nb_devices;
1342 int poll_index;
1343 } ADBBusState;
1344
1345 int adb_request(ADBBusState *s, uint8_t *buf_out,
1346 const uint8_t *buf, int len);
1347 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1348
1349 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1350 ADBDeviceRequest *devreq,
1351 ADBDeviceReset *devreset,
1352 void *opaque);
1353 void adb_kbd_init(ADBBusState *bus);
1354 void adb_mouse_init(ADBBusState *bus);
1355
1356 /* cuda.c */
1357
1358 extern ADBBusState adb_bus;
1359 int cuda_init(qemu_irq irq);
1360
1361 #include "hw/usb.h"
1362
1363 /* usb ports of the VM */
1364
1365 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1366 usb_attachfn attach);
1367
1368 #define VM_USB_HUB_SIZE 8
1369
1370 void do_usb_add(const char *devname);
1371 void do_usb_del(const char *devname);
1372 void usb_info(void);
1373
1374 /* scsi-disk.c */
1375 enum scsi_reason {
1376 SCSI_REASON_DONE, /* Command complete. */
1377 SCSI_REASON_DATA /* Transfer complete, more data required. */
1378 };
1379
1380 typedef struct SCSIDevice SCSIDevice;
1381 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1382 uint32_t arg);
1383
1384 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1385 int tcq,
1386 scsi_completionfn completion,
1387 void *opaque);
1388 void scsi_disk_destroy(SCSIDevice *s);
1389
1390 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1391 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1392 layer the completion routine may be called directly by
1393 scsi_{read,write}_data. */
1394 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1395 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1396 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1397 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1398
1399 /* lsi53c895a.c */
1400 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1401 void *lsi_scsi_init(PCIBus *bus, int devfn);
1402
1403 /* integratorcp.c */
1404 extern QEMUMachine integratorcp_machine;
1405
1406 /* versatilepb.c */
1407 extern QEMUMachine versatilepb_machine;
1408 extern QEMUMachine versatileab_machine;
1409
1410 /* realview.c */
1411 extern QEMUMachine realview_machine;
1412
1413 /* spitz.c */
1414 extern QEMUMachine akitapda_machine;
1415 extern QEMUMachine spitzpda_machine;
1416 extern QEMUMachine borzoipda_machine;
1417 extern QEMUMachine terrierpda_machine;
1418
1419 /* ps2.c */
1420 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1421 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1422 void ps2_write_mouse(void *, int val);
1423 void ps2_write_keyboard(void *, int val);
1424 uint32_t ps2_read_data(void *);
1425 void ps2_queue(void *, int b);
1426 void ps2_keyboard_set_translation(void *opaque, int mode);
1427 void ps2_mouse_fake_event(void *opaque);
1428
1429 /* smc91c111.c */
1430 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1431
1432 /* pl110.c */
1433 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1434
1435 /* pl011.c */
1436 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1437
1438 /* pl050.c */
1439 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1440
1441 /* pl080.c */
1442 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1443
1444 /* pl181.c */
1445 void pl181_init(uint32_t base, BlockDriverState *bd,
1446 qemu_irq irq0, qemu_irq irq1);
1447
1448 /* pl190.c */
1449 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1450
1451 /* arm-timer.c */
1452 void sp804_init(uint32_t base, qemu_irq irq);
1453 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1454
1455 /* arm_sysctl.c */
1456 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1457
1458 /* arm_gic.c */
1459 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1460
1461 /* arm_boot.c */
1462
1463 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1464 const char *kernel_cmdline, const char *initrd_filename,
1465 int board_id, target_phys_addr_t loader_start);
1466
1467 /* sh7750.c */
1468 struct SH7750State;
1469
1470 struct SH7750State *sh7750_init(CPUState * cpu);
1471
1472 typedef struct {
1473 /* The callback will be triggered if any of the designated lines change */
1474 uint16_t portamask_trigger;
1475 uint16_t portbmask_trigger;
1476 /* Return 0 if no action was taken */
1477 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1478 uint16_t * periph_pdtra,
1479 uint16_t * periph_portdira,
1480 uint16_t * periph_pdtrb,
1481 uint16_t * periph_portdirb);
1482 } sh7750_io_device;
1483
1484 int sh7750_register_io_device(struct SH7750State *s,
1485 sh7750_io_device * device);
1486 /* tc58128.c */
1487 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1488
1489 /* NOR flash devices */
1490 #define MAX_PFLASH 4
1491 extern BlockDriverState *pflash_table[MAX_PFLASH];
1492 typedef struct pflash_t pflash_t;
1493
1494 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1495 BlockDriverState *bs,
1496 uint32_t sector_len, int nb_blocs, int width,
1497 uint16_t id0, uint16_t id1,
1498 uint16_t id2, uint16_t id3);
1499
1500 /* nand.c */
1501 struct nand_flash_s;
1502 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1503 void nand_done(struct nand_flash_s *s);
1504 void nand_setpins(struct nand_flash_s *s,
1505 int cle, int ale, int ce, int wp, int gnd);
1506 void nand_getpins(struct nand_flash_s *s, int *rb);
1507 void nand_setio(struct nand_flash_s *s, uint8_t value);
1508 uint8_t nand_getio(struct nand_flash_s *s);
1509
1510 #define NAND_MFR_TOSHIBA 0x98
1511 #define NAND_MFR_SAMSUNG 0xec
1512 #define NAND_MFR_FUJITSU 0x04
1513 #define NAND_MFR_NATIONAL 0x8f
1514 #define NAND_MFR_RENESAS 0x07
1515 #define NAND_MFR_STMICRO 0x20
1516 #define NAND_MFR_HYNIX 0xad
1517 #define NAND_MFR_MICRON 0x2c
1518
1519 #include "ecc.h"
1520
1521 /* GPIO */
1522 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1523
1524 /* ads7846.c */
1525 struct ads7846_state_s;
1526 uint32_t ads7846_read(void *opaque);
1527 void ads7846_write(void *opaque, uint32_t value);
1528 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1529
1530 /* max111x.c */
1531 struct max111x_s;
1532 uint32_t max111x_read(void *opaque);
1533 void max111x_write(void *opaque, uint32_t value);
1534 struct max111x_s *max1110_init(qemu_irq cb);
1535 struct max111x_s *max1111_init(qemu_irq cb);
1536 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1537
1538 /* PCMCIA/Cardbus */
1539
1540 struct pcmcia_socket_s {
1541 qemu_irq irq;
1542 int attached;
1543 const char *slot_string;
1544 const char *card_string;
1545 };
1546
1547 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1548 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1549 void pcmcia_info(void);
1550
1551 struct pcmcia_card_s {
1552 void *state;
1553 struct pcmcia_socket_s *slot;
1554 int (*attach)(void *state);
1555 int (*detach)(void *state);
1556 const uint8_t *cis;
1557 int cis_len;
1558
1559 /* Only valid if attached */
1560 uint8_t (*attr_read)(void *state, uint32_t address);
1561 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1562 uint16_t (*common_read)(void *state, uint32_t address);
1563 void (*common_write)(void *state, uint32_t address, uint16_t value);
1564 uint16_t (*io_read)(void *state, uint32_t address);
1565 void (*io_write)(void *state, uint32_t address, uint16_t value);
1566 };
1567
1568 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1569 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1570 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1571 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1572 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1573 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1574 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1575 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1576 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1577 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1578 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1579 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1580 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1581 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1582 #define CISTPL_END 0xff /* Tuple End */
1583 #define CISTPL_ENDMARK 0xff
1584
1585 /* dscm1xxxx.c */
1586 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1587
1588 /* ptimer.c */
1589 typedef struct ptimer_state ptimer_state;
1590 typedef void (*ptimer_cb)(void *opaque);
1591
1592 ptimer_state *ptimer_init(QEMUBH *bh);
1593 void ptimer_set_period(ptimer_state *s, int64_t period);
1594 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1595 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1596 uint64_t ptimer_get_count(ptimer_state *s);
1597 void ptimer_set_count(ptimer_state *s, uint64_t count);
1598 void ptimer_run(ptimer_state *s, int oneshot);
1599 void ptimer_stop(ptimer_state *s);
1600 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1601 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1602
1603 #include "hw/pxa.h"
1604
1605 /* mcf_uart.c */
1606 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1607 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1608 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1609 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1610 CharDriverState *chr);
1611
1612 /* mcf_intc.c */
1613 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1614
1615 /* mcf_fec.c */
1616 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1617
1618 /* mcf5206.c */
1619 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1620
1621 /* an5206.c */
1622 extern QEMUMachine an5206_machine;
1623
1624 /* mcf5208.c */
1625 extern QEMUMachine mcf5208evb_machine;
1626
1627 #include "gdbstub.h"
1628
1629 #endif /* defined(QEMU_TOOL) */
1630
1631 /* monitor.c */
1632 void monitor_init(CharDriverState *hd, int show_banner);
1633 void term_puts(const char *str);
1634 void term_vprintf(const char *fmt, va_list ap);
1635 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1636 void term_print_filename(const char *filename);
1637 void term_flush(void);
1638 void term_print_help(void);
1639 void monitor_readline(const char *prompt, int is_password,
1640 char *buf, int buf_size);
1641
1642 /* readline.c */
1643 typedef void ReadLineFunc(void *opaque, const char *str);
1644
1645 extern int completion_index;
1646 void add_completion(const char *str);
1647 void readline_handle_byte(int ch);
1648 void readline_find_completion(const char *cmdline);
1649 const char *readline_get_history(unsigned int index);
1650 void readline_start(const char *prompt, int is_password,
1651 ReadLineFunc *readline_func, void *opaque);
1652
1653 void kqemu_record_dump(void);
1654
1655 #endif /* VL_H */
Stable branch of Qemu 0.9.1