2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag
;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env
->jmp_env
, 1);
51 /* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
54 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
56 #if !defined(CONFIG_SOFTMMU)
57 struct ucontext
*uc
= puc
;
62 /* XXX: restore cpu registers saved in host registers */
64 #if !defined(CONFIG_SOFTMMU)
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
70 longjmp(env
->jmp_env
, 1);
73 /* main execution loop */
75 int cpu_exec(CPUState
*env1
)
77 int saved_T0
, saved_T1
, saved_T2
;
104 int saved_i7
, tmp_T0
;
106 int code_gen_size
, ret
, interrupt_request
;
107 void (*gen_func
)(void);
108 TranslationBlock
*tb
, **ptb
;
109 target_ulong cs_base
, pc
;
113 /* first we save global registers */
120 /* we also save i7 because longjmp may not restore it */
121 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
124 #if defined(TARGET_I386)
151 /* put eflags in CPU temporary format */
152 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
153 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
154 CC_OP
= CC_OP_EFLAGS
;
155 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
156 #elif defined(TARGET_ARM)
160 env
->CF
= (psr
>> 29) & 1;
161 env
->NZF
= (psr
& 0xc0000000) ^ 0x40000000;
162 env
->VF
= (psr
<< 3) & 0x80000000;
163 env
->QF
= (psr
>> 27) & 1;
164 env
->cpsr
= psr
& ~CACHED_CPSR_BITS
;
166 #elif defined(TARGET_SPARC)
167 #elif defined(TARGET_PPC)
169 #error unsupported target CPU
171 env
->exception_index
= -1;
173 /* prepare setjmp context for exception handling */
175 if (setjmp(env
->jmp_env
) == 0) {
176 env
->current_tb
= NULL
;
177 /* if an exception is pending, we execute it here */
178 if (env
->exception_index
>= 0) {
179 if (env
->exception_index
>= EXCP_INTERRUPT
) {
180 /* exit request from the cpu execution loop */
181 ret
= env
->exception_index
;
183 } else if (env
->user_mode_only
) {
184 /* if user mode only, we simulate a fake exception
185 which will be hanlded outside the cpu execution
187 #if defined(TARGET_I386)
188 do_interrupt_user(env
->exception_index
,
189 env
->exception_is_int
,
191 env
->exception_next_eip
);
193 ret
= env
->exception_index
;
196 #if defined(TARGET_I386)
197 /* simulate a real cpu exception. On i386, it can
198 trigger new exceptions, but we do not handle
199 double or triple faults yet. */
200 do_interrupt(env
->exception_index
,
201 env
->exception_is_int
,
203 env
->exception_next_eip
, 0);
204 #elif defined(TARGET_PPC)
206 #elif defined(TARGET_SPARC)
207 do_interrupt(env
->exception_index
);
210 env
->exception_index
= -1;
213 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
215 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
216 ret
= kqemu_cpu_exec(env
);
217 /* put eflags in CPU temporary format */
218 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
219 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
220 CC_OP
= CC_OP_EFLAGS
;
221 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
224 longjmp(env
->jmp_env
, 1);
225 } else if (ret
== 2) {
226 /* softmmu execution needed */
228 if (env
->interrupt_request
!= 0) {
229 /* hardware interrupt will be executed just after */
231 /* otherwise, we restart */
232 longjmp(env
->jmp_env
, 1);
238 T0
= 0; /* force lookup of first TB */
241 /* g1 can be modified by some libc? functions */
244 interrupt_request
= env
->interrupt_request
;
245 if (__builtin_expect(interrupt_request
, 0)) {
246 #if defined(TARGET_I386)
247 /* if hardware interrupt pending, we execute it */
248 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
249 (env
->eflags
& IF_MASK
) &&
250 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
252 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
253 intno
= cpu_get_pic_interrupt(env
);
254 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
255 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
257 do_interrupt(intno
, 0, 0, 0, 1);
258 /* ensure that no TB jump will be modified as
259 the program flow was changed */
266 #elif defined(TARGET_PPC)
268 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
273 if ((interrupt_request
& CPU_INTERRUPT_HARD
)) {
275 env
->exception_index
= EXCP_EXTERNAL
;
278 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
279 } else if ((interrupt_request
& CPU_INTERRUPT_TIMER
)) {
281 env
->exception_index
= EXCP_DECR
;
284 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
287 #elif defined(TARGET_SPARC)
288 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
290 int pil
= env
->interrupt_index
& 15;
291 int type
= env
->interrupt_index
& 0xf0;
293 if (((type
== TT_EXTINT
) &&
294 (pil
== 15 || pil
> env
->psrpil
)) ||
296 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
297 do_interrupt(env
->interrupt_index
);
298 env
->interrupt_index
= 0;
300 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
301 //do_interrupt(0, 0, 0, 0, 0);
302 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
305 if (interrupt_request
& CPU_INTERRUPT_EXITTB
) {
306 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
307 /* ensure that no TB jump will be modified as
308 the program flow was changed */
315 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
316 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
317 env
->exception_index
= EXCP_INTERRUPT
;
322 if ((loglevel
& CPU_LOG_EXEC
)) {
323 #if defined(TARGET_I386)
324 /* restore flags in standard format */
325 env
->regs
[R_EAX
] = EAX
;
326 env
->regs
[R_EBX
] = EBX
;
327 env
->regs
[R_ECX
] = ECX
;
328 env
->regs
[R_EDX
] = EDX
;
329 env
->regs
[R_ESI
] = ESI
;
330 env
->regs
[R_EDI
] = EDI
;
331 env
->regs
[R_EBP
] = EBP
;
332 env
->regs
[R_ESP
] = ESP
;
333 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
334 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
335 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
336 #elif defined(TARGET_ARM)
337 env
->cpsr
= compute_cpsr();
338 cpu_dump_state(env
, logfile
, fprintf
, 0);
339 env
->cpsr
&= ~CACHED_CPSR_BITS
;
340 #elif defined(TARGET_SPARC)
341 cpu_dump_state (env
, logfile
, fprintf
, 0);
342 #elif defined(TARGET_PPC)
343 cpu_dump_state(env
, logfile
, fprintf
, 0);
345 #error unsupported target CPU
349 /* we record a subset of the CPU state. It will
350 always be the same before a given translated block
352 #if defined(TARGET_I386)
354 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
355 cs_base
= env
->segs
[R_CS
].base
;
356 pc
= cs_base
+ env
->eip
;
357 #elif defined(TARGET_ARM)
358 flags
= env
->thumb
| (env
->vfp
.vec_len
<< 1)
359 | (env
->vfp
.vec_stride
<< 4);
362 #elif defined(TARGET_SPARC)
366 #elif defined(TARGET_PPC)
367 flags
= (msr_pr
<< MSR_PR
) | (msr_fp
<< MSR_FP
) | (msr_se
<< MSR_SE
);
371 #error unsupported CPU
373 tb
= tb_find(&ptb
, pc
, cs_base
,
376 TranslationBlock
**ptb1
;
378 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
383 tb_invalidated_flag
= 0;
385 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
387 /* find translated block using physical mappings */
388 phys_pc
= get_phys_addr_code(env
, pc
);
389 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
391 h
= tb_phys_hash_func(phys_pc
);
392 ptb1
= &tb_phys_hash
[h
];
398 tb
->page_addr
[0] == phys_page1
&&
399 tb
->cs_base
== cs_base
&&
400 tb
->flags
== flags
) {
401 /* check next page if needed */
402 if (tb
->page_addr
[1] != -1) {
403 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
405 phys_page2
= get_phys_addr_code(env
, virt_page2
);
406 if (tb
->page_addr
[1] == phys_page2
)
412 ptb1
= &tb
->phys_hash_next
;
415 /* if no translated code available, then translate it now */
418 /* flush must be done */
420 /* cannot fail at this point */
422 /* don't forget to invalidate previous TB info */
423 ptb
= &tb_hash
[tb_hash_func(pc
)];
426 tc_ptr
= code_gen_ptr
;
428 tb
->cs_base
= cs_base
;
430 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
431 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
433 /* check next page if needed */
434 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
436 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
437 phys_page2
= get_phys_addr_code(env
, virt_page2
);
439 tb_link_phys(tb
, phys_pc
, phys_page2
);
442 if (tb_invalidated_flag
) {
443 /* as some TB could have been invalidated because
444 of memory exceptions while generating the code, we
445 must recompute the hash index here */
446 ptb
= &tb_hash
[tb_hash_func(pc
)];
448 ptb
= &(*ptb
)->hash_next
;
451 /* we add the TB in the virtual pc hash table */
453 tb
->hash_next
= NULL
;
455 spin_unlock(&tb_lock
);
458 if ((loglevel
& CPU_LOG_EXEC
)) {
459 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
460 (long)tb
->tc_ptr
, tb
->pc
,
461 lookup_symbol(tb
->pc
));
467 /* see if we can patch the calling TB. */
470 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
471 && (tb
->cflags
& CF_CODE_COPY
) ==
472 (((TranslationBlock
*)(T0
& ~3))->cflags
& CF_CODE_COPY
)
476 tb_add_jump((TranslationBlock
*)(long)(T0
& ~3), T0
& 3, tb
);
477 #if defined(USE_CODE_COPY)
478 /* propagates the FP use info */
479 ((TranslationBlock
*)(T0
& ~3))->cflags
|=
480 (tb
->cflags
& CF_FP_USED
);
482 spin_unlock(&tb_lock
);
486 env
->current_tb
= tb
;
487 /* execute the generated code */
488 gen_func
= (void *)tc_ptr
;
489 #if defined(__sparc__)
490 __asm__
__volatile__("call %0\n\t"
494 : "i0", "i1", "i2", "i3", "i4", "i5");
495 #elif defined(__arm__)
496 asm volatile ("mov pc, %0\n\t"
497 ".global exec_loop\n\t"
501 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
502 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
504 if (!(tb
->cflags
& CF_CODE_COPY
)) {
505 if ((tb
->cflags
& CF_FP_USED
) && env
->native_fp_regs
) {
506 save_native_fp_state(env
);
510 if ((tb
->cflags
& CF_FP_USED
) && !env
->native_fp_regs
) {
511 restore_native_fp_state(env
);
513 /* we work with native eflags */
514 CC_SRC
= cc_table
[CC_OP
].compute_all();
515 CC_OP
= CC_OP_EFLAGS
;
516 asm(".globl exec_loop\n"
521 " fs movl %11, %%eax\n"
522 " andl $0x400, %%eax\n"
523 " fs orl %8, %%eax\n"
526 " fs movl %%esp, %12\n"
527 " fs movl %0, %%eax\n"
528 " fs movl %1, %%ecx\n"
529 " fs movl %2, %%edx\n"
530 " fs movl %3, %%ebx\n"
531 " fs movl %4, %%esp\n"
532 " fs movl %5, %%ebp\n"
533 " fs movl %6, %%esi\n"
534 " fs movl %7, %%edi\n"
537 " fs movl %%esp, %4\n"
538 " fs movl %12, %%esp\n"
539 " fs movl %%eax, %0\n"
540 " fs movl %%ecx, %1\n"
541 " fs movl %%edx, %2\n"
542 " fs movl %%ebx, %3\n"
543 " fs movl %%ebp, %5\n"
544 " fs movl %%esi, %6\n"
545 " fs movl %%edi, %7\n"
548 " movl %%eax, %%ecx\n"
549 " andl $0x400, %%ecx\n"
551 " andl $0x8d5, %%eax\n"
552 " fs movl %%eax, %8\n"
554 " subl %%ecx, %%eax\n"
555 " fs movl %%eax, %11\n"
556 " fs movl %9, %%ebx\n" /* get T0 value */
559 : "m" (*(uint8_t *)offsetof(CPUState
, regs
[0])),
560 "m" (*(uint8_t *)offsetof(CPUState
, regs
[1])),
561 "m" (*(uint8_t *)offsetof(CPUState
, regs
[2])),
562 "m" (*(uint8_t *)offsetof(CPUState
, regs
[3])),
563 "m" (*(uint8_t *)offsetof(CPUState
, regs
[4])),
564 "m" (*(uint8_t *)offsetof(CPUState
, regs
[5])),
565 "m" (*(uint8_t *)offsetof(CPUState
, regs
[6])),
566 "m" (*(uint8_t *)offsetof(CPUState
, regs
[7])),
567 "m" (*(uint8_t *)offsetof(CPUState
, cc_src
)),
568 "m" (*(uint8_t *)offsetof(CPUState
, tmp0
)),
570 "m" (*(uint8_t *)offsetof(CPUState
, df
)),
571 "m" (*(uint8_t *)offsetof(CPUState
, saved_esp
))
579 env
->current_tb
= NULL
;
580 /* reset soft MMU for next block (it can currently
581 only be set by a memory fault) */
582 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
583 if (env
->hflags
& HF_SOFTMMU_MASK
) {
584 env
->hflags
&= ~HF_SOFTMMU_MASK
;
585 /* do not allow linking to another block */
596 #if defined(TARGET_I386)
597 #if defined(USE_CODE_COPY)
598 if (env
->native_fp_regs
) {
599 save_native_fp_state(env
);
602 /* restore flags in standard format */
603 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
605 /* restore global registers */
630 #elif defined(TARGET_ARM)
631 env
->cpsr
= compute_cpsr();
632 /* XXX: Save/restore host fpu exception state?. */
633 #elif defined(TARGET_SPARC)
634 #elif defined(TARGET_PPC)
636 #error unsupported target CPU
639 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
648 /* must only be called from the generated code as an exception can be
650 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
652 /* XXX: cannot enable it yet because it yields to MMU exception
653 where NIP != read address on PowerPC */
655 target_ulong phys_addr
;
656 phys_addr
= get_phys_addr_code(env
, start
);
657 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
661 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
663 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
665 CPUX86State
*saved_env
;
669 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
671 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
672 (selector
<< 4), 0xffff, 0);
674 load_seg(seg_reg
, selector
);
679 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
681 CPUX86State
*saved_env
;
686 helper_fsave((target_ulong
)ptr
, data32
);
691 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
693 CPUX86State
*saved_env
;
698 helper_frstor((target_ulong
)ptr
, data32
);
703 #endif /* TARGET_I386 */
705 #if !defined(CONFIG_SOFTMMU)
707 #if defined(TARGET_I386)
709 /* 'pc' is the host PC at which the exception was raised. 'address' is
710 the effective address of the memory exception. 'is_write' is 1 if a
711 write caused the exception and otherwise 0'. 'old_set' is the
712 signal set which should be restored */
713 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
714 int is_write
, sigset_t
*old_set
,
717 TranslationBlock
*tb
;
721 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
722 #if defined(DEBUG_SIGNAL)
723 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
724 pc
, address
, is_write
, *(unsigned long *)old_set
);
726 /* XXX: locking issue */
727 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
731 /* see if it is an MMU fault */
732 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
733 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
735 return 0; /* not an MMU fault */
737 return 1; /* the MMU fault was handled without causing real CPU fault */
738 /* now we have a real cpu fault */
741 /* the PC is inside the translated code. It means that we have
742 a virtual CPU fault */
743 cpu_restore_state(tb
, env
, pc
, puc
);
747 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
748 env
->eip
, env
->cr
[2], env
->error_code
);
750 /* we restore the process signal mask as the sigreturn should
751 do it (XXX: use sigsetjmp) */
752 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
753 raise_exception_err(EXCP0E_PAGE
, env
->error_code
);
755 /* activate soft MMU for this block */
756 env
->hflags
|= HF_SOFTMMU_MASK
;
757 cpu_resume_from_signal(env
, puc
);
759 /* never comes here */
763 #elif defined(TARGET_ARM)
764 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
765 int is_write
, sigset_t
*old_set
,
768 TranslationBlock
*tb
;
772 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
773 #if defined(DEBUG_SIGNAL)
774 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
775 pc
, address
, is_write
, *(unsigned long *)old_set
);
777 /* XXX: locking issue */
778 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
781 /* see if it is an MMU fault */
782 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, 1, 0);
784 return 0; /* not an MMU fault */
786 return 1; /* the MMU fault was handled without causing real CPU fault */
787 /* now we have a real cpu fault */
790 /* the PC is inside the translated code. It means that we have
791 a virtual CPU fault */
792 cpu_restore_state(tb
, env
, pc
, puc
);
794 /* we restore the process signal mask as the sigreturn should
795 do it (XXX: use sigsetjmp) */
796 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
799 #elif defined(TARGET_SPARC)
800 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
801 int is_write
, sigset_t
*old_set
,
804 TranslationBlock
*tb
;
808 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
809 #if defined(DEBUG_SIGNAL)
810 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
811 pc
, address
, is_write
, *(unsigned long *)old_set
);
813 /* XXX: locking issue */
814 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
817 /* see if it is an MMU fault */
818 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, 1, 0);
820 return 0; /* not an MMU fault */
822 return 1; /* the MMU fault was handled without causing real CPU fault */
823 /* now we have a real cpu fault */
826 /* the PC is inside the translated code. It means that we have
827 a virtual CPU fault */
828 cpu_restore_state(tb
, env
, pc
, puc
);
830 /* we restore the process signal mask as the sigreturn should
831 do it (XXX: use sigsetjmp) */
832 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
835 #elif defined (TARGET_PPC)
836 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
837 int is_write
, sigset_t
*old_set
,
840 TranslationBlock
*tb
;
844 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
845 #if defined(DEBUG_SIGNAL)
846 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
847 pc
, address
, is_write
, *(unsigned long *)old_set
);
849 /* XXX: locking issue */
850 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
854 /* see if it is an MMU fault */
855 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
857 return 0; /* not an MMU fault */
859 return 1; /* the MMU fault was handled without causing real CPU fault */
861 /* now we have a real cpu fault */
864 /* the PC is inside the translated code. It means that we have
865 a virtual CPU fault */
866 cpu_restore_state(tb
, env
, pc
, puc
);
870 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
871 env
->nip
, env
->error_code
, tb
);
873 /* we restore the process signal mask as the sigreturn should
874 do it (XXX: use sigsetjmp) */
875 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
876 do_raise_exception_err(env
->exception_index
, env
->error_code
);
878 /* activate soft MMU for this block */
879 cpu_resume_from_signal(env
, puc
);
881 /* never comes here */
885 #error unsupported target CPU
888 #if defined(__i386__)
890 #if defined(USE_CODE_COPY)
891 static void cpu_send_trap(unsigned long pc
, int trap
,
894 TranslationBlock
*tb
;
897 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
898 /* now we have a real cpu fault */
901 /* the PC is inside the translated code. It means that we have
902 a virtual CPU fault */
903 cpu_restore_state(tb
, env
, pc
, uc
);
905 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
906 raise_exception_err(trap
, env
->error_code
);
910 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
913 struct ucontext
*uc
= puc
;
921 #define REG_TRAPNO TRAPNO
923 pc
= uc
->uc_mcontext
.gregs
[REG_EIP
];
924 trapno
= uc
->uc_mcontext
.gregs
[REG_TRAPNO
];
925 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
926 if (trapno
== 0x00 || trapno
== 0x05) {
927 /* send division by zero or bound exception */
928 cpu_send_trap(pc
, trapno
, uc
);
932 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
934 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
935 &uc
->uc_sigmask
, puc
);
938 #elif defined(__x86_64__)
940 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
943 struct ucontext
*uc
= puc
;
946 pc
= uc
->uc_mcontext
.gregs
[REG_RIP
];
947 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
948 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
949 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
950 &uc
->uc_sigmask
, puc
);
953 #elif defined(__powerpc__)
955 /***********************************************************************
956 * signal context platform-specific definitions
960 /* All Registers access - only for local access */
961 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
962 /* Gpr Registers access */
963 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
964 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
965 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
966 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
967 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
968 # define LR_sig(context) REG_sig(link, context) /* Link register */
969 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
970 /* Float Registers access */
971 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
972 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
973 /* Exception Registers access */
974 # define DAR_sig(context) REG_sig(dar, context)
975 # define DSISR_sig(context) REG_sig(dsisr, context)
976 # define TRAP_sig(context) REG_sig(trap, context)
980 # include <sys/ucontext.h>
981 typedef struct ucontext SIGCONTEXT
;
982 /* All Registers access - only for local access */
983 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
984 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
985 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
986 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
987 /* Gpr Registers access */
988 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
989 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
990 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
991 # define CTR_sig(context) REG_sig(ctr, context)
992 # define XER_sig(context) REG_sig(xer, context) /* Link register */
993 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
994 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
995 /* Float Registers access */
996 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
997 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
998 /* Exception Registers access */
999 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1000 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1001 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1002 #endif /* __APPLE__ */
1004 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1007 struct ucontext
*uc
= puc
;
1015 if (DSISR_sig(uc
) & 0x00800000)
1018 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1021 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1022 is_write
, &uc
->uc_sigmask
, puc
);
1025 #elif defined(__alpha__)
1027 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1030 struct ucontext
*uc
= puc
;
1031 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1032 uint32_t insn
= *pc
;
1035 /* XXX: need kernel patch to get write flag faster */
1036 switch (insn
>> 26) {
1051 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1052 is_write
, &uc
->uc_sigmask
, puc
);
1054 #elif defined(__sparc__)
1056 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1059 uint32_t *regs
= (uint32_t *)(info
+ 1);
1060 void *sigmask
= (regs
+ 20);
1065 /* XXX: is there a standard glibc define ? */
1067 /* XXX: need kernel patch to get write flag faster */
1069 insn
= *(uint32_t *)pc
;
1070 if ((insn
>> 30) == 3) {
1071 switch((insn
>> 19) & 0x3f) {
1083 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1084 is_write
, sigmask
, NULL
);
1087 #elif defined(__arm__)
1089 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1092 struct ucontext
*uc
= puc
;
1096 pc
= uc
->uc_mcontext
.gregs
[R15
];
1097 /* XXX: compute is_write */
1099 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1104 #elif defined(__mc68000)
1106 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1109 struct ucontext
*uc
= puc
;
1113 pc
= uc
->uc_mcontext
.gregs
[16];
1114 /* XXX: compute is_write */
1116 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1118 &uc
->uc_sigmask
, puc
);
1123 #error host CPU specific signal handler needed
1127 #endif /* !defined(CONFIG_SOFTMMU) */