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enabled system emulator build on PowerPC - increased portability of soft mmu code
[qemu/qemu_0_9_1_stable.git] / ppc-dis.c
blobd01dcd6d1c44947c784198bd7c860dfddd953637
1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 #include "dis-asm.h"
21
22 /* ppc.h -- Header file for PowerPC opcode table
23 Copyright 1994 Free Software Foundation, Inc.
24 Written by Ian Lance Taylor, Cygnus Support
25
26 This file is part of GDB, GAS, and the GNU binutils.
27
28 GDB, GAS, and the GNU binutils are free software; you can redistribute
29 them and/or modify them under the terms of the GNU General Public
30 License as published by the Free Software Foundation; either version
31 1, or (at your option) any later version.
32
33 GDB, GAS, and the GNU binutils are distributed in the hope that they
34 will be useful, but WITHOUT ANY WARRANTY; without even the implied
35 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
36 the GNU General Public License for more details.
37
38 You should have received a copy of the GNU General Public License
39 along with this file; see the file COPYING. If not, write to the Free
40 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
41
42 /* The opcode table is an array of struct powerpc_opcode. */
43
44 struct powerpc_opcode
45 {
46 /* The opcode name. */
47 const char *name;
48
49 /* The opcode itself. Those bits which will be filled in with
50 operands are zeroes. */
51 unsigned long opcode;
52
53 /* The opcode mask. This is used by the disassembler. This is a
54 mask containing ones indicating those bits which must match the
55 opcode field, and zeroes indicating those bits which need not
56 match (and are presumably filled in by operands). */
57 unsigned long mask;
58
59 /* One bit flags for the opcode. These are used to indicate which
60 specific processors support the instructions. The defined values
61 are listed below. */
62 unsigned long flags;
63
64 /* An array of operand codes. Each code is an index into the
65 operand table. They appear in the order which the operands must
66 appear in assembly code, and are terminated by a zero. */
67 unsigned char operands[8];
68 };
69
70 /* The table itself is sorted by major opcode number, and is otherwise
71 in the order in which the disassembler should consider
72 instructions. */
73 extern const struct powerpc_opcode powerpc_opcodes[];
74 extern const int powerpc_num_opcodes;
75
76 /* Values defined for the flags field of a struct powerpc_opcode. */
77
78 /* Opcode is defined for the PowerPC architecture. */
79 #define PPC_OPCODE_PPC (01)
80
81 /* Opcode is defined for the POWER (RS/6000) architecture. */
82 #define PPC_OPCODE_POWER (02)
83
84 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
85 #define PPC_OPCODE_POWER2 (04)
86
87 /* Opcode is only defined on 32 bit architectures. */
88 #define PPC_OPCODE_32 (010)
89
90 /* Opcode is only defined on 64 bit architectures. */
91 #define PPC_OPCODE_64 (020)
92
93 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
94 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
95 but it also supports many additional POWER instructions. */
96 #define PPC_OPCODE_601 (040)
97
98 /* A macro to extract the major opcode from an instruction. */
99 #define PPC_OP(i) (((i) >> 26) & 0x3f)
100 \f
101 /* The operands table is an array of struct powerpc_operand. */
102
103 struct powerpc_operand
104 {
105 /* The number of bits in the operand. */
106 int bits;
107
108 /* How far the operand is left shifted in the instruction. */
109 int shift;
110
111 /* Insertion function. This is used by the assembler. To insert an
112 operand value into an instruction, check this field.
113
114 If it is NULL, execute
115 i |= (op & ((1 << o->bits) - 1)) << o->shift;
116 (i is the instruction which we are filling in, o is a pointer to
117 this structure, and op is the opcode value; this assumes twos
118 complement arithmetic).
119
120 If this field is not NULL, then simply call it with the
121 instruction and the operand value. It will return the new value
122 of the instruction. If the ERRMSG argument is not NULL, then if
123 the operand value is illegal, *ERRMSG will be set to a warning
124 string (the operand will be inserted in any case). If the
125 operand value is legal, *ERRMSG will be unchanged (most operands
126 can accept any value). */
127 unsigned long (*insert)(unsigned long instruction, long op,
128 const char **errmsg);
129
130 /* Extraction function. This is used by the disassembler. To
131 extract this operand type from an instruction, check this field.
132
133 If it is NULL, compute
134 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
135 if ((o->flags & PPC_OPERAND_SIGNED) != 0
136 && (op & (1 << (o->bits - 1))) != 0)
137 op -= 1 << o->bits;
138 (i is the instruction, o is a pointer to this structure, and op
139 is the result; this assumes twos complement arithmetic).
140
141 If this field is not NULL, then simply call it with the
142 instruction value. It will return the value of the operand. If
143 the INVALID argument is not NULL, *INVALID will be set to
144 non-zero if this operand type can not actually be extracted from
145 this operand (i.e., the instruction does not match). If the
146 operand is valid, *INVALID will not be changed. */
147 long (*extract) (unsigned long instruction, int *invalid);
148
149 /* One bit syntax flags. */
150 unsigned long flags;
151 };
152
153 /* Elements in the table are retrieved by indexing with values from
154 the operands field of the powerpc_opcodes table. */
155
156 extern const struct powerpc_operand powerpc_operands[];
157
158 /* Values defined for the flags field of a struct powerpc_operand. */
159
160 /* This operand takes signed values. */
161 #define PPC_OPERAND_SIGNED (01)
162
163 /* This operand takes signed values, but also accepts a full positive
164 range of values when running in 32 bit mode. That is, if bits is
165 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
166 this flag is ignored. */
167 #define PPC_OPERAND_SIGNOPT (02)
168
169 /* This operand does not actually exist in the assembler input. This
170 is used to support extended mnemonics such as mr, for which two
171 operands fields are identical. The assembler should call the
172 insert function with any op value. The disassembler should call
173 the extract function, ignore the return value, and check the value
174 placed in the valid argument. */
175 #define PPC_OPERAND_FAKE (04)
176
177 /* The next operand should be wrapped in parentheses rather than
178 separated from this one by a comma. This is used for the load and
179 store instructions which want their operands to look like
180 reg,displacement(reg)
181 */
182 #define PPC_OPERAND_PARENS (010)
183
184 /* This operand may use the symbolic names for the CR fields, which
185 are
186 lt 0 gt 1 eq 2 so 3 un 3
187 cr0 0 cr1 1 cr2 2 cr3 3
188 cr4 4 cr5 5 cr6 6 cr7 7
189 These may be combined arithmetically, as in cr2*4+gt. These are
190 only supported on the PowerPC, not the POWER. */
191 #define PPC_OPERAND_CR (020)
192
193 /* This operand names a register. The disassembler uses this to print
194 register names with a leading 'r'. */
195 #define PPC_OPERAND_GPR (040)
196
197 /* This operand names a floating point register. The disassembler
198 prints these with a leading 'f'. */
199 #define PPC_OPERAND_FPR (0100)
200
201 /* This operand is a relative branch displacement. The disassembler
202 prints these symbolically if possible. */
203 #define PPC_OPERAND_RELATIVE (0200)
204
205 /* This operand is an absolute branch address. The disassembler
206 prints these symbolically if possible. */
207 #define PPC_OPERAND_ABSOLUTE (0400)
208
209 /* This operand is optional, and is zero if omitted. This is used for
210 the optional BF and L fields in the comparison instructions. The
211 assembler must count the number of operands remaining on the line,
212 and the number of operands remaining for the opcode, and decide
213 whether this operand is present or not. The disassembler should
214 print this operand out only if it is not zero. */
215 #define PPC_OPERAND_OPTIONAL (01000)
216
217 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
218 is omitted, then for the next operand use this operand value plus
219 1, ignoring the next operand field for the opcode. This wretched
220 hack is needed because the Power rotate instructions can take
221 either 4 or 5 operands. The disassembler should print this operand
222 out regardless of the PPC_OPERAND_OPTIONAL field. */
223 #define PPC_OPERAND_NEXT (02000)
224
225 /* This operand should be regarded as a negative number for the
226 purposes of overflow checking (i.e., the normal most negative
227 number is disallowed and one more than the normal most positive
228 number is allowed). This flag will only be set for a signed
229 operand. */
230 #define PPC_OPERAND_NEGATIVE (04000)
231 \f
232 /* The POWER and PowerPC assemblers use a few macros. We keep them
233 with the operands table for simplicity. The macro table is an
234 array of struct powerpc_macro. */
235
236 struct powerpc_macro
237 {
238 /* The macro name. */
239 const char *name;
240
241 /* The number of operands the macro takes. */
242 unsigned int operands;
243
244 /* One bit flags for the opcode. These are used to indicate which
245 specific processors support the instructions. The values are the
246 same as those for the struct powerpc_opcode flags field. */
247 unsigned long flags;
248
249 /* A format string to turn the macro into a normal instruction.
250 Each %N in the string is replaced with operand number N (zero
251 based). */
252 const char *format;
253 };
254
255 extern const struct powerpc_macro powerpc_macros[];
256 extern const int powerpc_num_macros;
257
258 /* ppc-opc.c -- PowerPC opcode list
259 Copyright 1994 Free Software Foundation, Inc.
260 Written by Ian Lance Taylor, Cygnus Support
261
262 This file is part of GDB, GAS, and the GNU binutils.
263
264 GDB, GAS, and the GNU binutils are free software; you can redistribute
265 them and/or modify them under the terms of the GNU General Public
266 License as published by the Free Software Foundation; either version
267 2, or (at your option) any later version.
268
269 GDB, GAS, and the GNU binutils are distributed in the hope that they
270 will be useful, but WITHOUT ANY WARRANTY; without even the implied
271 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
272 the GNU General Public License for more details.
273
274 You should have received a copy of the GNU General Public License
275 along with this file; see the file COPYING. If not, write to the Free
276 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
277
278 /* This file holds the PowerPC opcode table. The opcode table
279 includes almost all of the extended instruction mnemonics. This
280 permits the disassembler to use them, and simplifies the assembler
281 logic, at the cost of increasing the table size. The table is
282 strictly constant data, so the compiler should be able to put it in
283 the .text section.
284
285 This file also holds the operand table. All knowledge about
286 inserting operands into instructions and vice-versa is kept in this
287 file. */
288 \f
289 /* Local insertion and extraction functions. */
290
291 static unsigned long insert_bat (unsigned long, long, const char **);
292 static long extract_bat(unsigned long, int *);
293 static unsigned long insert_bba(unsigned long, long, const char **);
294 static long extract_bba(unsigned long, int *);
295 static unsigned long insert_bd(unsigned long, long, const char **);
296 static long extract_bd(unsigned long, int *);
297 static unsigned long insert_bdm(unsigned long, long, const char **);
298 static long extract_bdm(unsigned long, int *);
299 static unsigned long insert_bdp(unsigned long, long, const char **);
300 static long extract_bdp(unsigned long, int *);
301 static unsigned long insert_bo(unsigned long, long, const char **);
302 static long extract_bo(unsigned long, int *);
303 static unsigned long insert_boe(unsigned long, long, const char **);
304 static long extract_boe(unsigned long, int *);
305 static unsigned long insert_ds(unsigned long, long, const char **);
306 static long extract_ds(unsigned long, int *);
307 static unsigned long insert_li(unsigned long, long, const char **);
308 static long extract_li(unsigned long, int *);
309 static unsigned long insert_mbe(unsigned long, long, const char **);
310 static long extract_mbe(unsigned long, int *);
311 static unsigned long insert_mb6(unsigned long, long, const char **);
312 static long extract_mb6(unsigned long, int *);
313 static unsigned long insert_nb(unsigned long, long, const char **);
314 static long extract_nb(unsigned long, int *);
315 static unsigned long insert_nsi(unsigned long, long, const char **);
316 static long extract_nsi(unsigned long, int *);
317 static unsigned long insert_ral(unsigned long, long, const char **);
318 static unsigned long insert_ram(unsigned long, long, const char **);
319 static unsigned long insert_ras(unsigned long, long, const char **);
320 static unsigned long insert_rbs(unsigned long, long, const char **);
321 static long extract_rbs(unsigned long, int *);
322 static unsigned long insert_sh6(unsigned long, long, const char **);
323 static long extract_sh6(unsigned long, int *);
324 static unsigned long insert_spr(unsigned long, long, const char **);
325 static long extract_spr(unsigned long, int *);
326 static unsigned long insert_tbr(unsigned long, long, const char **);
327 static long extract_tbr(unsigned long, int *);
328 \f
329 /* The operands table.
330
331 The fields are bits, shift, signed, insert, extract, flags. */
332
333 const struct powerpc_operand powerpc_operands[] =
334 {
335 /* The zero index is used to indicate the end of the list of
336 operands. */
337 #define UNUSED (0)
338 { 0, 0, 0, 0, 0 },
339
340 /* The BA field in an XL form instruction. */
341 #define BA (1)
342 #define BA_MASK (0x1f << 16)
343 { 5, 16, 0, 0, PPC_OPERAND_CR },
344
345 /* The BA field in an XL form instruction when it must be the same
346 as the BT field in the same instruction. */
347 #define BAT (2)
348 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
349
350 /* The BB field in an XL form instruction. */
351 #define BB (3)
352 #define BB_MASK (0x1f << 11)
353 { 5, 11, 0, 0, PPC_OPERAND_CR },
354
355 /* The BB field in an XL form instruction when it must be the same
356 as the BA field in the same instruction. */
357 #define BBA (4)
358 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
359
360 /* The BD field in a B form instruction. The lower two bits are
361 forced to zero. */
362 #define BD (5)
363 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
364
365 /* The BD field in a B form instruction when absolute addressing is
366 used. */
367 #define BDA (6)
368 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
369
370 /* The BD field in a B form instruction when the - modifier is used.
371 This sets the y bit of the BO field appropriately. */
372 #define BDM (7)
373 { 16, 0, insert_bdm, extract_bdm,
374 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
375
376 /* The BD field in a B form instruction when the - modifier is used
377 and absolute address is used. */
378 #define BDMA (8)
379 { 16, 0, insert_bdm, extract_bdm,
380 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
381
382 /* The BD field in a B form instruction when the + modifier is used.
383 This sets the y bit of the BO field appropriately. */
384 #define BDP (9)
385 { 16, 0, insert_bdp, extract_bdp,
386 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
387
388 /* The BD field in a B form instruction when the + modifier is used
389 and absolute addressing is used. */
390 #define BDPA (10)
391 { 16, 0, insert_bdp, extract_bdp,
392 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
393
394 /* The BF field in an X or XL form instruction. */
395 #define BF (11)
396 { 3, 23, 0, 0, PPC_OPERAND_CR },
397
398 /* An optional BF field. This is used for comparison instructions,
399 in which an omitted BF field is taken as zero. */
400 #define OBF (12)
401 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
402
403 /* The BFA field in an X or XL form instruction. */
404 #define BFA (13)
405 { 3, 18, 0, 0, PPC_OPERAND_CR },
406
407 /* The BI field in a B form or XL form instruction. */
408 #define BI (14)
409 #define BI_MASK (0x1f << 16)
410 { 5, 16, 0, 0, PPC_OPERAND_CR },
411
412 /* The BO field in a B form instruction. Certain values are
413 illegal. */
414 #define BO (15)
415 #define BO_MASK (0x1f << 21)
416 { 5, 21, insert_bo, extract_bo, 0 },
417
418 /* The BO field in a B form instruction when the + or - modifier is
419 used. This is like the BO field, but it must be even. */
420 #define BOE (16)
421 { 5, 21, insert_boe, extract_boe, 0 },
422
423 /* The BT field in an X or XL form instruction. */
424 #define BT (17)
425 { 5, 21, 0, 0, PPC_OPERAND_CR },
426
427 /* The condition register number portion of the BI field in a B form
428 or XL form instruction. This is used for the extended
429 conditional branch mnemonics, which set the lower two bits of the
430 BI field. This field is optional. */
431 #define CR (18)
432 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
433
434 /* The D field in a D form instruction. This is a displacement off
435 a register, and implies that the next operand is a register in
436 parentheses. */
437 #define D (19)
438 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
439
440 /* The DS field in a DS form instruction. This is like D, but the
441 lower two bits are forced to zero. */
442 #define DS (20)
443 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
444
445 /* The FL1 field in a POWER SC form instruction. */
446 #define FL1 (21)
447 { 4, 12, 0, 0, 0 },
448
449 /* The FL2 field in a POWER SC form instruction. */
450 #define FL2 (22)
451 { 3, 2, 0, 0, 0 },
452
453 /* The FLM field in an XFL form instruction. */
454 #define FLM (23)
455 { 8, 17, 0, 0, 0 },
456
457 /* The FRA field in an X or A form instruction. */
458 #define FRA (24)
459 #define FRA_MASK (0x1f << 16)
460 { 5, 16, 0, 0, PPC_OPERAND_FPR },
461
462 /* The FRB field in an X or A form instruction. */
463 #define FRB (25)
464 #define FRB_MASK (0x1f << 11)
465 { 5, 11, 0, 0, PPC_OPERAND_FPR },
466
467 /* The FRC field in an A form instruction. */
468 #define FRC (26)
469 #define FRC_MASK (0x1f << 6)
470 { 5, 6, 0, 0, PPC_OPERAND_FPR },
471
472 /* The FRS field in an X form instruction or the FRT field in a D, X
473 or A form instruction. */
474 #define FRS (27)
475 #define FRT (FRS)
476 { 5, 21, 0, 0, PPC_OPERAND_FPR },
477
478 /* The FXM field in an XFX instruction. */
479 #define FXM (28)
480 #define FXM_MASK (0xff << 12)
481 { 8, 12, 0, 0, 0 },
482
483 /* The L field in a D or X form instruction. */
484 #define L (29)
485 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
486
487 /* The LEV field in a POWER SC form instruction. */
488 #define LEV (30)
489 { 7, 5, 0, 0, 0 },
490
491 /* The LI field in an I form instruction. The lower two bits are
492 forced to zero. */
493 #define LI (31)
494 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
495
496 /* The LI field in an I form instruction when used as an absolute
497 address. */
498 #define LIA (32)
499 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
500
501 /* The MB field in an M form instruction. */
502 #define MB (33)
503 #define MB_MASK (0x1f << 6)
504 { 5, 6, 0, 0, 0 },
505
506 /* The ME field in an M form instruction. */
507 #define ME (34)
508 #define ME_MASK (0x1f << 1)
509 { 5, 1, 0, 0, 0 },
510
511 /* The MB and ME fields in an M form instruction expressed a single
512 operand which is a bitmask indicating which bits to select. This
513 is a two operand form using PPC_OPERAND_NEXT. See the
514 description in opcode/ppc.h for what this means. */
515 #define MBE (35)
516 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
517 { 32, 0, insert_mbe, extract_mbe, 0 },
518
519 /* The MB or ME field in an MD or MDS form instruction. The high
520 bit is wrapped to the low end. */
521 #define MB6 (37)
522 #define ME6 (MB6)
523 #define MB6_MASK (0x3f << 5)
524 { 6, 5, insert_mb6, extract_mb6, 0 },
525
526 /* The NB field in an X form instruction. The value 32 is stored as
527 0. */
528 #define NB (38)
529 { 6, 11, insert_nb, extract_nb, 0 },
530
531 /* The NSI field in a D form instruction. This is the same as the
532 SI field, only negated. */
533 #define NSI (39)
534 { 16, 0, insert_nsi, extract_nsi,
535 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
536
537 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
538 #define RA (40)
539 #define RA_MASK (0x1f << 16)
540 { 5, 16, 0, 0, PPC_OPERAND_GPR },
541
542 /* The RA field in a D or X form instruction which is an updating
543 load, which means that the RA field may not be zero and may not
544 equal the RT field. */
545 #define RAL (41)
546 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
547
548 /* The RA field in an lmw instruction, which has special value
549 restrictions. */
550 #define RAM (42)
551 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
552
553 /* The RA field in a D or X form instruction which is an updating
554 store or an updating floating point load, which means that the RA
555 field may not be zero. */
556 #define RAS (43)
557 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
558
559 /* The RB field in an X, XO, M, or MDS form instruction. */
560 #define RB (44)
561 #define RB_MASK (0x1f << 11)
562 { 5, 11, 0, 0, PPC_OPERAND_GPR },
563
564 /* The RB field in an X form instruction when it must be the same as
565 the RS field in the instruction. This is used for extended
566 mnemonics like mr. */
567 #define RBS (45)
568 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
569
570 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
571 instruction or the RT field in a D, DS, X, XFX or XO form
572 instruction. */
573 #define RS (46)
574 #define RT (RS)
575 #define RT_MASK (0x1f << 21)
576 { 5, 21, 0, 0, PPC_OPERAND_GPR },
577
578 /* The SH field in an X or M form instruction. */
579 #define SH (47)
580 #define SH_MASK (0x1f << 11)
581 { 5, 11, 0, 0, 0 },
582
583 /* The SH field in an MD form instruction. This is split. */
584 #define SH6 (48)
585 #define SH6_MASK ((0x1f << 11) | (1 << 1))
586 { 6, 1, insert_sh6, extract_sh6, 0 },
587
588 /* The SI field in a D form instruction. */
589 #define SI (49)
590 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
591
592 /* The SI field in a D form instruction when we accept a wide range
593 of positive values. */
594 #define SISIGNOPT (50)
595 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
596
597 /* The SPR field in an XFX form instruction. This is flipped--the
598 lower 5 bits are stored in the upper 5 and vice- versa. */
599 #define SPR (51)
600 #define SPR_MASK (0x3ff << 11)
601 { 10, 11, insert_spr, extract_spr, 0 },
602
603 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
604 #define SPRBAT (52)
605 #define SPRBAT_MASK (0x3 << 17)
606 { 2, 17, 0, 0, 0 },
607
608 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
609 #define SPRG (53)
610 #define SPRG_MASK (0x3 << 16)
611 { 2, 16, 0, 0, 0 },
612
613 /* The SR field in an X form instruction. */
614 #define SR (54)
615 { 4, 16, 0, 0, 0 },
616
617 /* The SV field in a POWER SC form instruction. */
618 #define SV (55)
619 { 14, 2, 0, 0, 0 },
620
621 /* The TBR field in an XFX form instruction. This is like the SPR
622 field, but it is optional. */
623 #define TBR (56)
624 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
625
626 /* The TO field in a D or X form instruction. */
627 #define TO (57)
628 #define TO_MASK (0x1f << 21)
629 { 5, 21, 0, 0, 0 },
630
631 /* The U field in an X form instruction. */
632 #define U (58)
633 { 4, 12, 0, 0, 0 },
634
635 /* The UI field in a D form instruction. */
636 #define UI (59)
637 { 16, 0, 0, 0, 0 },
638 };
639
640 /* The functions used to insert and extract complicated operands. */
641
642 /* The BA field in an XL form instruction when it must be the same as
643 the BT field in the same instruction. This operand is marked FAKE.
644 The insertion function just copies the BT field into the BA field,
645 and the extraction function just checks that the fields are the
646 same. */
647
648 /*ARGSUSED*/
649 static unsigned long
650 insert_bat (insn, value, errmsg)
651 unsigned long insn;
652 long value;
653 const char **errmsg;
654 {
655 return insn | (((insn >> 21) & 0x1f) << 16);
656 }
657
658 static long
659 extract_bat (insn, invalid)
660 unsigned long insn;
661 int *invalid;
662 {
663 if (invalid != (int *) NULL
664 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
665 *invalid = 1;
666 return 0;
667 }
668
669 /* The BB field in an XL form instruction when it must be the same as
670 the BA field in the same instruction. This operand is marked FAKE.
671 The insertion function just copies the BA field into the BB field,
672 and the extraction function just checks that the fields are the
673 same. */
674
675 /*ARGSUSED*/
676 static unsigned long
677 insert_bba (insn, value, errmsg)
678 unsigned long insn;
679 long value;
680 const char **errmsg;
681 {
682 return insn | (((insn >> 16) & 0x1f) << 11);
683 }
684
685 static long
686 extract_bba (insn, invalid)
687 unsigned long insn;
688 int *invalid;
689 {
690 if (invalid != (int *) NULL
691 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
692 *invalid = 1;
693 return 0;
694 }
695
696 /* The BD field in a B form instruction. The lower two bits are
697 forced to zero. */
698
699 /*ARGSUSED*/
700 static unsigned long
701 insert_bd (insn, value, errmsg)
702 unsigned long insn;
703 long value;
704 const char **errmsg;
705 {
706 return insn | (value & 0xfffc);
707 }
708
709 /*ARGSUSED*/
710 static long
711 extract_bd (insn, invalid)
712 unsigned long insn;
713 int *invalid;
714 {
715 if ((insn & 0x8000) != 0)
716 return (insn & 0xfffc) - 0x10000;
717 else
718 return insn & 0xfffc;
719 }
720
721 /* The BD field in a B form instruction when the - modifier is used.
722 This modifier means that the branch is not expected to be taken.
723 We must set the y bit of the BO field to 1 if the offset is
724 negative. When extracting, we require that the y bit be 1 and that
725 the offset be positive, since if the y bit is 0 we just want to
726 print the normal form of the instruction. */
727
728 /*ARGSUSED*/
729 static unsigned long
730 insert_bdm (insn, value, errmsg)
731 unsigned long insn;
732 long value;
733 const char **errmsg;
734 {
735 if ((value & 0x8000) != 0)
736 insn |= 1 << 21;
737 return insn | (value & 0xfffc);
738 }
739
740 static long
741 extract_bdm (insn, invalid)
742 unsigned long insn;
743 int *invalid;
744 {
745 if (invalid != (int *) NULL
746 && ((insn & (1 << 21)) == 0
747 || (insn & (1 << 15)) == 0))
748 *invalid = 1;
749 if ((insn & 0x8000) != 0)
750 return (insn & 0xfffc) - 0x10000;
751 else
752 return insn & 0xfffc;
753 }
754
755 /* The BD field in a B form instruction when the + modifier is used.
756 This is like BDM, above, except that the branch is expected to be
757 taken. */
758
759 /*ARGSUSED*/
760 static unsigned long
761 insert_bdp (insn, value, errmsg)
762 unsigned long insn;
763 long value;
764 const char **errmsg;
765 {
766 if ((value & 0x8000) == 0)
767 insn |= 1 << 21;
768 return insn | (value & 0xfffc);
769 }
770
771 static long
772 extract_bdp (insn, invalid)
773 unsigned long insn;
774 int *invalid;
775 {
776 if (invalid != (int *) NULL
777 && ((insn & (1 << 21)) == 0
778 || (insn & (1 << 15)) != 0))
779 *invalid = 1;
780 if ((insn & 0x8000) != 0)
781 return (insn & 0xfffc) - 0x10000;
782 else
783 return insn & 0xfffc;
784 }
785
786 /* Check for legal values of a BO field. */
787
788 static int
789 valid_bo (long value)
790 {
791 /* Certain encodings have bits that are required to be zero. These
792 are (z must be zero, y may be anything):
793 001zy
794 011zy
795 1z00y
796 1z01y
797 1z1zz
798 */
799 switch (value & 0x14)
800 {
801 default:
802 case 0:
803 return 1;
804 case 0x4:
805 return (value & 0x2) == 0;
806 case 0x10:
807 return (value & 0x8) == 0;
808 case 0x14:
809 return value == 0x14;
810 }
811 }
812
813 /* The BO field in a B form instruction. Warn about attempts to set
814 the field to an illegal value. */
815
816 static unsigned long
817 insert_bo (insn, value, errmsg)
818 unsigned long insn;
819 long value;
820 const char **errmsg;
821 {
822 if (errmsg != (const char **) NULL
823 && ! valid_bo (value))
824 *errmsg = "invalid conditional option";
825 return insn | ((value & 0x1f) << 21);
826 }
827
828 static long
829 extract_bo (insn, invalid)
830 unsigned long insn;
831 int *invalid;
832 {
833 long value;
834
835 value = (insn >> 21) & 0x1f;
836 if (invalid != (int *) NULL
837 && ! valid_bo (value))
838 *invalid = 1;
839 return value;
840 }
841
842 /* The BO field in a B form instruction when the + or - modifier is
843 used. This is like the BO field, but it must be even. When
844 extracting it, we force it to be even. */
845
846 static unsigned long
847 insert_boe (insn, value, errmsg)
848 unsigned long insn;
849 long value;
850 const char **errmsg;
851 {
852 if (errmsg != (const char **) NULL)
853 {
854 if (! valid_bo (value))
855 *errmsg = "invalid conditional option";
856 else if ((value & 1) != 0)
857 *errmsg = "attempt to set y bit when using + or - modifier";
858 }
859 return insn | ((value & 0x1f) << 21);
860 }
861
862 static long
863 extract_boe (insn, invalid)
864 unsigned long insn;
865 int *invalid;
866 {
867 long value;
868
869 value = (insn >> 21) & 0x1f;
870 if (invalid != (int *) NULL
871 && ! valid_bo (value))
872 *invalid = 1;
873 return value & 0x1e;
874 }
875
876 /* The DS field in a DS form instruction. This is like D, but the
877 lower two bits are forced to zero. */
878
879 /*ARGSUSED*/
880 static unsigned long
881 insert_ds (insn, value, errmsg)
882 unsigned long insn;
883 long value;
884 const char **errmsg;
885 {
886 return insn | (value & 0xfffc);
887 }
888
889 /*ARGSUSED*/
890 static long
891 extract_ds (insn, invalid)
892 unsigned long insn;
893 int *invalid;
894 {
895 if ((insn & 0x8000) != 0)
896 return (insn & 0xfffc) - 0x10000;
897 else
898 return insn & 0xfffc;
899 }
900
901 /* The LI field in an I form instruction. The lower two bits are
902 forced to zero. */
903
904 /*ARGSUSED*/
905 static unsigned long
906 insert_li (insn, value, errmsg)
907 unsigned long insn;
908 long value;
909 const char **errmsg;
910 {
911 return insn | (value & 0x3fffffc);
912 }
913
914 /*ARGSUSED*/
915 static long
916 extract_li (insn, invalid)
917 unsigned long insn;
918 int *invalid;
919 {
920 if ((insn & 0x2000000) != 0)
921 return (insn & 0x3fffffc) - 0x4000000;
922 else
923 return insn & 0x3fffffc;
924 }
925
926 /* The MB and ME fields in an M form instruction expressed as a single
927 operand which is itself a bitmask. The extraction function always
928 marks it as invalid, since we never want to recognize an
929 instruction which uses a field of this type. */
930
931 static unsigned long
932 insert_mbe (insn, value, errmsg)
933 unsigned long insn;
934 long value;
935 const char **errmsg;
936 {
937 unsigned long uval;
938 int mb, me;
939
940 uval = value;
941
942 if (uval == 0)
943 {
944 if (errmsg != (const char **) NULL)
945 *errmsg = "illegal bitmask";
946 return insn;
947 }
948
949 me = 31;
950 while ((uval & 1) == 0)
951 {
952 uval >>= 1;
953 --me;
954 }
955
956 mb = me;
957 uval >>= 1;
958 while ((uval & 1) != 0)
959 {
960 uval >>= 1;
961 --mb;
962 }
963
964 if (uval != 0)
965 {
966 if (errmsg != (const char **) NULL)
967 *errmsg = "illegal bitmask";
968 }
969
970 return insn | (mb << 6) | (me << 1);
971 }
972
973 static long
974 extract_mbe (insn, invalid)
975 unsigned long insn;
976 int *invalid;
977 {
978 long ret;
979 int mb, me;
980 int i;
981
982 if (invalid != (int *) NULL)
983 *invalid = 1;
984
985 ret = 0;
986 mb = (insn >> 6) & 0x1f;
987 me = (insn >> 1) & 0x1f;
988 for (i = mb; i < me; i++)
989 ret |= 1 << (31 - i);
990 return ret;
991 }
992
993 /* The MB or ME field in an MD or MDS form instruction. The high bit
994 is wrapped to the low end. */
995
996 /*ARGSUSED*/
997 static unsigned long
998 insert_mb6 (insn, value, errmsg)
999 unsigned long insn;
1000 long value;
1001 const char **errmsg;
1002 {
1003 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1004 }
1005
1006 /*ARGSUSED*/
1007 static long
1008 extract_mb6 (insn, invalid)
1009 unsigned long insn;
1010 int *invalid;
1011 {
1012 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1013 }
1014
1015 /* The NB field in an X form instruction. The value 32 is stored as
1016 0. */
1017
1018 static unsigned long
1019 insert_nb (insn, value, errmsg)
1020 unsigned long insn;
1021 long value;
1022 const char **errmsg;
1023 {
1024 if (value < 0 || value > 32)
1025 *errmsg = "value out of range";
1026 if (value == 32)
1027 value = 0;
1028 return insn | ((value & 0x1f) << 11);
1029 }
1030
1031 /*ARGSUSED*/
1032 static long
1033 extract_nb (insn, invalid)
1034 unsigned long insn;
1035 int *invalid;
1036 {
1037 long ret;
1038
1039 ret = (insn >> 11) & 0x1f;
1040 if (ret == 0)
1041 ret = 32;
1042 return ret;
1043 }
1044
1045 /* The NSI field in a D form instruction. This is the same as the SI
1046 field, only negated. The extraction function always marks it as
1047 invalid, since we never want to recognize an instruction which uses
1048 a field of this type. */
1049
1050 /*ARGSUSED*/
1051 static unsigned long
1052 insert_nsi (insn, value, errmsg)
1053 unsigned long insn;
1054 long value;
1055 const char **errmsg;
1056 {
1057 return insn | ((- value) & 0xffff);
1058 }
1059
1060 static long
1061 extract_nsi (insn, invalid)
1062 unsigned long insn;
1063 int *invalid;
1064 {
1065 if (invalid != (int *) NULL)
1066 *invalid = 1;
1067 if ((insn & 0x8000) != 0)
1068 return - ((insn & 0xffff) - 0x10000);
1069 else
1070 return - (insn & 0xffff);
1071 }
1072
1073 /* The RA field in a D or X form instruction which is an updating
1074 load, which means that the RA field may not be zero and may not
1075 equal the RT field. */
1076
1077 static unsigned long
1078 insert_ral (insn, value, errmsg)
1079 unsigned long insn;
1080 long value;
1081 const char **errmsg;
1082 {
1083 if (value == 0
1084 || value == ((insn >> 21) & 0x1f))
1085 *errmsg = "invalid register operand when updating";
1086 return insn | ((value & 0x1f) << 16);
1087 }
1088
1089 /* The RA field in an lmw instruction, which has special value
1090 restrictions. */
1091
1092 static unsigned long
1093 insert_ram (insn, value, errmsg)
1094 unsigned long insn;
1095 long value;
1096 const char **errmsg;
1097 {
1098 if (value >= ((insn >> 21) & 0x1f))
1099 *errmsg = "index register in load range";
1100 return insn | ((value & 0x1f) << 16);
1101 }
1102
1103 /* The RA field in a D or X form instruction which is an updating
1104 store or an updating floating point load, which means that the RA
1105 field may not be zero. */
1106
1107 static unsigned long
1108 insert_ras (insn, value, errmsg)
1109 unsigned long insn;
1110 long value;
1111 const char **errmsg;
1112 {
1113 if (value == 0)
1114 *errmsg = "invalid register operand when updating";
1115 return insn | ((value & 0x1f) << 16);
1116 }
1117
1118 /* The RB field in an X form instruction when it must be the same as
1119 the RS field in the instruction. This is used for extended
1120 mnemonics like mr. This operand is marked FAKE. The insertion
1121 function just copies the BT field into the BA field, and the
1122 extraction function just checks that the fields are the same. */
1123
1124 /*ARGSUSED*/
1125 static unsigned long
1126 insert_rbs (insn, value, errmsg)
1127 unsigned long insn;
1128 long value;
1129 const char **errmsg;
1130 {
1131 return insn | (((insn >> 21) & 0x1f) << 11);
1132 }
1133
1134 static long
1135 extract_rbs (insn, invalid)
1136 unsigned long insn;
1137 int *invalid;
1138 {
1139 if (invalid != (int *) NULL
1140 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1141 *invalid = 1;
1142 return 0;
1143 }
1144
1145 /* The SH field in an MD form instruction. This is split. */
1146
1147 /*ARGSUSED*/
1148 static unsigned long
1149 insert_sh6 (insn, value, errmsg)
1150 unsigned long insn;
1151 long value;
1152 const char **errmsg;
1153 {
1154 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1155 }
1156
1157 /*ARGSUSED*/
1158 static long
1159 extract_sh6 (insn, invalid)
1160 unsigned long insn;
1161 int *invalid;
1162 {
1163 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1164 }
1165
1166 /* The SPR field in an XFX form instruction. This is flipped--the
1167 lower 5 bits are stored in the upper 5 and vice- versa. */
1168
1169 static unsigned long
1170 insert_spr (insn, value, errmsg)
1171 unsigned long insn;
1172 long value;
1173 const char **errmsg;
1174 {
1175 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1176 }
1177
1178 static long
1179 extract_spr (insn, invalid)
1180 unsigned long insn;
1181 int *invalid;
1182 {
1183 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1184 }
1185
1186 /* The TBR field in an XFX instruction. This is just like SPR, but it
1187 is optional. When TBR is omitted, it must be inserted as 268 (the
1188 magic number of the TB register). These functions treat 0
1189 (indicating an omitted optional operand) as 268. This means that
1190 ``mftb 4,0'' is not handled correctly. This does not matter very
1191 much, since the architecture manual does not define mftb as
1192 accepting any values other than 268 or 269. */
1193
1194 #define TB (268)
1195
1196 static unsigned long
1197 insert_tbr (insn, value, errmsg)
1198 unsigned long insn;
1199 long value;
1200 const char **errmsg;
1201 {
1202 if (value == 0)
1203 value = TB;
1204 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1205 }
1206
1207 static long
1208 extract_tbr (insn, invalid)
1209 unsigned long insn;
1210 int *invalid;
1211 {
1212 long ret;
1213
1214 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1215 if (ret == TB)
1216 ret = 0;
1217 return ret;
1218 }
1219 \f
1220 /* Macros used to form opcodes. */
1221
1222 /* The main opcode. */
1223 #define OP(x) (((x) & 0x3f) << 26)
1224 #define OP_MASK OP (0x3f)
1225
1226 /* The main opcode combined with a trap code in the TO field of a D
1227 form instruction. Used for extended mnemonics for the trap
1228 instructions. */
1229 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
1230 #define OPTO_MASK (OP_MASK | TO_MASK)
1231
1232 /* The main opcode combined with a comparison size bit in the L field
1233 of a D form or X form instruction. Used for extended mnemonics for
1234 the comparison instructions. */
1235 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
1236 #define OPL_MASK OPL (0x3f,1)
1237
1238 /* An A form instruction. */
1239 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
1240 #define A_MASK A (0x3f, 0x1f, 1)
1241
1242 /* An A_MASK with the FRB field fixed. */
1243 #define AFRB_MASK (A_MASK | FRB_MASK)
1244
1245 /* An A_MASK with the FRC field fixed. */
1246 #define AFRC_MASK (A_MASK | FRC_MASK)
1247
1248 /* An A_MASK with the FRA and FRC fields fixed. */
1249 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1250
1251 /* A B form instruction. */
1252 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
1253 #define B_MASK B (0x3f, 1, 1)
1254
1255 /* A B form instruction setting the BO field. */
1256 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
1257 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1258
1259 /* A BBO_MASK with the y bit of the BO field removed. This permits
1260 matching a conditional branch regardless of the setting of the y
1261 bit. */
1262 #define Y_MASK (1 << 21)
1263 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1264
1265 /* A B form instruction setting the BO field and the condition bits of
1266 the BI field. */
1267 #define BBOCB(op, bo, cb, aa, lk) \
1268 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
1269 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1270
1271 /* A BBOCB_MASK with the y bit of the BO field removed. */
1272 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1273
1274 /* A BBOYCB_MASK in which the BI field is fixed. */
1275 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1276
1277 /* The main opcode mask with the RA field clear. */
1278 #define DRA_MASK (OP_MASK | RA_MASK)
1279
1280 /* A DS form instruction. */
1281 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1282 #define DS_MASK DSO (0x3f, 3)
1283
1284 /* An M form instruction. */
1285 #define M(op, rc) (OP (op) | ((rc) & 1))
1286 #define M_MASK M (0x3f, 1)
1287
1288 /* An M form instruction with the ME field specified. */
1289 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
1290
1291 /* An M_MASK with the MB and ME fields fixed. */
1292 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1293
1294 /* An M_MASK with the SH and ME fields fixed. */
1295 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1296
1297 /* An MD form instruction. */
1298 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
1299 #define MD_MASK MD (0x3f, 0x7, 1)
1300
1301 /* An MD_MASK with the MB field fixed. */
1302 #define MDMB_MASK (MD_MASK | MB6_MASK)
1303
1304 /* An MD_MASK with the SH field fixed. */
1305 #define MDSH_MASK (MD_MASK | SH6_MASK)
1306
1307 /* An MDS form instruction. */
1308 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
1309 #define MDS_MASK MDS (0x3f, 0xf, 1)
1310
1311 /* An MDS_MASK with the MB field fixed. */
1312 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1313
1314 /* An SC form instruction. */
1315 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
1316 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
1317
1318 /* An X form instruction. */
1319 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1320
1321 /* An X form instruction with the RC bit specified. */
1322 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1323
1324 /* The mask for an X form instruction. */
1325 #define X_MASK XRC (0x3f, 0x3ff, 1)
1326
1327 /* An X_MASK with the RA field fixed. */
1328 #define XRA_MASK (X_MASK | RA_MASK)
1329
1330 /* An X_MASK with the RB field fixed. */
1331 #define XRB_MASK (X_MASK | RB_MASK)
1332
1333 /* An X_MASK with the RT field fixed. */
1334 #define XRT_MASK (X_MASK | RT_MASK)
1335
1336 /* An X_MASK with the RA and RB fields fixed. */
1337 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1338
1339 /* An X_MASK with the RT and RA fields fixed. */
1340 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1341
1342 /* An X form comparison instruction. */
1343 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
1344
1345 /* The mask for an X form comparison instruction. */
1346 #define XCMP_MASK (X_MASK | (1 << 22))
1347
1348 /* The mask for an X form comparison instruction with the L field
1349 fixed. */
1350 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1351
1352 /* An X form trap instruction with the TO field specified. */
1353 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1354 #define XTO_MASK (X_MASK | TO_MASK)
1355
1356 /* An XFL form instruction. */
1357 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1358 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1359
1360 /* An XL form instruction with the LK field set to 0. */
1361 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1362
1363 /* An XL form instruction which uses the LK field. */
1364 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1365
1366 /* The mask for an XL form instruction. */
1367 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1368
1369 /* An XL form instruction which explicitly sets the BO field. */
1370 #define XLO(op, bo, xop, lk) \
1371 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1372 #define XLO_MASK (XL_MASK | BO_MASK)
1373
1374 /* An XL form instruction which explicitly sets the y bit of the BO
1375 field. */
1376 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1377 #define XLYLK_MASK (XL_MASK | Y_MASK)
1378
1379 /* An XL form instruction which sets the BO field and the condition
1380 bits of the BI field. */
1381 #define XLOCB(op, bo, cb, xop, lk) \
1382 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1383 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1384
1385 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1386 #define XLBB_MASK (XL_MASK | BB_MASK)
1387 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1388 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1389
1390 /* An XL_MASK with the BO and BB fields fixed. */
1391 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1392
1393 /* An XL_MASK with the BO, BI and BB fields fixed. */
1394 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1395
1396 /* An XO form instruction. */
1397 #define XO(op, xop, oe, rc) \
1398 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1399 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1400
1401 /* An XO_MASK with the RB field fixed. */
1402 #define XORB_MASK (XO_MASK | RB_MASK)
1403
1404 /* An XS form instruction. */
1405 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1406 #define XS_MASK XS (0x3f, 0x1ff, 1)
1407
1408 /* A mask for the FXM version of an XFX form instruction. */
1409 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1410
1411 /* An XFX form instruction with the FXM field filled in. */
1412 #define XFXM(op, xop, fxm) \
1413 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1414
1415 /* An XFX form instruction with the SPR field filled in. */
1416 #define XSPR(op, xop, spr) \
1417 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1418 #define XSPR_MASK (X_MASK | SPR_MASK)
1419
1420 /* An XFX form instruction with the SPR field filled in except for the
1421 SPRBAT field. */
1422 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1423
1424 /* An XFX form instruction with the SPR field filled in except for the
1425 SPRG field. */
1426 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1427
1428 /* The BO encodings used in extended conditional branch mnemonics. */
1429 #define BODNZF (0x0)
1430 #define BODNZFP (0x1)
1431 #define BODZF (0x2)
1432 #define BODZFP (0x3)
1433 #define BOF (0x4)
1434 #define BOFP (0x5)
1435 #define BODNZT (0x8)
1436 #define BODNZTP (0x9)
1437 #define BODZT (0xa)
1438 #define BODZTP (0xb)
1439 #define BOT (0xc)
1440 #define BOTP (0xd)
1441 #define BODNZ (0x10)
1442 #define BODNZP (0x11)
1443 #define BODZ (0x12)
1444 #define BODZP (0x13)
1445 #define BOU (0x14)
1446
1447 /* The BI condition bit encodings used in extended conditional branch
1448 mnemonics. */
1449 #define CBLT (0)
1450 #define CBGT (1)
1451 #define CBEQ (2)
1452 #define CBSO (3)
1453
1454 /* The TO encodings used in extended trap mnemonics. */
1455 #define TOLGT (0x1)
1456 #define TOLLT (0x2)
1457 #define TOEQ (0x4)
1458 #define TOLGE (0x5)
1459 #define TOLNL (0x5)
1460 #define TOLLE (0x6)
1461 #define TOLNG (0x6)
1462 #define TOGT (0x8)
1463 #define TOGE (0xc)
1464 #define TONL (0xc)
1465 #define TOLT (0x10)
1466 #define TOLE (0x14)
1467 #define TONG (0x14)
1468 #define TONE (0x18)
1469 #define TOU (0x1f)
1470 \f
1471 /* Smaller names for the flags so each entry in the opcodes table will
1472 fit on a single line. */
1473 #undef PPC
1474 #define PPC PPC_OPCODE_PPC
1475 #define POWER PPC_OPCODE_POWER
1476 #define POWER2 PPC_OPCODE_POWER2
1477 #define B32 PPC_OPCODE_32
1478 #define B64 PPC_OPCODE_64
1479 #define M601 PPC_OPCODE_601
1480 \f
1481 /* The opcode table.
1482
1483 The format of the opcode table is:
1484
1485 NAME OPCODE MASK FLAGS { OPERANDS }
1486
1487 NAME is the name of the instruction.
1488 OPCODE is the instruction opcode.
1489 MASK is the opcode mask; this is used to tell the disassembler
1490 which bits in the actual opcode must match OPCODE.
1491 FLAGS are flags indicated what processors support the instruction.
1492 OPERANDS is the list of operands.
1493
1494 The disassembler reads the table in order and prints the first
1495 instruction which matches, so this table is sorted to put more
1496 specific instructions before more general instructions. It is also
1497 sorted by major opcode. */
1498
1499 const struct powerpc_opcode powerpc_opcodes[] = {
1500 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1501 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1502 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1503 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1504 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1505 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1506 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1507 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1508 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1509 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1510 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1511 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1512 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1513 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1514 { "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1515
1516 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1517 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1518 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1519 { "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1520 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1521 { "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1522 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1523 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1524 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1525 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1526 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1527 { "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1528 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1529 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1530 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1531 { "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1532 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1533 { "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1534 { "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1535 { "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1536 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1537 { "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1538 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1539 { "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1540 { "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1541 { "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1542 { "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1543 { "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1544 { "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1545 { "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1546
1547 { "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1548 { "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1549
1550 { "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1551 { "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1552
1553 { "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
1554
1555 { "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1556 { "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1557 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1558 { "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1559
1560 { "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1561 { "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1562 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1563 { "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1564
1565 { "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1566 { "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1567 { "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1568
1569 { "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1570 { "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1571 { "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1572
1573 { "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1574 { "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1575 { "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1576 { "cal", OP(14), OP_MASK, POWER, { RT, D, RA } },
1577 { "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1578 { "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1579
1580 { "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
1581 { "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
1582 { "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
1583 { "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
1584 { "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1585
1586 { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1587 { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1588 { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
1589 { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
1590 { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1591 { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1592 { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
1593 { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
1594 { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1595 { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1596 { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
1597 { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
1598 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1599 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1600 { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
1601 { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
1602 { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1603 { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1604 { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1605 { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1606 { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1607 { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1608 { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1609 { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1610 { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1611 { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1612 { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1613 { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1614 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1615 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1616 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1617 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1618 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1619 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1620 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1621 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1622 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1623 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1624 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1625 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1626 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1627 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1628 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1629 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1630 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1631 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1632 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1633 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1634 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1635 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1636 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1637 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1638 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1639 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1640 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1641 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1642 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1643 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1644 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1645 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1646 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1647 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1648 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1649 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1650 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1651 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1652 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1653 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1654 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1655 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1656 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1657 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1658 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1659 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1660 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1661 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1662 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1663 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1664 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1665 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1666 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1667 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1668 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1669 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1670 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1671 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1672 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1673 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1674 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1675 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1676 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1677 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1678 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1679 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1680 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1681 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1682 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1683 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1684 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1685 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1686 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1687 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1688 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1689 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1690 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1691 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1692 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1693 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1694 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1695 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1696 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1697 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1698 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1699 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1700 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1701 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1702 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1703 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1704 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1705 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1706 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1707 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1708 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1709 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1710 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1711 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1712 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1713 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1714 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1715 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1716 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1717 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1718 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1719 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1720 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1721 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1722 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1723 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1724 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1725 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1726 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1727 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1728 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1729 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1730 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1731 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1732 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1733 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1734 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1735 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1736 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1737 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1738 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1739 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1740 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1741 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1742 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1743 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1744 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1745 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1746 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1747 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1748 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1749 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1750 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1751 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1752 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1753 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1754 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1755 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1756 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1757 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1758 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1759 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1760 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1761 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1762 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1763 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1764 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1765 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1766 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1767 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1768 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1769 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1770 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1771 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1772 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1773 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1774 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1775 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1776 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1777 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1778 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1779 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1780 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1781 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1782 { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1783 { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1784 { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1785 { "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1786 { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1787 { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1788 { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1789 { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1790 { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1791 { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1792 { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1793 { "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1794 { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1795 { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1796 { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1797 { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1798 { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1799 { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1800 { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1801 { "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1802 { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1803 { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1804 { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1805 { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1806 { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1807 { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1808 { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1809 { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1810 { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1811 { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1812 { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1813 { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1814 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1815 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1816 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1817 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1818 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1819 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1820 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1821 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1822 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1823 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1824 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1825 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1826 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1827 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1828 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1829 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1830 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1831 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1832 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1833 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1834 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1835 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1836 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1837 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1838 { "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1839 { "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1840 { "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1841 { "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1842 { "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1843 { "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1844 { "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1845 { "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1846 { "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1847 { "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1848 { "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1849 { "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1850
1851 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1852 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1853 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1854 { "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1855 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1856
1857 { "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1858 { "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1859 { "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1860 { "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1861
1862 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1863
1864 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1865 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1866 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1867 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1868 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1869 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1870 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1871 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1872 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1873 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1874 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1875 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1876 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1877 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1878 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1879 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1880 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1881 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1882 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1883 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1884 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1885 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1886 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1887 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1888 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1889 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1890 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1891 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1892 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1893 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1894 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1895 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1896 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1897 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1898 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1899 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1900 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1901 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1902 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1903 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1904 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1905 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1906 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1907 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1908 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1909 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1910 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1911 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1912 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1913 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1914 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1915 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1916 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1917 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1918 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1919 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1920 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1921 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1922 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1923 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1924 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1925 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1926 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1927 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1928 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1929 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1930 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1931 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1932 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1933 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1934 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1935 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1936 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1937 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1938 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1939 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1940 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1941 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1942 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1943 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1944 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1945 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1946 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1947 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1948 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1949 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1950 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1951 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1952 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1953 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1954 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1955 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1956 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1957 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1958 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1959 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1960 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1961 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1962 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1963 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1964 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1965 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1966 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1967 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1968 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1969 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1970 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1971 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1972 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1973 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1974 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1975 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1976 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1977 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1978 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1979 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1980 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1981 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1982 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1983 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1984 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1985 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1986 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1987 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1988 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1989 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1990 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1991 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1992 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1993 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1994 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1995 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1996 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1997 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1998 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1999 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
2000 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
2001 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
2002 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
2003 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
2004 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
2005 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
2006 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
2007 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
2008 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
2009 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
2010 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
2011 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
2012 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
2013 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
2014 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
2015 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
2016 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
2017 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
2018 { "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
2019 { "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
2020
2021 { "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
2022 { "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
2023
2024 { "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
2025 { "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
2026
2027 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2028
2029 { "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
2030
2031 { "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
2032 { "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
2033
2034 { "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
2035 { "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
2036
2037 { "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
2038
2039 { "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
2040
2041 { "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
2042 { "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
2043
2044 { "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
2045
2046 { "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
2047 { "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
2048
2049 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
2050 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
2051 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2052 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2053 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2054 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2055 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2056 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2057 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2058 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2059 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2060 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2061 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2062 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2063 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2064 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2065 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2066 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2067 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2068 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2069 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2070 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2071 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2072 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2073 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2074 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2075 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2076 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2077 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2078 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2079 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2080 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2081 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2082 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2083 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2084 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2085 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2086 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2087 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2088 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2089 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2090 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2091 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2092 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2093 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2094 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2095 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2096 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2097 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2098 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2099 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2100 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2101 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
2102 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2103 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2104 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
2105 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2106 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2107 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
2108 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2109 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2110 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
2111 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2112 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2113 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2114 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2115 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2116 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2117 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2118 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2119 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
2120 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2121 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2122 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
2123 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
2124 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
2125 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
2126 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
2127 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
2128 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
2129 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
2130 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
2131 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
2132 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
2133 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
2134 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
2135 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
2136 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
2137 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
2138 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
2139 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
2140 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
2141 { "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
2142 { "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
2143
2144 { "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2145 { "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2146
2147 { "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2148 { "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2149
2150 { "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
2151 { "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
2152 { "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2153 { "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2154 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
2155 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
2156 { "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
2157 { "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
2158
2159 { "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
2160 { "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
2161
2162 { "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
2163 { "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
2164 { "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
2165 { "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
2166 { "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
2167 { "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
2168
2169 { "nop", OP(24), 0xffffffff, PPC, { 0 } },
2170 { "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
2171 { "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
2172
2173 { "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
2174 { "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
2175
2176 { "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
2177 { "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
2178
2179 { "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
2180 { "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
2181
2182 { "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
2183 { "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
2184
2185 { "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
2186 { "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
2187
2188 { "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
2189 { "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
2190 { "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2191 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
2192 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
2193 { "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2194
2195 { "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
2196 { "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
2197
2198 { "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2199 { "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2200
2201 { "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2202 { "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
2203
2204 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
2205 { "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
2206 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
2207 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
2208
2209 { "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
2210 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
2211
2212 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
2213 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
2214 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
2215 { "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
2216
2217 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
2218 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
2219 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
2220 { "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
2221 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
2222 { "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
2223 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
2224 { "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
2225 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
2226 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
2227 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
2228 { "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
2229 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
2230 { "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
2231 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
2232 { "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
2233 { "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
2234 { "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
2235 { "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
2236 { "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
2237 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
2238 { "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
2239 { "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
2240 { "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
2241 { "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
2242 { "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
2243 { "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
2244 { "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
2245 { "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
2246 { "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
2247 { "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
2248
2249 { "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
2250 { "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
2251 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2252 { "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
2253 { "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
2254 { "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
2255 { "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
2256 { "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
2257 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2258 { "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
2259 { "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
2260 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2261
2262 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2263 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2264
2265 { "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
2266 { "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
2267 { "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
2268 { "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
2269 { "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
2270 { "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
2271 { "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
2272 { "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
2273
2274 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2275 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2276
2277 { "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
2278
2279 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2280
2281 { "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
2282
2283 { "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
2284 { "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
2285
2286 { "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
2287 { "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
2288 { "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
2289 { "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
2290
2291 { "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
2292 { "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
2293 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
2294 { "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
2295
2296 { "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
2297 { "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
2298
2299 { "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2300 { "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2301
2302 { "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
2303 { "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
2304
2305 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
2306 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
2307 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
2308 { "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
2309
2310 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2311 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2312 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2313 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2314 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2315 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2316 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2317 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2318
2319 { "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
2320
2321 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2322
2323 { "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
2324 { "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
2325
2326 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
2327 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
2328
2329 { "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2330 { "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2331
2332 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
2333 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
2334 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
2335 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
2336 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
2337 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
2338 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
2339 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
2340 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
2341 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
2342 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
2343 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
2344 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
2345 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
2346 { "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2347
2348 { "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2349 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2350
2351 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2352 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2353
2354 { "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
2355
2356 { "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2357
2358 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2359
2360 { "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2361
2362 { "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
2363 { "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
2364 { "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
2365 { "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
2366
2367 { "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2368 { "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2369 { "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2370 { "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2371
2372 { "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2373
2374 { "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
2375
2376 { "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2377 { "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2378 { "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2379 { "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2380
2381 { "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
2382 { "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
2383 { "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
2384 { "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
2385 { "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
2386 { "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
2387 { "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
2388 { "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
2389
2390 { "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
2391 { "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
2392 { "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } },
2393 { "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } },
2394 { "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } },
2395 { "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } },
2396 { "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
2397 { "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
2398
2399 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
2400 { "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
2401
2402 { "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
2403
2404 { "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
2405
2406 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2407
2408 { "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
2409 { "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
2410
2411 { "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
2412 { "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
2413
2414 { "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
2415 { "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
2416
2417 { "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
2418
2419 { "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
2420 { "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
2421
2422 { "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
2423 { "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
2424
2425 { "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
2426 { "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
2427 { "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } },
2428 { "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } },
2429 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } },
2430 { "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } },
2431 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } },
2432 { "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } },
2433
2434 { "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } },
2435 { "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } },
2436 { "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } },
2437 { "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } },
2438 { "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } },
2439 { "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } },
2440 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } },
2441 { "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } },
2442
2443 { "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
2444
2445 { "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
2446
2447 { "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
2448
2449 { "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
2450 { "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
2451
2452 { "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
2453 { "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
2454
2455 { "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
2456 { "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
2457 { "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } },
2458 { "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } },
2459 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } },
2460 { "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } },
2461 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } },
2462 { "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } },
2463
2464 { "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2465 { "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2466 { "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2467 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2468
2469 { "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } },
2470 { "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } },
2471 { "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } },
2472 { "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } },
2473 { "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } },
2474 { "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } },
2475 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } },
2476 { "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } },
2477
2478 { "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } },
2479 { "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } },
2480 { "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } },
2481 { "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } },
2482 { "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } },
2483 { "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } },
2484 { "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } },
2485 { "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } },
2486
2487 { "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } },
2488 { "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } },
2489
2490 { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2491
2492 { "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
2493
2494 { "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
2495 { "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
2496
2497 { "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2498 { "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2499 { "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2500 { "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2501
2502 { "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
2503 { "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
2504 { "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } },
2505 { "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } },
2506 { "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } },
2507 { "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } },
2508 { "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
2509 { "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
2510
2511 { "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
2512 { "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
2513
2514 { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2515
2516 { "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2517
2518 { "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
2519
2520 { "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2521 { "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2522
2523 { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2524 { "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } },
2525
2526 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2527
2528 { "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
2529
2530 { "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2531 { "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2532
2533 { "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
2534
2535 { "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2536 { "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2537 { "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2538 { "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2539
2540 { "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
2541 { "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
2542 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
2543 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
2544 { "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
2545 { "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
2546 { "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
2547 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2548 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
2549 { "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
2550 { "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
2551 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2552 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
2553 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
2554 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
2555 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2556 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
2557 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2558 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2559 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2560 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2561 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2562 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2563 { "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2564
2565 { "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2566
2567 { "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2568
2569 { "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
2570
2571 { "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2572 { "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2573 { "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2574 { "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2575
2576 { "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2577 { "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2578 { "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2579 { "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2580
2581 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2582
2583 { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2584 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2585
2586 { "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
2587
2588 { "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
2589
2590 { "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2591
2592 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2593
2594 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2595
2596 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2597
2598 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2599
2600 { "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2601 { "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2602
2603 { "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2604 { "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2605
2606 { "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } },
2607
2608 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2609
2610 { "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
2611
2612 { "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2613 { "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2614 { "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2615 { "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2616
2617 { "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
2618
2619 { "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2620 { "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2621 { "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2622 { "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2623
2624 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2625 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2626 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2627 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2628
2629 { "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } },
2630 { "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
2631 { "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
2632 { "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
2633 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2634 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
2635 { "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
2636 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
2637 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
2638 { "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
2639 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2640 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
2641 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
2642 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
2643 { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2644 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
2645 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2646 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2647 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2648 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2649 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2650 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2651 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2652 { "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2653
2654 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2655
2656 { "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2657 { "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2658
2659 { "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2660 { "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2661 { "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2662 { "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2663
2664 { "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2665 { "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2666 { "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2667 { "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2668
2669 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2670 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2671 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2672 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2673
2674 { "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } },
2675
2676 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2677
2678 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
2679
2680 { "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } },
2681
2682 { "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2683 { "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2684
2685 { "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2686 { "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2687
2688 { "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2689
2690 { "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2691 { "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2692 { "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2693 { "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2694
2695 { "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
2696 { "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
2697
2698 { "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2699 { "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2700
2701 { "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
2702 { "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
2703
2704 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2705
2706 { "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2707
2708 { "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2709
2710 { "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2711 { "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2712
2713 { "sync", X(31,598), 0xffffffff, PPC, { 0 } },
2714 { "dcs", X(31,598), 0xffffffff, POWER, { 0 } },
2715
2716 { "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2717
2718 { "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2719
2720 { "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
2721
2722 { "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2723
2724 { "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
2725
2726 { "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2727 { "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2728
2729 { "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2730 { "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2731
2732 { "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2733
2734 { "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
2735 { "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
2736
2737 { "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
2738 { "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
2739
2740 { "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2741
2742 { "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
2743 { "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
2744
2745 { "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2746 { "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2747
2748 { "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2749
2750 { "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
2751 { "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
2752
2753 { "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
2754 { "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
2755
2756 { "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2757
2758 { "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
2759 { "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
2760
2761 { "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2762
2763 { "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2764 { "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2765 { "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2766 { "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2767
2768 { "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2769 { "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2770
2771 { "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2772
2773 { "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2774 { "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2775 { "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2776 { "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2777
2778 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2779
2780 { "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2781
2782 { "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
2783 { "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
2784
2785 { "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
2786 { "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
2787
2788 { "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
2789 { "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
2790 { "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
2791 { "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
2792
2793 { "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
2794 { "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
2795
2796 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2797 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2798
2799 { "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
2800
2801 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2802
2803 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2804
2805 { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2806 { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2807
2808 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2809 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2810
2811 { "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
2812 { "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
2813
2814 { "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
2815 { "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
2816
2817 { "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
2818
2819 { "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
2820
2821 { "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
2822 { "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
2823
2824 { "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
2825 { "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
2826
2827 { "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
2828
2829 { "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
2830
2831 { "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
2832
2833 { "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
2834
2835 { "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
2836
2837 { "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
2838
2839 { "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
2840
2841 { "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
2842
2843 { "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
2844 { "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
2845
2846 { "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
2847 { "stm", OP(47), OP_MASK, POWER, { RS, D, RA } },
2848
2849 { "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
2850
2851 { "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2852
2853 { "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
2854
2855 { "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2856
2857 { "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
2858
2859 { "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2860
2861 { "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
2862
2863 { "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2864
2865 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
2866
2867 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
2868
2869 { "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
2870
2871 { "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
2872
2873 { "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
2874
2875 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2876 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2877
2878 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2879 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2880
2881 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2882 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2883
2884 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2885 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2886
2887 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2888 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2889
2890 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2891 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2892
2893 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2894 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2895
2896 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2897 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2898
2899 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2900 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2901
2902 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2903 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2904
2905 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
2906
2907 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
2908
2909 { "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
2910
2911 { "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
2912
2913 { "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2914
2915 { "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2916 { "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2917
2918 { "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
2919 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
2920 { "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
2921 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
2922
2923 { "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
2924 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
2925 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
2926 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
2927
2928 { "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2929 { "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2930 { "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2931 { "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2932
2933 { "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2934 { "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2935 { "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2936 { "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2937
2938 { "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2939 { "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2940 { "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2941 { "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2942
2943 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2944 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2945
2946 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2947 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2948
2949 { "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2950 { "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2951 { "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2952 { "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2953
2954 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2955 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2956
2957 { "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2958 { "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2959 { "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2960 { "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2961
2962 { "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2963 { "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2964 { "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2965 { "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2966
2967 { "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2968 { "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2969 { "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2970 { "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2971
2972 { "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2973 { "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2974 { "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2975 { "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2976
2977 { "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2978
2979 { "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } },
2980 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } },
2981
2982 { "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2983 { "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2984
2985 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2986
2987 { "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } },
2988 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } },
2989
2990 { "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2991 { "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2992
2993 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2994 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2995
2996 { "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2997 { "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2998
2999 { "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
3000 { "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
3001
3002 { "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } },
3003 { "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } },
3004
3005 { "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } },
3006 { "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } },
3007
3008 { "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } },
3009 { "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } },
3010
3011 { "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } },
3012 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } },
3013
3014 { "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } },
3015 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } },
3016
3017 };
3018
3019 const int powerpc_num_opcodes =
3020 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3021 \f
3022 /* The macro table. This is only used by the assembler. */
3023
3024 const struct powerpc_macro powerpc_macros[] = {
3025 { "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" },
3026 { "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" },
3027 { "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3028 { "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3029 { "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
3030 { "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3031 { "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" },
3032 { "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" },
3033 { "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" },
3034 { "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" },
3035 { "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" },
3036 { "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" },
3037 { "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" },
3038 { "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" },
3039 { "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" },
3040 { "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" },
3041
3042 { "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" },
3043 { "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" },
3044 { "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3045 { "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3046 { "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
3047 { "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
3048 { "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3049 { "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3050 { "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" },
3051 { "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" },
3052 { "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" },
3053 { "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" },
3054 { "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" },
3055 { "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" },
3056 { "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" },
3057 { "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" },
3058 { "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" },
3059 { "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" },
3060 { "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" },
3061 { "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" },
3062 { "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3063 { "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3064
3065 };
3066
3067 const int powerpc_num_macros =
3068 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
3069
3070 static int print_insn_powerpc(FILE *, unsigned long insn, unsigned memaddr, int dialect);
3071
3072 /* Print a big endian PowerPC instruction. For convenience, also
3073 disassemble instructions supported by the Motorola PowerPC 601. */
3074
3075 int print_insn_ppc (bfd_vma pc, disassemble_info *info)
3076 {
3077 return print_insn_powerpc (info->stream,
3078 (unsigned int)bfd_getb32((bfd_byte *)pc), pc,
3079 PPC_OPCODE_PPC | PPC_OPCODE_601);
3080 }
3081
3082 /* Print a PowerPC or POWER instruction. */
3083
3084 static int
3085 print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
3086 int dialect)
3087 {
3088 const struct powerpc_opcode *opcode;
3089 const struct powerpc_opcode *opcode_end;
3090 unsigned long op;
3091
3092 /* Get the major opcode of the instruction. */
3093 op = PPC_OP (insn);
3094
3095 /* Find the first match in the opcode table. We could speed this up
3096 a bit by doing a binary search on the major opcode. */
3097 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
3098 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
3099 {
3100 unsigned long table_op;
3101 const unsigned char *opindex;
3102 const struct powerpc_operand *operand;
3103 int invalid;
3104 int need_comma;
3105 int need_paren;
3106
3107 table_op = PPC_OP (opcode->opcode);
3108 if (op < table_op)
3109 break;
3110 if (op > table_op)
3111 continue;
3112
3113 if ((insn & opcode->mask) != opcode->opcode
3114 || (opcode->flags & dialect) == 0)
3115 continue;
3116
3117 /* Make two passes over the operands. First see if any of them
3118 have extraction functions, and, if they do, make sure the
3119 instruction is valid. */
3120 invalid = 0;
3121 for (opindex = opcode->operands; *opindex != 0; opindex++)
3122 {
3123 operand = powerpc_operands + *opindex;
3124 if (operand->extract)
3125 (*operand->extract) (insn, &invalid);
3126 }
3127 if (invalid)
3128 continue;
3129
3130 /* The instruction is valid. */
3131 fprintf(out, "%s", opcode->name);
3132 if (opcode->operands[0] != 0)
3133 fprintf(out, "\t");
3134
3135 /* Now extract and print the operands. */
3136 need_comma = 0;
3137 need_paren = 0;
3138 for (opindex = opcode->operands; *opindex != 0; opindex++)
3139 {
3140 long value;
3141
3142 operand = powerpc_operands + *opindex;
3143
3144 /* Operands that are marked FAKE are simply ignored. We
3145 already made sure that the extract function considered
3146 the instruction to be valid. */
3147 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
3148 continue;
3149
3150 /* Extract the value from the instruction. */
3151 if (operand->extract)
3152 value = (*operand->extract) (insn, (int *) 0);
3153 else
3154 {
3155 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
3156 if ((operand->flags & PPC_OPERAND_SIGNED) != 0
3157 && (value & (1 << (operand->bits - 1))) != 0)
3158 value -= 1 << operand->bits;
3159 }
3160
3161 /* If the operand is optional, and the value is zero, don't
3162 print anything. */
3163 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
3164 && (operand->flags & PPC_OPERAND_NEXT) == 0
3165 && value == 0)
3166 continue;
3167
3168 if (need_comma)
3169 {
3170 fprintf(out, ",");
3171 need_comma = 0;
3172 }
3173
3174 /* Print the operand as directed by the flags. */
3175 if ((operand->flags & PPC_OPERAND_GPR) != 0)
3176 fprintf(out, "r%ld", value);
3177 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
3178 fprintf(out, "f%ld", value);
3179 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
3180 fprintf(out, "%08lX", memaddr + value);
3181 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
3182 fprintf(out, "%08lX", value & 0xffffffff);
3183 else if ((operand->flags & PPC_OPERAND_CR) == 0
3184 || (dialect & PPC_OPCODE_PPC) == 0)
3185 fprintf(out, "%ld", value);
3186 else
3187 {
3188 if (operand->bits == 3)
3189 fprintf(out, "cr%ld", value);
3190 else
3191 {
3192 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
3193 int cr;
3194 int cc;
3195
3196 cr = value >> 2;
3197 if (cr != 0)
3198 fprintf(out, "4*cr%d", cr);
3199 cc = value & 3;
3200 if (cc != 0)
3201 {
3202 if (cr != 0)
3203 fprintf(out, "+");
3204 fprintf(out, "%s", cbnames[cc]);
3205 }
3206 }
3207 }
3208
3209 if (need_paren)
3210 {
3211 fprintf(out, ")");
3212 need_paren = 0;
3213 }
3214
3215 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
3216 need_comma = 1;
3217 else
3218 {
3219 fprintf(out, "(");
3220 need_paren = 1;
3221 }
3222 }
3223
3224 /* We have found and printed an instruction; return. */
3225 return 4;
3226 }
3227
3228 /* We could not find a match. */
3229 fprintf(out, ".long 0x%lx", insn);
3230
3231 return 4;
3232 }
Stable branch of Qemu 0.9.1