cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_DEFS_H
  21 #define CPU_DEFS_H
  22
  23 #include "config.h"
  24 #include <setjmp.h>
  25 #include <inttypes.h>
  26 #include "osdep.h"
  27
  28 #ifndef TARGET_LONG_BITS
  29 #error TARGET_LONG_BITS must be defined before including this header
  30 #endif
  31
  32 #ifndef TARGET_PHYS_ADDR_BITS
  33 #if TARGET_LONG_BITS >= HOST_LONG_BITS
  34 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
  35 #else
  36 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
  37 #endif
  38 #endif
  39
  40 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  41
  42 /* target_ulong is the type of a virtual address */
  43 #if TARGET_LONG_SIZE == 4
  44 typedef int32_t target_long;
  45 typedef uint32_t target_ulong;
  46 #define TARGET_FMT_lx "%08x"
  47 #define TARGET_FMT_ld "%d"
  48 #define TARGET_FMT_lu "%u"
  49 #elif TARGET_LONG_SIZE == 8
  50 typedef int64_t target_long;
  51 typedef uint64_t target_ulong;
  52 #define TARGET_FMT_lx "%016" PRIx64
  53 #define TARGET_FMT_ld "%" PRId64
  54 #define TARGET_FMT_lu "%" PRIu64
  55 #else
  56 #error TARGET_LONG_SIZE undefined
  57 #endif
  58
  59 /* target_phys_addr_t is the type of a physical address (its size can
  60    be different from 'target_ulong'). We have sizeof(target_phys_addr)
  61    = max(sizeof(unsigned long),
  62    sizeof(size_of_target_physical_address)) because we must pass a
  63    host pointer to memory operations in some cases */
  64
  65 #if TARGET_PHYS_ADDR_BITS == 32
  66 typedef uint32_t target_phys_addr_t;
  67 #define TARGET_FMT_plx "%08x"
  68 #elif TARGET_PHYS_ADDR_BITS == 64
  69 typedef uint64_t target_phys_addr_t;
  70 #define TARGET_FMT_plx "%016" PRIx64
  71 #else
  72 #error TARGET_PHYS_ADDR_BITS undefined
  73 #endif
  74
  75 /* address in the RAM (different from a physical address) */
  76 typedef unsigned long ram_addr_t;
  77
  78 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
  79
  80 #define EXCP_INTERRUPT  0x10000 /* async interruption */
  81 #define EXCP_HLT        0x10001 /* hlt instruction reached */
  82 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  83 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  84 #define MAX_BREAKPOINTS 32
  85 #define MAX_WATCHPOINTS 32
  86
  87 #define TB_JMP_CACHE_BITS 12
  88 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
  89
  90 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
  91    addresses on the same page.  The top bits are the same.  This allows
  92    TLB invalidation to quickly clear a subset of the hash table.  */
  93 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
  94 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
  95 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
  96 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
  97
  98 #define CPU_TLB_BITS 8
  99 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
 100
 101 typedef struct CPUTLBEntry {
 102     /* bit 31 to TARGET_PAGE_BITS : virtual address
 103        bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
 104                                               zone number
 105        bit 3                      : indicates that the entry is invalid
 106        bit 2..0                   : zero
 107     */
 108     target_ulong addr_read;
 109     target_ulong addr_write;
 110     target_ulong addr_code;
 111     /* addend to virtual address to get physical address */
 112     target_phys_addr_t addend;
 113 } CPUTLBEntry;
 114
 115 /* Alpha has 4 different running levels */
 116 #if defined(TARGET_ALPHA)
 117 #define NB_MMU_MODES 4
 118 #elif defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 119 #define NB_MMU_MODES 3
 120 #else
 121 #define NB_MMU_MODES 2
 122 #endif
 123
 124 #define CPU_COMMON                                                      \
 125     struct TranslationBlock *current_tb; /* currently executing TB  */  \
 126     /* soft mmu support */                                              \
 127     /* in order to avoid passing too many arguments to the memory       \
 128        write helpers, we store some rarely used information in the CPU  \
 129        context) */                                                      \
 130     unsigned long mem_write_pc; /* host pc at which the memory was      \
 131                                    written */                           \
 132     target_ulong mem_write_vaddr; /* target virtual addr at which the   \
 133                                      memory was written */              \
 134     /* 0 = kernel, 1 = user */                                          \
 135     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 136     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
 137                                                                         \
 138     /* from this point: preserved by CPU reset */                       \
 139     /* ice debug support */                                             \
 140     target_ulong breakpoints[MAX_BREAKPOINTS];                          \
 141     int nb_breakpoints;                                                 \
 142     int singlestep_enabled;                                             \
 143                                                                         \
 144     struct {                                                            \
 145         target_ulong vaddr;                                             \
 146         target_phys_addr_t addend;                                      \
 147     } watchpoint[MAX_WATCHPOINTS];                                      \
 148     int nb_watchpoints;                                                 \
 149     int watchpoint_hit;                                                 \
 150                                                                         \
 151     void *next_cpu; /* next CPU sharing TB cache */                     \
 152     int cpu_index; /* CPU index (informative) */                        \
 153     /* user data */                                                     \
 154     void *opaque;
 155
 156 #endif