2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define DO_SINGLE_STEP
31 #define ALPHA_DEBUG_DISAS
34 typedef struct DisasContext DisasContext
;
38 #if !defined (CONFIG_USER_ONLY)
44 #ifdef USE_DIRECT_JUMP
47 #define TBPARAM(x) (long)(x)
51 #define DEF(s, n, copy_size) INDEX_op_ ## s,
57 static uint16_t *gen_opc_ptr
;
58 static uint32_t *gen_opparam_ptr
;
62 static inline void gen_op_nop (void)
64 #if defined(GENERATE_NOP)
69 #define GEN32(func, NAME) \
70 static GenOpFunc *NAME ## _table [32] = { \
71 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
72 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
73 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
74 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
75 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
76 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
77 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
78 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
80 static inline void func(int n) \
82 NAME ## _table[n](); \
86 /* Special hacks for ir31 */
87 #define gen_op_load_T0_ir31 gen_op_reset_T0
88 #define gen_op_load_T1_ir31 gen_op_reset_T1
89 #define gen_op_load_T2_ir31 gen_op_reset_T2
90 #define gen_op_store_T0_ir31 gen_op_nop
91 #define gen_op_store_T1_ir31 gen_op_nop
92 #define gen_op_store_T2_ir31 gen_op_nop
93 #define gen_op_cmov_ir31 gen_op_nop
94 GEN32(gen_op_load_T0_ir
, gen_op_load_T0_ir
);
95 GEN32(gen_op_load_T1_ir
, gen_op_load_T1_ir
);
96 GEN32(gen_op_load_T2_ir
, gen_op_load_T2_ir
);
97 GEN32(gen_op_store_T0_ir
, gen_op_store_T0_ir
);
98 GEN32(gen_op_store_T1_ir
, gen_op_store_T1_ir
);
99 GEN32(gen_op_store_T2_ir
, gen_op_store_T2_ir
);
100 GEN32(gen_op_cmov_ir
, gen_op_cmov_ir
);
102 static inline void gen_load_ir (DisasContext
*ctx
, int irn
, int Tn
)
106 gen_op_load_T0_ir(irn
);
109 gen_op_load_T1_ir(irn
);
112 gen_op_load_T2_ir(irn
);
117 static inline void gen_store_ir (DisasContext
*ctx
, int irn
, int Tn
)
121 gen_op_store_T0_ir(irn
);
124 gen_op_store_T1_ir(irn
);
127 gen_op_store_T2_ir(irn
);
133 /* Special hacks for fir31 */
134 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
135 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
136 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
137 #define gen_op_store_FT0_fir31 gen_op_nop
138 #define gen_op_store_FT1_fir31 gen_op_nop
139 #define gen_op_store_FT2_fir31 gen_op_nop
140 #define gen_op_cmov_fir31 gen_op_nop
141 GEN32(gen_op_load_FT0_fir
, gen_op_load_FT0_fir
);
142 GEN32(gen_op_load_FT1_fir
, gen_op_load_FT1_fir
);
143 GEN32(gen_op_load_FT2_fir
, gen_op_load_FT2_fir
);
144 GEN32(gen_op_store_FT0_fir
, gen_op_store_FT0_fir
);
145 GEN32(gen_op_store_FT1_fir
, gen_op_store_FT1_fir
);
146 GEN32(gen_op_store_FT2_fir
, gen_op_store_FT2_fir
);
147 GEN32(gen_op_cmov_fir
, gen_op_cmov_fir
);
149 static inline void gen_load_fir (DisasContext
*ctx
, int firn
, int Tn
)
153 gen_op_load_FT0_fir(firn
);
156 gen_op_load_FT1_fir(firn
);
159 gen_op_load_FT2_fir(firn
);
164 static inline void gen_store_fir (DisasContext
*ctx
, int firn
, int Tn
)
168 gen_op_store_FT0_fir(firn
);
171 gen_op_store_FT1_fir(firn
);
174 gen_op_store_FT2_fir(firn
);
180 #if defined(CONFIG_USER_ONLY)
181 #define OP_LD_TABLE(width) \
182 static GenOpFunc *gen_op_ld##width[] = { \
183 &gen_op_ld##width##_raw, \
185 #define OP_ST_TABLE(width) \
186 static GenOpFunc *gen_op_st##width[] = { \
187 &gen_op_st##width##_raw, \
190 #define OP_LD_TABLE(width) \
191 static GenOpFunc *gen_op_ld##width[] = { \
192 &gen_op_ld##width##_kernel, \
193 &gen_op_ld##width##_user, /* executive */ \
194 &gen_op_ld##width##_data, /* supervisor */ \
195 &gen_op_ld##width##_data, /* user */ \
197 #define OP_ST_TABLE(width) \
198 static GenOpFunc *gen_op_st##width[] = { \
199 &gen_op_st##width##_kernel, \
200 &gen_op_st##width##_user, /* executive */ \
201 &gen_op_st##width##_data, /* supervisor */ \
202 &gen_op_st##width##_data, /* user */ \
206 #define GEN_LD(width) \
207 OP_LD_TABLE(width); \
208 static void gen_ld##width (DisasContext *ctx) \
210 (*gen_op_ld##width[ctx->mem_idx])(); \
213 #define GEN_ST(width) \
214 OP_ST_TABLE(width); \
215 static void gen_st##width (DisasContext *ctx) \
217 (*gen_op_st##width[ctx->mem_idx])(); \
244 #if defined(__i386__) || defined(__x86_64__)
245 static inline void gen_op_set_s16_T0 (int16_t imm
)
247 gen_op_set_s32_T0((int32_t)imm
);
250 static inline void gen_op_set_s16_T1 (int16_t imm
)
252 gen_op_set_s32_T1((int32_t)imm
);
255 static inline void gen_op_set_u16_T0 (uint16_t imm
)
257 gen_op_set_s32_T0((uint32_t)imm
);
260 static inline void gen_op_set_u16_T1 (uint16_t imm
)
262 gen_op_set_s32_T1((uint32_t)imm
);
266 static inline void gen_set_sT0 (DisasContext
*ctx
, int64_t imm
)
278 gen_op_set_s16_T0(imm16
);
281 gen_op_set_s32_T0(imm32
);
284 #if 0 // Qemu does not know how to do this...
285 gen_op_set_64_T0(imm
);
287 gen_op_set_64_T0(imm
>> 32, imm
);
292 static inline void gen_set_sT1 (DisasContext
*ctx
, int64_t imm
)
304 gen_op_set_s16_T1(imm16
);
307 gen_op_set_s32_T1(imm32
);
310 #if 0 // Qemu does not know how to do this...
311 gen_op_set_64_T1(imm
);
313 gen_op_set_64_T1(imm
>> 32, imm
);
318 static inline void gen_set_uT0 (DisasContext
*ctx
, uint64_t imm
)
325 gen_op_set_u16_T0(imm
);
327 gen_op_set_u32_T0(imm
);
330 #if 0 // Qemu does not know how to do this...
331 gen_op_set_64_T0(imm
);
333 gen_op_set_64_T0(imm
>> 32, imm
);
338 static inline void gen_set_uT1 (DisasContext
*ctx
, uint64_t imm
)
345 gen_op_set_u16_T1(imm
);
347 gen_op_set_u32_T1(imm
);
350 #if 0 // Qemu does not know how to do this...
351 gen_op_set_64_T1(imm
);
353 gen_op_set_64_T1(imm
>> 32, imm
);
358 static inline void gen_update_pc (DisasContext
*ctx
)
360 if (!(ctx
->pc
>> 32)) {
361 gen_op_update_pc32(ctx
->pc
);
363 #if 0 // Qemu does not know how to do this...
364 gen_op_update_pc(ctx
->pc
);
366 gen_op_update_pc(ctx
->pc
>> 32, ctx
->pc
);
371 static inline void _gen_op_bcond (DisasContext
*ctx
)
373 #if 0 // Qemu does not know how to do this...
374 gen_op_bcond(ctx
->pc
);
376 gen_op_bcond(ctx
->pc
>> 32, ctx
->pc
);
380 static inline void gen_excp (DisasContext
*ctx
, int exception
, int error_code
)
383 gen_op_excp(exception
, error_code
);
386 static inline void gen_invalid (DisasContext
*ctx
)
388 gen_excp(ctx
, EXCP_OPCDEC
, 0);
391 static void gen_load_mem (DisasContext
*ctx
,
392 void (*gen_load_op
)(DisasContext
*ctx
),
393 int ra
, int rb
, int32_t disp16
, int clear
)
395 if (ra
== 31 && disp16
== 0) {
399 gen_load_ir(ctx
, rb
, 0);
401 gen_set_sT1(ctx
, disp16
);
407 gen_store_ir(ctx
, ra
, 1);
411 static void gen_store_mem (DisasContext
*ctx
,
412 void (*gen_store_op
)(DisasContext
*ctx
),
413 int ra
, int rb
, int32_t disp16
, int clear
)
415 gen_load_ir(ctx
, rb
, 0);
417 gen_set_sT1(ctx
, disp16
);
422 gen_load_ir(ctx
, ra
, 1);
423 (*gen_store_op
)(ctx
);
426 static void gen_load_fmem (DisasContext
*ctx
,
427 void (*gen_load_fop
)(DisasContext
*ctx
),
428 int ra
, int rb
, int32_t disp16
)
430 gen_load_ir(ctx
, rb
, 0);
432 gen_set_sT1(ctx
, disp16
);
435 (*gen_load_fop
)(ctx
);
436 gen_store_fir(ctx
, ra
, 1);
439 static void gen_store_fmem (DisasContext
*ctx
,
440 void (*gen_store_fop
)(DisasContext
*ctx
),
441 int ra
, int rb
, int32_t disp16
)
443 gen_load_ir(ctx
, rb
, 0);
445 gen_set_sT1(ctx
, disp16
);
448 gen_load_fir(ctx
, ra
, 1);
449 (*gen_store_fop
)(ctx
);
452 static void gen_bcond (DisasContext
*ctx
, void (*gen_test_op
)(void),
453 int ra
, int32_t disp16
)
456 gen_set_uT0(ctx
, ctx
->pc
);
457 gen_set_sT1(ctx
, disp16
<< 2);
460 gen_set_uT1(ctx
, ctx
->pc
);
462 gen_load_ir(ctx
, ra
, 0);
467 static void gen_fbcond (DisasContext
*ctx
, void (*gen_test_op
)(void),
468 int ra
, int32_t disp16
)
471 gen_set_uT0(ctx
, ctx
->pc
);
472 gen_set_sT1(ctx
, disp16
<< 2);
475 gen_set_uT1(ctx
, ctx
->pc
);
477 gen_load_fir(ctx
, ra
, 0);
482 static void gen_arith2 (DisasContext
*ctx
, void (*gen_arith_op
)(void),
483 int rb
, int rc
, int islit
, int8_t lit
)
486 gen_set_sT0(ctx
, lit
);
488 gen_load_ir(ctx
, rb
, 0);
490 gen_store_ir(ctx
, rc
, 0);
493 static void gen_arith3 (DisasContext
*ctx
, void (*gen_arith_op
)(void),
494 int ra
, int rb
, int rc
, int islit
, int8_t lit
)
496 gen_load_ir(ctx
, ra
, 0);
498 gen_set_sT1(ctx
, lit
);
500 gen_load_ir(ctx
, rb
, 1);
502 gen_store_ir(ctx
, rc
, 0);
505 static void gen_cmov (DisasContext
*ctx
, void (*gen_test_op
)(void),
506 int ra
, int rb
, int rc
, int islit
, int8_t lit
)
508 gen_load_ir(ctx
, ra
, 1);
510 gen_set_sT0(ctx
, lit
);
512 gen_load_ir(ctx
, rb
, 0);
517 static void gen_farith2 (DisasContext
*ctx
, void (*gen_arith_fop
)(void),
520 gen_load_fir(ctx
, rb
, 0);
522 gen_store_fir(ctx
, rc
, 0);
525 static void gen_farith3 (DisasContext
*ctx
, void (*gen_arith_fop
)(void),
526 int ra
, int rb
, int rc
)
528 gen_load_fir(ctx
, ra
, 0);
529 gen_load_fir(ctx
, rb
, 1);
531 gen_store_fir(ctx
, rc
, 0);
534 static void gen_fcmov (DisasContext
*ctx
, void (*gen_test_fop
)(void),
535 int ra
, int rb
, int rc
)
537 gen_load_fir(ctx
, ra
, 0);
538 gen_load_fir(ctx
, rb
, 1);
543 static void gen_fti (DisasContext
*ctx
, void (*gen_move_fop
)(void),
546 gen_load_fir(ctx
, rc
, 0);
548 gen_store_ir(ctx
, ra
, 0);
551 static void gen_itf (DisasContext
*ctx
, void (*gen_move_fop
)(void),
554 gen_load_ir(ctx
, ra
, 0);
556 gen_store_fir(ctx
, rc
, 0);
559 static void gen_s4addl (void)
565 static void gen_s4subl (void)
571 static void gen_s8addl (void)
577 static void gen_s8subl (void)
583 static void gen_s4addq (void)
589 static void gen_s4subq (void)
595 static void gen_s8addq (void)
601 static void gen_s8subq (void)
607 static void gen_amask (void)
613 static int translate_one (DisasContext
*ctx
, uint32_t insn
)
616 int32_t disp21
, disp16
, disp12
;
618 uint8_t opc
, ra
, rb
, rc
, sbz
, fpfn
, fn7
, fn2
, islit
;
622 /* Decode all instruction fields */
624 ra
= (insn
>> 21) & 0x1F;
625 rb
= (insn
>> 16) & 0x1F;
627 sbz
= (insn
>> 13) & 0x07;
628 islit
= (insn
>> 12) & 1;
629 lit
= (insn
>> 13) & 0xFF;
630 palcode
= insn
& 0x03FFFFFF;
631 disp21
= ((int32_t)((insn
& 0x001FFFFF) << 11)) >> 11;
632 disp16
= (int16_t)(insn
& 0x0000FFFF);
633 disp12
= (int32_t)((insn
& 0x00000FFF) << 20) >> 20;
634 fn16
= insn
& 0x0000FFFF;
635 fn11
= (insn
>> 5) & 0x000007FF;
637 fn7
= (insn
>> 5) & 0x0000007F;
638 fn2
= (insn
>> 5) & 0x00000003;
640 #if defined ALPHA_DEBUG_DISAS
641 if (logfile
!= NULL
) {
642 fprintf(logfile
, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
643 opc
, ra
, rb
, rc
, disp16
);
649 if (palcode
>= 0x80 && palcode
< 0xC0) {
650 /* Unprivileged PAL call */
651 gen_excp(ctx
, EXCP_CALL_PAL
+ ((palcode
& 0x1F) << 6), 0);
652 #if !defined (CONFIG_USER_ONLY)
653 } else if (palcode
< 0x40) {
654 /* Privileged PAL code */
655 if (ctx
->mem_idx
& 1)
658 gen_excp(ctx
, EXCP_CALL_PALP
+ ((palcode
& 0x1F) << 6), 0);
661 /* Invalid PAL call */
689 gen_load_ir(ctx
, rb
, 0);
690 gen_set_sT1(ctx
, disp16
);
692 gen_store_ir(ctx
, ra
, 0);
696 gen_load_ir(ctx
, rb
, 0);
697 gen_set_sT1(ctx
, disp16
<< 16);
699 gen_store_ir(ctx
, ra
, 0);
703 if (!(ctx
->amask
& AMASK_BWX
))
705 gen_load_mem(ctx
, &gen_ldbu
, ra
, rb
, disp16
, 0);
709 gen_load_mem(ctx
, &gen_ldq_u
, ra
, rb
, disp16
, 1);
713 if (!(ctx
->amask
& AMASK_BWX
))
715 gen_load_mem(ctx
, &gen_ldwu
, ra
, rb
, disp16
, 0);
719 if (!(ctx
->amask
& AMASK_BWX
))
721 gen_store_mem(ctx
, &gen_stw
, ra
, rb
, disp16
, 0);
725 if (!(ctx
->amask
& AMASK_BWX
))
727 gen_store_mem(ctx
, &gen_stb
, ra
, rb
, disp16
, 0);
731 gen_store_mem(ctx
, &gen_stq_u
, ra
, rb
, disp16
, 1);
737 gen_arith3(ctx
, &gen_op_addl
, ra
, rb
, rc
, islit
, lit
);
741 gen_arith3(ctx
, &gen_s4addl
, ra
, rb
, rc
, islit
, lit
);
745 gen_arith3(ctx
, &gen_op_subl
, ra
, rb
, rc
, islit
, lit
);
749 gen_arith3(ctx
, &gen_s4subl
, ra
, rb
, rc
, islit
, lit
);
753 gen_arith3(ctx
, &gen_op_cmpbge
, ra
, rb
, rc
, islit
, lit
);
757 gen_arith3(ctx
, &gen_s8addl
, ra
, rb
, rc
, islit
, lit
);
761 gen_arith3(ctx
, &gen_s8subl
, ra
, rb
, rc
, islit
, lit
);
765 gen_arith3(ctx
, &gen_op_cmpult
, ra
, rb
, rc
, islit
, lit
);
769 gen_arith3(ctx
, &gen_op_addq
, ra
, rb
, rc
, islit
, lit
);
773 gen_arith3(ctx
, &gen_s4addq
, ra
, rb
, rc
, islit
, lit
);
777 gen_arith3(ctx
, &gen_op_subq
, ra
, rb
, rc
, islit
, lit
);
781 gen_arith3(ctx
, &gen_s4subq
, ra
, rb
, rc
, islit
, lit
);
785 gen_arith3(ctx
, &gen_op_cmpeq
, ra
, rb
, rc
, islit
, lit
);
789 gen_arith3(ctx
, &gen_s8addq
, ra
, rb
, rc
, islit
, lit
);
793 gen_arith3(ctx
, &gen_s8subq
, ra
, rb
, rc
, islit
, lit
);
797 gen_arith3(ctx
, &gen_op_cmpule
, ra
, rb
, rc
, islit
, lit
);
801 gen_arith3(ctx
, &gen_op_addlv
, ra
, rb
, rc
, islit
, lit
);
805 gen_arith3(ctx
, &gen_op_sublv
, ra
, rb
, rc
, islit
, lit
);
809 gen_arith3(ctx
, &gen_op_cmplt
, ra
, rb
, rc
, islit
, lit
);
813 gen_arith3(ctx
, &gen_op_addqv
, ra
, rb
, rc
, islit
, lit
);
817 gen_arith3(ctx
, &gen_op_subqv
, ra
, rb
, rc
, islit
, lit
);
821 gen_arith3(ctx
, &gen_op_cmple
, ra
, rb
, rc
, islit
, lit
);
831 gen_arith3(ctx
, &gen_op_and
, ra
, rb
, rc
, islit
, lit
);
835 gen_arith3(ctx
, &gen_op_bic
, ra
, rb
, rc
, islit
, lit
);
839 gen_cmov(ctx
, &gen_op_cmplbs
, ra
, rb
, rc
, islit
, lit
);
843 gen_cmov(ctx
, &gen_op_cmplbc
, ra
, rb
, rc
, islit
, lit
);
847 if (ra
== rb
|| ra
== 31 || rb
== 31) {
848 if (ra
== 31 && rc
== 31) {
853 gen_load_ir(ctx
, rb
, 0);
854 gen_store_ir(ctx
, rc
, 0);
857 gen_arith3(ctx
, &gen_op_bis
, ra
, rb
, rc
, islit
, lit
);
862 gen_cmov(ctx
, &gen_op_cmpeqz
, ra
, rb
, rc
, islit
, lit
);
866 gen_cmov(ctx
, &gen_op_cmpnez
, ra
, rb
, rc
, islit
, lit
);
870 gen_arith3(ctx
, &gen_op_ornot
, ra
, rb
, rc
, islit
, lit
);
874 gen_arith3(ctx
, &gen_op_xor
, ra
, rb
, rc
, islit
, lit
);
878 gen_cmov(ctx
, &gen_op_cmpltz
, ra
, rb
, rc
, islit
, lit
);
882 gen_cmov(ctx
, &gen_op_cmpgez
, ra
, rb
, rc
, islit
, lit
);
886 gen_arith3(ctx
, &gen_op_eqv
, ra
, rb
, rc
, islit
, lit
);
890 gen_arith2(ctx
, &gen_amask
, rb
, rc
, islit
, lit
);
894 gen_cmov(ctx
, &gen_op_cmplez
, ra
, rb
, rc
, islit
, lit
);
898 gen_cmov(ctx
, &gen_op_cmpgtz
, ra
, rb
, rc
, islit
, lit
);
902 gen_op_load_implver();
903 gen_store_ir(ctx
, rc
, 0);
913 gen_arith3(ctx
, &gen_op_mskbl
, ra
, rb
, rc
, islit
, lit
);
917 gen_arith3(ctx
, &gen_op_extbl
, ra
, rb
, rc
, islit
, lit
);
921 gen_arith3(ctx
, &gen_op_insbl
, ra
, rb
, rc
, islit
, lit
);
925 gen_arith3(ctx
, &gen_op_mskwl
, ra
, rb
, rc
, islit
, lit
);
929 gen_arith3(ctx
, &gen_op_extwl
, ra
, rb
, rc
, islit
, lit
);
933 gen_arith3(ctx
, &gen_op_inswl
, ra
, rb
, rc
, islit
, lit
);
937 gen_arith3(ctx
, &gen_op_mskll
, ra
, rb
, rc
, islit
, lit
);
941 gen_arith3(ctx
, &gen_op_extll
, ra
, rb
, rc
, islit
, lit
);
945 gen_arith3(ctx
, &gen_op_insll
, ra
, rb
, rc
, islit
, lit
);
949 gen_arith3(ctx
, &gen_op_zap
, ra
, rb
, rc
, islit
, lit
);
953 gen_arith3(ctx
, &gen_op_zapnot
, ra
, rb
, rc
, islit
, lit
);
957 gen_arith3(ctx
, &gen_op_mskql
, ra
, rb
, rc
, islit
, lit
);
961 gen_arith3(ctx
, &gen_op_srl
, ra
, rb
, rc
, islit
, lit
);
965 gen_arith3(ctx
, &gen_op_extql
, ra
, rb
, rc
, islit
, lit
);
969 gen_arith3(ctx
, &gen_op_sll
, ra
, rb
, rc
, islit
, lit
);
973 gen_arith3(ctx
, &gen_op_insql
, ra
, rb
, rc
, islit
, lit
);
977 gen_arith3(ctx
, &gen_op_sra
, ra
, rb
, rc
, islit
, lit
);
981 gen_arith3(ctx
, &gen_op_mskwh
, ra
, rb
, rc
, islit
, lit
);
985 gen_arith3(ctx
, &gen_op_inswh
, ra
, rb
, rc
, islit
, lit
);
989 gen_arith3(ctx
, &gen_op_extwh
, ra
, rb
, rc
, islit
, lit
);
993 gen_arith3(ctx
, &gen_op_msklh
, ra
, rb
, rc
, islit
, lit
);
997 gen_arith3(ctx
, &gen_op_inslh
, ra
, rb
, rc
, islit
, lit
);
1001 gen_arith3(ctx
, &gen_op_extlh
, ra
, rb
, rc
, islit
, lit
);
1005 gen_arith3(ctx
, &gen_op_mskqh
, ra
, rb
, rc
, islit
, lit
);
1009 gen_arith3(ctx
, &gen_op_insqh
, ra
, rb
, rc
, islit
, lit
);
1013 gen_arith3(ctx
, &gen_op_extqh
, ra
, rb
, rc
, islit
, lit
);
1023 gen_arith3(ctx
, &gen_op_mull
, ra
, rb
, rc
, islit
, lit
);
1027 gen_arith3(ctx
, &gen_op_mulq
, ra
, rb
, rc
, islit
, lit
);
1031 gen_arith3(ctx
, &gen_op_umulh
, ra
, rb
, rc
, islit
, lit
);
1035 gen_arith3(ctx
, &gen_op_mullv
, ra
, rb
, rc
, islit
, lit
);
1039 gen_arith3(ctx
, &gen_op_mulqv
, ra
, rb
, rc
, islit
, lit
);
1046 switch (fpfn
) { /* f11 & 0x3F */
1049 if (!(ctx
->amask
& AMASK_FIX
))
1051 gen_itf(ctx
, &gen_op_itofs
, ra
, rc
);
1055 if (!(ctx
->amask
& AMASK_FIX
))
1057 gen_farith2(ctx
, &gen_op_sqrtf
, rb
, rc
);
1061 if (!(ctx
->amask
& AMASK_FIX
))
1063 gen_farith2(ctx
, &gen_op_sqrts
, rb
, rc
);
1067 if (!(ctx
->amask
& AMASK_FIX
))
1070 gen_itf(ctx
, &gen_op_itoff
, ra
, rc
);
1077 if (!(ctx
->amask
& AMASK_FIX
))
1079 gen_itf(ctx
, &gen_op_itoft
, ra
, rc
);
1083 if (!(ctx
->amask
& AMASK_FIX
))
1085 gen_farith2(ctx
, &gen_op_sqrtg
, rb
, rc
);
1089 if (!(ctx
->amask
& AMASK_FIX
))
1091 gen_farith2(ctx
, &gen_op_sqrtt
, rb
, rc
);
1098 /* VAX floating point */
1099 /* XXX: rounding mode and trap are ignored (!) */
1100 switch (fpfn
) { /* f11 & 0x3F */
1103 gen_farith3(ctx
, &gen_op_addf
, ra
, rb
, rc
);
1107 gen_farith3(ctx
, &gen_op_subf
, ra
, rb
, rc
);
1111 gen_farith3(ctx
, &gen_op_mulf
, ra
, rb
, rc
);
1115 gen_farith3(ctx
, &gen_op_divf
, ra
, rb
, rc
);
1120 gen_farith2(ctx
, &gen_op_cvtdg
, rb
, rc
);
1127 gen_farith3(ctx
, &gen_op_addg
, ra
, rb
, rc
);
1131 gen_farith3(ctx
, &gen_op_subg
, ra
, rb
, rc
);
1135 gen_farith3(ctx
, &gen_op_mulg
, ra
, rb
, rc
);
1139 gen_farith3(ctx
, &gen_op_divg
, ra
, rb
, rc
);
1143 gen_farith3(ctx
, &gen_op_cmpgeq
, ra
, rb
, rc
);
1147 gen_farith3(ctx
, &gen_op_cmpglt
, ra
, rb
, rc
);
1151 gen_farith3(ctx
, &gen_op_cmpgle
, ra
, rb
, rc
);
1155 gen_farith2(ctx
, &gen_op_cvtgf
, rb
, rc
);
1160 gen_farith2(ctx
, &gen_op_cvtgd
, rb
, rc
);
1167 gen_farith2(ctx
, &gen_op_cvtgq
, rb
, rc
);
1171 gen_farith2(ctx
, &gen_op_cvtqf
, rb
, rc
);
1175 gen_farith2(ctx
, &gen_op_cvtqg
, rb
, rc
);
1182 /* IEEE floating-point */
1183 /* XXX: rounding mode and traps are ignored (!) */
1184 switch (fpfn
) { /* f11 & 0x3F */
1187 gen_farith3(ctx
, &gen_op_adds
, ra
, rb
, rc
);
1191 gen_farith3(ctx
, &gen_op_subs
, ra
, rb
, rc
);
1195 gen_farith3(ctx
, &gen_op_muls
, ra
, rb
, rc
);
1199 gen_farith3(ctx
, &gen_op_divs
, ra
, rb
, rc
);
1203 gen_farith3(ctx
, &gen_op_addt
, ra
, rb
, rc
);
1207 gen_farith3(ctx
, &gen_op_subt
, ra
, rb
, rc
);
1211 gen_farith3(ctx
, &gen_op_mult
, ra
, rb
, rc
);
1215 gen_farith3(ctx
, &gen_op_divt
, ra
, rb
, rc
);
1219 gen_farith3(ctx
, &gen_op_cmptun
, ra
, rb
, rc
);
1223 gen_farith3(ctx
, &gen_op_cmpteq
, ra
, rb
, rc
);
1227 gen_farith3(ctx
, &gen_op_cmptlt
, ra
, rb
, rc
);
1231 gen_farith3(ctx
, &gen_op_cmptle
, ra
, rb
, rc
);
1234 /* XXX: incorrect */
1235 if (fn11
== 0x2AC) {
1237 gen_farith2(ctx
, &gen_op_cvtst
, rb
, rc
);
1240 gen_farith2(ctx
, &gen_op_cvtts
, rb
, rc
);
1245 gen_farith2(ctx
, &gen_op_cvttq
, rb
, rc
);
1249 gen_farith2(ctx
, &gen_op_cvtqs
, rb
, rc
);
1253 gen_farith2(ctx
, &gen_op_cvtqt
, rb
, rc
);
1263 gen_farith2(ctx
, &gen_op_cvtlq
, rb
, rc
);
1268 if (ra
== 31 && rc
== 31) {
1273 gen_load_fir(ctx
, rb
, 0);
1274 gen_store_fir(ctx
, rc
, 0);
1277 gen_farith3(ctx
, &gen_op_cpys
, ra
, rb
, rc
);
1282 gen_farith2(ctx
, &gen_op_cpysn
, rb
, rc
);
1286 gen_farith2(ctx
, &gen_op_cpyse
, rb
, rc
);
1290 gen_load_fir(ctx
, ra
, 0);
1291 gen_op_store_fpcr();
1296 gen_store_fir(ctx
, ra
, 0);
1300 gen_fcmov(ctx
, &gen_op_cmpfeq
, ra
, rb
, rc
);
1304 gen_fcmov(ctx
, &gen_op_cmpfne
, ra
, rb
, rc
);
1308 gen_fcmov(ctx
, &gen_op_cmpflt
, ra
, rb
, rc
);
1312 gen_fcmov(ctx
, &gen_op_cmpfge
, ra
, rb
, rc
);
1316 gen_fcmov(ctx
, &gen_op_cmpfle
, ra
, rb
, rc
);
1320 gen_fcmov(ctx
, &gen_op_cmpfgt
, ra
, rb
, rc
);
1324 gen_farith2(ctx
, &gen_op_cvtql
, rb
, rc
);
1328 gen_farith2(ctx
, &gen_op_cvtqlv
, rb
, rc
);
1332 gen_farith2(ctx
, &gen_op_cvtqlsv
, rb
, rc
);
1339 switch ((uint16_t)disp16
) {
1342 /* No-op. Just exit from the current tb */
1347 /* No-op. Just exit from the current tb */
1369 gen_store_ir(ctx
, ra
, 0);
1374 gen_store_ir(ctx
, ra
, 0);
1379 /* XXX: TODO: evict tb cache at address rb */
1389 gen_store_ir(ctx
, ra
, 0);
1401 /* HW_MFPR (PALcode) */
1402 #if defined (CONFIG_USER_ONLY)
1407 gen_op_mfpr(insn
& 0xFF);
1408 gen_store_ir(ctx
, ra
, 0);
1412 gen_load_ir(ctx
, rb
, 0);
1414 gen_set_uT1(ctx
, ctx
->pc
);
1415 gen_store_ir(ctx
, ra
, 1);
1418 /* Those four jumps only differ by the branch prediction hint */
1436 /* HW_LD (PALcode) */
1437 #if defined (CONFIG_USER_ONLY)
1442 gen_load_ir(ctx
, rb
, 0);
1443 gen_set_sT1(ctx
, disp12
);
1445 switch ((insn
>> 12) & 0xF) {
1447 /* Longword physical access */
1451 /* Quadword physical access */
1455 /* Longword physical access with lock */
1459 /* Quadword physical access with lock */
1463 /* Longword virtual PTE fetch */
1464 gen_op_ldl_kernel();
1467 /* Quadword virtual PTE fetch */
1468 gen_op_ldq_kernel();
1477 /* Longword virtual access */
1478 gen_op_ld_phys_to_virt();
1482 /* Quadword virtual access */
1483 gen_op_ld_phys_to_virt();
1487 /* Longword virtual access with protection check */
1491 /* Quadword virtual access with protection check */
1495 /* Longword virtual access with altenate access mode */
1496 gen_op_set_alt_mode();
1497 gen_op_ld_phys_to_virt();
1499 gen_op_restore_mode();
1502 /* Quadword virtual access with altenate access mode */
1503 gen_op_set_alt_mode();
1504 gen_op_ld_phys_to_virt();
1506 gen_op_restore_mode();
1509 /* Longword virtual access with alternate access mode and
1512 gen_op_set_alt_mode();
1514 gen_op_restore_mode();
1517 /* Quadword virtual access with alternate access mode and
1520 gen_op_set_alt_mode();
1522 gen_op_restore_mode();
1525 gen_store_ir(ctx
, ra
, 1);
1532 if (!(ctx
->amask
& AMASK_BWX
))
1534 gen_arith2(ctx
, &gen_op_sextb
, rb
, rc
, islit
, lit
);
1538 if (!(ctx
->amask
& AMASK_BWX
))
1540 gen_arith2(ctx
, &gen_op_sextw
, rb
, rc
, islit
, lit
);
1544 if (!(ctx
->amask
& AMASK_CIX
))
1546 gen_arith2(ctx
, &gen_op_ctpop
, rb
, rc
, 0, 0);
1550 if (!(ctx
->amask
& AMASK_MVI
))
1557 if (!(ctx
->amask
& AMASK_CIX
))
1559 gen_arith2(ctx
, &gen_op_ctlz
, rb
, rc
, 0, 0);
1563 if (!(ctx
->amask
& AMASK_CIX
))
1565 gen_arith2(ctx
, &gen_op_cttz
, rb
, rc
, 0, 0);
1569 if (!(ctx
->amask
& AMASK_MVI
))
1576 if (!(ctx
->amask
& AMASK_MVI
))
1583 if (!(ctx
->amask
& AMASK_MVI
))
1590 if (!(ctx
->amask
& AMASK_MVI
))
1597 if (!(ctx
->amask
& AMASK_MVI
))
1604 if (!(ctx
->amask
& AMASK_MVI
))
1611 if (!(ctx
->amask
& AMASK_MVI
))
1618 if (!(ctx
->amask
& AMASK_MVI
))
1625 if (!(ctx
->amask
& AMASK_MVI
))
1632 if (!(ctx
->amask
& AMASK_MVI
))
1639 if (!(ctx
->amask
& AMASK_MVI
))
1646 if (!(ctx
->amask
& AMASK_MVI
))
1653 if (!(ctx
->amask
& AMASK_FIX
))
1655 gen_fti(ctx
, &gen_op_ftoit
, ra
, rb
);
1659 if (!(ctx
->amask
& AMASK_FIX
))
1661 gen_fti(ctx
, &gen_op_ftois
, ra
, rb
);
1668 /* HW_MTPR (PALcode) */
1669 #if defined (CONFIG_USER_ONLY)
1674 gen_load_ir(ctx
, ra
, 0);
1675 gen_op_mtpr(insn
& 0xFF);
1680 /* HW_REI (PALcode) */
1681 #if defined (CONFIG_USER_ONLY)
1690 gen_load_ir(ctx
, rb
, 0);
1691 gen_set_uT1(ctx
, (((int64_t)insn
<< 51) >> 51));
1699 /* HW_ST (PALcode) */
1700 #if defined (CONFIG_USER_ONLY)
1705 gen_load_ir(ctx
, rb
, 0);
1706 gen_set_sT1(ctx
, disp12
);
1708 gen_load_ir(ctx
, ra
, 1);
1709 switch ((insn
>> 12) & 0xF) {
1711 /* Longword physical access */
1715 /* Quadword physical access */
1719 /* Longword physical access with lock */
1723 /* Quadword physical access with lock */
1727 /* Longword virtual access */
1728 gen_op_st_phys_to_virt();
1732 /* Quadword virtual access */
1733 gen_op_st_phys_to_virt();
1755 /* Longword virtual access with alternate access mode */
1756 gen_op_set_alt_mode();
1757 gen_op_st_phys_to_virt();
1759 gen_op_restore_mode();
1762 /* Quadword virtual access with alternate access mode */
1763 gen_op_set_alt_mode();
1764 gen_op_st_phys_to_virt();
1766 gen_op_restore_mode();
1781 gen_load_fmem(ctx
, &gen_ldf
, ra
, rb
, disp16
);
1789 gen_load_fmem(ctx
, &gen_ldg
, ra
, rb
, disp16
);
1796 gen_load_fmem(ctx
, &gen_lds
, ra
, rb
, disp16
);
1800 gen_load_fmem(ctx
, &gen_ldt
, ra
, rb
, disp16
);
1805 gen_store_fmem(ctx
, &gen_stf
, ra
, rb
, disp16
);
1813 gen_store_fmem(ctx
, &gen_stg
, ra
, rb
, disp16
);
1820 gen_store_fmem(ctx
, &gen_sts
, ra
, rb
, disp16
);
1824 gen_store_fmem(ctx
, &gen_stt
, ra
, rb
, disp16
);
1828 gen_load_mem(ctx
, &gen_ldl
, ra
, rb
, disp16
, 0);
1832 gen_load_mem(ctx
, &gen_ldq
, ra
, rb
, disp16
, 0);
1836 gen_load_mem(ctx
, &gen_ldl_l
, ra
, rb
, disp16
, 0);
1840 gen_load_mem(ctx
, &gen_ldq_l
, ra
, rb
, disp16
, 0);
1844 gen_store_mem(ctx
, &gen_stl
, ra
, rb
, disp16
, 0);
1848 gen_store_mem(ctx
, &gen_stq
, ra
, rb
, disp16
, 0);
1852 gen_store_mem(ctx
, &gen_stl_c
, ra
, rb
, disp16
, 0);
1856 gen_store_mem(ctx
, &gen_stq_c
, ra
, rb
, disp16
, 0);
1860 gen_set_uT0(ctx
, ctx
->pc
);
1861 gen_store_ir(ctx
, ra
, 0);
1863 gen_set_sT1(ctx
, disp21
<< 2);
1871 gen_fbcond(ctx
, &gen_op_cmpfeq
, ra
, disp16
);
1876 gen_fbcond(ctx
, &gen_op_cmpflt
, ra
, disp16
);
1881 gen_fbcond(ctx
, &gen_op_cmpfle
, ra
, disp16
);
1886 gen_set_uT0(ctx
, ctx
->pc
);
1887 gen_store_ir(ctx
, ra
, 0);
1889 gen_set_sT1(ctx
, disp21
<< 2);
1897 gen_fbcond(ctx
, &gen_op_cmpfne
, ra
, disp16
);
1902 gen_fbcond(ctx
, &gen_op_cmpfge
, ra
, disp16
);
1907 gen_fbcond(ctx
, &gen_op_cmpfgt
, ra
, disp16
);
1912 gen_bcond(ctx
, &gen_op_cmplbc
, ra
, disp16
);
1917 gen_bcond(ctx
, &gen_op_cmpeqz
, ra
, disp16
);
1922 gen_bcond(ctx
, &gen_op_cmpltz
, ra
, disp16
);
1927 gen_bcond(ctx
, &gen_op_cmplez
, ra
, disp16
);
1932 gen_bcond(ctx
, &gen_op_cmplbs
, ra
, disp16
);
1937 gen_bcond(ctx
, &gen_op_cmpnez
, ra
, disp16
);
1942 gen_bcond(ctx
, &gen_op_cmpgez
, ra
, disp16
);
1947 gen_bcond(ctx
, &gen_op_cmpgtz
, ra
, disp16
);
1959 int gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
1962 #if defined ALPHA_DEBUG_DISAS
1963 static int insn_count
;
1965 DisasContext ctx
, *ctxp
= &ctx
;
1966 target_ulong pc_start
;
1968 uint16_t *gen_opc_end
;
1973 gen_opc_ptr
= gen_opc_buf
;
1974 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1975 gen_opparam_ptr
= gen_opparam_buf
;
1978 ctx
.amask
= env
->amask
;
1979 #if defined (CONFIG_USER_ONLY)
1982 ctx
.mem_idx
= ((env
->ps
>> 3) & 3);
1983 ctx
.pal_mode
= env
->ipr
[IPR_EXC_ADDR
] & 1;
1985 for (ret
= 0; ret
== 0;) {
1986 if (env
->nb_breakpoints
> 0) {
1987 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
1988 if (env
->breakpoints
[j
] == ctx
.pc
) {
1989 gen_excp(&ctx
, EXCP_DEBUG
, 0);
1995 j
= gen_opc_ptr
- gen_opc_buf
;
1999 gen_opc_instr_start
[lj
++] = 0;
2000 gen_opc_pc
[lj
] = ctx
.pc
;
2001 gen_opc_instr_start
[lj
] = 1;
2004 #if defined ALPHA_DEBUG_DISAS
2006 if (logfile
!= NULL
) {
2007 fprintf(logfile
, "pc " TARGET_FMT_lx
" mem_idx %d\n",
2008 ctx
.pc
, ctx
.mem_idx
);
2011 insn
= ldl_code(ctx
.pc
);
2012 #if defined ALPHA_DEBUG_DISAS
2014 if (logfile
!= NULL
) {
2015 fprintf(logfile
, "opcode %08x %d\n", insn
, insn_count
);
2019 ret
= translate_one(ctxp
, insn
);
2022 /* if we reach a page boundary or are single stepping, stop
2025 if (((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
2026 (env
->singlestep_enabled
)) {
2029 #if defined (DO_SINGLE_STEP)
2033 if (ret
!= 1 && ret
!= 3) {
2034 gen_update_pc(&ctx
);
2037 #if defined (DO_TB_FLUSH)
2040 /* Generate the return instruction */
2042 *gen_opc_ptr
= INDEX_op_end
;
2044 j
= gen_opc_ptr
- gen_opc_buf
;
2047 gen_opc_instr_start
[lj
++] = 0;
2050 tb
->size
= ctx
.pc
- pc_start
;
2052 #if defined ALPHA_DEBUG_DISAS
2053 if (loglevel
& CPU_LOG_TB_CPU
) {
2054 cpu_dump_state(env
, logfile
, fprintf
, 0);
2056 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2057 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2058 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 1);
2059 fprintf(logfile
, "\n");
2061 if (loglevel
& CPU_LOG_TB_OP
) {
2062 fprintf(logfile
, "OP:\n");
2063 dump_ops(gen_opc_buf
, gen_opparam_buf
);
2064 fprintf(logfile
, "\n");
2071 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2073 return gen_intermediate_code_internal(env
, tb
, 0);
2076 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2078 return gen_intermediate_code_internal(env
, tb
, 1);
2081 CPUAlphaState
* cpu_alpha_init (void)
2086 env
= qemu_mallocz(sizeof(CPUAlphaState
));
2091 /* XXX: should not be hardcoded */
2092 env
->implver
= IMPLVER_2106x
;
2094 #if defined (CONFIG_USER_ONLY)
2098 /* Initialize IPR */
2099 hwpcb
= env
->ipr
[IPR_PCBB
];
2100 env
->ipr
[IPR_ASN
] = 0;
2101 env
->ipr
[IPR_ASTEN
] = 0;
2102 env
->ipr
[IPR_ASTSR
] = 0;
2103 env
->ipr
[IPR_DATFX
] = 0;
2105 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2106 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2107 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2108 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2109 env
->ipr
[IPR_FEN
] = 0;
2110 env
->ipr
[IPR_IPL
] = 31;
2111 env
->ipr
[IPR_MCES
] = 0;
2112 env
->ipr
[IPR_PERFMON
] = 0; /* Implementation specific */
2113 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2114 env
->ipr
[IPR_SISR
] = 0;
2115 env
->ipr
[IPR_VIRBND
] = -1ULL;