target-mips/translate_init.c

   1 /*
   2  *  MIPS emulation for qemu: CPU initialisation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2007 Herve Poussineau
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /* CPU / CPU family specific config register values. */
  23
  24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
  25    uncached coherency */
  26 #define MIPS_CONFIG0                                              \
  27   ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
  28    (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
  29    (0x2 << CP0C0_K0))
  30
  31 /* Have config2, no coprocessor2 attached, no MDMX support attached,
  32    no performance counters, watch registers present,
  33    no code compression, EJTAG present, no FPU */
  34 #define MIPS_CONFIG1                                              \
  35 ((1 << CP0C1_M) |                                                 \
  36  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
  37  (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
  38  (0 << CP0C1_FP))
  39
  40 /* Have config3, no tertiary/secondary caches implemented */
  41 #define MIPS_CONFIG2                                              \
  42 ((1 << CP0C2_M))
  43
  44 /* No config4, no DSP ASE, no large physaddr,
  45    no external interrupt controller, no vectored interupts,
  46    no 1kb pages, no SmartMIPS ASE, no trace logic */
  47 #define MIPS_CONFIG3                                              \
  48 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  49  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  50  (0 << CP0C3_SM) | (0 << CP0C3_TL))
  51
  52 /* Define a implementation number of 1.
  53    Define a major version 1, minor version 0. */
  54 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
  55
  56
  57 struct mips_def_t {
  58     const unsigned char *name;
  59     int32_t CP0_PRid;
  60     int32_t CP0_Config0;
  61     int32_t CP0_Config1;
  62     int32_t CP0_Config2;
  63     int32_t CP0_Config3;
  64     int32_t CP0_Config6;
  65     int32_t CP0_Config7;
  66     int32_t SYNCI_Step;
  67     int32_t CCRes;
  68     int32_t CP0_Status_rw_bitmask;
  69     int32_t CP0_TCStatus_rw_bitmask;
  70     int32_t CP0_SRSCtl;
  71     int32_t CP1_fcr0;
  72     int32_t SEGBITS;
  73     int32_t CP0_SRSConf0_rw_bitmask;
  74     int32_t CP0_SRSConf0;
  75     int32_t CP0_SRSConf1_rw_bitmask;
  76     int32_t CP0_SRSConf1;
  77     int32_t CP0_SRSConf2_rw_bitmask;
  78     int32_t CP0_SRSConf2;
  79     int32_t CP0_SRSConf3_rw_bitmask;
  80     int32_t CP0_SRSConf3;
  81     int32_t CP0_SRSConf4_rw_bitmask;
  82     int32_t CP0_SRSConf4;
  83     int insn_flags;
  84 };
  85
  86 /*****************************************************************************/
  87 /* MIPS CPU definitions */
  88 static mips_def_t mips_defs[] =
  89 {
  90     {
  91         .name = "4Kc",
  92         .CP0_PRid = 0x00018000,
  93         .CP0_Config0 = MIPS_CONFIG0,
  94         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  95                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  96                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  97         .CP0_Config2 = MIPS_CONFIG2,
  98         .CP0_Config3 = MIPS_CONFIG3,
  99         .SYNCI_Step = 32,
 100         .CCRes = 2,
 101         .CP0_Status_rw_bitmask = 0x1278FF17,
 102         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 103     },
 104     {
 105         .name = "4KEcR1",
 106         .CP0_PRid = 0x00018400,
 107         .CP0_Config0 = MIPS_CONFIG0,
 108         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 109                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 110                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 111         .CP0_Config2 = MIPS_CONFIG2,
 112         .CP0_Config3 = MIPS_CONFIG3,
 113         .SYNCI_Step = 32,
 114         .CCRes = 2,
 115         .CP0_Status_rw_bitmask = 0x1278FF17,
 116         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 117     },
 118     {
 119         .name = "4KEc",
 120         .CP0_PRid = 0x00019000,
 121         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 122         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 123                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 124                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 125         .CP0_Config2 = MIPS_CONFIG2,
 126         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 127         .SYNCI_Step = 32,
 128         .CCRes = 2,
 129         .CP0_Status_rw_bitmask = 0x1278FF17,
 130         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 131     },
 132     {
 133         .name = "24Kc",
 134         .CP0_PRid = 0x00019300,
 135         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 136         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 137                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 138                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 139         .CP0_Config2 = MIPS_CONFIG2,
 140         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 141         .SYNCI_Step = 32,
 142         .CCRes = 2,
 143         /* No DSP implemented. */
 144         .CP0_Status_rw_bitmask = 0x1278FF1F,
 145         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
 146     },
 147     {
 148         .name = "24Kf",
 149         .CP0_PRid = 0x00019300,
 150         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 151         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 152                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 153                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 154         .CP0_Config2 = MIPS_CONFIG2,
 155         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 156         .SYNCI_Step = 32,
 157         .CCRes = 2,
 158         /* No DSP implemented. */
 159         .CP0_Status_rw_bitmask = 0x3678FF1F,
 160         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 161                     (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 162         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
 163     },
 164     {
 165         .name = "34Kf",
 166         .CP0_PRid = 0x00019500,
 167         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 168         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 169                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 170                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 171         .CP0_Config2 = MIPS_CONFIG2,
 172         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
 173         .SYNCI_Step = 32,
 174         .CCRes = 2,
 175         /* No DSP implemented. */
 176         .CP0_Status_rw_bitmask = 0x3678FF1F,
 177         /* No DSP implemented. */
 178         .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
 179                     (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
 180                     (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
 181                     (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
 182                     (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
 183                     (0xff << CP0TCSt_TASID),
 184         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 185                     (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
 186         .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 187         .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
 188         .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
 189                     (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
 190         .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
 191         .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
 192                     (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
 193         .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
 194         .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
 195                     (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
 196         .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
 197         .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
 198                     (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
 199         .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
 200         .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
 201                     (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
 202         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
 203     },
 204 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
 205     {
 206         .name = "R4000",
 207         .CP0_PRid = 0x00000400,
 208         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 209         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
 210                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 211                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 212         .CP0_Config2 = MIPS_CONFIG2,
 213         .CP0_Config3 = MIPS_CONFIG3,
 214         .SYNCI_Step = 16,
 215         .CCRes = 2,
 216         .CP0_Status_rw_bitmask = 0x3678FFFF,
 217         /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
 218         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
 219         .SEGBITS = 40,
 220         .insn_flags = CPU_MIPS3,
 221     },
 222     {
 223         .name = "5Kc",
 224         .CP0_PRid = 0x00018100,
 225         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 226         .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
 227                     (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 228                     (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 229                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 230         .CP0_Config2 = MIPS_CONFIG2,
 231         .CP0_Config3 = MIPS_CONFIG3,
 232         .SYNCI_Step = 32,
 233         .CCRes = 2,
 234         .CP0_Status_rw_bitmask = 0x32F8FFFF,
 235         .SEGBITS = 42,
 236         .insn_flags = CPU_MIPS64,
 237     },
 238     {
 239         .name = "5Kf",
 240         .CP0_PRid = 0x00018100,
 241         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 242         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 243                     (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 244                     (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 245                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 246         .CP0_Config2 = MIPS_CONFIG2,
 247         .CP0_Config3 = MIPS_CONFIG3,
 248         .SYNCI_Step = 32,
 249         .CCRes = 2,
 250         .CP0_Status_rw_bitmask = 0x36F8FFFF,
 251         /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 252         .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 253                     (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
 254         .SEGBITS = 42,
 255         .insn_flags = CPU_MIPS64,
 256     },
 257     {
 258         .name = "20Kc",
 259         /* We emulate a later version of the 20Kc, earlier ones had a broken
 260            WAIT instruction. */
 261         .CP0_PRid = 0x000182a0,
 262         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
 263         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
 264                     (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 265                     (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 266                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 267         .CP0_Config2 = MIPS_CONFIG2,
 268         .CP0_Config3 = MIPS_CONFIG3,
 269         .SYNCI_Step = 32,
 270         .CCRes = 2,
 271         .CP0_Status_rw_bitmask = 0x36FBFFFF,
 272         /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
 273         .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 274                     (1 << FCR0_D) | (1 << FCR0_S) |
 275                     (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
 276         .SEGBITS = 40,
 277         .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
 278     },
 279 #endif
 280 };
 281
 282 int mips_find_by_name (const unsigned char *name, mips_def_t **def)
 283 {
 284     int i, ret;
 285
 286     ret = -1;
 287     *def = NULL;
 288     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 289         if (strcasecmp(name, mips_defs[i].name) == 0) {
 290             *def = &mips_defs[i];
 291             ret = 0;
 292             break;
 293         }
 294     }
 295
 296     return ret;
 297 }
 298
 299 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 300 {
 301     int i;
 302
 303     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 304         (*cpu_fprintf)(f, "MIPS '%s'\n",
 305                        mips_defs[i].name);
 306     }
 307 }
 308
 309 #ifndef CONFIG_USER_ONLY
 310 static void no_mmu_init (CPUMIPSState *env, mips_def_t *def)
 311 {
 312     env->tlb->nb_tlb = 1;
 313     env->tlb->map_address = &no_mmu_map_address;
 314 }
 315
 316 static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def)
 317 {
 318     env->tlb->nb_tlb = 1;
 319     env->tlb->map_address = &fixed_mmu_map_address;
 320 }
 321
 322 static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def)
 323 {
 324     env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
 325     env->tlb->map_address = &r4k_map_address;
 326     env->tlb->do_tlbwi = r4k_do_tlbwi;
 327     env->tlb->do_tlbwr = r4k_do_tlbwr;
 328     env->tlb->do_tlbp = r4k_do_tlbp;
 329     env->tlb->do_tlbr = r4k_do_tlbr;
 330 }
 331
 332 static void mmu_init (CPUMIPSState *env, mips_def_t *def)
 333 {
 334     env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
 335
 336     /* There are more full-featured MMU variants in older MIPS CPUs,
 337        R3000, R6000 and R8000 come to mind. If we ever support them,
 338        this check will need to look up a different place than those
 339        newfangled config registers. */
 340     switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
 341         case 0:
 342             no_mmu_init(env, def);
 343             break;
 344         case 1:
 345             r4k_mmu_init(env, def);
 346             break;
 347         case 3:
 348             fixed_mmu_init(env, def);
 349             break;
 350         default:
 351             cpu_abort(env, "MMU type not supported\n");
 352     }
 353     env->CP0_Random = env->tlb->nb_tlb - 1;
 354     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 355 }
 356 #endif /* CONFIG_USER_ONLY */
 357
 358 static void fpu_init (CPUMIPSState *env, mips_def_t *def)
 359 {
 360     env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
 361
 362     env->fpu->fcr0 = def->CP1_fcr0;
 363 #ifdef CONFIG_USER_ONLY
 364     if (env->CP0_Config1 & (1 << CP0C1_FP))
 365         env->hflags |= MIPS_HFLAG_FPU;
 366     if (env->fpu->fcr0 & (1 << FCR0_F64))
 367         env->hflags |= MIPS_HFLAG_F64;
 368 #endif
 369 }
 370
 371 static void mvp_init (CPUMIPSState *env, mips_def_t *def)
 372 {
 373     env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
 374
 375     /* MVPConf1 implemented, TLB sharable, no gating storage support,
 376        programmable cache partitioning implemented, number of allocatable
 377        and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
 378        implemented, 5 TCs implemented. */
 379     env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
 380                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
 381 #ifndef CONFIG_USER_ONLY
 382                              /* Usermode has no TLB support */
 383                              (env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
 384 #endif
 385 // TODO: actually do 2 VPEs.
 386 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
 387 //                             (0x04 << CP0MVPC0_PTC);
 388                              (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
 389                              (0x04 << CP0MVPC0_PTC);
 390     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
 391        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
 392     env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
 393                              (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
 394                              (0x1 << CP0MVPC1_PCP1);
 395 }
 396
 397 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
 398 {
 399     if (!def)
 400         def = env->cpu_model;
 401     if (!def)
 402         cpu_abort(env, "Unable to find MIPS CPU definition\n");
 403     env->cpu_model = def;
 404     env->CP0_PRid = def->CP0_PRid;
 405     env->CP0_Config0 = def->CP0_Config0;
 406 #ifdef TARGET_WORDS_BIGENDIAN
 407     env->CP0_Config0 |= (1 << CP0C0_BE);
 408 #endif
 409     env->CP0_Config1 = def->CP0_Config1;
 410     env->CP0_Config2 = def->CP0_Config2;
 411     env->CP0_Config3 = def->CP0_Config3;
 412     env->CP0_Config6 = def->CP0_Config6;
 413     env->CP0_Config7 = def->CP0_Config7;
 414     env->SYNCI_Step = def->SYNCI_Step;
 415     env->CCRes = def->CCRes;
 416     env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
 417     env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
 418     env->CP0_SRSCtl = def->CP0_SRSCtl;
 419 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
 420     if (def->insn_flags & ISA_MIPS3)
 421     {
 422         env->hflags |= MIPS_HFLAG_64;
 423         env->SEGBITS = def->SEGBITS;
 424         env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
 425     } else {
 426         env->SEGBITS = 32;
 427         env->SEGMask = 0xFFFFFFFF;
 428     }
 429 #endif
 430     env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask;
 431     env->CP0_SRSConf0 = def->CP0_SRSConf0;
 432     env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask;
 433     env->CP0_SRSConf1 = def->CP0_SRSConf1;
 434     env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask;
 435     env->CP0_SRSConf2 = def->CP0_SRSConf2;
 436     env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask;
 437     env->CP0_SRSConf3 = def->CP0_SRSConf3;
 438     env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask;
 439     env->CP0_SRSConf4 = def->CP0_SRSConf4;
 440     env->insn_flags = def->insn_flags;
 441
 442 #ifndef CONFIG_USER_ONLY
 443     mmu_init(env, def);
 444 #endif
 445     fpu_init(env, def);
 446     mvp_init(env, def);
 447     return 0;
 448 }