2 * PPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 //#define DO_SINGLE_STEP
31 //#define PPC_DEBUG_DISAS
34 #define DEF(s, n, copy_size) INDEX_op_ ## s,
40 static uint16_t *gen_opc_ptr
;
41 static uint32_t *gen_opparam_ptr
;
45 #define GEN8(func, NAME) \
46 static GenOpFunc *NAME ## _table [8] = { \
47 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
50 static inline void func(int n) \
52 NAME ## _table[n](); \
55 #define GEN16(func, NAME) \
56 static GenOpFunc *NAME ## _table [16] = { \
57 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
62 static inline void func(int n) \
64 NAME ## _table[n](); \
67 #define GEN32(func, NAME) \
68 static GenOpFunc *NAME ## _table [32] = { \
69 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
78 static inline void func(int n) \
80 NAME ## _table[n](); \
83 /* Condition register moves */
84 GEN8(gen_op_load_crf_T0
, gen_op_load_crf_T0_crf
);
85 GEN8(gen_op_load_crf_T1
, gen_op_load_crf_T1_crf
);
86 GEN8(gen_op_store_T0_crf
, gen_op_store_T0_crf_crf
);
87 GEN8(gen_op_store_T1_crf
, gen_op_store_T1_crf_crf
);
89 /* Floating point condition and status register moves */
90 GEN8(gen_op_load_fpscr_T0
, gen_op_load_fpscr_T0_fpscr
);
91 GEN8(gen_op_store_T0_fpscr
, gen_op_store_T0_fpscr_fpscr
);
92 GEN8(gen_op_clear_fpscr
, gen_op_clear_fpscr_fpscr
);
93 static GenOpFunc1
*gen_op_store_T0_fpscri_fpscr_table
[8] = {
94 &gen_op_store_T0_fpscri_fpscr0
,
95 &gen_op_store_T0_fpscri_fpscr1
,
96 &gen_op_store_T0_fpscri_fpscr2
,
97 &gen_op_store_T0_fpscri_fpscr3
,
98 &gen_op_store_T0_fpscri_fpscr4
,
99 &gen_op_store_T0_fpscri_fpscr5
,
100 &gen_op_store_T0_fpscri_fpscr6
,
101 &gen_op_store_T0_fpscri_fpscr7
,
103 static inline void gen_op_store_T0_fpscri(int n
, uint8_t param
)
105 (*gen_op_store_T0_fpscri_fpscr_table
[n
])(param
);
108 /* Segment register moves */
109 GEN16(gen_op_load_sr
, gen_op_load_sr
);
110 GEN16(gen_op_store_sr
, gen_op_store_sr
);
112 /* General purpose registers moves */
113 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
114 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
115 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
117 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
118 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
119 GEN32(gen_op_store_T2_gpr
, gen_op_store_T2_gpr_gpr
);
121 /* floating point registers moves */
122 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fpr
);
123 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fpr
);
124 GEN32(gen_op_load_fpr_FT2
, gen_op_load_fpr_FT2_fpr
);
125 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fpr
);
126 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fpr
);
127 GEN32(gen_op_store_FT2_fpr
, gen_op_store_FT2_fpr_fpr
);
129 static uint8_t spr_access
[1024 / 2];
131 /* internal defines */
132 typedef struct DisasContext
{
133 struct TranslationBlock
*tb
;
137 /* Routine used to access memory */
139 /* Translation flags */
140 #if !defined(CONFIG_USER_ONLY)
146 typedef struct opc_handler_t
{
149 /* instruction type */
152 void (*handler
)(DisasContext
*ctx
);
155 #define RET_EXCP(ctx, excp, error) \
157 if ((ctx)->exception == EXCP_NONE) { \
158 gen_op_update_nip((ctx)->nip); \
160 gen_op_raise_exception_err((excp), (error)); \
161 ctx->exception = (excp); \
164 #define RET_INVAL(ctx) \
165 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
167 #define RET_PRIVOPC(ctx) \
168 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
170 #define RET_PRIVREG(ctx) \
171 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
173 #define RET_MTMSR(ctx) \
174 RET_EXCP((ctx), EXCP_MTMSR, 0)
176 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
177 static void gen_##name (DisasContext *ctx); \
178 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
179 static void gen_##name (DisasContext *ctx)
181 typedef struct opcode_t
{
182 unsigned char opc1
, opc2
, opc3
;
183 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
184 unsigned char pad
[5];
186 unsigned char pad
[1];
188 opc_handler_t handler
;
191 /*** Instruction decoding ***/
192 #define EXTRACT_HELPER(name, shift, nb) \
193 static inline uint32_t name (uint32_t opcode) \
195 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
198 #define EXTRACT_SHELPER(name, shift, nb) \
199 static inline int32_t name (uint32_t opcode) \
201 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
205 EXTRACT_HELPER(opc1
, 26, 6);
207 EXTRACT_HELPER(opc2
, 1, 5);
209 EXTRACT_HELPER(opc3
, 6, 5);
210 /* Update Cr0 flags */
211 EXTRACT_HELPER(Rc
, 0, 1);
213 EXTRACT_HELPER(rD
, 21, 5);
215 EXTRACT_HELPER(rS
, 21, 5);
217 EXTRACT_HELPER(rA
, 16, 5);
219 EXTRACT_HELPER(rB
, 11, 5);
221 EXTRACT_HELPER(rC
, 6, 5);
223 EXTRACT_HELPER(crfD
, 23, 3);
224 EXTRACT_HELPER(crfS
, 18, 3);
225 EXTRACT_HELPER(crbD
, 21, 5);
226 EXTRACT_HELPER(crbA
, 16, 5);
227 EXTRACT_HELPER(crbB
, 11, 5);
229 EXTRACT_HELPER(SPR
, 11, 10);
230 /*** Get constants ***/
231 EXTRACT_HELPER(IMM
, 12, 8);
232 /* 16 bits signed immediate value */
233 EXTRACT_SHELPER(SIMM
, 0, 16);
234 /* 16 bits unsigned immediate value */
235 EXTRACT_HELPER(UIMM
, 0, 16);
237 EXTRACT_HELPER(NB
, 11, 5);
239 EXTRACT_HELPER(SH
, 11, 5);
241 EXTRACT_HELPER(MB
, 6, 5);
243 EXTRACT_HELPER(ME
, 1, 5);
245 EXTRACT_HELPER(TO
, 21, 5);
247 EXTRACT_HELPER(CRM
, 12, 8);
248 EXTRACT_HELPER(FM
, 17, 8);
249 EXTRACT_HELPER(SR
, 16, 4);
250 EXTRACT_HELPER(FPIMM
, 20, 4);
252 /*** Jump target decoding ***/
254 EXTRACT_SHELPER(d
, 0, 16);
255 /* Immediate address */
256 static inline uint32_t LI (uint32_t opcode
)
258 return (opcode
>> 0) & 0x03FFFFFC;
261 static inline uint32_t BD (uint32_t opcode
)
263 return (opcode
>> 0) & 0xFFFC;
266 EXTRACT_HELPER(BO
, 21, 5);
267 EXTRACT_HELPER(BI
, 16, 5);
268 /* Absolute/relative address */
269 EXTRACT_HELPER(AA
, 1, 1);
271 EXTRACT_HELPER(LK
, 0, 1);
273 /* Create a mask between <start> and <end> bits */
274 static inline uint32_t MASK (uint32_t start
, uint32_t end
)
278 ret
= (((uint32_t)(-1)) >> (start
)) ^ (((uint32_t)(-1) >> (end
)) >> 1);
285 #if defined(__APPLE__)
286 #define OPCODES_SECTION \
287 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
289 #define OPCODES_SECTION \
290 __attribute__ ((section(".opcodes"), unused, aligned (8) ))
293 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
294 OPCODES_SECTION opcode_t opc_##name = { \
302 .handler = &gen_##name, \
306 #define GEN_OPCODE_MARK(name) \
307 OPCODES_SECTION opcode_t opc_##name = { \
313 .inval = 0x00000000, \
319 /* Start opcode list */
320 GEN_OPCODE_MARK(start
);
322 /* Invalid instruction */
323 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
)
328 static opc_handler_t invalid_handler
= {
331 .handler
= gen_invalid
,
334 /*** Integer arithmetic ***/
335 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
336 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
338 gen_op_load_gpr_T0(rA(ctx->opcode)); \
339 gen_op_load_gpr_T1(rB(ctx->opcode)); \
341 if (Rc(ctx->opcode) != 0) \
343 gen_op_store_T0_gpr(rD(ctx->opcode)); \
346 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
347 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
349 gen_op_load_gpr_T0(rA(ctx->opcode)); \
350 gen_op_load_gpr_T1(rB(ctx->opcode)); \
352 if (Rc(ctx->opcode) != 0) \
354 gen_op_store_T0_gpr(rD(ctx->opcode)); \
357 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
358 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
360 gen_op_load_gpr_T0(rA(ctx->opcode)); \
362 if (Rc(ctx->opcode) != 0) \
364 gen_op_store_T0_gpr(rD(ctx->opcode)); \
366 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
367 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
369 gen_op_load_gpr_T0(rA(ctx->opcode)); \
371 if (Rc(ctx->opcode) != 0) \
373 gen_op_store_T0_gpr(rD(ctx->opcode)); \
376 /* Two operands arithmetic functions */
377 #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
378 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
379 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
381 /* Two operands arithmetic functions with no overflow allowed */
382 #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
383 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
385 /* One operand arithmetic functions */
386 #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
387 __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
388 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
390 /* add add. addo addo. */
391 GEN_INT_ARITH2 (add
, 0x1F, 0x0A, 0x08);
392 /* addc addc. addco addco. */
393 GEN_INT_ARITH2 (addc
, 0x1F, 0x0A, 0x00);
394 /* adde adde. addeo addeo. */
395 GEN_INT_ARITH2 (adde
, 0x1F, 0x0A, 0x04);
396 /* addme addme. addmeo addmeo. */
397 GEN_INT_ARITH1 (addme
, 0x1F, 0x0A, 0x07);
398 /* addze addze. addzeo addzeo. */
399 GEN_INT_ARITH1 (addze
, 0x1F, 0x0A, 0x06);
400 /* divw divw. divwo divwo. */
401 GEN_INT_ARITH2 (divw
, 0x1F, 0x0B, 0x0F);
402 /* divwu divwu. divwuo divwuo. */
403 GEN_INT_ARITH2 (divwu
, 0x1F, 0x0B, 0x0E);
405 GEN_INT_ARITHN (mulhw
, 0x1F, 0x0B, 0x02);
407 GEN_INT_ARITHN (mulhwu
, 0x1F, 0x0B, 0x00);
408 /* mullw mullw. mullwo mullwo. */
409 GEN_INT_ARITH2 (mullw
, 0x1F, 0x0B, 0x07);
410 /* neg neg. nego nego. */
411 GEN_INT_ARITH1 (neg
, 0x1F, 0x08, 0x03);
412 /* subf subf. subfo subfo. */
413 GEN_INT_ARITH2 (subf
, 0x1F, 0x08, 0x01);
414 /* subfc subfc. subfco subfco. */
415 GEN_INT_ARITH2 (subfc
, 0x1F, 0x08, 0x00);
416 /* subfe subfe. subfeo subfeo. */
417 GEN_INT_ARITH2 (subfe
, 0x1F, 0x08, 0x04);
418 /* subfme subfme. subfmeo subfmeo. */
419 GEN_INT_ARITH1 (subfme
, 0x1F, 0x08, 0x07);
420 /* subfze subfze. subfzeo subfzeo. */
421 GEN_INT_ARITH1 (subfze
, 0x1F, 0x08, 0x06);
423 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
425 int32_t simm
= SIMM(ctx
->opcode
);
427 if (rA(ctx
->opcode
) == 0) {
430 gen_op_load_gpr_T0(rA(ctx
->opcode
));
433 gen_op_store_T0_gpr(rD(ctx
->opcode
));
436 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
438 gen_op_load_gpr_T0(rA(ctx
->opcode
));
439 gen_op_addic(SIMM(ctx
->opcode
));
440 gen_op_store_T0_gpr(rD(ctx
->opcode
));
443 GEN_HANDLER(addic_
, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
445 gen_op_load_gpr_T0(rA(ctx
->opcode
));
446 gen_op_addic(SIMM(ctx
->opcode
));
448 gen_op_store_T0_gpr(rD(ctx
->opcode
));
451 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
453 int32_t simm
= SIMM(ctx
->opcode
);
455 if (rA(ctx
->opcode
) == 0) {
456 gen_op_set_T0(simm
<< 16);
458 gen_op_load_gpr_T0(rA(ctx
->opcode
));
459 gen_op_addi(simm
<< 16);
461 gen_op_store_T0_gpr(rD(ctx
->opcode
));
464 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
466 gen_op_load_gpr_T0(rA(ctx
->opcode
));
467 gen_op_mulli(SIMM(ctx
->opcode
));
468 gen_op_store_T0_gpr(rD(ctx
->opcode
));
471 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
473 gen_op_load_gpr_T0(rA(ctx
->opcode
));
474 gen_op_subfic(SIMM(ctx
->opcode
));
475 gen_op_store_T0_gpr(rD(ctx
->opcode
));
478 /*** Integer comparison ***/
479 #define GEN_CMP(name, opc) \
480 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
482 gen_op_load_gpr_T0(rA(ctx->opcode)); \
483 gen_op_load_gpr_T1(rB(ctx->opcode)); \
485 gen_op_store_T0_crf(crfD(ctx->opcode)); \
491 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
493 gen_op_load_gpr_T0(rA(ctx
->opcode
));
494 gen_op_cmpi(SIMM(ctx
->opcode
));
495 gen_op_store_T0_crf(crfD(ctx
->opcode
));
500 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
502 gen_op_load_gpr_T0(rA(ctx
->opcode
));
503 gen_op_cmpli(UIMM(ctx
->opcode
));
504 gen_op_store_T0_crf(crfD(ctx
->opcode
));
507 /*** Integer logical ***/
508 #define __GEN_LOGICAL2(name, opc2, opc3) \
509 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
511 gen_op_load_gpr_T0(rS(ctx->opcode)); \
512 gen_op_load_gpr_T1(rB(ctx->opcode)); \
514 if (Rc(ctx->opcode) != 0) \
516 gen_op_store_T0_gpr(rA(ctx->opcode)); \
518 #define GEN_LOGICAL2(name, opc) \
519 __GEN_LOGICAL2(name, 0x1C, opc)
521 #define GEN_LOGICAL1(name, opc) \
522 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
524 gen_op_load_gpr_T0(rS(ctx->opcode)); \
526 if (Rc(ctx->opcode) != 0) \
528 gen_op_store_T0_gpr(rA(ctx->opcode)); \
532 GEN_LOGICAL2(and, 0x00);
534 GEN_LOGICAL2(andc
, 0x01);
536 GEN_HANDLER(andi_
, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
538 gen_op_load_gpr_T0(rS(ctx
->opcode
));
539 gen_op_andi_(UIMM(ctx
->opcode
));
541 gen_op_store_T0_gpr(rA(ctx
->opcode
));
544 GEN_HANDLER(andis_
, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
546 gen_op_load_gpr_T0(rS(ctx
->opcode
));
547 gen_op_andi_(UIMM(ctx
->opcode
) << 16);
549 gen_op_store_T0_gpr(rA(ctx
->opcode
));
553 GEN_LOGICAL1(cntlzw
, 0x00);
555 GEN_LOGICAL2(eqv
, 0x08);
557 GEN_LOGICAL1(extsb
, 0x1D);
559 GEN_LOGICAL1(extsh
, 0x1C);
561 GEN_LOGICAL2(nand
, 0x0E);
563 GEN_LOGICAL2(nor
, 0x03);
566 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
)
568 gen_op_load_gpr_T0(rS(ctx
->opcode
));
569 /* Optimisation for mr case */
570 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
571 gen_op_load_gpr_T1(rB(ctx
->opcode
));
574 if (Rc(ctx
->opcode
) != 0)
576 gen_op_store_T0_gpr(rA(ctx
->opcode
));
580 GEN_LOGICAL2(orc
, 0x0C);
582 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
)
584 gen_op_load_gpr_T0(rS(ctx
->opcode
));
585 /* Optimisation for "set to zero" case */
586 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
587 gen_op_load_gpr_T1(rB(ctx
->opcode
));
592 if (Rc(ctx
->opcode
) != 0)
594 gen_op_store_T0_gpr(rA(ctx
->opcode
));
597 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
599 uint32_t uimm
= UIMM(ctx
->opcode
);
601 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
605 gen_op_load_gpr_T0(rS(ctx
->opcode
));
608 gen_op_store_T0_gpr(rA(ctx
->opcode
));
611 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
613 uint32_t uimm
= UIMM(ctx
->opcode
);
615 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
619 gen_op_load_gpr_T0(rS(ctx
->opcode
));
621 gen_op_ori(uimm
<< 16);
622 gen_op_store_T0_gpr(rA(ctx
->opcode
));
625 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
627 uint32_t uimm
= UIMM(ctx
->opcode
);
629 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
633 gen_op_load_gpr_T0(rS(ctx
->opcode
));
636 gen_op_store_T0_gpr(rA(ctx
->opcode
));
640 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
642 uint32_t uimm
= UIMM(ctx
->opcode
);
644 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
648 gen_op_load_gpr_T0(rS(ctx
->opcode
));
650 gen_op_xori(uimm
<< 16);
651 gen_op_store_T0_gpr(rA(ctx
->opcode
));
654 /*** Integer rotate ***/
655 /* rlwimi & rlwimi. */
656 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
660 mb
= MB(ctx
->opcode
);
661 me
= ME(ctx
->opcode
);
662 gen_op_load_gpr_T0(rS(ctx
->opcode
));
663 gen_op_load_gpr_T1(rA(ctx
->opcode
));
664 gen_op_rlwimi(SH(ctx
->opcode
), MASK(mb
, me
), ~MASK(mb
, me
));
665 if (Rc(ctx
->opcode
) != 0)
667 gen_op_store_T0_gpr(rA(ctx
->opcode
));
669 /* rlwinm & rlwinm. */
670 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
674 sh
= SH(ctx
->opcode
);
675 mb
= MB(ctx
->opcode
);
676 me
= ME(ctx
->opcode
);
677 gen_op_load_gpr_T0(rS(ctx
->opcode
));
680 gen_op_andi_(MASK(mb
, me
));
689 } else if (me
== (31 - sh
)) {
694 } else if (me
== 31) {
696 if (sh
== (32 - mb
)) {
702 gen_op_rlwinm(sh
, MASK(mb
, me
));
704 if (Rc(ctx
->opcode
) != 0)
706 gen_op_store_T0_gpr(rA(ctx
->opcode
));
709 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
713 mb
= MB(ctx
->opcode
);
714 me
= ME(ctx
->opcode
);
715 gen_op_load_gpr_T0(rS(ctx
->opcode
));
716 gen_op_load_gpr_T1(rB(ctx
->opcode
));
717 if (mb
== 0 && me
== 31) {
721 gen_op_rlwnm(MASK(mb
, me
));
723 if (Rc(ctx
->opcode
) != 0)
725 gen_op_store_T0_gpr(rA(ctx
->opcode
));
728 /*** Integer shift ***/
730 __GEN_LOGICAL2(slw
, 0x18, 0x00);
732 __GEN_LOGICAL2(sraw
, 0x18, 0x18);
734 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
)
736 gen_op_load_gpr_T0(rS(ctx
->opcode
));
737 if (SH(ctx
->opcode
) != 0)
738 gen_op_srawi(SH(ctx
->opcode
), MASK(32 - SH(ctx
->opcode
), 31));
739 if (Rc(ctx
->opcode
) != 0)
741 gen_op_store_T0_gpr(rA(ctx
->opcode
));
744 __GEN_LOGICAL2(srw
, 0x18, 0x10);
746 /*** Floating-Point arithmetic ***/
747 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
748 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
750 if (!ctx->fpu_enabled) { \
751 RET_EXCP(ctx, EXCP_NO_FP, 0); \
754 gen_op_reset_scrfx(); \
755 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
756 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
757 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
762 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
763 if (Rc(ctx->opcode)) \
767 #define GEN_FLOAT_ACB(name, op2) \
768 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
769 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
771 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
772 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
774 if (!ctx->fpu_enabled) { \
775 RET_EXCP(ctx, EXCP_NO_FP, 0); \
778 gen_op_reset_scrfx(); \
779 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
780 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
785 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
786 if (Rc(ctx->opcode)) \
789 #define GEN_FLOAT_AB(name, op2, inval) \
790 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
791 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
793 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
794 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
796 if (!ctx->fpu_enabled) { \
797 RET_EXCP(ctx, EXCP_NO_FP, 0); \
800 gen_op_reset_scrfx(); \
801 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
802 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
807 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
808 if (Rc(ctx->opcode)) \
811 #define GEN_FLOAT_AC(name, op2, inval) \
812 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
813 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
815 #define GEN_FLOAT_B(name, op2, op3) \
816 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
818 if (!ctx->fpu_enabled) { \
819 RET_EXCP(ctx, EXCP_NO_FP, 0); \
822 gen_op_reset_scrfx(); \
823 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
825 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
826 if (Rc(ctx->opcode)) \
830 #define GEN_FLOAT_BS(name, op1, op2) \
831 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
833 if (!ctx->fpu_enabled) { \
834 RET_EXCP(ctx, EXCP_NO_FP, 0); \
837 gen_op_reset_scrfx(); \
838 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
840 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
841 if (Rc(ctx->opcode)) \
846 GEN_FLOAT_AB(add
, 0x15, 0x000007C0);
848 GEN_FLOAT_AB(div
, 0x12, 0x000007C0);
850 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800);
853 GEN_FLOAT_BS(res
, 0x3B, 0x18);
856 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A);
859 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0);
861 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0);
864 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT
)
866 if (!ctx
->fpu_enabled
) {
867 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
870 gen_op_reset_scrfx();
871 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
873 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
878 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT
)
880 if (!ctx
->fpu_enabled
) {
881 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
884 gen_op_reset_scrfx();
885 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
888 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
893 /*** Floating-Point multiply-and-add ***/
895 GEN_FLOAT_ACB(madd
, 0x1D);
897 GEN_FLOAT_ACB(msub
, 0x1C);
898 /* fnmadd - fnmadds */
899 GEN_FLOAT_ACB(nmadd
, 0x1F);
900 /* fnmsub - fnmsubs */
901 GEN_FLOAT_ACB(nmsub
, 0x1E);
903 /*** Floating-Point round & convert ***/
905 GEN_FLOAT_B(ctiw
, 0x0E, 0x00);
907 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00);
909 GEN_FLOAT_B(rsp
, 0x0C, 0x00);
911 /*** Floating-Point compare ***/
913 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
)
915 if (!ctx
->fpu_enabled
) {
916 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
919 gen_op_reset_scrfx();
920 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
921 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
923 gen_op_store_T0_crf(crfD(ctx
->opcode
));
927 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
)
929 if (!ctx
->fpu_enabled
) {
930 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
933 gen_op_reset_scrfx();
934 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
935 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
937 gen_op_store_T0_crf(crfD(ctx
->opcode
));
940 /*** Floating-point move ***/
942 GEN_FLOAT_B(abs
, 0x08, 0x08);
945 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
)
947 if (!ctx
->fpu_enabled
) {
948 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
951 gen_op_reset_scrfx();
952 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
953 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
959 GEN_FLOAT_B(nabs
, 0x08, 0x04);
961 GEN_FLOAT_B(neg
, 0x08, 0x01);
963 /*** Floating-Point status & ctrl register ***/
965 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
)
967 if (!ctx
->fpu_enabled
) {
968 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
971 gen_op_load_fpscr_T0(crfS(ctx
->opcode
));
972 gen_op_store_T0_crf(crfD(ctx
->opcode
));
973 gen_op_clear_fpscr(crfS(ctx
->opcode
));
977 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
)
979 if (!ctx
->fpu_enabled
) {
980 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
984 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
990 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
)
994 if (!ctx
->fpu_enabled
) {
995 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
998 crb
= crbD(ctx
->opcode
) >> 2;
999 gen_op_load_fpscr_T0(crb
);
1000 gen_op_andi_(~(1 << (crbD(ctx
->opcode
) & 0x03)));
1001 gen_op_store_T0_fpscr(crb
);
1002 if (Rc(ctx
->opcode
))
1007 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
)
1011 if (!ctx
->fpu_enabled
) {
1012 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
1015 crb
= crbD(ctx
->opcode
) >> 2;
1016 gen_op_load_fpscr_T0(crb
);
1017 gen_op_ori(1 << (crbD(ctx
->opcode
) & 0x03));
1018 gen_op_store_T0_fpscr(crb
);
1019 if (Rc(ctx
->opcode
))
1024 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT
)
1026 if (!ctx
->fpu_enabled
) {
1027 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
1030 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1031 gen_op_store_fpscr(FM(ctx
->opcode
));
1032 if (Rc(ctx
->opcode
))
1037 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
)
1039 if (!ctx
->fpu_enabled
) {
1040 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
1043 gen_op_store_T0_fpscri(crbD(ctx
->opcode
) >> 2, FPIMM(ctx
->opcode
));
1044 if (Rc(ctx
->opcode
))
1048 /*** Integer load ***/
1049 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1050 #if defined(CONFIG_USER_ONLY)
1051 #define OP_LD_TABLE(width) \
1052 static GenOpFunc *gen_op_l##width[] = { \
1053 &gen_op_l##width##_raw, \
1054 &gen_op_l##width##_le_raw, \
1056 #define OP_ST_TABLE(width) \
1057 static GenOpFunc *gen_op_st##width[] = { \
1058 &gen_op_st##width##_raw, \
1059 &gen_op_st##width##_le_raw, \
1061 /* Byte access routine are endian safe */
1062 #define gen_op_stb_le_raw gen_op_stb_raw
1063 #define gen_op_lbz_le_raw gen_op_lbz_raw
1065 #define OP_LD_TABLE(width) \
1066 static GenOpFunc *gen_op_l##width[] = { \
1067 &gen_op_l##width##_user, \
1068 &gen_op_l##width##_le_user, \
1069 &gen_op_l##width##_kernel, \
1070 &gen_op_l##width##_le_kernel, \
1072 #define OP_ST_TABLE(width) \
1073 static GenOpFunc *gen_op_st##width[] = { \
1074 &gen_op_st##width##_user, \
1075 &gen_op_st##width##_le_user, \
1076 &gen_op_st##width##_kernel, \
1077 &gen_op_st##width##_le_kernel, \
1079 /* Byte access routine are endian safe */
1080 #define gen_op_stb_le_user gen_op_stb_user
1081 #define gen_op_lbz_le_user gen_op_lbz_user
1082 #define gen_op_stb_le_kernel gen_op_stb_kernel
1083 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
1086 #define GEN_LD(width, opc) \
1087 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1089 uint32_t simm = SIMM(ctx->opcode); \
1090 if (rA(ctx->opcode) == 0) { \
1091 gen_op_set_T0(simm); \
1093 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1095 gen_op_addi(simm); \
1097 op_ldst(l##width); \
1098 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1101 #define GEN_LDU(width, opc) \
1102 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1104 uint32_t simm = SIMM(ctx->opcode); \
1105 if (rA(ctx->opcode) == 0 || \
1106 rA(ctx->opcode) == rD(ctx->opcode)) { \
1110 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1112 gen_op_addi(simm); \
1113 op_ldst(l##width); \
1114 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1115 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1118 #define GEN_LDUX(width, opc) \
1119 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1121 if (rA(ctx->opcode) == 0 || \
1122 rA(ctx->opcode) == rD(ctx->opcode)) { \
1126 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1127 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1129 op_ldst(l##width); \
1130 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1131 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1134 #define GEN_LDX(width, opc2, opc3) \
1135 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1137 if (rA(ctx->opcode) == 0) { \
1138 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1140 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1141 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1144 op_ldst(l##width); \
1145 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1148 #define GEN_LDS(width, op) \
1149 OP_LD_TABLE(width); \
1150 GEN_LD(width, op | 0x20); \
1151 GEN_LDU(width, op | 0x21); \
1152 GEN_LDUX(width, op | 0x01); \
1153 GEN_LDX(width, 0x17, op | 0x00)
1155 /* lbz lbzu lbzux lbzx */
1157 /* lha lhau lhaux lhax */
1159 /* lhz lhzu lhzux lhzx */
1161 /* lwz lwzu lwzux lwzx */
1164 /*** Integer store ***/
1165 #define GEN_ST(width, opc) \
1166 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1168 uint32_t simm = SIMM(ctx->opcode); \
1169 if (rA(ctx->opcode) == 0) { \
1170 gen_op_set_T0(simm); \
1172 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1174 gen_op_addi(simm); \
1176 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1177 op_ldst(st##width); \
1180 #define GEN_STU(width, opc) \
1181 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1183 uint32_t simm = SIMM(ctx->opcode); \
1184 if (rA(ctx->opcode) == 0) { \
1188 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1190 gen_op_addi(simm); \
1191 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1192 op_ldst(st##width); \
1193 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1196 #define GEN_STUX(width, opc) \
1197 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1199 if (rA(ctx->opcode) == 0) { \
1203 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1204 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1206 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1207 op_ldst(st##width); \
1208 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1211 #define GEN_STX(width, opc2, opc3) \
1212 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1214 if (rA(ctx->opcode) == 0) { \
1215 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1217 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1218 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1221 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1222 op_ldst(st##width); \
1225 #define GEN_STS(width, op) \
1226 OP_ST_TABLE(width); \
1227 GEN_ST(width, op | 0x20); \
1228 GEN_STU(width, op | 0x21); \
1229 GEN_STUX(width, op | 0x01); \
1230 GEN_STX(width, 0x17, op | 0x00)
1232 /* stb stbu stbux stbx */
1234 /* sth sthu sthux sthx */
1236 /* stw stwu stwux stwx */
1239 /*** Integer load and store with byte reverse ***/
1242 GEN_LDX(hbr
, 0x16, 0x18);
1245 GEN_LDX(wbr
, 0x16, 0x10);
1248 GEN_STX(hbr
, 0x16, 0x1C);
1251 GEN_STX(wbr
, 0x16, 0x14);
1253 /*** Integer load and store multiple ***/
1254 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1255 #if defined(CONFIG_USER_ONLY)
1256 static GenOpFunc1
*gen_op_lmw
[] = {
1260 static GenOpFunc1
*gen_op_stmw
[] = {
1262 &gen_op_stmw_le_raw
,
1265 static GenOpFunc1
*gen_op_lmw
[] = {
1267 &gen_op_lmw_le_user
,
1269 &gen_op_lmw_le_kernel
,
1271 static GenOpFunc1
*gen_op_stmw
[] = {
1273 &gen_op_stmw_le_user
,
1274 &gen_op_stmw_kernel
,
1275 &gen_op_stmw_le_kernel
,
1280 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1282 int simm
= SIMM(ctx
->opcode
);
1284 if (rA(ctx
->opcode
) == 0) {
1285 gen_op_set_T0(simm
);
1287 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1291 op_ldstm(lmw
, rD(ctx
->opcode
));
1295 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1297 int simm
= SIMM(ctx
->opcode
);
1299 if (rA(ctx
->opcode
) == 0) {
1300 gen_op_set_T0(simm
);
1302 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1306 op_ldstm(stmw
, rS(ctx
->opcode
));
1309 /*** Integer load and store strings ***/
1310 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1311 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1312 #if defined(CONFIG_USER_ONLY)
1313 static GenOpFunc1
*gen_op_lswi
[] = {
1315 &gen_op_lswi_le_raw
,
1317 static GenOpFunc3
*gen_op_lswx
[] = {
1319 &gen_op_lswx_le_raw
,
1321 static GenOpFunc1
*gen_op_stsw
[] = {
1323 &gen_op_stsw_le_raw
,
1326 static GenOpFunc1
*gen_op_lswi
[] = {
1328 &gen_op_lswi_le_user
,
1329 &gen_op_lswi_kernel
,
1330 &gen_op_lswi_le_kernel
,
1332 static GenOpFunc3
*gen_op_lswx
[] = {
1334 &gen_op_lswx_le_user
,
1335 &gen_op_lswx_kernel
,
1336 &gen_op_lswx_le_kernel
,
1338 static GenOpFunc1
*gen_op_stsw
[] = {
1340 &gen_op_stsw_le_user
,
1341 &gen_op_stsw_kernel
,
1342 &gen_op_stsw_le_kernel
,
1347 /* PPC32 specification says we must generate an exception if
1348 * rA is in the range of registers to be loaded.
1349 * In an other hand, IBM says this is valid, but rA won't be loaded.
1350 * For now, I'll follow the spec...
1352 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER
)
1354 int nb
= NB(ctx
->opcode
);
1355 int start
= rD(ctx
->opcode
);
1356 int ra
= rA(ctx
->opcode
);
1362 if (((start
+ nr
) > 32 && start
<= ra
&& (start
+ nr
- 32) > ra
) ||
1363 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
)) {
1364 RET_EXCP(ctx
, EXCP_PROGRAM
, EXCP_INVAL
| EXCP_INVAL_LSWX
);
1370 gen_op_load_gpr_T0(ra
);
1373 op_ldsts(lswi
, start
);
1377 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER
)
1379 int ra
= rA(ctx
->opcode
);
1380 int rb
= rB(ctx
->opcode
);
1383 gen_op_load_gpr_T0(rb
);
1386 gen_op_load_gpr_T0(ra
);
1387 gen_op_load_gpr_T1(rb
);
1390 gen_op_load_xer_bc();
1391 op_ldstsx(lswx
, rD(ctx
->opcode
), ra
, rb
);
1395 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER
)
1397 int nb
= NB(ctx
->opcode
);
1399 if (rA(ctx
->opcode
) == 0) {
1402 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1407 op_ldsts(stsw
, rS(ctx
->opcode
));
1411 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER
)
1413 int ra
= rA(ctx
->opcode
);
1416 gen_op_load_gpr_T0(rB(ctx
->opcode
));
1417 ra
= rB(ctx
->opcode
);
1419 gen_op_load_gpr_T0(ra
);
1420 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1423 gen_op_load_xer_bc();
1424 op_ldsts(stsw
, rS(ctx
->opcode
));
1427 /*** Memory synchronisation ***/
1429 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM
)
1434 GEN_HANDLER(isync
, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM
)
1438 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1439 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1440 #if defined(CONFIG_USER_ONLY)
1441 static GenOpFunc
*gen_op_lwarx
[] = {
1443 &gen_op_lwarx_le_raw
,
1445 static GenOpFunc
*gen_op_stwcx
[] = {
1447 &gen_op_stwcx_le_raw
,
1450 static GenOpFunc
*gen_op_lwarx
[] = {
1452 &gen_op_lwarx_le_user
,
1453 &gen_op_lwarx_kernel
,
1454 &gen_op_lwarx_le_kernel
,
1456 static GenOpFunc
*gen_op_stwcx
[] = {
1458 &gen_op_stwcx_le_user
,
1459 &gen_op_stwcx_kernel
,
1460 &gen_op_stwcx_le_kernel
,
1465 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES
)
1467 if (rA(ctx
->opcode
) == 0) {
1468 gen_op_load_gpr_T0(rB(ctx
->opcode
));
1470 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1471 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1475 gen_op_store_T1_gpr(rD(ctx
->opcode
));
1479 GEN_HANDLER(stwcx_
, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
1481 if (rA(ctx
->opcode
) == 0) {
1482 gen_op_load_gpr_T0(rB(ctx
->opcode
));
1484 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1485 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1488 gen_op_load_gpr_T1(rS(ctx
->opcode
));
1493 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM
)
1497 /*** Floating-point load ***/
1498 #define GEN_LDF(width, opc) \
1499 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1501 uint32_t simm = SIMM(ctx->opcode); \
1502 if (!ctx->fpu_enabled) { \
1503 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1506 if (rA(ctx->opcode) == 0) { \
1507 gen_op_set_T0(simm); \
1509 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1511 gen_op_addi(simm); \
1513 op_ldst(l##width); \
1514 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1517 #define GEN_LDUF(width, opc) \
1518 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1520 uint32_t simm = SIMM(ctx->opcode); \
1521 if (!ctx->fpu_enabled) { \
1522 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1525 if (rA(ctx->opcode) == 0 || \
1526 rA(ctx->opcode) == rD(ctx->opcode)) { \
1530 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1532 gen_op_addi(simm); \
1533 op_ldst(l##width); \
1534 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1535 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1538 #define GEN_LDUXF(width, opc) \
1539 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
1541 if (!ctx->fpu_enabled) { \
1542 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1545 if (rA(ctx->opcode) == 0 || \
1546 rA(ctx->opcode) == rD(ctx->opcode)) { \
1550 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1551 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1553 op_ldst(l##width); \
1554 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1555 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1558 #define GEN_LDXF(width, opc2, opc3) \
1559 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
1561 if (!ctx->fpu_enabled) { \
1562 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1565 if (rA(ctx->opcode) == 0) { \
1566 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1568 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1569 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1572 op_ldst(l##width); \
1573 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1576 #define GEN_LDFS(width, op) \
1577 OP_LD_TABLE(width); \
1578 GEN_LDF(width, op | 0x20); \
1579 GEN_LDUF(width, op | 0x21); \
1580 GEN_LDUXF(width, op | 0x01); \
1581 GEN_LDXF(width, 0x17, op | 0x00)
1583 /* lfd lfdu lfdux lfdx */
1585 /* lfs lfsu lfsux lfsx */
1588 /*** Floating-point store ***/
1589 #define GEN_STF(width, opc) \
1590 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1592 uint32_t simm = SIMM(ctx->opcode); \
1593 if (!ctx->fpu_enabled) { \
1594 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1597 if (rA(ctx->opcode) == 0) { \
1598 gen_op_set_T0(simm); \
1600 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1602 gen_op_addi(simm); \
1604 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1605 op_ldst(st##width); \
1608 #define GEN_STUF(width, opc) \
1609 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1611 uint32_t simm = SIMM(ctx->opcode); \
1612 if (!ctx->fpu_enabled) { \
1613 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1616 if (rA(ctx->opcode) == 0) { \
1620 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1622 gen_op_addi(simm); \
1623 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1624 op_ldst(st##width); \
1625 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1628 #define GEN_STUXF(width, opc) \
1629 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
1631 if (!ctx->fpu_enabled) { \
1632 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1635 if (rA(ctx->opcode) == 0) { \
1639 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1640 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1642 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1643 op_ldst(st##width); \
1644 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1647 #define GEN_STXF(width, opc2, opc3) \
1648 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
1650 if (!ctx->fpu_enabled) { \
1651 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1654 if (rA(ctx->opcode) == 0) { \
1655 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1657 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1658 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1661 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1662 op_ldst(st##width); \
1665 #define GEN_STFS(width, op) \
1666 OP_ST_TABLE(width); \
1667 GEN_STF(width, op | 0x20); \
1668 GEN_STUF(width, op | 0x21); \
1669 GEN_STUXF(width, op | 0x01); \
1670 GEN_STXF(width, 0x17, op | 0x00)
1672 /* stfd stfdu stfdux stfdx */
1674 /* stfs stfsu stfsux stfsx */
1679 GEN_HANDLER(stfiwx
, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT
)
1681 if (!ctx
->fpu_enabled
) {
1682 RET_EXCP(ctx
, EXCP_NO_FP
, 0);
1691 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
1693 uint32_t li
, target
;
1695 /* sign extend LI */
1696 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
1698 if (AA(ctx
->opcode
) == 0)
1699 target
= ctx
->nip
+ li
- 4;
1702 if (LK(ctx
->opcode
)) {
1703 gen_op_setlr(ctx
->nip
);
1705 gen_op_b((long)ctx
->tb
, target
);
1706 ctx
->exception
= EXCP_BRANCH
;
1713 static inline void gen_bcond(DisasContext
*ctx
, int type
)
1715 uint32_t target
= 0;
1716 uint32_t bo
= BO(ctx
->opcode
);
1717 uint32_t bi
= BI(ctx
->opcode
);
1721 if ((bo
& 0x4) == 0)
1725 li
= (int32_t)((int16_t)(BD(ctx
->opcode
)));
1726 if (AA(ctx
->opcode
) == 0) {
1727 target
= ctx
->nip
+ li
- 4;
1733 gen_op_movl_T1_ctr();
1737 gen_op_movl_T1_lr();
1740 if (LK(ctx
->opcode
)) {
1741 gen_op_setlr(ctx
->nip
);
1744 /* No CR condition */
1755 if (type
== BCOND_IM
) {
1756 gen_op_b((long)ctx
->tb
, target
);
1763 mask
= 1 << (3 - (bi
& 0x03));
1764 gen_op_load_crf_T0(bi
>> 2);
1768 gen_op_test_ctr_true(mask
);
1771 gen_op_test_ctrz_true(mask
);
1776 gen_op_test_true(mask
);
1782 gen_op_test_ctr_false(mask
);
1785 gen_op_test_ctrz_false(mask
);
1790 gen_op_test_false(mask
);
1795 if (type
== BCOND_IM
) {
1796 gen_op_btest((long)ctx
->tb
, target
, ctx
->nip
);
1798 gen_op_btest_T1(ctx
->nip
);
1801 ctx
->exception
= EXCP_BRANCH
;
1804 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
1806 gen_bcond(ctx
, BCOND_IM
);
1809 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
)
1811 gen_bcond(ctx
, BCOND_CTR
);
1814 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
)
1816 gen_bcond(ctx
, BCOND_LR
);
1819 /*** Condition register logical ***/
1820 #define GEN_CRLOGIC(op, opc) \
1821 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1823 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1824 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1825 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1826 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1828 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1829 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1830 3 - (crbD(ctx->opcode) & 0x03)); \
1831 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
1835 GEN_CRLOGIC(and, 0x08)
1837 GEN_CRLOGIC(andc
, 0x04)
1839 GEN_CRLOGIC(eqv
, 0x09)
1841 GEN_CRLOGIC(nand
, 0x07)
1843 GEN_CRLOGIC(nor
, 0x01)
1845 GEN_CRLOGIC(or, 0x0E)
1847 GEN_CRLOGIC(orc
, 0x0D)
1849 GEN_CRLOGIC(xor, 0x06)
1851 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
)
1853 gen_op_load_crf_T0(crfS(ctx
->opcode
));
1854 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1857 /*** System linkage ***/
1858 /* rfi (supervisor only) */
1859 GEN_HANDLER(rfi
, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW
)
1861 #if defined(CONFIG_USER_ONLY)
1864 /* Restore CPU state */
1865 if (!ctx
->supervisor
) {
1870 RET_EXCP(ctx
, EXCP_RFI
, 0);
1875 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW
)
1877 #if defined(CONFIG_USER_ONLY)
1878 RET_EXCP(ctx
, EXCP_SYSCALL_USER
, 0);
1880 RET_EXCP(ctx
, EXCP_SYSCALL
, 0);
1886 GEN_HANDLER(tw
, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW
)
1888 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1889 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1890 gen_op_tw(TO(ctx
->opcode
));
1894 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
1896 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1898 printf("%s: param=0x%04x T0=0x%04x\n", __func__
,
1899 SIMM(ctx
->opcode
), TO(ctx
->opcode
));
1901 gen_op_twi(SIMM(ctx
->opcode
), TO(ctx
->opcode
));
1904 /*** Processor control ***/
1905 static inline int check_spr_access (int spr
, int rw
, int supervisor
)
1907 uint32_t rights
= spr_access
[spr
>> 1] >> (4 * (spr
& 1));
1910 if (spr
!= LR
&& spr
!= CTR
) {
1912 fprintf(logfile
, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__
,
1913 SPR_ENCODE(spr
), supervisor
, rw
, rights
,
1914 (rights
>> ((2 * supervisor
) + rw
)) & 1);
1916 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__
,
1917 SPR_ENCODE(spr
), supervisor
, rw
, rights
,
1918 (rights
>> ((2 * supervisor
) + rw
)) & 1);
1924 rights
= rights
>> (2 * supervisor
);
1925 rights
= rights
>> rw
;
1931 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
)
1933 gen_op_load_xer_cr();
1934 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1935 gen_op_clear_xer_cr();
1939 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC
)
1942 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1946 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
)
1948 #if defined(CONFIG_USER_ONLY)
1951 if (!ctx
->supervisor
) {
1956 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1961 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
)
1963 uint32_t sprn
= SPR(ctx
->opcode
);
1965 #if defined(CONFIG_USER_ONLY)
1966 switch (check_spr_access(sprn
, 0, 0))
1968 switch (check_spr_access(sprn
, 0, ctx
->supervisor
))
1972 RET_EXCP(ctx
, EXCP_PROGRAM
, EXCP_INVAL
| EXCP_INVAL_SPR
);
1991 gen_op_load_ibat(0, 0);
1994 gen_op_load_ibat(0, 1);
1997 gen_op_load_ibat(0, 2);
2000 gen_op_load_ibat(0, 3);
2003 gen_op_load_ibat(0, 4);
2006 gen_op_load_ibat(0, 5);
2009 gen_op_load_ibat(0, 6);
2012 gen_op_load_ibat(0, 7);
2015 gen_op_load_ibat(1, 0);
2018 gen_op_load_ibat(1, 1);
2021 gen_op_load_ibat(1, 2);
2024 gen_op_load_ibat(1, 3);
2027 gen_op_load_ibat(1, 4);
2030 gen_op_load_ibat(1, 5);
2033 gen_op_load_ibat(1, 6);
2036 gen_op_load_ibat(1, 7);
2039 gen_op_load_dbat(0, 0);
2042 gen_op_load_dbat(0, 1);
2045 gen_op_load_dbat(0, 2);
2048 gen_op_load_dbat(0, 3);
2051 gen_op_load_dbat(0, 4);
2054 gen_op_load_dbat(0, 5);
2057 gen_op_load_dbat(0, 6);
2060 gen_op_load_dbat(0, 7);
2063 gen_op_load_dbat(1, 0);
2066 gen_op_load_dbat(1, 1);
2069 gen_op_load_dbat(1, 2);
2072 gen_op_load_dbat(1, 3);
2075 gen_op_load_dbat(1, 4);
2078 gen_op_load_dbat(1, 5);
2081 gen_op_load_dbat(1, 6);
2084 gen_op_load_dbat(1, 7);
2099 gen_op_load_spr(sprn
);
2102 gen_op_store_T0_gpr(rD(ctx
->opcode
));
2106 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC
)
2108 uint32_t sprn
= SPR(ctx
->opcode
);
2110 /* We need to update the time base before reading it */
2122 gen_op_store_T0_gpr(rD(ctx
->opcode
));
2126 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC
)
2128 gen_op_load_gpr_T0(rS(ctx
->opcode
));
2129 gen_op_store_cr(CRM(ctx
->opcode
));
2133 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
)
2135 #if defined(CONFIG_USER_ONLY)
2138 if (!ctx
->supervisor
) {
2142 gen_op_load_gpr_T0(rS(ctx
->opcode
));
2144 /* Must stop the translation as machine state (may have) changed */
2150 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
)
2152 uint32_t sprn
= SPR(ctx
->opcode
);
2156 fprintf(logfile
, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn
),
2157 rS(ctx
->opcode
), sprn
);
2160 #if defined(CONFIG_USER_ONLY)
2161 switch (check_spr_access(sprn
, 1, 0))
2163 switch (check_spr_access(sprn
, 1, ctx
->supervisor
))
2167 RET_EXCP(ctx
, EXCP_PROGRAM
, EXCP_INVAL
| EXCP_INVAL_SPR
);
2175 gen_op_load_gpr_T0(rS(ctx
->opcode
));
2187 gen_op_store_ibat(0, 0);
2191 gen_op_store_ibat(0, 1);
2195 gen_op_store_ibat(0, 2);
2199 gen_op_store_ibat(0, 3);
2203 gen_op_store_ibat(0, 4);
2207 gen_op_store_ibat(0, 5);
2211 gen_op_store_ibat(0, 6);
2215 gen_op_store_ibat(0, 7);
2219 gen_op_store_ibat(1, 0);
2223 gen_op_store_ibat(1, 1);
2227 gen_op_store_ibat(1, 2);
2231 gen_op_store_ibat(1, 3);
2235 gen_op_store_ibat(1, 4);
2239 gen_op_store_ibat(1, 5);
2243 gen_op_store_ibat(1, 6);
2247 gen_op_store_ibat(1, 7);
2251 gen_op_store_dbat(0, 0);
2255 gen_op_store_dbat(0, 1);
2259 gen_op_store_dbat(0, 2);
2263 gen_op_store_dbat(0, 3);
2267 gen_op_store_dbat(0, 4);
2271 gen_op_store_dbat(0, 5);
2275 gen_op_store_dbat(0, 6);
2279 gen_op_store_dbat(0, 7);
2283 gen_op_store_dbat(1, 0);
2287 gen_op_store_dbat(1, 1);
2291 gen_op_store_dbat(1, 2);
2295 gen_op_store_dbat(1, 3);
2299 gen_op_store_dbat(1, 4);
2303 gen_op_store_dbat(1, 5);
2307 gen_op_store_dbat(1, 6);
2311 gen_op_store_dbat(1, 7);
2315 gen_op_store_sdr1();
2325 gen_op_store_decr();
2328 gen_op_store_spr(sprn
);
2333 /*** Cache management ***/
2334 /* For now, all those will be implemented as nop:
2335 * this is valid, regarding the PowerPC specs...
2336 * We just have to flush tb while invalidating instruction cache lines...
2339 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE
)
2341 if (rA(ctx
->opcode
) == 0) {
2342 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2344 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2345 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2351 /* dcbi (Supervisor only) */
2352 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
)
2354 #if defined(CONFIG_USER_ONLY)
2357 if (!ctx
->supervisor
) {
2361 if (rA(ctx
->opcode
) == 0) {
2362 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2364 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2365 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2374 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
)
2376 if (rA(ctx
->opcode
) == 0) {
2377 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2379 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2380 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2387 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE
)
2392 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE
)
2397 #if defined(CONFIG_USER_ONLY)
2398 #define op_dcbz() gen_op_dcbz_raw()
2400 #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2401 static GenOpFunc
*gen_op_dcbz
[] = {
2403 &gen_op_dcbz_kernel
,
2407 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE
)
2409 if (rA(ctx
->opcode
) == 0) {
2410 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2412 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2413 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2417 gen_op_check_reservation();
2421 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE
)
2423 if (rA(ctx
->opcode
) == 0) {
2424 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2426 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2427 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2435 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT
)
2439 /*** Segment register manipulation ***/
2440 /* Supervisor only: */
2442 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
)
2444 #if defined(CONFIG_USER_ONLY)
2447 if (!ctx
->supervisor
) {
2451 gen_op_load_sr(SR(ctx
->opcode
));
2452 gen_op_store_T0_gpr(rD(ctx
->opcode
));
2457 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
)
2459 #if defined(CONFIG_USER_ONLY)
2462 if (!ctx
->supervisor
) {
2466 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2468 gen_op_store_T0_gpr(rD(ctx
->opcode
));
2473 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
)
2475 #if defined(CONFIG_USER_ONLY)
2478 if (!ctx
->supervisor
) {
2482 gen_op_load_gpr_T0(rS(ctx
->opcode
));
2483 gen_op_store_sr(SR(ctx
->opcode
));
2488 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
)
2490 #if defined(CONFIG_USER_ONLY)
2493 if (!ctx
->supervisor
) {
2497 gen_op_load_gpr_T0(rS(ctx
->opcode
));
2498 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2499 gen_op_store_srin();
2503 /*** Lookaside buffer management ***/
2504 /* Optional & supervisor only: */
2506 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT
)
2508 #if defined(CONFIG_USER_ONLY)
2511 if (!ctx
->supervisor
) {
2513 fprintf(logfile
, "%s: ! supervisor\n", __func__
);
2523 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM
)
2525 #if defined(CONFIG_USER_ONLY)
2528 if (!ctx
->supervisor
) {
2532 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2539 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM
)
2541 #if defined(CONFIG_USER_ONLY)
2544 if (!ctx
->supervisor
) {
2548 /* This has no effect: it should ensure that all previous
2549 * tlbie have completed
2555 /*** External control ***/
2557 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2558 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2559 #if defined(CONFIG_USER_ONLY)
2560 static GenOpFunc
*gen_op_eciwx
[] = {
2562 &gen_op_eciwx_le_raw
,
2564 static GenOpFunc
*gen_op_ecowx
[] = {
2566 &gen_op_ecowx_le_raw
,
2569 static GenOpFunc
*gen_op_eciwx
[] = {
2571 &gen_op_eciwx_le_user
,
2572 &gen_op_eciwx_kernel
,
2573 &gen_op_eciwx_le_kernel
,
2575 static GenOpFunc
*gen_op_ecowx
[] = {
2577 &gen_op_ecowx_le_user
,
2578 &gen_op_ecowx_kernel
,
2579 &gen_op_ecowx_le_kernel
,
2584 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
)
2586 /* Should check EAR[E] & alignment ! */
2587 if (rA(ctx
->opcode
) == 0) {
2588 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2590 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2591 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2595 gen_op_store_T0_gpr(rD(ctx
->opcode
));
2599 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
)
2601 /* Should check EAR[E] & alignment ! */
2602 if (rA(ctx
->opcode
) == 0) {
2603 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2605 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2606 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2609 gen_op_load_gpr_T2(rS(ctx
->opcode
));
2613 /* End opcode list */
2614 GEN_OPCODE_MARK(end
);
2616 /*****************************************************************************/
2620 int fflush (FILE *stream
);
2622 /* Main ppc opcodes table:
2623 * at init, all opcodes are invalids
2625 static opc_handler_t
*ppc_opcodes
[0x40];
2629 PPC_DIRECT
= 0, /* Opcode routine */
2630 PPC_INDIRECT
= 1, /* Indirect opcode table */
2633 static inline int is_indirect_opcode (void *handler
)
2635 return ((unsigned long)handler
& 0x03) == PPC_INDIRECT
;
2638 static inline opc_handler_t
**ind_table(void *handler
)
2640 return (opc_handler_t
**)((unsigned long)handler
& ~3);
2643 /* Instruction table creation */
2644 /* Opcodes tables creation */
2645 static void fill_new_table (opc_handler_t
**table
, int len
)
2649 for (i
= 0; i
< len
; i
++)
2650 table
[i
] = &invalid_handler
;
2653 static int create_new_table (opc_handler_t
**table
, unsigned char idx
)
2655 opc_handler_t
**tmp
;
2657 tmp
= malloc(0x20 * sizeof(opc_handler_t
));
2660 fill_new_table(tmp
, 0x20);
2661 table
[idx
] = (opc_handler_t
*)((unsigned long)tmp
| PPC_INDIRECT
);
2666 static int insert_in_table (opc_handler_t
**table
, unsigned char idx
,
2667 opc_handler_t
*handler
)
2669 if (table
[idx
] != &invalid_handler
)
2671 table
[idx
] = handler
;
2676 static int register_direct_insn (opc_handler_t
**ppc_opcodes
,
2677 unsigned char idx
, opc_handler_t
*handler
)
2679 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
2680 printf("*** ERROR: opcode %02x already assigned in main "
2681 "opcode table\n", idx
);
2688 static int register_ind_in_table (opc_handler_t
**table
,
2689 unsigned char idx1
, unsigned char idx2
,
2690 opc_handler_t
*handler
)
2692 if (table
[idx1
] == &invalid_handler
) {
2693 if (create_new_table(table
, idx1
) < 0) {
2694 printf("*** ERROR: unable to create indirect table "
2695 "idx=%02x\n", idx1
);
2699 if (!is_indirect_opcode(table
[idx1
])) {
2700 printf("*** ERROR: idx %02x already assigned to a direct "
2705 if (handler
!= NULL
&&
2706 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
2707 printf("*** ERROR: opcode %02x already assigned in "
2708 "opcode table %02x\n", idx2
, idx1
);
2715 static int register_ind_insn (opc_handler_t
**ppc_opcodes
,
2716 unsigned char idx1
, unsigned char idx2
,
2717 opc_handler_t
*handler
)
2721 ret
= register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
2726 static int register_dblind_insn (opc_handler_t
**ppc_opcodes
,
2727 unsigned char idx1
, unsigned char idx2
,
2728 unsigned char idx3
, opc_handler_t
*handler
)
2730 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
2731 printf("*** ERROR: unable to join indirect table idx "
2732 "[%02x-%02x]\n", idx1
, idx2
);
2735 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
2737 printf("*** ERROR: unable to insert opcode "
2738 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
2745 static int register_insn (opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
2747 if (insn
->opc2
!= 0xFF) {
2748 if (insn
->opc3
!= 0xFF) {
2749 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
2750 insn
->opc3
, &insn
->handler
) < 0)
2753 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
2754 insn
->opc2
, &insn
->handler
) < 0)
2758 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0)
2765 static int test_opcode_table (opc_handler_t
**table
, int len
)
2769 for (i
= 0, count
= 0; i
< len
; i
++) {
2770 /* Consistency fixup */
2771 if (table
[i
] == NULL
)
2772 table
[i
] = &invalid_handler
;
2773 if (table
[i
] != &invalid_handler
) {
2774 if (is_indirect_opcode(table
[i
])) {
2775 tmp
= test_opcode_table(ind_table(table
[i
]), 0x20);
2778 table
[i
] = &invalid_handler
;
2791 static void fix_opcode_tables (opc_handler_t
**ppc_opcodes
)
2793 if (test_opcode_table(ppc_opcodes
, 0x40) == 0)
2794 printf("*** WARNING: no opcode defined !\n");
2797 #define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
2798 #define SPR_UR SPR_RIGHTS(0, 0)
2799 #define SPR_UW SPR_RIGHTS(1, 0)
2800 #define SPR_SR SPR_RIGHTS(0, 1)
2801 #define SPR_SW SPR_RIGHTS(1, 1)
2803 #define spr_set_rights(spr, rights) \
2805 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2808 static void init_spr_rights (uint32_t pvr
)
2811 spr_set_rights(XER
, SPR_UR
| SPR_UW
| SPR_SR
| SPR_SW
);
2813 spr_set_rights(LR
, SPR_UR
| SPR_UW
| SPR_SR
| SPR_SW
);
2815 spr_set_rights(CTR
, SPR_UR
| SPR_UW
| SPR_SR
| SPR_SW
);
2817 spr_set_rights(V_TBL
, SPR_UR
| SPR_SR
);
2819 spr_set_rights(V_TBU
, SPR_UR
| SPR_SR
);
2820 /* DSISR (SPR 18) */
2821 spr_set_rights(DSISR
, SPR_SR
| SPR_SW
);
2823 spr_set_rights(DAR
, SPR_SR
| SPR_SW
);
2825 spr_set_rights(DECR
, SPR_SR
| SPR_SW
);
2827 spr_set_rights(SDR1
, SPR_SR
| SPR_SW
);
2829 spr_set_rights(SRR0
, SPR_SR
| SPR_SW
);
2831 spr_set_rights(SRR1
, SPR_SR
| SPR_SW
);
2832 /* SPRG0 (SPR 272) */
2833 spr_set_rights(SPRG0
, SPR_SR
| SPR_SW
);
2834 /* SPRG1 (SPR 273) */
2835 spr_set_rights(SPRG1
, SPR_SR
| SPR_SW
);
2836 /* SPRG2 (SPR 274) */
2837 spr_set_rights(SPRG2
, SPR_SR
| SPR_SW
);
2838 /* SPRG3 (SPR 275) */
2839 spr_set_rights(SPRG3
, SPR_SR
| SPR_SW
);
2841 spr_set_rights(ASR
, SPR_SR
| SPR_SW
);
2843 spr_set_rights(EAR
, SPR_SR
| SPR_SW
);
2845 spr_set_rights(O_TBL
, SPR_SW
);
2847 spr_set_rights(O_TBU
, SPR_SW
);
2849 spr_set_rights(PVR
, SPR_SR
);
2850 /* IBAT0U (SPR 528) */
2851 spr_set_rights(IBAT0U
, SPR_SR
| SPR_SW
);
2852 /* IBAT0L (SPR 529) */
2853 spr_set_rights(IBAT0L
, SPR_SR
| SPR_SW
);
2854 /* IBAT1U (SPR 530) */
2855 spr_set_rights(IBAT1U
, SPR_SR
| SPR_SW
);
2856 /* IBAT1L (SPR 531) */
2857 spr_set_rights(IBAT1L
, SPR_SR
| SPR_SW
);
2858 /* IBAT2U (SPR 532) */
2859 spr_set_rights(IBAT2U
, SPR_SR
| SPR_SW
);
2860 /* IBAT2L (SPR 533) */
2861 spr_set_rights(IBAT2L
, SPR_SR
| SPR_SW
);
2862 /* IBAT3U (SPR 534) */
2863 spr_set_rights(IBAT3U
, SPR_SR
| SPR_SW
);
2864 /* IBAT3L (SPR 535) */
2865 spr_set_rights(IBAT3L
, SPR_SR
| SPR_SW
);
2866 /* DBAT0U (SPR 536) */
2867 spr_set_rights(DBAT0U
, SPR_SR
| SPR_SW
);
2868 /* DBAT0L (SPR 537) */
2869 spr_set_rights(DBAT0L
, SPR_SR
| SPR_SW
);
2870 /* DBAT1U (SPR 538) */
2871 spr_set_rights(DBAT1U
, SPR_SR
| SPR_SW
);
2872 /* DBAT1L (SPR 539) */
2873 spr_set_rights(DBAT1L
, SPR_SR
| SPR_SW
);
2874 /* DBAT2U (SPR 540) */
2875 spr_set_rights(DBAT2U
, SPR_SR
| SPR_SW
);
2876 /* DBAT2L (SPR 541) */
2877 spr_set_rights(DBAT2L
, SPR_SR
| SPR_SW
);
2878 /* DBAT3U (SPR 542) */
2879 spr_set_rights(DBAT3U
, SPR_SR
| SPR_SW
);
2880 /* DBAT3L (SPR 543) */
2881 spr_set_rights(DBAT3L
, SPR_SR
| SPR_SW
);
2882 /* FPECR (SPR 1022) */
2883 spr_set_rights(FPECR
, SPR_SR
| SPR_SW
);
2884 /* Special registers for PPC 604 */
2885 if ((pvr
& 0xFFFF0000) == 0x00040000) {
2887 spr_set_rights(IABR
, SPR_SR
| SPR_SW
);
2888 /* DABR (SPR 1013) */
2889 spr_set_rights(DABR
, SPR_SR
| SPR_SW
);
2891 spr_set_rights(HID0
, SPR_SR
| SPR_SW
);
2893 spr_set_rights(PIR
, SPR_SR
| SPR_SW
);
2895 spr_set_rights(PMC1
, SPR_SR
| SPR_SW
);
2897 spr_set_rights(PMC2
, SPR_SR
| SPR_SW
);
2899 spr_set_rights(MMCR0
, SPR_SR
| SPR_SW
);
2901 spr_set_rights(SIA
, SPR_SR
| SPR_SW
);
2903 spr_set_rights(SDA
, SPR_SR
| SPR_SW
);
2905 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2906 if ((pvr
& 0xFFFF0000) == 0x00080000 ||
2907 (pvr
& 0xFFFF0000) == 0x70000000) {
2909 spr_set_rights(HID0
, SPR_SR
| SPR_SW
);
2911 spr_set_rights(HID1
, SPR_SR
| SPR_SW
);
2913 spr_set_rights(IABR
, SPR_SR
| SPR_SW
);
2915 spr_set_rights(ICTC
, SPR_SR
| SPR_SW
);
2917 spr_set_rights(L2CR
, SPR_SR
| SPR_SW
);
2919 spr_set_rights(MMCR0
, SPR_SR
| SPR_SW
);
2921 spr_set_rights(MMCR1
, SPR_SR
| SPR_SW
);
2923 spr_set_rights(PMC1
, SPR_SR
| SPR_SW
);
2925 spr_set_rights(PMC2
, SPR_SR
| SPR_SW
);
2927 spr_set_rights(PMC3
, SPR_SR
| SPR_SW
);
2929 spr_set_rights(PMC4
, SPR_SR
| SPR_SW
);
2931 spr_set_rights(SIA
, SPR_SR
| SPR_SW
);
2933 spr_set_rights(SDA
, SPR_SR
| SPR_SW
);
2935 spr_set_rights(THRM1
, SPR_SR
| SPR_SW
);
2937 spr_set_rights(THRM2
, SPR_SR
| SPR_SW
);
2939 spr_set_rights(THRM3
, SPR_SR
| SPR_SW
);
2941 spr_set_rights(UMMCR0
, SPR_UR
| SPR_UW
);
2943 spr_set_rights(UMMCR1
, SPR_UR
| SPR_UW
);
2945 spr_set_rights(UPMC1
, SPR_UR
| SPR_UW
);
2947 spr_set_rights(UPMC2
, SPR_UR
| SPR_UW
);
2949 spr_set_rights(UPMC3
, SPR_UR
| SPR_UW
);
2951 spr_set_rights(UPMC4
, SPR_UR
| SPR_UW
);
2953 spr_set_rights(USIA
, SPR_UR
| SPR_UW
);
2955 /* MPC755 has special registers */
2956 if (pvr
== 0x00083100) {
2958 spr_set_rights(SPRG4
, SPR_SR
| SPR_SW
);
2960 spr_set_rights(SPRG5
, SPR_SR
| SPR_SW
);
2962 spr_set_rights(SPRG6
, SPR_SR
| SPR_SW
);
2964 spr_set_rights(SPRG7
, SPR_SR
| SPR_SW
);
2966 spr_set_rights(IBAT4U
, SPR_SR
| SPR_SW
);
2968 spr_set_rights(IBAT4L
, SPR_SR
| SPR_SW
);
2970 spr_set_rights(IBAT5U
, SPR_SR
| SPR_SW
);
2972 spr_set_rights(IBAT5L
, SPR_SR
| SPR_SW
);
2974 spr_set_rights(IBAT6U
, SPR_SR
| SPR_SW
);
2976 spr_set_rights(IBAT6L
, SPR_SR
| SPR_SW
);
2978 spr_set_rights(IBAT7U
, SPR_SR
| SPR_SW
);
2980 spr_set_rights(IBAT7L
, SPR_SR
| SPR_SW
);
2982 spr_set_rights(DBAT4U
, SPR_SR
| SPR_SW
);
2984 spr_set_rights(DBAT4L
, SPR_SR
| SPR_SW
);
2986 spr_set_rights(DBAT5U
, SPR_SR
| SPR_SW
);
2988 spr_set_rights(DBAT5L
, SPR_SR
| SPR_SW
);
2990 spr_set_rights(DBAT6U
, SPR_SR
| SPR_SW
);
2992 spr_set_rights(DBAT6L
, SPR_SR
| SPR_SW
);
2994 spr_set_rights(DBAT7U
, SPR_SR
| SPR_SW
);
2996 spr_set_rights(DBAT7L
, SPR_SR
| SPR_SW
);
2998 spr_set_rights(DMISS
, SPR_SR
| SPR_SW
);
3000 spr_set_rights(DCMP
, SPR_SR
| SPR_SW
);
3002 spr_set_rights(DHASH1
, SPR_SR
| SPR_SW
);
3004 spr_set_rights(DHASH2
, SPR_SR
| SPR_SW
);
3006 spr_set_rights(IMISS
, SPR_SR
| SPR_SW
);
3008 spr_set_rights(ICMP
, SPR_SR
| SPR_SW
);
3010 spr_set_rights(RPA
, SPR_SR
| SPR_SW
);
3012 spr_set_rights(HID2
, SPR_SR
| SPR_SW
);
3014 spr_set_rights(L2PM
, SPR_SR
| SPR_SW
);
3018 /*****************************************************************************/
3019 /* PPC "main stream" common instructions (no optional ones) */
3021 typedef struct ppc_proc_t
{
3026 typedef struct ppc_def_t
{
3028 unsigned long pvr_mask
;
3032 static ppc_proc_t ppc_proc_common
= {
3033 .flags
= PPC_COMMON
,
3037 static ppc_proc_t ppc_proc_G3
= {
3042 static ppc_def_t ppc_defs
[] =
3044 /* MPC740/745/750/755 (G3) */
3047 .pvr_mask
= 0xFFFF0000,
3048 .proc
= &ppc_proc_G3
,
3050 /* IBM 750FX (G3 embedded) */
3053 .pvr_mask
= 0xFFFF0000,
3054 .proc
= &ppc_proc_G3
,
3056 /* Fallback (generic PPC) */
3059 .pvr_mask
= 0x00000000,
3060 .proc
= &ppc_proc_common
,
3064 static int create_ppc_proc (opc_handler_t
**ppc_opcodes
, unsigned long pvr
)
3066 opcode_t
*opc
, *start
, *end
;
3069 fill_new_table(ppc_opcodes
, 0x40);
3070 for (i
= 0; ; i
++) {
3071 if ((ppc_defs
[i
].pvr
& ppc_defs
[i
].pvr_mask
) ==
3072 (pvr
& ppc_defs
[i
].pvr_mask
)) {
3073 flags
= ppc_defs
[i
].proc
->flags
;
3078 if (&opc_start
< &opc_end
) {
3085 for (opc
= start
+ 1; opc
!= end
; opc
++) {
3086 if ((opc
->handler
.type
& flags
) != 0)
3087 if (register_insn(ppc_opcodes
, opc
) < 0) {
3088 printf("*** ERROR initializing PPC instruction "
3089 "0x%02x 0x%02x 0x%02x\n", opc
->opc1
, opc
->opc2
,
3094 fix_opcode_tables(ppc_opcodes
);
3100 /*****************************************************************************/
3101 /* Misc PPC helpers */
3103 void cpu_dump_state(CPUState
*env
, FILE *f
,
3104 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
3109 cpu_fprintf(f
, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
3110 "MSR=0x%08x\n", env
->nip
, env
->lr
, env
->ctr
,
3111 _load_xer(env
), _load_msr(env
));
3112 for (i
= 0; i
< 32; i
++) {
3114 cpu_fprintf(f
, "GPR%02d:", i
);
3115 cpu_fprintf(f
, " %08x", env
->gpr
[i
]);
3117 cpu_fprintf(f
, "\n");
3119 cpu_fprintf(f
, "CR: 0x");
3120 for (i
= 0; i
< 8; i
++)
3121 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
3122 cpu_fprintf(f
, " [");
3123 for (i
= 0; i
< 8; i
++) {
3125 if (env
->crf
[i
] & 0x08)
3127 else if (env
->crf
[i
] & 0x04)
3129 else if (env
->crf
[i
] & 0x02)
3131 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
3133 cpu_fprintf(f
, " ] ");
3134 cpu_fprintf(f
, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env
),
3135 cpu_ppc_load_tbl(env
));
3136 for (i
= 0; i
< 16; i
++) {
3138 cpu_fprintf(f
, "FPR%02d:", i
);
3139 cpu_fprintf(f
, " %016llx", *((uint64_t *)&env
->fpr
[i
]));
3141 cpu_fprintf(f
, "\n");
3143 cpu_fprintf(f
, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
3144 env
->spr
[SRR0
], env
->spr
[SRR1
], cpu_ppc_load_decr(env
));
3145 cpu_fprintf(f
, "reservation 0x%08x\n", env
->reserve
);
3148 CPUPPCState
*cpu_ppc_init(void)
3154 env
= qemu_mallocz(sizeof(CPUPPCState
));
3157 // env->spr[PVR] = 0; /* Basic PPC */
3158 env
->spr
[PVR
] = 0x00080100; /* G3 CPU */
3159 // env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
3160 // env->spr[PVR] = 0x00070100; /* IBM 750FX */
3162 #if defined (DO_SINGLE_STEP)
3163 /* Single step trace mode */
3166 msr_fp
= 1; /* Allow floating point exceptions */
3167 msr_me
= 1; /* Allow machine check exceptions */
3168 #if defined(CONFIG_USER_ONLY)
3170 cpu_ppc_register(env
, 0x00080000);
3172 env
->nip
= 0xFFFFFFFC;
3174 cpu_single_env
= env
;
3178 int cpu_ppc_register (CPUPPCState
*env
, uint32_t pvr
)
3180 env
->spr
[PVR
] = pvr
;
3181 if (create_ppc_proc(ppc_opcodes
, env
->spr
[PVR
]) < 0)
3183 init_spr_rights(env
->spr
[PVR
]);
3188 void cpu_ppc_close(CPUPPCState
*env
)
3190 /* Should also remove all opcode tables... */
3194 /*****************************************************************************/
3195 int gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
3198 DisasContext ctx
, *ctxp
= &ctx
;
3199 opc_handler_t
**table
, *handler
;
3200 target_ulong pc_start
;
3201 uint16_t *gen_opc_end
;
3205 gen_opc_ptr
= gen_opc_buf
;
3206 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
3207 gen_opparam_ptr
= gen_opparam_buf
;
3210 ctx
.exception
= EXCP_NONE
;
3211 #if defined(CONFIG_USER_ONLY)
3212 ctx
.mem_idx
= msr_le
;
3214 ctx
.supervisor
= 1 - msr_pr
;
3215 ctx
.mem_idx
= ((1 - msr_pr
) << 1) | msr_le
;
3217 ctx
.fpu_enabled
= msr_fp
;
3218 #if defined (DO_SINGLE_STEP)
3219 /* Single step trace mode */
3222 /* Set env in case of segfault during code fetch */
3223 while (ctx
.exception
== EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
3225 j
= gen_opc_ptr
- gen_opc_buf
;
3229 gen_opc_instr_start
[lj
++] = 0;
3230 gen_opc_pc
[lj
] = ctx
.nip
;
3231 gen_opc_instr_start
[lj
] = 1;
3234 #if defined PPC_DEBUG_DISAS
3235 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3236 fprintf(logfile
, "----------------\n");
3237 fprintf(logfile
, "nip=%08x super=%d ir=%d\n",
3238 ctx
.nip
, 1 - msr_pr
, msr_ir
);
3241 ctx
.opcode
= ldl_code(ctx
.nip
);
3243 ctx
.opcode
= ((ctx
.opcode
& 0xFF000000) >> 24) |
3244 ((ctx
.opcode
& 0x00FF0000) >> 8) |
3245 ((ctx
.opcode
& 0x0000FF00) << 8) |
3246 ((ctx
.opcode
& 0x000000FF) << 24);
3248 #if defined PPC_DEBUG_DISAS
3249 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3250 fprintf(logfile
, "translate opcode %08x (%02x %02x %02x) (%s)\n",
3251 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
3252 opc3(ctx
.opcode
), msr_le
? "little" : "big");
3256 table
= ppc_opcodes
;
3257 handler
= table
[opc1(ctx
.opcode
)];
3258 if (is_indirect_opcode(handler
)) {
3259 table
= ind_table(handler
);
3260 handler
= table
[opc2(ctx
.opcode
)];
3261 if (is_indirect_opcode(handler
)) {
3262 table
= ind_table(handler
);
3263 handler
= table
[opc3(ctx
.opcode
)];
3266 /* Is opcode *REALLY* valid ? */
3267 if (handler
->handler
== &gen_invalid
) {
3269 fprintf(logfile
, "invalid/unsupported opcode: "
3270 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3271 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
3272 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, msr_ir
);
3274 printf("invalid/unsupported opcode: "
3275 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3276 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
3277 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, msr_ir
);
3280 if ((ctx
.opcode
& handler
->inval
) != 0) {
3282 fprintf(logfile
, "invalid bits: %08x for opcode: "
3283 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3284 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
3285 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
3286 ctx
.opcode
, ctx
.nip
- 4);
3288 printf("invalid bits: %08x for opcode: "
3289 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3290 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
3291 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
3292 ctx
.opcode
, ctx
.nip
- 4);
3298 (*(handler
->handler
))(&ctx
);
3299 /* Check trace mode exceptions */
3300 if ((msr_be
&& ctx
.exception
== EXCP_BRANCH
) ||
3301 /* Check in single step trace mode
3302 * we need to stop except if:
3303 * - rfi, trap or syscall
3304 * - first instruction of an exception handler
3306 (msr_se
&& (ctx
.nip
< 0x100 ||
3308 (ctx
.nip
& 0xFC) != 0x04) &&
3309 ctx
.exception
!= EXCP_SYSCALL
&& ctx
.exception
!= EXCP_RFI
&&
3310 ctx
.exception
!= EXCP_TRAP
)) {
3311 RET_EXCP(ctxp
, EXCP_TRACE
, 0);
3313 /* if we reach a page boundary, stop generation */
3314 if ((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) {
3315 RET_EXCP(ctxp
, EXCP_BRANCH
, 0);
3318 if (ctx
.exception
== EXCP_NONE
) {
3319 gen_op_b((unsigned long)ctx
.tb
, ctx
.nip
);
3320 } else if (ctx
.exception
!= EXCP_BRANCH
) {
3324 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3325 * do bad business and then qemu crashes !
3329 /* Generate the return instruction */
3331 *gen_opc_ptr
= INDEX_op_end
;
3333 j
= gen_opc_ptr
- gen_opc_buf
;
3336 gen_opc_instr_start
[lj
++] = 0;
3344 tb
->size
= ctx
.nip
- pc_start
;
3347 if (loglevel
& CPU_LOG_TB_CPU
) {
3348 fprintf(logfile
, "---------------- excp: %04x\n", ctx
.exception
);
3349 cpu_dump_state(env
, logfile
, fprintf
, 0);
3351 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3352 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
3353 target_disas(logfile
, pc_start
, ctx
.nip
- pc_start
, 0);
3354 fprintf(logfile
, "\n");
3356 if (loglevel
& CPU_LOG_TB_OP
) {
3357 fprintf(logfile
, "OP:\n");
3358 dump_ops(gen_opc_buf
, gen_opparam_buf
);
3359 fprintf(logfile
, "\n");
3365 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
3367 return gen_intermediate_code_internal(env
, tb
, 0);
3370 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
3372 return gen_intermediate_code_internal(env
, tb
, 1);