target-ppc/cpu.h

   1 /*
   2  *  PPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #include "cpu-defs.h"
  26
  27 #include "config.h"
  28 #include <setjmp.h>
  29
  30 #include "softfloat.h"
  31
  32 #define TARGET_HAS_ICE 1
  33
  34 /* Instruction types */
  35 enum {
  36     PPC_NONE     = 0x0000,
  37     PPC_INTEGER  = 0x0001, /* CPU has integer operations instructions        */
  38     PPC_FLOAT    = 0x0002, /* CPU has floating point operations instructions */
  39     PPC_FLOW     = 0x0004, /* CPU has flow control instructions              */
  40     PPC_MEM      = 0x0008, /* CPU has virtual memory instructions            */
  41     PPC_RES      = 0x0010, /* CPU has ld/st with reservation instructions    */
  42     PPC_CACHE    = 0x0020, /* CPU has cache control instructions             */
  43     PPC_MISC     = 0x0040, /* CPU has spr/msr access instructions            */
  44     PPC_EXTERN   = 0x0080, /* CPU has external control instructions          */
  45     PPC_SEGMENT  = 0x0100, /* CPU has memory segment instructions            */
  46     PPC_CACHE_OPT= 0x0200,
  47     PPC_FLOAT_OPT= 0x0400,
  48     PPC_MEM_OPT  = 0x0800,
  49 };
  50
  51 #define PPC_COMMON  (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |           \
  52                      PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
  53 /* PPC 604 */
  54 #define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
  55                  PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT    \
  56                  PPC_MEM_OPT)
  57 /* PPC 740/745/750/755 (aka G3) has external access instructions */
  58 #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
  59                  PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
  60
  61 typedef struct ppc_tb_t ppc_tb_t;
  62
  63 /* Supervisor mode registers */
  64 /* Machine state register */
  65 #define MSR_POW 18
  66 #define MSR_ILE 16
  67 #define MSR_EE  15
  68 #define MSR_PR  14
  69 #define MSR_FP  13
  70 #define MSR_ME  12
  71 #define MSR_FE0 11
  72 #define MSR_SE  10
  73 #define MSR_BE  9
  74 #define MSR_FE1 8
  75 #define MSR_IP 6
  76 #define MSR_IR 5
  77 #define MSR_DR 4
  78 #define MSR_RI 1
  79 #define MSR_LE 0
  80 #define msr_pow env->msr[MSR_POW]
  81 #define msr_ile env->msr[MSR_ILE]
  82 #define msr_ee  env->msr[MSR_EE]
  83 #define msr_pr  env->msr[MSR_PR]
  84 #define msr_fp  env->msr[MSR_FP]
  85 #define msr_me  env->msr[MSR_ME]
  86 #define msr_fe0 env->msr[MSR_FE0]
  87 #define msr_se  env->msr[MSR_SE]
  88 #define msr_be  env->msr[MSR_BE]
  89 #define msr_fe1 env->msr[MSR_FE1]
  90 #define msr_ip  env->msr[MSR_IP]
  91 #define msr_ir  env->msr[MSR_IR]
  92 #define msr_dr  env->msr[MSR_DR]
  93 #define msr_ri  env->msr[MSR_RI]
  94 #define msr_le  env->msr[MSR_LE]
  95
  96 /* Segment registers */
  97 typedef struct CPUPPCState {
  98     /* general purpose registers */
  99     uint32_t gpr[32];
 100     /* floating point registers */
 101     float64 fpr[32];
 102     /* segment registers */
 103     uint32_t sdr1;
 104     uint32_t sr[16];
 105     /* XER */
 106     uint8_t xer[4];
 107     /* Reservation address */
 108     uint32_t reserve;
 109     /* machine state register */
 110     uint8_t msr[32];
 111     /* condition register */
 112     uint8_t crf[8];
 113     /* floating point status and control register */
 114     uint8_t fpscr[8];
 115     uint32_t nip;
 116     /* special purpose registers */
 117     uint32_t lr;
 118     uint32_t ctr;
 119     /* BATs */
 120     uint32_t DBAT[2][8];
 121     uint32_t IBAT[2][8];
 122     /* all others */
 123     uint32_t spr[1024];
 124     /* qemu dedicated */
 125      /* temporary float registers */
 126     float64 ft0;
 127     float64 ft1;
 128     float64 ft2;
 129     float_status fp_status;
 130
 131     int interrupt_request;
 132     jmp_buf jmp_env;
 133     int exception_index;
 134     int error_code;
 135     int access_type; /* when a memory exception occurs, the access
 136                         type is stored here */
 137     int user_mode_only; /* user mode only simulation */
 138     struct TranslationBlock *current_tb; /* currently executing TB */
 139     /* soft mmu support */
 140     /* in order to avoid passing too many arguments to the memory
 141        write helpers, we store some rarely used information in the CPU
 142        context) */
 143     unsigned long mem_write_pc; /* host pc at which the memory was
 144                                    written */
 145     unsigned long mem_write_vaddr; /* target virtual addr at which the
 146                                       memory was written */
 147     /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
 148     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 149     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 150
 151     /* ice debug support */
 152     uint32_t breakpoints[MAX_BREAKPOINTS];
 153     int nb_breakpoints;
 154     int singlestep_enabled; /* XXX: should use CPU single step mode instead */
 155
 156     /* Time base and decrementer */
 157     ppc_tb_t *tb_env;
 158
 159     /* Power management */
 160     int power_mode;
 161
 162     /* user data */
 163     void *opaque;
 164 } CPUPPCState;
 165
 166 CPUPPCState *cpu_ppc_init(void);
 167 int cpu_ppc_exec(CPUPPCState *s);
 168 void cpu_ppc_close(CPUPPCState *s);
 169 /* you can call this signal handler from your SIGBUS and SIGSEGV
 170    signal handlers to inform the virtual CPU of exceptions. non zero
 171    is returned if the signal was handled by the virtual CPU.  */
 172 struct siginfo;
 173 int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
 174                            void *puc);
 175
 176 void do_interrupt (CPUPPCState *env);
 177 void cpu_loop_exit(void);
 178
 179 void dump_stack (CPUPPCState *env);
 180
 181 uint32_t _load_xer (CPUPPCState *env);
 182 void _store_xer (CPUPPCState *env, uint32_t value);
 183 uint32_t _load_msr (CPUPPCState *env);
 184 void _store_msr (CPUPPCState *env, uint32_t value);
 185
 186 int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
 187
 188 /* Time-base and decrementer management */
 189 #ifndef NO_CPU_IO_DEFS
 190 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
 191 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 192 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
 193 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
 194 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
 195 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
 196 #endif
 197
 198 #define TARGET_PAGE_BITS 12
 199 #include "cpu-all.h"
 200
 201 #define ugpr(n) (env->gpr[n])
 202 #define fprd(n) (env->fpr[n])
 203 #define fprs(n) ((float)env->fpr[n])
 204 #define fpru(n) ((uint32_t)env->fpr[n])
 205 #define fpri(n) ((int32_t)env->fpr[n])
 206
 207 #define SPR_ENCODE(sprn)                               \
 208 (((sprn) >> 5) | (((sprn) & 0x1F) << 5))
 209
 210 /* User mode SPR */
 211 #define spr(n) env->spr[n]
 212 #define XER_SO 31
 213 #define XER_OV 30
 214 #define XER_CA 29
 215 #define XER_BC 0
 216 #define xer_so env->xer[3]
 217 #define xer_ov env->xer[2]
 218 #define xer_ca env->xer[1]
 219 #define xer_bc env->xer[0]
 220
 221 #define MQ     SPR_ENCODE(0)
 222 #define XER    SPR_ENCODE(1)
 223 #define RTCUR  SPR_ENCODE(4)
 224 #define RTCLR  SPR_ENCODE(5)
 225 #define LR     SPR_ENCODE(8)
 226 #define CTR    SPR_ENCODE(9)
 227 /* VEA mode SPR */
 228 #define V_TBL  SPR_ENCODE(268)
 229 #define V_TBU  SPR_ENCODE(269)
 230 /* supervisor mode SPR */
 231 #define DSISR  SPR_ENCODE(18)
 232 #define DAR    SPR_ENCODE(19)
 233 #define RTCUW  SPR_ENCODE(20)
 234 #define RTCLW  SPR_ENCODE(21)
 235 #define DECR   SPR_ENCODE(22)
 236 #define SDR1   SPR_ENCODE(25)
 237 #define SRR0   SPR_ENCODE(26)
 238 #define SRR1   SPR_ENCODE(27)
 239 #define SPRG0  SPR_ENCODE(272)
 240 #define SPRG1  SPR_ENCODE(273)
 241 #define SPRG2  SPR_ENCODE(274)
 242 #define SPRG3  SPR_ENCODE(275)
 243 #define SPRG4  SPR_ENCODE(276)
 244 #define SPRG5  SPR_ENCODE(277)
 245 #define SPRG6  SPR_ENCODE(278)
 246 #define SPRG7  SPR_ENCODE(279)
 247 #define ASR    SPR_ENCODE(280)
 248 #define EAR    SPR_ENCODE(282)
 249 #define O_TBL  SPR_ENCODE(284)
 250 #define O_TBU  SPR_ENCODE(285)
 251 #define PVR    SPR_ENCODE(287)
 252 #define IBAT0U SPR_ENCODE(528)
 253 #define IBAT0L SPR_ENCODE(529)
 254 #define IBAT1U SPR_ENCODE(530)
 255 #define IBAT1L SPR_ENCODE(531)
 256 #define IBAT2U SPR_ENCODE(532)
 257 #define IBAT2L SPR_ENCODE(533)
 258 #define IBAT3U SPR_ENCODE(534)
 259 #define IBAT3L SPR_ENCODE(535)
 260 #define DBAT0U SPR_ENCODE(536)
 261 #define DBAT0L SPR_ENCODE(537)
 262 #define DBAT1U SPR_ENCODE(538)
 263 #define DBAT1L SPR_ENCODE(539)
 264 #define DBAT2U SPR_ENCODE(540)
 265 #define DBAT2L SPR_ENCODE(541)
 266 #define DBAT3U SPR_ENCODE(542)
 267 #define DBAT3L SPR_ENCODE(543)
 268 #define IBAT4U SPR_ENCODE(560)
 269 #define IBAT4L SPR_ENCODE(561)
 270 #define IBAT5U SPR_ENCODE(562)
 271 #define IBAT5L SPR_ENCODE(563)
 272 #define IBAT6U SPR_ENCODE(564)
 273 #define IBAT6L SPR_ENCODE(565)
 274 #define IBAT7U SPR_ENCODE(566)
 275 #define IBAT7L SPR_ENCODE(567)
 276 #define DBAT4U SPR_ENCODE(568)
 277 #define DBAT4L SPR_ENCODE(569)
 278 #define DBAT5U SPR_ENCODE(570)
 279 #define DBAT5L SPR_ENCODE(571)
 280 #define DBAT6U SPR_ENCODE(572)
 281 #define DBAT6L SPR_ENCODE(573)
 282 #define DBAT7U SPR_ENCODE(574)
 283 #define DBAT7L SPR_ENCODE(575)
 284 #define UMMCR0 SPR_ENCODE(936)
 285 #define UPMC1  SPR_ENCODE(937)
 286 #define UPMC2  SPR_ENCODE(938)
 287 #define USIA   SPR_ENCODE(939)
 288 #define UMMCR1 SPR_ENCODE(940)
 289 #define UPMC3  SPR_ENCODE(941)
 290 #define UPMC4  SPR_ENCODE(942)
 291 #define MMCR0  SPR_ENCODE(952)
 292 #define PMC1   SPR_ENCODE(953)
 293 #define PMC2   SPR_ENCODE(954)
 294 #define SIA    SPR_ENCODE(955)
 295 #define MMCR1  SPR_ENCODE(956)
 296 #define PMC3   SPR_ENCODE(957)
 297 #define PMC4   SPR_ENCODE(958)
 298 #define SDA    SPR_ENCODE(959)
 299 #define DMISS  SPR_ENCODE(976)
 300 #define DCMP   SPR_ENCODE(977)
 301 #define DHASH1 SPR_ENCODE(978)
 302 #define DHASH2 SPR_ENCODE(979)
 303 #define IMISS  SPR_ENCODE(980)
 304 #define ICMP   SPR_ENCODE(981)
 305 #define RPA    SPR_ENCODE(982)
 306 #define TCR    SPR_ENCODE(984)
 307 #define IBR    SPR_ENCODE(986)
 308 #define ESASRR SPR_ENCODE(987)
 309 #define SEBR   SPR_ENCODE(990)
 310 #define SER    SPR_ENCODE(991)
 311 #define HID0   SPR_ENCODE(1008)
 312 #define HID1   SPR_ENCODE(1009)
 313 #define IABR   SPR_ENCODE(1010)
 314 #define HID2   SPR_ENCODE(1011)
 315 #define DABR   SPR_ENCODE(1013)
 316 #define L2PM   SPR_ENCODE(1016)
 317 #define L2CR   SPR_ENCODE(1017)
 318 #define ICTC   SPR_ENCODE(1019)
 319 #define THRM1  SPR_ENCODE(1020)
 320 #define THRM2  SPR_ENCODE(1021)
 321 #define THRM3  SPR_ENCODE(1022)
 322 #define SP     SPR_ENCODE(1021)
 323 #define SPR_LP SPR_ENCODE(1022)
 324 #define DABR_MASK 0xFFFFFFF8
 325 #define FPECR  SPR_ENCODE(1022)
 326 #define PIR    SPR_ENCODE(1023)
 327
 328 /* Memory access type :
 329  * may be needed for precise access rights control and precise exceptions.
 330  */
 331 enum {
 332     /* 1 bit to define user level / supervisor access */
 333     ACCESS_USER  = 0x00,
 334     ACCESS_SUPER = 0x01,
 335     /* Type of instruction that generated the access */
 336     ACCESS_CODE  = 0x10, /* Code fetch access                */
 337     ACCESS_INT   = 0x20, /* Integer load/store access        */
 338     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 339     ACCESS_RES   = 0x40, /* load/store with reservation      */
 340     ACCESS_EXT   = 0x50, /* external access                  */
 341     ACCESS_CACHE = 0x60, /* Cache manipulation               */
 342 };
 343
 344 /*****************************************************************************/
 345 /* Exceptions */
 346 enum {
 347     EXCP_NONE          = -1,
 348     /* PPC hardware exceptions : exception vector / 0x100 */
 349     EXCP_RESET         = 0x01, /* System reset                     */
 350     EXCP_MACHINE_CHECK = 0x02, /* Machine check exception          */
 351     EXCP_DSI           = 0x03, /* Impossible memory access         */
 352     EXCP_ISI           = 0x04, /* Impossible instruction fetch     */
 353     EXCP_EXTERNAL      = 0x05, /* External interruption            */
 354     EXCP_ALIGN         = 0x06, /* Alignment exception              */
 355     EXCP_PROGRAM       = 0x07, /* Program exception                */
 356     EXCP_NO_FP         = 0x08, /* No floating point                */
 357     EXCP_DECR          = 0x09, /* Decrementer exception            */
 358     EXCP_RESA          = 0x0A, /* Implementation specific          */
 359     EXCP_RESB          = 0x0B, /* Implementation specific          */
 360     EXCP_SYSCALL       = 0x0C, /* System call                      */
 361     EXCP_TRACE         = 0x0D, /* Trace exception (optional)       */
 362     EXCP_FP_ASSIST     = 0x0E, /* Floating-point assist (optional) */
 363     /* MPC740/745/750 & IBM 750 */
 364     EXCP_PERF          = 0x0F,  /* Performance monitor              */
 365     EXCP_IABR          = 0x13,  /* Instruction address breakpoint   */
 366     EXCP_SMI           = 0x14,  /* System management interrupt      */
 367     EXCP_THRM          = 0x15,  /* Thermal management interrupt     */
 368     /* MPC755 */
 369     EXCP_TLBMISS       = 0x10,  /* Instruction TLB miss             */
 370     EXCP_TLBMISS_DL    = 0x11,  /* Data TLB miss for load           */
 371     EXCP_TLBMISS_DS    = 0x12,  /* Data TLB miss for store          */
 372     EXCP_PPC_MAX       = 0x16,
 373     /* Qemu exception */
 374     EXCP_OFCALL        = 0x20,  /* Call open-firmware emulator      */
 375     EXCP_RTASCALL      = 0x21,  /* Call RTAS emulator               */
 376     /* Special cases where we want to stop translation */
 377     EXCP_MTMSR         = 0x104, /* mtmsr instruction:               */
 378                                 /* may change privilege level       */
 379     EXCP_BRANCH        = 0x108, /* branch instruction               */
 380     EXCP_RFI           = 0x10C, /* return from interrupt            */
 381     EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
 382 };
 383 /* Error codes */
 384 enum {
 385     /* Exception subtypes for EXCP_DSI                              */
 386     EXCP_DSI_TRANSLATE = 0x01,  /* Data address can't be translated */
 387     EXCP_DSI_NOTSUP    = 0x02,  /* Access type not supported        */
 388     EXCP_DSI_PROT      = 0x03,  /* Memory protection violation      */
 389     EXCP_DSI_EXTERNAL  = 0x04,  /* External access disabled         */
 390     EXCP_DSI_DABR      = 0x05,  /* Data address breakpoint          */
 391     /* flags for EXCP_DSI */
 392     EXCP_DSI_DIRECT    = 0x10,
 393     EXCP_DSI_STORE     = 0x20,
 394     EXCP_DSI_ECXW      = 0x40,
 395     /* Exception subtypes for EXCP_ISI                              */
 396     EXCP_ISI_TRANSLATE = 0x01,  /* Code address can't be translated */
 397     EXCP_ISI_NOEXEC    = 0x02,  /* Try to fetch from a data segment */
 398     EXCP_ISI_GUARD     = 0x03,  /* Fetch from guarded memory        */
 399     EXCP_ISI_PROT      = 0x04,  /* Memory protection violation      */
 400     EXCP_ISI_DIRECT    = 0x05,  /* Trying to fetch from             *
 401                                  * a direct store segment           */
 402     /* Exception subtypes for EXCP_ALIGN                            */
 403     EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
 404     EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
 405     EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
 406     EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
 407     EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
 408     EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
 409     /* Exception subtypes for EXCP_PROGRAM                          */
 410     /* FP exceptions */
 411     EXCP_FP            = 0x10,
 412     EXCP_FP_OX         = 0x01,  /* FP overflow                      */
 413     EXCP_FP_UX         = 0x02,  /* FP underflow                     */
 414     EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
 415     EXCP_FP_XX         = 0x04,  /* FP inexact                       */
 416     EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
 417     EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
 418     EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
 419     EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
 420     EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
 421     EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
 422     EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
 423     EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
 424     EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
 425     /* Invalid instruction */
 426     EXCP_INVAL         = 0x20,
 427     EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
 428     EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
 429     EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
 430     EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
 431     /* Privileged instruction */
 432     EXCP_PRIV          = 0x30,
 433     EXCP_PRIV_OPC      = 0x01,
 434     EXCP_PRIV_REG      = 0x02,
 435     /* Trap */
 436     EXCP_TRAP          = 0x40,
 437 };
 438
 439 /*****************************************************************************/
 440
 441 #endif /* !defined (__CPU_PPC_H__) */