hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug PIC */
  27 //#define DEBUG_PIC
  28
  29 //#define DEBUG_IRQ_LATENCY
  30 //#define DEBUG_IRQ_COUNT
  31
  32 typedef struct PicState {
  33     uint8_t last_irr; /* edge detection */
  34     uint8_t irr; /* interrupt request register */
  35     uint8_t imr; /* interrupt mask register */
  36     uint8_t isr; /* interrupt service register */
  37     uint8_t priority_add; /* highest irq priority */
  38     uint8_t irq_base;
  39     uint8_t read_reg_select;
  40     uint8_t poll;
  41     uint8_t special_mask;
  42     uint8_t init_state;
  43     uint8_t auto_eoi;
  44     uint8_t rotate_on_auto_eoi;
  45     uint8_t special_fully_nested_mode;
  46     uint8_t init4; /* true if 4 byte init */
  47     uint8_t elcr; /* PIIX edge/trigger selection*/
  48     uint8_t elcr_mask;
  49 } PicState;
  50
  51 /* 0 is master pic, 1 is slave pic */
  52 static PicState pics[2];
  53
  54 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  55 static int irq_level[16];
  56 #endif
  57 #ifdef DEBUG_IRQ_COUNT
  58 static uint64_t irq_count[16];
  59 #endif
  60
  61 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  62 static inline void pic_set_irq1(PicState *s, int irq, int level)
  63 {
  64     int mask;
  65     mask = 1 << irq;
  66     if (s->elcr & mask) {
  67         /* level triggered */
  68         if (level) {
  69             s->irr |= mask;
  70             s->last_irr |= mask;
  71         } else {
  72             s->irr &= ~mask;
  73             s->last_irr &= ~mask;
  74         }
  75     } else {
  76         /* edge triggered */
  77         if (level) {
  78             if ((s->last_irr & mask) == 0)
  79                 s->irr |= mask;
  80             s->last_irr |= mask;
  81         } else {
  82             s->last_irr &= ~mask;
  83         }
  84     }
  85 }
  86
  87 /* return the highest priority found in mask (highest = smallest
  88    number). Return 8 if no irq */
  89 static inline int get_priority(PicState *s, int mask)
  90 {
  91     int priority;
  92     if (mask == 0)
  93         return 8;
  94     priority = 0;
  95     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  96         priority++;
  97     return priority;
  98 }
  99
 100 /* return the pic wanted interrupt. return -1 if none */
 101 static int pic_get_irq(PicState *s)
 102 {
 103     int mask, cur_priority, priority;
 104
 105     mask = s->irr & ~s->imr;
 106     priority = get_priority(s, mask);
 107     if (priority == 8)
 108         return -1;
 109     /* compute current priority. If special fully nested mode on the
 110        master, the IRQ coming from the slave is not taken into account
 111        for the priority computation. */
 112     mask = s->isr;
 113     if (s->special_fully_nested_mode && s == &pics[0])
 114         mask &= ~(1 << 2);
 115     cur_priority = get_priority(s, mask);
 116     if (priority < cur_priority) {
 117         /* higher priority found: an irq should be generated */
 118         return (priority + s->priority_add) & 7;
 119     } else {
 120         return -1;
 121     }
 122 }
 123
 124 /* raise irq to CPU if necessary. must be called every time the active
 125    irq may change */
 126 static void pic_update_irq(void)
 127 {
 128     int irq2, irq;
 129
 130     /* first look at slave pic */
 131     irq2 = pic_get_irq(&pics[1]);
 132     if (irq2 >= 0) {
 133         /* if irq request by slave pic, signal master PIC */
 134         pic_set_irq1(&pics[0], 2, 1);
 135         pic_set_irq1(&pics[0], 2, 0);
 136     }
 137     /* look at requested irq */
 138     irq = pic_get_irq(&pics[0]);
 139     if (irq >= 0) {
 140 #if defined(DEBUG_PIC)
 141         {
 142             int i;
 143             for(i = 0; i < 2; i++) {
 144                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 145                        i, pics[i].imr, pics[i].irr, pics[i].priority_add);
 146
 147             }
 148         }
 149         printf("pic: cpu_interrupt\n");
 150 #endif
 151         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 152     }
 153 }
 154
 155 #ifdef DEBUG_IRQ_LATENCY
 156 int64_t irq_time[16];
 157 #endif
 158
 159 void pic_set_irq(int irq, int level)
 160 {
 161 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 162     if (level != irq_level[irq]) {
 163 #if defined(DEBUG_PIC)
 164         printf("pic_set_irq: irq=%d level=%d\n", irq, level);
 165 #endif
 166         irq_level[irq] = level;
 167 #ifdef DEBUG_IRQ_COUNT
 168         if (level == 1)
 169             irq_count[irq]++;
 170 #endif
 171     }
 172 #endif
 173 #ifdef DEBUG_IRQ_LATENCY
 174     if (level) {
 175         irq_time[irq] = qemu_get_clock(vm_clock);
 176     }
 177 #endif
 178     pic_set_irq1(&pics[irq >> 3], irq & 7, level);
 179     pic_update_irq();
 180 }
 181
 182 /* acknowledge interrupt 'irq' */
 183 static inline void pic_intack(PicState *s, int irq)
 184 {
 185     if (s->auto_eoi) {
 186         if (s->rotate_on_auto_eoi)
 187             s->priority_add = (irq + 1) & 7;
 188     } else {
 189         s->isr |= (1 << irq);
 190     }
 191     /* We don't clear a level sensitive interrupt here */
 192     if (!(s->elcr & (1 << irq)))
 193         s->irr &= ~(1 << irq);
 194 }
 195
 196 int cpu_get_pic_interrupt(CPUState *env)
 197 {
 198     int irq, irq2, intno;
 199
 200 #ifdef TARGET_X86_64
 201     intno = apic_get_interrupt(env);
 202     if (intno >= 0) {
 203         /* set irq request if a PIC irq is still pending */
 204         /* XXX: improve that */
 205         pic_update_irq();
 206         return intno;
 207     }
 208 #endif
 209     /* read the irq from the PIC */
 210
 211     irq = pic_get_irq(&pics[0]);
 212     if (irq >= 0) {
 213         pic_intack(&pics[0], irq);
 214         if (irq == 2) {
 215             irq2 = pic_get_irq(&pics[1]);
 216             if (irq2 >= 0) {
 217                 pic_intack(&pics[1], irq2);
 218             } else {
 219                 /* spurious IRQ on slave controller */
 220                 irq2 = 7;
 221             }
 222             intno = pics[1].irq_base + irq2;
 223             irq = irq2 + 8;
 224         } else {
 225             intno = pics[0].irq_base + irq;
 226         }
 227     } else {
 228         /* spurious IRQ on host controller */
 229         irq = 7;
 230         intno = pics[0].irq_base + irq;
 231     }
 232     pic_update_irq();
 233
 234 #ifdef DEBUG_IRQ_LATENCY
 235     printf("IRQ%d latency=%0.3fus\n",
 236            irq,
 237            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 238 #endif
 239 #if defined(DEBUG_PIC)
 240     printf("pic_interrupt: irq=%d\n", irq);
 241 #endif
 242     return intno;
 243 }
 244
 245 static void pic_reset(void *opaque)
 246 {
 247     PicState *s = opaque;
 248     int tmp;
 249
 250     tmp = s->elcr_mask;
 251     memset(s, 0, sizeof(PicState));
 252     s->elcr_mask = tmp;
 253 }
 254
 255 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 256 {
 257     PicState *s = opaque;
 258     int priority, cmd, irq;
 259
 260 #ifdef DEBUG_PIC
 261     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 262 #endif
 263     addr &= 1;
 264     if (addr == 0) {
 265         if (val & 0x10) {
 266             /* init */
 267             pic_reset(s);
 268             /* deassert a pending interrupt */
 269             cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 270
 271             s->init_state = 1;
 272             s->init4 = val & 1;
 273             if (val & 0x02)
 274                 hw_error("single mode not supported");
 275             if (val & 0x08)
 276                 hw_error("level sensitive irq not supported");
 277         } else if (val & 0x08) {
 278             if (val & 0x04)
 279                 s->poll = 1;
 280             if (val & 0x02)
 281                 s->read_reg_select = val & 1;
 282             if (val & 0x40)
 283                 s->special_mask = (val >> 5) & 1;
 284         } else {
 285             cmd = val >> 5;
 286             switch(cmd) {
 287             case 0:
 288             case 4:
 289                 s->rotate_on_auto_eoi = cmd >> 2;
 290                 break;
 291             case 1: /* end of interrupt */
 292             case 5:
 293                 priority = get_priority(s, s->isr);
 294                 if (priority != 8) {
 295                     irq = (priority + s->priority_add) & 7;
 296                     s->isr &= ~(1 << irq);
 297                     if (cmd == 5)
 298                         s->priority_add = (irq + 1) & 7;
 299                     pic_update_irq();
 300                 }
 301                 break;
 302             case 3:
 303                 irq = val & 7;
 304                 s->isr &= ~(1 << irq);
 305                 pic_update_irq();
 306                 break;
 307             case 6:
 308                 s->priority_add = (val + 1) & 7;
 309                 pic_update_irq();
 310                 break;
 311             case 7:
 312                 irq = val & 7;
 313                 s->isr &= ~(1 << irq);
 314                 s->priority_add = (irq + 1) & 7;
 315                 pic_update_irq();
 316                 break;
 317             default:
 318                 /* no operation */
 319                 break;
 320             }
 321         }
 322     } else {
 323         switch(s->init_state) {
 324         case 0:
 325             /* normal mode */
 326             s->imr = val;
 327             pic_update_irq();
 328             break;
 329         case 1:
 330             s->irq_base = val & 0xf8;
 331             s->init_state = 2;
 332             break;
 333         case 2:
 334             if (s->init4) {
 335                 s->init_state = 3;
 336             } else {
 337                 s->init_state = 0;
 338             }
 339             break;
 340         case 3:
 341             s->special_fully_nested_mode = (val >> 4) & 1;
 342             s->auto_eoi = (val >> 1) & 1;
 343             s->init_state = 0;
 344             break;
 345         }
 346     }
 347 }
 348
 349 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 350 {
 351     int ret;
 352
 353     ret = pic_get_irq(s);
 354     if (ret >= 0) {
 355         if (addr1 >> 7) {
 356             pics[0].isr &= ~(1 << 2);
 357             pics[0].irr &= ~(1 << 2);
 358         }
 359         s->irr &= ~(1 << ret);
 360         s->isr &= ~(1 << ret);
 361         if (addr1 >> 7 || ret != 2)
 362             pic_update_irq();
 363     } else {
 364         ret = 0x07;
 365         pic_update_irq();
 366     }
 367
 368     return ret;
 369 }
 370
 371 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 372 {
 373     PicState *s = opaque;
 374     unsigned int addr;
 375     int ret;
 376
 377     addr = addr1;
 378     addr &= 1;
 379     if (s->poll) {
 380         ret = pic_poll_read(s, addr1);
 381         s->poll = 0;
 382     } else {
 383         if (addr == 0) {
 384             if (s->read_reg_select)
 385                 ret = s->isr;
 386             else
 387                 ret = s->irr;
 388         } else {
 389             ret = s->imr;
 390         }
 391     }
 392 #ifdef DEBUG_PIC
 393     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 394 #endif
 395     return ret;
 396 }
 397
 398 /* memory mapped interrupt status */
 399 uint32_t pic_intack_read(CPUState *env)
 400 {
 401     int ret;
 402
 403     ret = pic_poll_read(&pics[0], 0x00);
 404     if (ret == 2)
 405         ret = pic_poll_read(&pics[1], 0x80) + 8;
 406     /* Prepare for ISR read */
 407     pics[0].read_reg_select = 1;
 408
 409     return ret;
 410 }
 411
 412 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 413 {
 414     PicState *s = opaque;
 415     s->elcr = val & s->elcr_mask;
 416 }
 417
 418 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 419 {
 420     PicState *s = opaque;
 421     return s->elcr;
 422 }
 423
 424 static void pic_save(QEMUFile *f, void *opaque)
 425 {
 426     PicState *s = opaque;
 427
 428     qemu_put_8s(f, &s->last_irr);
 429     qemu_put_8s(f, &s->irr);
 430     qemu_put_8s(f, &s->imr);
 431     qemu_put_8s(f, &s->isr);
 432     qemu_put_8s(f, &s->priority_add);
 433     qemu_put_8s(f, &s->irq_base);
 434     qemu_put_8s(f, &s->read_reg_select);
 435     qemu_put_8s(f, &s->poll);
 436     qemu_put_8s(f, &s->special_mask);
 437     qemu_put_8s(f, &s->init_state);
 438     qemu_put_8s(f, &s->auto_eoi);
 439     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 440     qemu_put_8s(f, &s->special_fully_nested_mode);
 441     qemu_put_8s(f, &s->init4);
 442     qemu_put_8s(f, &s->elcr);
 443 }
 444
 445 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 446 {
 447     PicState *s = opaque;
 448
 449     if (version_id != 1)
 450         return -EINVAL;
 451
 452     qemu_get_8s(f, &s->last_irr);
 453     qemu_get_8s(f, &s->irr);
 454     qemu_get_8s(f, &s->imr);
 455     qemu_get_8s(f, &s->isr);
 456     qemu_get_8s(f, &s->priority_add);
 457     qemu_get_8s(f, &s->irq_base);
 458     qemu_get_8s(f, &s->read_reg_select);
 459     qemu_get_8s(f, &s->poll);
 460     qemu_get_8s(f, &s->special_mask);
 461     qemu_get_8s(f, &s->init_state);
 462     qemu_get_8s(f, &s->auto_eoi);
 463     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 464     qemu_get_8s(f, &s->special_fully_nested_mode);
 465     qemu_get_8s(f, &s->init4);
 466     qemu_get_8s(f, &s->elcr);
 467     return 0;
 468 }
 469
 470 /* XXX: add generic master/slave system */
 471 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 472 {
 473     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 474     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 475     if (elcr_addr >= 0) {
 476         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 477         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 478     }
 479     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 480     qemu_register_reset(pic_reset, s);
 481 }
 482
 483 void pic_info(void)
 484 {
 485     int i;
 486     PicState *s;
 487
 488     for(i=0;i<2;i++) {
 489         s = &pics[i];
 490         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 491                     i, s->irr, s->imr, s->isr, s->priority_add,
 492                     s->irq_base, s->read_reg_select, s->elcr,
 493                     s->special_fully_nested_mode);
 494     }
 495 }
 496
 497 void irq_info(void)
 498 {
 499 #ifndef DEBUG_IRQ_COUNT
 500     term_printf("irq statistic code not compiled.\n");
 501 #else
 502     int i;
 503     int64_t count;
 504
 505     term_printf("IRQ statistics:\n");
 506     for (i = 0; i < 16; i++) {
 507         count = irq_count[i];
 508         if (count > 0)
 509             term_printf("%2d: %lld\n", i, count);
 510     }
 511 #endif
 512 }
 513
 514 void pic_init(void)
 515 {
 516     pic_init1(0x20, 0x4d0, &pics[0]);
 517     pic_init1(0xa0, 0x4d1, &pics[1]);
 518     pics[0].elcr_mask = 0xf8;
 519     pics[1].elcr_mask = 0xde;
 520 }
 521