2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define MIPS_DEBUG_DISAS
34 //#define MIPS_DEBUG_SIGN_EXTENSIONS
35 //#define MIPS_SINGLE_STEP
37 #ifdef USE_DIRECT_JUMP
40 #define TBPARAM(x) (long)(x)
44 #define DEF(s, n, copy_size) INDEX_op_ ## s,
50 static uint16_t *gen_opc_ptr
;
51 static uint32_t *gen_opparam_ptr
;
55 /* MIPS major opcodes */
56 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
59 /* indirect opcode tables */
60 OPC_SPECIAL
= (0x00 << 26),
61 OPC_REGIMM
= (0x01 << 26),
62 OPC_CP0
= (0x10 << 26),
63 OPC_CP1
= (0x11 << 26),
64 OPC_CP2
= (0x12 << 26),
65 OPC_CP3
= (0x13 << 26),
66 OPC_SPECIAL2
= (0x1C << 26),
67 OPC_SPECIAL3
= (0x1F << 26),
68 /* arithmetic with immediate */
69 OPC_ADDI
= (0x08 << 26),
70 OPC_ADDIU
= (0x09 << 26),
71 OPC_SLTI
= (0x0A << 26),
72 OPC_SLTIU
= (0x0B << 26),
73 OPC_ANDI
= (0x0C << 26),
74 OPC_ORI
= (0x0D << 26),
75 OPC_XORI
= (0x0E << 26),
76 OPC_LUI
= (0x0F << 26),
77 OPC_DADDI
= (0x18 << 26),
78 OPC_DADDIU
= (0x19 << 26),
79 /* Jump and branches */
81 OPC_JAL
= (0x03 << 26),
82 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
83 OPC_BEQL
= (0x14 << 26),
84 OPC_BNE
= (0x05 << 26),
85 OPC_BNEL
= (0x15 << 26),
86 OPC_BLEZ
= (0x06 << 26),
87 OPC_BLEZL
= (0x16 << 26),
88 OPC_BGTZ
= (0x07 << 26),
89 OPC_BGTZL
= (0x17 << 26),
90 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
92 OPC_LDL
= (0x1A << 26),
93 OPC_LDR
= (0x1B << 26),
94 OPC_LB
= (0x20 << 26),
95 OPC_LH
= (0x21 << 26),
96 OPC_LWL
= (0x22 << 26),
97 OPC_LW
= (0x23 << 26),
98 OPC_LBU
= (0x24 << 26),
99 OPC_LHU
= (0x25 << 26),
100 OPC_LWR
= (0x26 << 26),
101 OPC_LWU
= (0x27 << 26),
102 OPC_SB
= (0x28 << 26),
103 OPC_SH
= (0x29 << 26),
104 OPC_SWL
= (0x2A << 26),
105 OPC_SW
= (0x2B << 26),
106 OPC_SDL
= (0x2C << 26),
107 OPC_SDR
= (0x2D << 26),
108 OPC_SWR
= (0x2E << 26),
109 OPC_LL
= (0x30 << 26),
110 OPC_LLD
= (0x34 << 26),
111 OPC_LD
= (0x37 << 26),
112 OPC_SC
= (0x38 << 26),
113 OPC_SCD
= (0x3C << 26),
114 OPC_SD
= (0x3F << 26),
115 /* Floating point load/store */
116 OPC_LWC1
= (0x31 << 26),
117 OPC_LWC2
= (0x32 << 26),
118 OPC_LDC1
= (0x35 << 26),
119 OPC_LDC2
= (0x36 << 26),
120 OPC_SWC1
= (0x39 << 26),
121 OPC_SWC2
= (0x3A << 26),
122 OPC_SDC1
= (0x3D << 26),
123 OPC_SDC2
= (0x3E << 26),
124 /* MDMX ASE specific */
125 OPC_MDMX
= (0x1E << 26),
126 /* Cache and prefetch */
127 OPC_CACHE
= (0x2F << 26),
128 OPC_PREF
= (0x33 << 26),
129 /* Reserved major opcode */
130 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
133 /* MIPS special opcodes */
134 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
138 OPC_SLL
= 0x00 | OPC_SPECIAL
,
139 /* NOP is SLL r0, r0, 0 */
140 /* SSNOP is SLL r0, r0, 1 */
141 /* EHB is SLL r0, r0, 3 */
142 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
143 OPC_SRA
= 0x03 | OPC_SPECIAL
,
144 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
145 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
146 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
147 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
148 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
149 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
150 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
151 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
152 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
153 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
154 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
155 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
156 /* Multiplication / division */
157 OPC_MULT
= 0x18 | OPC_SPECIAL
,
158 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
159 OPC_DIV
= 0x1A | OPC_SPECIAL
,
160 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
161 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
162 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
163 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
164 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
165 /* 2 registers arithmetic / logic */
166 OPC_ADD
= 0x20 | OPC_SPECIAL
,
167 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
168 OPC_SUB
= 0x22 | OPC_SPECIAL
,
169 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
170 OPC_AND
= 0x24 | OPC_SPECIAL
,
171 OPC_OR
= 0x25 | OPC_SPECIAL
,
172 OPC_XOR
= 0x26 | OPC_SPECIAL
,
173 OPC_NOR
= 0x27 | OPC_SPECIAL
,
174 OPC_SLT
= 0x2A | OPC_SPECIAL
,
175 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
176 OPC_DADD
= 0x2C | OPC_SPECIAL
,
177 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
178 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
179 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
181 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
182 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
184 OPC_TGE
= 0x30 | OPC_SPECIAL
,
185 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
186 OPC_TLT
= 0x32 | OPC_SPECIAL
,
187 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
188 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
189 OPC_TNE
= 0x36 | OPC_SPECIAL
,
190 /* HI / LO registers load & stores */
191 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
192 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
193 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
194 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
195 /* Conditional moves */
196 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
197 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
199 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
202 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
203 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
204 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
205 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
206 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
208 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
209 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
210 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
211 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
212 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
213 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
214 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
217 /* REGIMM (rt field) opcodes */
218 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
221 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
222 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
223 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
224 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
225 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
226 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
227 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
228 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
229 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
230 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
231 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
232 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
233 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
234 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
235 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
238 /* Special2 opcodes */
239 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
242 /* Multiply & xxx operations */
243 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
244 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
245 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
246 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
247 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
249 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
250 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
251 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
252 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
254 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
257 /* Special3 opcodes */
258 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
261 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
262 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
263 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
264 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
265 OPC_INS
= 0x04 | OPC_SPECIAL3
,
266 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
267 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
268 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
269 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
270 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
271 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
272 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
273 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
277 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
280 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
281 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
282 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
286 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
289 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
290 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
293 /* Coprocessor 0 (rs field) */
294 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
297 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
298 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
299 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
300 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
301 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
302 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
303 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
304 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
305 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
306 OPC_C0
= (0x10 << 21) | OPC_CP0
,
307 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
308 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
312 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
315 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
316 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
317 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
318 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
319 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
320 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
323 /* Coprocessor 0 (with rs == C0) */
324 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
327 OPC_TLBR
= 0x01 | OPC_C0
,
328 OPC_TLBWI
= 0x02 | OPC_C0
,
329 OPC_TLBWR
= 0x06 | OPC_C0
,
330 OPC_TLBP
= 0x08 | OPC_C0
,
331 OPC_RFE
= 0x10 | OPC_C0
,
332 OPC_ERET
= 0x18 | OPC_C0
,
333 OPC_DERET
= 0x1F | OPC_C0
,
334 OPC_WAIT
= 0x20 | OPC_C0
,
337 /* Coprocessor 1 (rs field) */
338 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
341 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
342 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
343 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
344 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
345 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
346 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
347 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
348 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
349 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
350 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
351 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
352 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
353 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
354 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
355 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
356 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
357 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
358 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
361 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
362 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
365 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
366 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
367 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
368 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
372 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
373 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
377 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
378 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
381 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
384 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
385 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
386 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
387 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
388 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
389 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
390 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
391 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
392 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
395 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
398 OPC_LWXC1
= 0x00 | OPC_CP3
,
399 OPC_LDXC1
= 0x01 | OPC_CP3
,
400 OPC_LUXC1
= 0x05 | OPC_CP3
,
401 OPC_SWXC1
= 0x08 | OPC_CP3
,
402 OPC_SDXC1
= 0x09 | OPC_CP3
,
403 OPC_SUXC1
= 0x0D | OPC_CP3
,
404 OPC_PREFX
= 0x0F | OPC_CP3
,
405 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
406 OPC_MADD_S
= 0x20 | OPC_CP3
,
407 OPC_MADD_D
= 0x21 | OPC_CP3
,
408 OPC_MADD_PS
= 0x26 | OPC_CP3
,
409 OPC_MSUB_S
= 0x28 | OPC_CP3
,
410 OPC_MSUB_D
= 0x29 | OPC_CP3
,
411 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
412 OPC_NMADD_S
= 0x30 | OPC_CP3
,
413 OPC_NMADD_D
= 0x31 | OPC_CP3
,
414 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
415 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
416 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
417 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
421 const unsigned char *regnames
[] =
422 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
423 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
424 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
425 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
427 /* Warning: no function for r0 register (hard wired to zero) */
428 #define GEN32(func, NAME) \
429 static GenOpFunc *NAME ## _table [32] = { \
430 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
431 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
432 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
433 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
434 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
435 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
436 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
437 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
439 static always_inline void func(int n) \
441 NAME ## _table[n](); \
444 /* General purpose registers moves */
445 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
446 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
447 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
449 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
450 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
452 /* Moves to/from shadow registers */
453 GEN32(gen_op_load_srsgpr_T0
, gen_op_load_srsgpr_T0_gpr
);
454 GEN32(gen_op_store_T0_srsgpr
, gen_op_store_T0_srsgpr_gpr
);
456 static const char *fregnames
[] =
457 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
458 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
459 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
460 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
462 #define FGEN32(func, NAME) \
463 static GenOpFunc *NAME ## _table [32] = { \
464 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
465 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
466 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
467 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
468 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
469 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
470 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
471 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
473 static always_inline void func(int n) \
475 NAME ## _table[n](); \
478 FGEN32(gen_op_load_fpr_WT0
, gen_op_load_fpr_WT0_fpr
);
479 FGEN32(gen_op_store_fpr_WT0
, gen_op_store_fpr_WT0_fpr
);
481 FGEN32(gen_op_load_fpr_WT1
, gen_op_load_fpr_WT1_fpr
);
482 FGEN32(gen_op_store_fpr_WT1
, gen_op_store_fpr_WT1_fpr
);
484 FGEN32(gen_op_load_fpr_WT2
, gen_op_load_fpr_WT2_fpr
);
485 FGEN32(gen_op_store_fpr_WT2
, gen_op_store_fpr_WT2_fpr
);
487 FGEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fpr
);
488 FGEN32(gen_op_store_fpr_DT0
, gen_op_store_fpr_DT0_fpr
);
490 FGEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fpr
);
491 FGEN32(gen_op_store_fpr_DT1
, gen_op_store_fpr_DT1_fpr
);
493 FGEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fpr
);
494 FGEN32(gen_op_store_fpr_DT2
, gen_op_store_fpr_DT2_fpr
);
496 FGEN32(gen_op_load_fpr_WTH0
, gen_op_load_fpr_WTH0_fpr
);
497 FGEN32(gen_op_store_fpr_WTH0
, gen_op_store_fpr_WTH0_fpr
);
499 FGEN32(gen_op_load_fpr_WTH1
, gen_op_load_fpr_WTH1_fpr
);
500 FGEN32(gen_op_store_fpr_WTH1
, gen_op_store_fpr_WTH1_fpr
);
502 FGEN32(gen_op_load_fpr_WTH2
, gen_op_load_fpr_WTH2_fpr
);
503 FGEN32(gen_op_store_fpr_WTH2
, gen_op_store_fpr_WTH2_fpr
);
505 #define FOP_CONDS(type, fmt) \
506 static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
507 gen_op_cmp ## type ## _ ## fmt ## _f, \
508 gen_op_cmp ## type ## _ ## fmt ## _un, \
509 gen_op_cmp ## type ## _ ## fmt ## _eq, \
510 gen_op_cmp ## type ## _ ## fmt ## _ueq, \
511 gen_op_cmp ## type ## _ ## fmt ## _olt, \
512 gen_op_cmp ## type ## _ ## fmt ## _ult, \
513 gen_op_cmp ## type ## _ ## fmt ## _ole, \
514 gen_op_cmp ## type ## _ ## fmt ## _ule, \
515 gen_op_cmp ## type ## _ ## fmt ## _sf, \
516 gen_op_cmp ## type ## _ ## fmt ## _ngle, \
517 gen_op_cmp ## type ## _ ## fmt ## _seq, \
518 gen_op_cmp ## type ## _ ## fmt ## _ngl, \
519 gen_op_cmp ## type ## _ ## fmt ## _lt, \
520 gen_op_cmp ## type ## _ ## fmt ## _nge, \
521 gen_op_cmp ## type ## _ ## fmt ## _le, \
522 gen_op_cmp ## type ## _ ## fmt ## _ngt, \
524 static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
526 gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
536 typedef struct DisasContext
{
537 struct TranslationBlock
*tb
;
538 target_ulong pc
, saved_pc
;
541 /* Routine used to access memory */
543 uint32_t hflags
, saved_hflags
;
545 target_ulong btarget
;
551 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
552 * exception condition
554 BS_STOP
= 1, /* We want to stop translation for any reason */
555 BS_BRANCH
= 2, /* We reached a branch condition */
556 BS_EXCP
= 3, /* We reached an exception condition */
559 #ifdef MIPS_DEBUG_DISAS
560 #define MIPS_DEBUG(fmt, args...) \
562 if (loglevel & CPU_LOG_TB_IN_ASM) { \
563 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
564 ctx->pc, ctx->opcode , ##args); \
568 #define MIPS_DEBUG(fmt, args...) do { } while(0)
571 #define MIPS_INVAL(op) \
573 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
574 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
577 #define GEN_LOAD_REG_T0(Rn) \
582 if (ctx->glue(last_T0, _store) != gen_opc_ptr \
583 || ctx->glue(last_T0, _gpr) != Rn) { \
584 gen_op_load_gpr_T0(Rn); \
589 #define GEN_LOAD_REG_T1(Rn) \
594 gen_op_load_gpr_T1(Rn); \
598 #define GEN_LOAD_REG_T2(Rn) \
603 gen_op_load_gpr_T2(Rn); \
607 #define GEN_LOAD_SRSREG_TN(Tn, Rn) \
610 glue(gen_op_reset_, Tn)(); \
612 glue(gen_op_load_srsgpr_, Tn)(Rn); \
616 #if defined(TARGET_MIPS64)
617 #define GEN_LOAD_IMM_TN(Tn, Imm) \
620 glue(gen_op_reset_, Tn)(); \
621 } else if ((int32_t)Imm == Imm) { \
622 glue(gen_op_set_, Tn)(Imm); \
624 glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm); \
628 #define GEN_LOAD_IMM_TN(Tn, Imm) \
631 glue(gen_op_reset_, Tn)(); \
633 glue(gen_op_set_, Tn)(Imm); \
638 #define GEN_STORE_T0_REG(Rn) \
641 glue(gen_op_store_T0,_gpr)(Rn); \
642 ctx->glue(last_T0,_store) = gen_opc_ptr; \
643 ctx->glue(last_T0,_gpr) = Rn; \
647 #define GEN_STORE_T1_REG(Rn) \
650 glue(gen_op_store_T1,_gpr)(Rn); \
653 #define GEN_STORE_TN_SRSREG(Rn, Tn) \
656 glue(glue(gen_op_store_, Tn),_srsgpr)(Rn); \
660 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
662 glue(gen_op_load_fpr_, FTn)(Fn); \
665 #define GEN_STORE_FTN_FREG(Fn, FTn) \
667 glue(gen_op_store_fpr_, FTn)(Fn); \
670 static always_inline
void gen_save_pc(target_ulong pc
)
672 #if defined(TARGET_MIPS64)
673 if (pc
== (int32_t)pc
) {
676 gen_op_save_pc64(pc
>> 32, (uint32_t)pc
);
683 static always_inline
void gen_save_btarget(target_ulong btarget
)
685 #if defined(TARGET_MIPS64)
686 if (btarget
== (int32_t)btarget
) {
687 gen_op_save_btarget(btarget
);
689 gen_op_save_btarget64(btarget
>> 32, (uint32_t)btarget
);
692 gen_op_save_btarget(btarget
);
696 static always_inline
void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
698 #if defined MIPS_DEBUG_DISAS
699 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
700 fprintf(logfile
, "hflags %08x saved %08x\n",
701 ctx
->hflags
, ctx
->saved_hflags
);
704 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
705 gen_save_pc(ctx
->pc
);
706 ctx
->saved_pc
= ctx
->pc
;
708 if (ctx
->hflags
!= ctx
->saved_hflags
) {
709 gen_op_save_state(ctx
->hflags
);
710 ctx
->saved_hflags
= ctx
->hflags
;
711 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
713 gen_op_save_breg_target();
719 /* bcond was already saved by the BL insn */
722 gen_save_btarget(ctx
->btarget
);
728 static always_inline
void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
730 ctx
->saved_hflags
= ctx
->hflags
;
731 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
733 gen_op_restore_breg_target();
736 ctx
->btarget
= env
->btarget
;
740 ctx
->btarget
= env
->btarget
;
741 gen_op_restore_bcond();
746 static always_inline
void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
748 #if defined MIPS_DEBUG_DISAS
749 if (loglevel
& CPU_LOG_TB_IN_ASM
)
750 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
752 save_cpu_state(ctx
, 1);
754 gen_op_raise_exception(excp
);
756 gen_op_raise_exception_err(excp
, err
);
757 ctx
->bstate
= BS_EXCP
;
760 static always_inline
void generate_exception (DisasContext
*ctx
, int excp
)
762 generate_exception_err (ctx
, excp
, 0);
765 static always_inline
void check_cp0_enabled(DisasContext
*ctx
)
767 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
768 generate_exception_err(ctx
, EXCP_CpU
, 1);
771 static always_inline
void check_cp1_enabled(DisasContext
*ctx
)
773 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
774 generate_exception_err(ctx
, EXCP_CpU
, 1);
777 static always_inline
void check_cp1_64bitmode(DisasContext
*ctx
)
779 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
)))
780 generate_exception(ctx
, EXCP_RI
);
784 * Verify if floating point register is valid; an operation is not defined
785 * if bit 0 of any register specification is set and the FR bit in the
786 * Status register equals zero, since the register numbers specify an
787 * even-odd pair of adjacent coprocessor general registers. When the FR bit
788 * in the Status register equals one, both even and odd register numbers
789 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
791 * Multiple 64 bit wide registers can be checked by calling
792 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
794 void check_cp1_registers(DisasContext
*ctx
, int regs
)
796 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
797 generate_exception(ctx
, EXCP_RI
);
800 /* This code generates a "reserved instruction" exception if the
801 CPU does not support the instruction set corresponding to flags. */
802 static always_inline
void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
804 if (unlikely(!(env
->insn_flags
& flags
)))
805 generate_exception(ctx
, EXCP_RI
);
808 /* This code generates a "reserved instruction" exception if 64-bit
809 instructions are not enabled. */
810 static always_inline
void check_mips_64(DisasContext
*ctx
)
812 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
813 generate_exception(ctx
, EXCP_RI
);
816 #if defined(CONFIG_USER_ONLY)
817 #define op_ldst(name) gen_op_##name##_raw()
818 #define OP_LD_TABLE(width)
819 #define OP_ST_TABLE(width)
821 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
822 #define OP_LD_TABLE(width) \
823 static GenOpFunc *gen_op_l##width[] = { \
824 &gen_op_l##width##_kernel, \
825 &gen_op_l##width##_super, \
826 &gen_op_l##width##_user, \
828 #define OP_ST_TABLE(width) \
829 static GenOpFunc *gen_op_s##width[] = { \
830 &gen_op_s##width##_kernel, \
831 &gen_op_s##width##_super, \
832 &gen_op_s##width##_user, \
836 #if defined(TARGET_MIPS64)
869 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
870 int base
, int16_t offset
)
872 const char *opn
= "ldst";
875 GEN_LOAD_IMM_TN(T0
, offset
);
876 } else if (offset
== 0) {
877 gen_op_load_gpr_T0(base
);
879 gen_op_load_gpr_T0(base
);
880 gen_op_set_T1(offset
);
883 /* Don't do NOP if destination is zero: we must perform the actual
886 #if defined(TARGET_MIPS64)
889 GEN_STORE_T0_REG(rt
);
894 GEN_STORE_T0_REG(rt
);
899 GEN_STORE_T0_REG(rt
);
908 save_cpu_state(ctx
, 1);
911 GEN_STORE_T0_REG(rt
);
917 GEN_STORE_T1_REG(rt
);
928 GEN_STORE_T1_REG(rt
);
939 GEN_STORE_T0_REG(rt
);
949 GEN_STORE_T0_REG(rt
);
959 GEN_STORE_T0_REG(rt
);
964 GEN_STORE_T0_REG(rt
);
974 GEN_STORE_T0_REG(rt
);
980 GEN_STORE_T1_REG(rt
);
991 GEN_STORE_T1_REG(rt
);
1001 GEN_STORE_T0_REG(rt
);
1005 save_cpu_state(ctx
, 1);
1006 GEN_LOAD_REG_T1(rt
);
1008 GEN_STORE_T0_REG(rt
);
1013 generate_exception(ctx
, EXCP_RI
);
1016 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1019 /* Load and store */
1020 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1021 int base
, int16_t offset
)
1023 const char *opn
= "flt_ldst";
1026 GEN_LOAD_IMM_TN(T0
, offset
);
1027 } else if (offset
== 0) {
1028 gen_op_load_gpr_T0(base
);
1030 gen_op_load_gpr_T0(base
);
1031 gen_op_set_T1(offset
);
1034 /* Don't do NOP if destination is zero: we must perform the actual
1039 GEN_STORE_FTN_FREG(ft
, WT0
);
1043 GEN_LOAD_FREG_FTN(WT0
, ft
);
1049 GEN_STORE_FTN_FREG(ft
, DT0
);
1053 GEN_LOAD_FREG_FTN(DT0
, ft
);
1059 generate_exception(ctx
, EXCP_RI
);
1062 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1065 /* Arithmetic with immediate operand */
1066 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1067 int rt
, int rs
, int16_t imm
)
1070 const char *opn
= "imm arith";
1072 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1073 /* If no destination, treat it as a NOP.
1074 For addi, we must generate the overflow exception when needed. */
1078 uimm
= (uint16_t)imm
;
1082 #if defined(TARGET_MIPS64)
1088 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1093 GEN_LOAD_REG_T0(rs
);
1094 GEN_LOAD_IMM_TN(T1
, uimm
);
1097 GEN_LOAD_IMM_TN(T0
, imm
<< 16);
1102 #if defined(TARGET_MIPS64)
1111 GEN_LOAD_REG_T0(rs
);
1112 GEN_LOAD_IMM_TN(T1
, uimm
);
1117 save_cpu_state(ctx
, 1);
1125 #if defined(TARGET_MIPS64)
1127 save_cpu_state(ctx
, 1);
1168 switch ((ctx
->opcode
>> 21) & 0x1f) {
1174 /* rotr is decoded as srl on non-R2 CPUs */
1175 if (env
->insn_flags
& ISA_MIPS32R2
) {
1184 MIPS_INVAL("invalid srl flag");
1185 generate_exception(ctx
, EXCP_RI
);
1189 #if defined(TARGET_MIPS64)
1199 switch ((ctx
->opcode
>> 21) & 0x1f) {
1205 /* drotr is decoded as dsrl on non-R2 CPUs */
1206 if (env
->insn_flags
& ISA_MIPS32R2
) {
1215 MIPS_INVAL("invalid dsrl flag");
1216 generate_exception(ctx
, EXCP_RI
);
1229 switch ((ctx
->opcode
>> 21) & 0x1f) {
1235 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1236 if (env
->insn_flags
& ISA_MIPS32R2
) {
1245 MIPS_INVAL("invalid dsrl32 flag");
1246 generate_exception(ctx
, EXCP_RI
);
1253 generate_exception(ctx
, EXCP_RI
);
1256 GEN_STORE_T0_REG(rt
);
1257 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1261 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1262 int rd
, int rs
, int rt
)
1264 const char *opn
= "arith";
1266 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1267 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1268 /* If no destination, treat it as a NOP.
1269 For add & sub, we must generate the overflow exception when needed. */
1273 GEN_LOAD_REG_T0(rs
);
1274 /* Specialcase the conventional move operation. */
1275 if (rt
== 0 && (opc
== OPC_ADDU
|| opc
== OPC_DADDU
1276 || opc
== OPC_SUBU
|| opc
== OPC_DSUBU
)) {
1277 GEN_STORE_T0_REG(rd
);
1280 GEN_LOAD_REG_T1(rt
);
1283 save_cpu_state(ctx
, 1);
1292 save_cpu_state(ctx
, 1);
1300 #if defined(TARGET_MIPS64)
1302 save_cpu_state(ctx
, 1);
1311 save_cpu_state(ctx
, 1);
1365 switch ((ctx
->opcode
>> 6) & 0x1f) {
1371 /* rotrv is decoded as srlv on non-R2 CPUs */
1372 if (env
->insn_flags
& ISA_MIPS32R2
) {
1381 MIPS_INVAL("invalid srlv flag");
1382 generate_exception(ctx
, EXCP_RI
);
1386 #if defined(TARGET_MIPS64)
1396 switch ((ctx
->opcode
>> 6) & 0x1f) {
1402 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1403 if (env
->insn_flags
& ISA_MIPS32R2
) {
1412 MIPS_INVAL("invalid dsrlv flag");
1413 generate_exception(ctx
, EXCP_RI
);
1420 generate_exception(ctx
, EXCP_RI
);
1423 GEN_STORE_T0_REG(rd
);
1425 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1428 /* Arithmetic on HI/LO registers */
1429 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1431 const char *opn
= "hilo";
1433 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1441 GEN_STORE_T0_REG(reg
);
1446 GEN_STORE_T0_REG(reg
);
1450 GEN_LOAD_REG_T0(reg
);
1455 GEN_LOAD_REG_T0(reg
);
1461 generate_exception(ctx
, EXCP_RI
);
1464 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1467 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1470 const char *opn
= "mul/div";
1472 GEN_LOAD_REG_T0(rs
);
1473 GEN_LOAD_REG_T1(rt
);
1491 #if defined(TARGET_MIPS64)
1527 generate_exception(ctx
, EXCP_RI
);
1530 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
1533 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
1536 const char *opn
= "CLx";
1542 GEN_LOAD_REG_T0(rs
);
1552 #if defined(TARGET_MIPS64)
1564 generate_exception(ctx
, EXCP_RI
);
1567 gen_op_store_T0_gpr(rd
);
1568 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
1572 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
1573 int rs
, int rt
, int16_t imm
)
1578 /* Load needed operands */
1586 /* Compare two registers */
1588 GEN_LOAD_REG_T0(rs
);
1589 GEN_LOAD_REG_T1(rt
);
1599 /* Compare register to immediate */
1600 if (rs
!= 0 || imm
!= 0) {
1601 GEN_LOAD_REG_T0(rs
);
1602 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
1609 case OPC_TEQ
: /* rs == rs */
1610 case OPC_TEQI
: /* r0 == 0 */
1611 case OPC_TGE
: /* rs >= rs */
1612 case OPC_TGEI
: /* r0 >= 0 */
1613 case OPC_TGEU
: /* rs >= rs unsigned */
1614 case OPC_TGEIU
: /* r0 >= 0 unsigned */
1618 case OPC_TLT
: /* rs < rs */
1619 case OPC_TLTI
: /* r0 < 0 */
1620 case OPC_TLTU
: /* rs < rs unsigned */
1621 case OPC_TLTIU
: /* r0 < 0 unsigned */
1622 case OPC_TNE
: /* rs != rs */
1623 case OPC_TNEI
: /* r0 != 0 */
1624 /* Never trap: treat as NOP. */
1628 generate_exception(ctx
, EXCP_RI
);
1659 generate_exception(ctx
, EXCP_RI
);
1663 save_cpu_state(ctx
, 1);
1665 ctx
->bstate
= BS_STOP
;
1668 static always_inline
void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1670 TranslationBlock
*tb
;
1672 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1674 gen_op_goto_tb0(TBPARAM(tb
));
1676 gen_op_goto_tb1(TBPARAM(tb
));
1678 gen_op_set_T0((long)tb
+ n
);
1686 /* Branches (before delay slot) */
1687 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
1688 int rs
, int rt
, int32_t offset
)
1690 target_ulong btarget
= -1;
1694 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
1695 #ifdef MIPS_DEBUG_DISAS
1696 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1698 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
1702 generate_exception(ctx
, EXCP_RI
);
1706 /* Load needed operands */
1712 /* Compare two registers */
1714 GEN_LOAD_REG_T0(rs
);
1715 GEN_LOAD_REG_T1(rt
);
1718 btarget
= ctx
->pc
+ 4 + offset
;
1732 /* Compare to zero */
1734 gen_op_load_gpr_T0(rs
);
1737 btarget
= ctx
->pc
+ 4 + offset
;
1741 /* Jump to immediate */
1742 btarget
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
1746 /* Jump to register */
1747 if (offset
!= 0 && offset
!= 16) {
1748 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1749 others are reserved. */
1750 MIPS_INVAL("jump hint");
1751 generate_exception(ctx
, EXCP_RI
);
1754 GEN_LOAD_REG_T2(rs
);
1757 MIPS_INVAL("branch/jump");
1758 generate_exception(ctx
, EXCP_RI
);
1762 /* No condition to be computed */
1764 case OPC_BEQ
: /* rx == rx */
1765 case OPC_BEQL
: /* rx == rx likely */
1766 case OPC_BGEZ
: /* 0 >= 0 */
1767 case OPC_BGEZL
: /* 0 >= 0 likely */
1768 case OPC_BLEZ
: /* 0 <= 0 */
1769 case OPC_BLEZL
: /* 0 <= 0 likely */
1771 ctx
->hflags
|= MIPS_HFLAG_B
;
1772 MIPS_DEBUG("balways");
1774 case OPC_BGEZAL
: /* 0 >= 0 */
1775 case OPC_BGEZALL
: /* 0 >= 0 likely */
1776 /* Always take and link */
1778 ctx
->hflags
|= MIPS_HFLAG_B
;
1779 MIPS_DEBUG("balways and link");
1781 case OPC_BNE
: /* rx != rx */
1782 case OPC_BGTZ
: /* 0 > 0 */
1783 case OPC_BLTZ
: /* 0 < 0 */
1785 MIPS_DEBUG("bnever (NOP)");
1787 case OPC_BLTZAL
: /* 0 < 0 */
1788 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1789 gen_op_store_T0_gpr(31);
1790 MIPS_DEBUG("bnever and link");
1792 case OPC_BLTZALL
: /* 0 < 0 likely */
1793 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1794 gen_op_store_T0_gpr(31);
1795 /* Skip the instruction in the delay slot */
1796 MIPS_DEBUG("bnever, link and skip");
1799 case OPC_BNEL
: /* rx != rx likely */
1800 case OPC_BGTZL
: /* 0 > 0 likely */
1801 case OPC_BLTZL
: /* 0 < 0 likely */
1802 /* Skip the instruction in the delay slot */
1803 MIPS_DEBUG("bnever and skip");
1807 ctx
->hflags
|= MIPS_HFLAG_B
;
1808 MIPS_DEBUG("j " TARGET_FMT_lx
, btarget
);
1812 ctx
->hflags
|= MIPS_HFLAG_B
;
1813 MIPS_DEBUG("jal " TARGET_FMT_lx
, btarget
);
1816 ctx
->hflags
|= MIPS_HFLAG_BR
;
1817 MIPS_DEBUG("jr %s", regnames
[rs
]);
1821 ctx
->hflags
|= MIPS_HFLAG_BR
;
1822 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
1825 MIPS_INVAL("branch/jump");
1826 generate_exception(ctx
, EXCP_RI
);
1833 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
1834 regnames
[rs
], regnames
[rt
], btarget
);
1838 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
1839 regnames
[rs
], regnames
[rt
], btarget
);
1843 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
1844 regnames
[rs
], regnames
[rt
], btarget
);
1848 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
1849 regnames
[rs
], regnames
[rt
], btarget
);
1853 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1857 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1861 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1867 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1871 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1875 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1879 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1883 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1887 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1891 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1896 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1898 ctx
->hflags
|= MIPS_HFLAG_BC
;
1904 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1906 ctx
->hflags
|= MIPS_HFLAG_BL
;
1908 gen_op_save_bcond();
1911 MIPS_INVAL("conditional branch/jump");
1912 generate_exception(ctx
, EXCP_RI
);
1916 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
1917 blink
, ctx
->hflags
, btarget
);
1919 ctx
->btarget
= btarget
;
1921 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1922 gen_op_store_T0_gpr(blink
);
1926 /* special3 bitfield operations */
1927 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
1928 int rs
, int lsb
, int msb
)
1930 GEN_LOAD_REG_T1(rs
);
1935 gen_op_ext(lsb
, msb
+ 1);
1937 #if defined(TARGET_MIPS64)
1941 gen_op_dext(lsb
, msb
+ 1 + 32);
1946 gen_op_dext(lsb
+ 32, msb
+ 1);
1951 gen_op_dext(lsb
, msb
+ 1);
1957 GEN_LOAD_REG_T0(rt
);
1958 gen_op_ins(lsb
, msb
- lsb
+ 1);
1960 #if defined(TARGET_MIPS64)
1964 GEN_LOAD_REG_T0(rt
);
1965 gen_op_dins(lsb
, msb
- lsb
+ 1 + 32);
1970 GEN_LOAD_REG_T0(rt
);
1971 gen_op_dins(lsb
+ 32, msb
- lsb
+ 1);
1976 GEN_LOAD_REG_T0(rt
);
1977 gen_op_dins(lsb
, msb
- lsb
+ 1);
1982 MIPS_INVAL("bitops");
1983 generate_exception(ctx
, EXCP_RI
);
1986 GEN_STORE_T0_REG(rt
);
1989 /* CP0 (MMU and control) */
1990 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
1992 const char *rn
= "invalid";
1995 check_insn(env
, ctx
, ISA_MIPS32
);
2001 gen_op_mfc0_index();
2005 check_insn(env
, ctx
, ASE_MT
);
2006 gen_op_mfc0_mvpcontrol();
2010 check_insn(env
, ctx
, ASE_MT
);
2011 gen_op_mfc0_mvpconf0();
2015 check_insn(env
, ctx
, ASE_MT
);
2016 gen_op_mfc0_mvpconf1();
2026 gen_op_mfc0_random();
2030 check_insn(env
, ctx
, ASE_MT
);
2031 gen_op_mfc0_vpecontrol();
2035 check_insn(env
, ctx
, ASE_MT
);
2036 gen_op_mfc0_vpeconf0();
2040 check_insn(env
, ctx
, ASE_MT
);
2041 gen_op_mfc0_vpeconf1();
2045 check_insn(env
, ctx
, ASE_MT
);
2046 gen_op_mfc0_yqmask();
2050 check_insn(env
, ctx
, ASE_MT
);
2051 gen_op_mfc0_vpeschedule();
2055 check_insn(env
, ctx
, ASE_MT
);
2056 gen_op_mfc0_vpeschefback();
2057 rn
= "VPEScheFBack";
2060 check_insn(env
, ctx
, ASE_MT
);
2061 gen_op_mfc0_vpeopt();
2071 gen_op_mfc0_entrylo0();
2075 check_insn(env
, ctx
, ASE_MT
);
2076 gen_op_mfc0_tcstatus();
2080 check_insn(env
, ctx
, ASE_MT
);
2081 gen_op_mfc0_tcbind();
2085 check_insn(env
, ctx
, ASE_MT
);
2086 gen_op_mfc0_tcrestart();
2090 check_insn(env
, ctx
, ASE_MT
);
2091 gen_op_mfc0_tchalt();
2095 check_insn(env
, ctx
, ASE_MT
);
2096 gen_op_mfc0_tccontext();
2100 check_insn(env
, ctx
, ASE_MT
);
2101 gen_op_mfc0_tcschedule();
2105 check_insn(env
, ctx
, ASE_MT
);
2106 gen_op_mfc0_tcschefback();
2116 gen_op_mfc0_entrylo1();
2126 gen_op_mfc0_context();
2130 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
2131 rn
= "ContextConfig";
2140 gen_op_mfc0_pagemask();
2144 check_insn(env
, ctx
, ISA_MIPS32R2
);
2145 gen_op_mfc0_pagegrain();
2155 gen_op_mfc0_wired();
2159 check_insn(env
, ctx
, ISA_MIPS32R2
);
2160 gen_op_mfc0_srsconf0();
2164 check_insn(env
, ctx
, ISA_MIPS32R2
);
2165 gen_op_mfc0_srsconf1();
2169 check_insn(env
, ctx
, ISA_MIPS32R2
);
2170 gen_op_mfc0_srsconf2();
2174 check_insn(env
, ctx
, ISA_MIPS32R2
);
2175 gen_op_mfc0_srsconf3();
2179 check_insn(env
, ctx
, ISA_MIPS32R2
);
2180 gen_op_mfc0_srsconf4();
2190 check_insn(env
, ctx
, ISA_MIPS32R2
);
2191 gen_op_mfc0_hwrena();
2201 gen_op_mfc0_badvaddr();
2211 gen_op_mfc0_count();
2214 /* 6,7 are implementation dependent */
2222 gen_op_mfc0_entryhi();
2232 gen_op_mfc0_compare();
2235 /* 6,7 are implementation dependent */
2243 gen_op_mfc0_status();
2247 check_insn(env
, ctx
, ISA_MIPS32R2
);
2248 gen_op_mfc0_intctl();
2252 check_insn(env
, ctx
, ISA_MIPS32R2
);
2253 gen_op_mfc0_srsctl();
2257 check_insn(env
, ctx
, ISA_MIPS32R2
);
2258 gen_op_mfc0_srsmap();
2268 gen_op_mfc0_cause();
2292 check_insn(env
, ctx
, ISA_MIPS32R2
);
2293 gen_op_mfc0_ebase();
2303 gen_op_mfc0_config0();
2307 gen_op_mfc0_config1();
2311 gen_op_mfc0_config2();
2315 gen_op_mfc0_config3();
2318 /* 4,5 are reserved */
2319 /* 6,7 are implementation dependent */
2321 gen_op_mfc0_config6();
2325 gen_op_mfc0_config7();
2335 gen_op_mfc0_lladdr();
2345 gen_op_mfc0_watchlo(sel
);
2355 gen_op_mfc0_watchhi(sel
);
2365 #if defined(TARGET_MIPS64)
2366 check_insn(env
, ctx
, ISA_MIPS3
);
2367 gen_op_mfc0_xcontext();
2376 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2379 gen_op_mfc0_framemask();
2388 rn
= "'Diagnostic"; /* implementation dependent */
2393 gen_op_mfc0_debug(); /* EJTAG support */
2397 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2398 rn
= "TraceControl";
2401 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2402 rn
= "TraceControl2";
2405 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2406 rn
= "UserTraceData";
2409 // gen_op_mfc0_debug(); /* PDtrace support */
2419 gen_op_mfc0_depc(); /* EJTAG support */
2429 gen_op_mfc0_performance0();
2430 rn
= "Performance0";
2433 // gen_op_mfc0_performance1();
2434 rn
= "Performance1";
2437 // gen_op_mfc0_performance2();
2438 rn
= "Performance2";
2441 // gen_op_mfc0_performance3();
2442 rn
= "Performance3";
2445 // gen_op_mfc0_performance4();
2446 rn
= "Performance4";
2449 // gen_op_mfc0_performance5();
2450 rn
= "Performance5";
2453 // gen_op_mfc0_performance6();
2454 rn
= "Performance6";
2457 // gen_op_mfc0_performance7();
2458 rn
= "Performance7";
2483 gen_op_mfc0_taglo();
2490 gen_op_mfc0_datalo();
2503 gen_op_mfc0_taghi();
2510 gen_op_mfc0_datahi();
2520 gen_op_mfc0_errorepc();
2530 gen_op_mfc0_desave(); /* EJTAG support */
2540 #if defined MIPS_DEBUG_DISAS
2541 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2542 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2549 #if defined MIPS_DEBUG_DISAS
2550 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2551 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2555 generate_exception(ctx
, EXCP_RI
);
2558 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2560 const char *rn
= "invalid";
2563 check_insn(env
, ctx
, ISA_MIPS32
);
2569 gen_op_mtc0_index();
2573 check_insn(env
, ctx
, ASE_MT
);
2574 gen_op_mtc0_mvpcontrol();
2578 check_insn(env
, ctx
, ASE_MT
);
2583 check_insn(env
, ctx
, ASE_MT
);
2598 check_insn(env
, ctx
, ASE_MT
);
2599 gen_op_mtc0_vpecontrol();
2603 check_insn(env
, ctx
, ASE_MT
);
2604 gen_op_mtc0_vpeconf0();
2608 check_insn(env
, ctx
, ASE_MT
);
2609 gen_op_mtc0_vpeconf1();
2613 check_insn(env
, ctx
, ASE_MT
);
2614 gen_op_mtc0_yqmask();
2618 check_insn(env
, ctx
, ASE_MT
);
2619 gen_op_mtc0_vpeschedule();
2623 check_insn(env
, ctx
, ASE_MT
);
2624 gen_op_mtc0_vpeschefback();
2625 rn
= "VPEScheFBack";
2628 check_insn(env
, ctx
, ASE_MT
);
2629 gen_op_mtc0_vpeopt();
2639 gen_op_mtc0_entrylo0();
2643 check_insn(env
, ctx
, ASE_MT
);
2644 gen_op_mtc0_tcstatus();
2648 check_insn(env
, ctx
, ASE_MT
);
2649 gen_op_mtc0_tcbind();
2653 check_insn(env
, ctx
, ASE_MT
);
2654 gen_op_mtc0_tcrestart();
2658 check_insn(env
, ctx
, ASE_MT
);
2659 gen_op_mtc0_tchalt();
2663 check_insn(env
, ctx
, ASE_MT
);
2664 gen_op_mtc0_tccontext();
2668 check_insn(env
, ctx
, ASE_MT
);
2669 gen_op_mtc0_tcschedule();
2673 check_insn(env
, ctx
, ASE_MT
);
2674 gen_op_mtc0_tcschefback();
2684 gen_op_mtc0_entrylo1();
2694 gen_op_mtc0_context();
2698 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2699 rn
= "ContextConfig";
2708 gen_op_mtc0_pagemask();
2712 check_insn(env
, ctx
, ISA_MIPS32R2
);
2713 gen_op_mtc0_pagegrain();
2723 gen_op_mtc0_wired();
2727 check_insn(env
, ctx
, ISA_MIPS32R2
);
2728 gen_op_mtc0_srsconf0();
2732 check_insn(env
, ctx
, ISA_MIPS32R2
);
2733 gen_op_mtc0_srsconf1();
2737 check_insn(env
, ctx
, ISA_MIPS32R2
);
2738 gen_op_mtc0_srsconf2();
2742 check_insn(env
, ctx
, ISA_MIPS32R2
);
2743 gen_op_mtc0_srsconf3();
2747 check_insn(env
, ctx
, ISA_MIPS32R2
);
2748 gen_op_mtc0_srsconf4();
2758 check_insn(env
, ctx
, ISA_MIPS32R2
);
2759 gen_op_mtc0_hwrena();
2773 gen_op_mtc0_count();
2776 /* 6,7 are implementation dependent */
2780 /* Stop translation as we may have switched the execution mode */
2781 ctx
->bstate
= BS_STOP
;
2786 gen_op_mtc0_entryhi();
2796 gen_op_mtc0_compare();
2799 /* 6,7 are implementation dependent */
2803 /* Stop translation as we may have switched the execution mode */
2804 ctx
->bstate
= BS_STOP
;
2809 gen_op_mtc0_status();
2810 /* BS_STOP isn't good enough here, hflags may have changed. */
2811 gen_save_pc(ctx
->pc
+ 4);
2812 ctx
->bstate
= BS_EXCP
;
2816 check_insn(env
, ctx
, ISA_MIPS32R2
);
2817 gen_op_mtc0_intctl();
2818 /* Stop translation as we may have switched the execution mode */
2819 ctx
->bstate
= BS_STOP
;
2823 check_insn(env
, ctx
, ISA_MIPS32R2
);
2824 gen_op_mtc0_srsctl();
2825 /* Stop translation as we may have switched the execution mode */
2826 ctx
->bstate
= BS_STOP
;
2830 check_insn(env
, ctx
, ISA_MIPS32R2
);
2831 gen_op_mtc0_srsmap();
2832 /* Stop translation as we may have switched the execution mode */
2833 ctx
->bstate
= BS_STOP
;
2843 gen_op_mtc0_cause();
2849 /* Stop translation as we may have switched the execution mode */
2850 ctx
->bstate
= BS_STOP
;
2869 check_insn(env
, ctx
, ISA_MIPS32R2
);
2870 gen_op_mtc0_ebase();
2880 gen_op_mtc0_config0();
2882 /* Stop translation as we may have switched the execution mode */
2883 ctx
->bstate
= BS_STOP
;
2886 /* ignored, read only */
2890 gen_op_mtc0_config2();
2892 /* Stop translation as we may have switched the execution mode */
2893 ctx
->bstate
= BS_STOP
;
2896 /* ignored, read only */
2899 /* 4,5 are reserved */
2900 /* 6,7 are implementation dependent */
2910 rn
= "Invalid config selector";
2927 gen_op_mtc0_watchlo(sel
);
2937 gen_op_mtc0_watchhi(sel
);
2947 #if defined(TARGET_MIPS64)
2948 check_insn(env
, ctx
, ISA_MIPS3
);
2949 gen_op_mtc0_xcontext();
2958 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2961 gen_op_mtc0_framemask();
2970 rn
= "Diagnostic"; /* implementation dependent */
2975 gen_op_mtc0_debug(); /* EJTAG support */
2976 /* BS_STOP isn't good enough here, hflags may have changed. */
2977 gen_save_pc(ctx
->pc
+ 4);
2978 ctx
->bstate
= BS_EXCP
;
2982 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
2983 rn
= "TraceControl";
2984 /* Stop translation as we may have switched the execution mode */
2985 ctx
->bstate
= BS_STOP
;
2988 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2989 rn
= "TraceControl2";
2990 /* Stop translation as we may have switched the execution mode */
2991 ctx
->bstate
= BS_STOP
;
2994 /* Stop translation as we may have switched the execution mode */
2995 ctx
->bstate
= BS_STOP
;
2996 // gen_op_mtc0_usertracedata(); /* PDtrace support */
2997 rn
= "UserTraceData";
2998 /* Stop translation as we may have switched the execution mode */
2999 ctx
->bstate
= BS_STOP
;
3002 // gen_op_mtc0_debug(); /* PDtrace support */
3003 /* Stop translation as we may have switched the execution mode */
3004 ctx
->bstate
= BS_STOP
;
3014 gen_op_mtc0_depc(); /* EJTAG support */
3024 gen_op_mtc0_performance0();
3025 rn
= "Performance0";
3028 // gen_op_mtc0_performance1();
3029 rn
= "Performance1";
3032 // gen_op_mtc0_performance2();
3033 rn
= "Performance2";
3036 // gen_op_mtc0_performance3();
3037 rn
= "Performance3";
3040 // gen_op_mtc0_performance4();
3041 rn
= "Performance4";
3044 // gen_op_mtc0_performance5();
3045 rn
= "Performance5";
3048 // gen_op_mtc0_performance6();
3049 rn
= "Performance6";
3052 // gen_op_mtc0_performance7();
3053 rn
= "Performance7";
3079 gen_op_mtc0_taglo();
3086 gen_op_mtc0_datalo();
3099 gen_op_mtc0_taghi();
3106 gen_op_mtc0_datahi();
3117 gen_op_mtc0_errorepc();
3127 gen_op_mtc0_desave(); /* EJTAG support */
3133 /* Stop translation as we may have switched the execution mode */
3134 ctx
->bstate
= BS_STOP
;
3139 #if defined MIPS_DEBUG_DISAS
3140 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3141 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3148 #if defined MIPS_DEBUG_DISAS
3149 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3150 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
3154 generate_exception(ctx
, EXCP_RI
);
3157 #if defined(TARGET_MIPS64)
3158 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3160 const char *rn
= "invalid";
3163 check_insn(env
, ctx
, ISA_MIPS64
);
3169 gen_op_mfc0_index();
3173 check_insn(env
, ctx
, ASE_MT
);
3174 gen_op_mfc0_mvpcontrol();
3178 check_insn(env
, ctx
, ASE_MT
);
3179 gen_op_mfc0_mvpconf0();
3183 check_insn(env
, ctx
, ASE_MT
);
3184 gen_op_mfc0_mvpconf1();
3194 gen_op_mfc0_random();
3198 check_insn(env
, ctx
, ASE_MT
);
3199 gen_op_mfc0_vpecontrol();
3203 check_insn(env
, ctx
, ASE_MT
);
3204 gen_op_mfc0_vpeconf0();
3208 check_insn(env
, ctx
, ASE_MT
);
3209 gen_op_mfc0_vpeconf1();
3213 check_insn(env
, ctx
, ASE_MT
);
3214 gen_op_dmfc0_yqmask();
3218 check_insn(env
, ctx
, ASE_MT
);
3219 gen_op_dmfc0_vpeschedule();
3223 check_insn(env
, ctx
, ASE_MT
);
3224 gen_op_dmfc0_vpeschefback();
3225 rn
= "VPEScheFBack";
3228 check_insn(env
, ctx
, ASE_MT
);
3229 gen_op_mfc0_vpeopt();
3239 gen_op_dmfc0_entrylo0();
3243 check_insn(env
, ctx
, ASE_MT
);
3244 gen_op_mfc0_tcstatus();
3248 check_insn(env
, ctx
, ASE_MT
);
3249 gen_op_mfc0_tcbind();
3253 check_insn(env
, ctx
, ASE_MT
);
3254 gen_op_dmfc0_tcrestart();
3258 check_insn(env
, ctx
, ASE_MT
);
3259 gen_op_dmfc0_tchalt();
3263 check_insn(env
, ctx
, ASE_MT
);
3264 gen_op_dmfc0_tccontext();
3268 check_insn(env
, ctx
, ASE_MT
);
3269 gen_op_dmfc0_tcschedule();
3273 check_insn(env
, ctx
, ASE_MT
);
3274 gen_op_dmfc0_tcschefback();
3284 gen_op_dmfc0_entrylo1();
3294 gen_op_dmfc0_context();
3298 // gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
3299 rn
= "ContextConfig";
3308 gen_op_mfc0_pagemask();
3312 check_insn(env
, ctx
, ISA_MIPS32R2
);
3313 gen_op_mfc0_pagegrain();
3323 gen_op_mfc0_wired();
3327 check_insn(env
, ctx
, ISA_MIPS32R2
);
3328 gen_op_mfc0_srsconf0();
3332 check_insn(env
, ctx
, ISA_MIPS32R2
);
3333 gen_op_mfc0_srsconf1();
3337 check_insn(env
, ctx
, ISA_MIPS32R2
);
3338 gen_op_mfc0_srsconf2();
3342 check_insn(env
, ctx
, ISA_MIPS32R2
);
3343 gen_op_mfc0_srsconf3();
3347 check_insn(env
, ctx
, ISA_MIPS32R2
);
3348 gen_op_mfc0_srsconf4();
3358 check_insn(env
, ctx
, ISA_MIPS32R2
);
3359 gen_op_mfc0_hwrena();
3369 gen_op_dmfc0_badvaddr();
3379 gen_op_mfc0_count();
3382 /* 6,7 are implementation dependent */
3390 gen_op_dmfc0_entryhi();
3400 gen_op_mfc0_compare();
3403 /* 6,7 are implementation dependent */
3411 gen_op_mfc0_status();
3415 check_insn(env
, ctx
, ISA_MIPS32R2
);
3416 gen_op_mfc0_intctl();
3420 check_insn(env
, ctx
, ISA_MIPS32R2
);
3421 gen_op_mfc0_srsctl();
3425 check_insn(env
, ctx
, ISA_MIPS32R2
);
3426 gen_op_mfc0_srsmap();
3436 gen_op_mfc0_cause();
3460 check_insn(env
, ctx
, ISA_MIPS32R2
);
3461 gen_op_mfc0_ebase();
3471 gen_op_mfc0_config0();
3475 gen_op_mfc0_config1();
3479 gen_op_mfc0_config2();
3483 gen_op_mfc0_config3();
3486 /* 6,7 are implementation dependent */
3494 gen_op_dmfc0_lladdr();
3504 gen_op_dmfc0_watchlo(sel
);
3514 gen_op_mfc0_watchhi(sel
);
3524 check_insn(env
, ctx
, ISA_MIPS3
);
3525 gen_op_dmfc0_xcontext();
3533 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3536 gen_op_mfc0_framemask();
3545 rn
= "'Diagnostic"; /* implementation dependent */
3550 gen_op_mfc0_debug(); /* EJTAG support */
3554 // gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3555 rn
= "TraceControl";
3558 // gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3559 rn
= "TraceControl2";
3562 // gen_op_dmfc0_usertracedata(); /* PDtrace support */
3563 rn
= "UserTraceData";
3566 // gen_op_dmfc0_debug(); /* PDtrace support */
3576 gen_op_dmfc0_depc(); /* EJTAG support */
3586 gen_op_mfc0_performance0();
3587 rn
= "Performance0";
3590 // gen_op_dmfc0_performance1();
3591 rn
= "Performance1";
3594 // gen_op_dmfc0_performance2();
3595 rn
= "Performance2";
3598 // gen_op_dmfc0_performance3();
3599 rn
= "Performance3";
3602 // gen_op_dmfc0_performance4();
3603 rn
= "Performance4";
3606 // gen_op_dmfc0_performance5();
3607 rn
= "Performance5";
3610 // gen_op_dmfc0_performance6();
3611 rn
= "Performance6";
3614 // gen_op_dmfc0_performance7();
3615 rn
= "Performance7";
3640 gen_op_mfc0_taglo();
3647 gen_op_mfc0_datalo();
3660 gen_op_mfc0_taghi();
3667 gen_op_mfc0_datahi();
3677 gen_op_dmfc0_errorepc();
3687 gen_op_mfc0_desave(); /* EJTAG support */
3697 #if defined MIPS_DEBUG_DISAS
3698 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3699 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3706 #if defined MIPS_DEBUG_DISAS
3707 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3708 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3712 generate_exception(ctx
, EXCP_RI
);
3715 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3717 const char *rn
= "invalid";
3720 check_insn(env
, ctx
, ISA_MIPS64
);
3726 gen_op_mtc0_index();
3730 check_insn(env
, ctx
, ASE_MT
);
3731 gen_op_mtc0_mvpcontrol();
3735 check_insn(env
, ctx
, ASE_MT
);
3740 check_insn(env
, ctx
, ASE_MT
);
3755 check_insn(env
, ctx
, ASE_MT
);
3756 gen_op_mtc0_vpecontrol();
3760 check_insn(env
, ctx
, ASE_MT
);
3761 gen_op_mtc0_vpeconf0();
3765 check_insn(env
, ctx
, ASE_MT
);
3766 gen_op_mtc0_vpeconf1();
3770 check_insn(env
, ctx
, ASE_MT
);
3771 gen_op_mtc0_yqmask();
3775 check_insn(env
, ctx
, ASE_MT
);
3776 gen_op_mtc0_vpeschedule();
3780 check_insn(env
, ctx
, ASE_MT
);
3781 gen_op_mtc0_vpeschefback();
3782 rn
= "VPEScheFBack";
3785 check_insn(env
, ctx
, ASE_MT
);
3786 gen_op_mtc0_vpeopt();
3796 gen_op_mtc0_entrylo0();
3800 check_insn(env
, ctx
, ASE_MT
);
3801 gen_op_mtc0_tcstatus();
3805 check_insn(env
, ctx
, ASE_MT
);
3806 gen_op_mtc0_tcbind();
3810 check_insn(env
, ctx
, ASE_MT
);
3811 gen_op_mtc0_tcrestart();
3815 check_insn(env
, ctx
, ASE_MT
);
3816 gen_op_mtc0_tchalt();
3820 check_insn(env
, ctx
, ASE_MT
);
3821 gen_op_mtc0_tccontext();
3825 check_insn(env
, ctx
, ASE_MT
);
3826 gen_op_mtc0_tcschedule();
3830 check_insn(env
, ctx
, ASE_MT
);
3831 gen_op_mtc0_tcschefback();
3841 gen_op_mtc0_entrylo1();
3851 gen_op_mtc0_context();
3855 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
3856 rn
= "ContextConfig";
3865 gen_op_mtc0_pagemask();
3869 check_insn(env
, ctx
, ISA_MIPS32R2
);
3870 gen_op_mtc0_pagegrain();
3880 gen_op_mtc0_wired();
3884 check_insn(env
, ctx
, ISA_MIPS32R2
);
3885 gen_op_mtc0_srsconf0();
3889 check_insn(env
, ctx
, ISA_MIPS32R2
);
3890 gen_op_mtc0_srsconf1();
3894 check_insn(env
, ctx
, ISA_MIPS32R2
);
3895 gen_op_mtc0_srsconf2();
3899 check_insn(env
, ctx
, ISA_MIPS32R2
);
3900 gen_op_mtc0_srsconf3();
3904 check_insn(env
, ctx
, ISA_MIPS32R2
);
3905 gen_op_mtc0_srsconf4();
3915 check_insn(env
, ctx
, ISA_MIPS32R2
);
3916 gen_op_mtc0_hwrena();
3930 gen_op_mtc0_count();
3933 /* 6,7 are implementation dependent */
3937 /* Stop translation as we may have switched the execution mode */
3938 ctx
->bstate
= BS_STOP
;
3943 gen_op_mtc0_entryhi();
3953 gen_op_mtc0_compare();
3956 /* 6,7 are implementation dependent */
3960 /* Stop translation as we may have switched the execution mode */
3961 ctx
->bstate
= BS_STOP
;
3966 gen_op_mtc0_status();
3967 /* BS_STOP isn't good enough here, hflags may have changed. */
3968 gen_save_pc(ctx
->pc
+ 4);
3969 ctx
->bstate
= BS_EXCP
;
3973 check_insn(env
, ctx
, ISA_MIPS32R2
);
3974 gen_op_mtc0_intctl();
3975 /* Stop translation as we may have switched the execution mode */
3976 ctx
->bstate
= BS_STOP
;
3980 check_insn(env
, ctx
, ISA_MIPS32R2
);
3981 gen_op_mtc0_srsctl();
3982 /* Stop translation as we may have switched the execution mode */
3983 ctx
->bstate
= BS_STOP
;
3987 check_insn(env
, ctx
, ISA_MIPS32R2
);
3988 gen_op_mtc0_srsmap();
3989 /* Stop translation as we may have switched the execution mode */
3990 ctx
->bstate
= BS_STOP
;
4000 gen_op_mtc0_cause();
4006 /* Stop translation as we may have switched the execution mode */
4007 ctx
->bstate
= BS_STOP
;
4026 check_insn(env
, ctx
, ISA_MIPS32R2
);
4027 gen_op_mtc0_ebase();
4037 gen_op_mtc0_config0();
4039 /* Stop translation as we may have switched the execution mode */
4040 ctx
->bstate
= BS_STOP
;
4047 gen_op_mtc0_config2();
4049 /* Stop translation as we may have switched the execution mode */
4050 ctx
->bstate
= BS_STOP
;
4056 /* 6,7 are implementation dependent */
4058 rn
= "Invalid config selector";
4075 gen_op_mtc0_watchlo(sel
);
4085 gen_op_mtc0_watchhi(sel
);
4095 check_insn(env
, ctx
, ISA_MIPS3
);
4096 gen_op_mtc0_xcontext();
4104 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4107 gen_op_mtc0_framemask();
4116 rn
= "Diagnostic"; /* implementation dependent */
4121 gen_op_mtc0_debug(); /* EJTAG support */
4122 /* BS_STOP isn't good enough here, hflags may have changed. */
4123 gen_save_pc(ctx
->pc
+ 4);
4124 ctx
->bstate
= BS_EXCP
;
4128 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
4129 /* Stop translation as we may have switched the execution mode */
4130 ctx
->bstate
= BS_STOP
;
4131 rn
= "TraceControl";
4134 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
4135 /* Stop translation as we may have switched the execution mode */
4136 ctx
->bstate
= BS_STOP
;
4137 rn
= "TraceControl2";
4140 // gen_op_mtc0_usertracedata(); /* PDtrace support */
4141 /* Stop translation as we may have switched the execution mode */
4142 ctx
->bstate
= BS_STOP
;
4143 rn
= "UserTraceData";
4146 // gen_op_mtc0_debug(); /* PDtrace support */
4147 /* Stop translation as we may have switched the execution mode */
4148 ctx
->bstate
= BS_STOP
;
4158 gen_op_mtc0_depc(); /* EJTAG support */
4168 gen_op_mtc0_performance0();
4169 rn
= "Performance0";
4172 // gen_op_mtc0_performance1();
4173 rn
= "Performance1";
4176 // gen_op_mtc0_performance2();
4177 rn
= "Performance2";
4180 // gen_op_mtc0_performance3();
4181 rn
= "Performance3";
4184 // gen_op_mtc0_performance4();
4185 rn
= "Performance4";
4188 // gen_op_mtc0_performance5();
4189 rn
= "Performance5";
4192 // gen_op_mtc0_performance6();
4193 rn
= "Performance6";
4196 // gen_op_mtc0_performance7();
4197 rn
= "Performance7";
4223 gen_op_mtc0_taglo();
4230 gen_op_mtc0_datalo();
4243 gen_op_mtc0_taghi();
4250 gen_op_mtc0_datahi();
4261 gen_op_mtc0_errorepc();
4271 gen_op_mtc0_desave(); /* EJTAG support */
4277 /* Stop translation as we may have switched the execution mode */
4278 ctx
->bstate
= BS_STOP
;
4283 #if defined MIPS_DEBUG_DISAS
4284 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4285 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4292 #if defined MIPS_DEBUG_DISAS
4293 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4294 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4298 generate_exception(ctx
, EXCP_RI
);
4300 #endif /* TARGET_MIPS64 */
4302 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
,
4303 int u
, int sel
, int h
)
4305 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4307 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4308 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4309 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4311 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4312 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4319 gen_op_mftc0_tcstatus();
4322 gen_op_mftc0_tcbind();
4325 gen_op_mftc0_tcrestart();
4328 gen_op_mftc0_tchalt();
4331 gen_op_mftc0_tccontext();
4334 gen_op_mftc0_tcschedule();
4337 gen_op_mftc0_tcschefback();
4340 gen_mfc0(env
, ctx
, rt
, sel
);
4347 gen_op_mftc0_entryhi();
4350 gen_mfc0(env
, ctx
, rt
, sel
);
4356 gen_op_mftc0_status();
4359 gen_mfc0(env
, ctx
, rt
, sel
);
4365 gen_op_mftc0_debug();
4368 gen_mfc0(env
, ctx
, rt
, sel
);
4373 gen_mfc0(env
, ctx
, rt
, sel
);
4375 } else switch (sel
) {
4376 /* GPR registers. */
4380 /* Auxiliary CPU registers */
4426 /* Floating point (COP1). */
4428 /* XXX: For now we support only a single FPU context. */
4430 GEN_LOAD_FREG_FTN(WT0
, rt
);
4433 GEN_LOAD_FREG_FTN(WTH0
, rt
);
4438 /* XXX: For now we support only a single FPU context. */
4441 /* COP2: Not implemented. */
4448 #if defined MIPS_DEBUG_DISAS
4449 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4450 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4457 #if defined MIPS_DEBUG_DISAS
4458 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4459 fprintf(logfile
, "mftr (reg %d u %d sel %d h %d)\n",
4463 generate_exception(ctx
, EXCP_RI
);
4466 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
,
4467 int u
, int sel
, int h
)
4469 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
4471 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
4472 ((env
->CP0_TCBind
[other_tc
] & (0xf << CP0TCBd_CurVPE
)) !=
4473 (env
->CP0_TCBind
[env
->current_tc
] & (0xf << CP0TCBd_CurVPE
))))
4475 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
4476 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
4483 gen_op_mttc0_tcstatus();
4486 gen_op_mttc0_tcbind();
4489 gen_op_mttc0_tcrestart();
4492 gen_op_mttc0_tchalt();
4495 gen_op_mttc0_tccontext();
4498 gen_op_mttc0_tcschedule();
4501 gen_op_mttc0_tcschefback();
4504 gen_mtc0(env
, ctx
, rd
, sel
);
4511 gen_op_mttc0_entryhi();
4514 gen_mtc0(env
, ctx
, rd
, sel
);
4520 gen_op_mttc0_status();
4523 gen_mtc0(env
, ctx
, rd
, sel
);
4529 gen_op_mttc0_debug();
4532 gen_mtc0(env
, ctx
, rd
, sel
);
4537 gen_mtc0(env
, ctx
, rd
, sel
);
4539 } else switch (sel
) {
4540 /* GPR registers. */
4544 /* Auxiliary CPU registers */
4590 /* Floating point (COP1). */
4592 /* XXX: For now we support only a single FPU context. */
4595 GEN_STORE_FTN_FREG(rd
, WT0
);
4598 GEN_STORE_FTN_FREG(rd
, WTH0
);
4602 /* XXX: For now we support only a single FPU context. */
4605 /* COP2: Not implemented. */
4612 #if defined MIPS_DEBUG_DISAS
4613 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4614 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4621 #if defined MIPS_DEBUG_DISAS
4622 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4623 fprintf(logfile
, "mttr (reg %d u %d sel %d h %d)\n",
4627 generate_exception(ctx
, EXCP_RI
);
4630 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
4632 const char *opn
= "ldst";
4640 gen_mfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4641 gen_op_store_T0_gpr(rt
);
4645 GEN_LOAD_REG_T0(rt
);
4646 save_cpu_state(ctx
, 1);
4647 gen_mtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4650 #if defined(TARGET_MIPS64)
4652 check_insn(env
, ctx
, ISA_MIPS3
);
4657 gen_dmfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4658 gen_op_store_T0_gpr(rt
);
4662 check_insn(env
, ctx
, ISA_MIPS3
);
4663 GEN_LOAD_REG_T0(rt
);
4664 save_cpu_state(ctx
, 1);
4665 gen_dmtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4670 check_insn(env
, ctx
, ASE_MT
);
4675 gen_mftr(env
, ctx
, rt
, (ctx
->opcode
>> 5) & 1,
4676 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4677 gen_op_store_T0_gpr(rd
);
4681 check_insn(env
, ctx
, ASE_MT
);
4682 GEN_LOAD_REG_T0(rt
);
4683 gen_mttr(env
, ctx
, rd
, (ctx
->opcode
>> 5) & 1,
4684 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
4689 if (!env
->tlb
->do_tlbwi
)
4695 if (!env
->tlb
->do_tlbwr
)
4701 if (!env
->tlb
->do_tlbp
)
4707 if (!env
->tlb
->do_tlbr
)
4713 check_insn(env
, ctx
, ISA_MIPS2
);
4714 save_cpu_state(ctx
, 1);
4716 ctx
->bstate
= BS_EXCP
;
4720 check_insn(env
, ctx
, ISA_MIPS32
);
4721 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
4723 generate_exception(ctx
, EXCP_RI
);
4725 save_cpu_state(ctx
, 1);
4727 ctx
->bstate
= BS_EXCP
;
4732 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
4733 /* If we get an exception, we want to restart at next instruction */
4735 save_cpu_state(ctx
, 1);
4738 ctx
->bstate
= BS_EXCP
;
4743 generate_exception(ctx
, EXCP_RI
);
4746 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
4749 /* CP1 Branches (before delay slot) */
4750 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
4751 int32_t cc
, int32_t offset
)
4753 target_ulong btarget
;
4754 const char *opn
= "cp1 cond branch";
4757 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
4759 btarget
= ctx
->pc
+ 4 + offset
;
4778 ctx
->hflags
|= MIPS_HFLAG_BL
;
4780 gen_op_save_bcond();
4783 gen_op_bc1any2f(cc
);
4787 gen_op_bc1any2t(cc
);
4791 gen_op_bc1any4f(cc
);
4795 gen_op_bc1any4t(cc
);
4798 ctx
->hflags
|= MIPS_HFLAG_BC
;
4803 generate_exception (ctx
, EXCP_RI
);
4806 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
4807 ctx
->hflags
, btarget
);
4808 ctx
->btarget
= btarget
;
4811 /* Coprocessor 1 (FPU) */
4813 #define FOP(func, fmt) (((fmt) << 21) | (func))
4815 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
4817 const char *opn
= "cp1 move";
4821 GEN_LOAD_FREG_FTN(WT0
, fs
);
4823 GEN_STORE_T0_REG(rt
);
4827 GEN_LOAD_REG_T0(rt
);
4829 GEN_STORE_FTN_FREG(fs
, WT0
);
4834 GEN_STORE_T0_REG(rt
);
4838 GEN_LOAD_REG_T0(rt
);
4843 GEN_LOAD_FREG_FTN(DT0
, fs
);
4845 GEN_STORE_T0_REG(rt
);
4849 GEN_LOAD_REG_T0(rt
);
4851 GEN_STORE_FTN_FREG(fs
, DT0
);
4855 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4857 GEN_STORE_T0_REG(rt
);
4861 GEN_LOAD_REG_T0(rt
);
4863 GEN_STORE_FTN_FREG(fs
, WTH0
);
4868 generate_exception (ctx
, EXCP_RI
);
4871 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
4874 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
4878 GEN_LOAD_REG_T0(rd
);
4879 GEN_LOAD_REG_T1(rs
);
4881 ccbit
= 1 << (24 + cc
);
4888 GEN_STORE_T0_REG(rd
);
4891 #define GEN_MOVCF(fmt) \
4892 static void glue(gen_movcf_, fmt) (DisasContext *ctx, int cc, int tf) \
4897 ccbit = 1 << (24 + cc); \
4901 glue(gen_op_float_movf_, fmt)(ccbit); \
4903 glue(gen_op_float_movt_, fmt)(ccbit); \
4910 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
4911 int ft
, int fs
, int fd
, int cc
)
4913 const char *opn
= "farith";
4914 const char *condnames
[] = {
4932 const char *condnames_abs
[] = {
4950 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
4951 uint32_t func
= ctx
->opcode
& 0x3f;
4953 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
4955 GEN_LOAD_FREG_FTN(WT0
, fs
);
4956 GEN_LOAD_FREG_FTN(WT1
, ft
);
4957 gen_op_float_add_s();
4958 GEN_STORE_FTN_FREG(fd
, WT2
);
4963 GEN_LOAD_FREG_FTN(WT0
, fs
);
4964 GEN_LOAD_FREG_FTN(WT1
, ft
);
4965 gen_op_float_sub_s();
4966 GEN_STORE_FTN_FREG(fd
, WT2
);
4971 GEN_LOAD_FREG_FTN(WT0
, fs
);
4972 GEN_LOAD_FREG_FTN(WT1
, ft
);
4973 gen_op_float_mul_s();
4974 GEN_STORE_FTN_FREG(fd
, WT2
);
4979 GEN_LOAD_FREG_FTN(WT0
, fs
);
4980 GEN_LOAD_FREG_FTN(WT1
, ft
);
4981 gen_op_float_div_s();
4982 GEN_STORE_FTN_FREG(fd
, WT2
);
4987 GEN_LOAD_FREG_FTN(WT0
, fs
);
4988 gen_op_float_sqrt_s();
4989 GEN_STORE_FTN_FREG(fd
, WT2
);
4993 GEN_LOAD_FREG_FTN(WT0
, fs
);
4994 gen_op_float_abs_s();
4995 GEN_STORE_FTN_FREG(fd
, WT2
);
4999 GEN_LOAD_FREG_FTN(WT0
, fs
);
5000 gen_op_float_mov_s();
5001 GEN_STORE_FTN_FREG(fd
, WT2
);
5005 GEN_LOAD_FREG_FTN(WT0
, fs
);
5006 gen_op_float_chs_s();
5007 GEN_STORE_FTN_FREG(fd
, WT2
);
5011 check_cp1_64bitmode(ctx
);
5012 GEN_LOAD_FREG_FTN(WT0
, fs
);
5013 gen_op_float_roundl_s();
5014 GEN_STORE_FTN_FREG(fd
, DT2
);
5018 check_cp1_64bitmode(ctx
);
5019 GEN_LOAD_FREG_FTN(WT0
, fs
);
5020 gen_op_float_truncl_s();
5021 GEN_STORE_FTN_FREG(fd
, DT2
);
5025 check_cp1_64bitmode(ctx
);
5026 GEN_LOAD_FREG_FTN(WT0
, fs
);
5027 gen_op_float_ceill_s();
5028 GEN_STORE_FTN_FREG(fd
, DT2
);
5032 check_cp1_64bitmode(ctx
);
5033 GEN_LOAD_FREG_FTN(WT0
, fs
);
5034 gen_op_float_floorl_s();
5035 GEN_STORE_FTN_FREG(fd
, DT2
);
5039 GEN_LOAD_FREG_FTN(WT0
, fs
);
5040 gen_op_float_roundw_s();
5041 GEN_STORE_FTN_FREG(fd
, WT2
);
5045 GEN_LOAD_FREG_FTN(WT0
, fs
);
5046 gen_op_float_truncw_s();
5047 GEN_STORE_FTN_FREG(fd
, WT2
);
5051 GEN_LOAD_FREG_FTN(WT0
, fs
);
5052 gen_op_float_ceilw_s();
5053 GEN_STORE_FTN_FREG(fd
, WT2
);
5057 GEN_LOAD_FREG_FTN(WT0
, fs
);
5058 gen_op_float_floorw_s();
5059 GEN_STORE_FTN_FREG(fd
, WT2
);
5063 GEN_LOAD_REG_T0(ft
);
5064 GEN_LOAD_FREG_FTN(WT0
, fs
);
5065 GEN_LOAD_FREG_FTN(WT2
, fd
);
5066 gen_movcf_s(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5067 GEN_STORE_FTN_FREG(fd
, WT2
);
5071 GEN_LOAD_REG_T0(ft
);
5072 GEN_LOAD_FREG_FTN(WT0
, fs
);
5073 GEN_LOAD_FREG_FTN(WT2
, fd
);
5074 gen_op_float_movz_s();
5075 GEN_STORE_FTN_FREG(fd
, WT2
);
5079 GEN_LOAD_REG_T0(ft
);
5080 GEN_LOAD_FREG_FTN(WT0
, fs
);
5081 GEN_LOAD_FREG_FTN(WT2
, fd
);
5082 gen_op_float_movn_s();
5083 GEN_STORE_FTN_FREG(fd
, WT2
);
5087 GEN_LOAD_FREG_FTN(WT0
, fs
);
5088 gen_op_float_recip_s();
5089 GEN_STORE_FTN_FREG(fd
, WT2
);
5093 GEN_LOAD_FREG_FTN(WT0
, fs
);
5094 gen_op_float_rsqrt_s();
5095 GEN_STORE_FTN_FREG(fd
, WT2
);
5099 check_cp1_64bitmode(ctx
);
5100 GEN_LOAD_FREG_FTN(WT0
, fs
);
5101 GEN_LOAD_FREG_FTN(WT2
, fd
);
5102 gen_op_float_recip2_s();
5103 GEN_STORE_FTN_FREG(fd
, WT2
);
5107 check_cp1_64bitmode(ctx
);
5108 GEN_LOAD_FREG_FTN(WT0
, fs
);
5109 gen_op_float_recip1_s();
5110 GEN_STORE_FTN_FREG(fd
, WT2
);
5114 check_cp1_64bitmode(ctx
);
5115 GEN_LOAD_FREG_FTN(WT0
, fs
);
5116 gen_op_float_rsqrt1_s();
5117 GEN_STORE_FTN_FREG(fd
, WT2
);
5121 check_cp1_64bitmode(ctx
);
5122 GEN_LOAD_FREG_FTN(WT0
, fs
);
5123 GEN_LOAD_FREG_FTN(WT2
, ft
);
5124 gen_op_float_rsqrt2_s();
5125 GEN_STORE_FTN_FREG(fd
, WT2
);
5129 check_cp1_registers(ctx
, fd
);
5130 GEN_LOAD_FREG_FTN(WT0
, fs
);
5131 gen_op_float_cvtd_s();
5132 GEN_STORE_FTN_FREG(fd
, DT2
);
5136 GEN_LOAD_FREG_FTN(WT0
, fs
);
5137 gen_op_float_cvtw_s();
5138 GEN_STORE_FTN_FREG(fd
, WT2
);
5142 check_cp1_64bitmode(ctx
);
5143 GEN_LOAD_FREG_FTN(WT0
, fs
);
5144 gen_op_float_cvtl_s();
5145 GEN_STORE_FTN_FREG(fd
, DT2
);
5149 check_cp1_64bitmode(ctx
);
5150 GEN_LOAD_FREG_FTN(WT1
, fs
);
5151 GEN_LOAD_FREG_FTN(WT0
, ft
);
5152 gen_op_float_cvtps_s();
5153 GEN_STORE_FTN_FREG(fd
, DT2
);
5172 GEN_LOAD_FREG_FTN(WT0
, fs
);
5173 GEN_LOAD_FREG_FTN(WT1
, ft
);
5174 if (ctx
->opcode
& (1 << 6)) {
5175 check_cp1_64bitmode(ctx
);
5176 gen_cmpabs_s(func
-48, cc
);
5177 opn
= condnames_abs
[func
-48];
5179 gen_cmp_s(func
-48, cc
);
5180 opn
= condnames
[func
-48];
5184 check_cp1_registers(ctx
, fs
| ft
| fd
);
5185 GEN_LOAD_FREG_FTN(DT0
, fs
);
5186 GEN_LOAD_FREG_FTN(DT1
, ft
);
5187 gen_op_float_add_d();
5188 GEN_STORE_FTN_FREG(fd
, DT2
);
5193 check_cp1_registers(ctx
, fs
| ft
| fd
);
5194 GEN_LOAD_FREG_FTN(DT0
, fs
);
5195 GEN_LOAD_FREG_FTN(DT1
, ft
);
5196 gen_op_float_sub_d();
5197 GEN_STORE_FTN_FREG(fd
, DT2
);
5202 check_cp1_registers(ctx
, fs
| ft
| fd
);
5203 GEN_LOAD_FREG_FTN(DT0
, fs
);
5204 GEN_LOAD_FREG_FTN(DT1
, ft
);
5205 gen_op_float_mul_d();
5206 GEN_STORE_FTN_FREG(fd
, DT2
);
5211 check_cp1_registers(ctx
, fs
| ft
| fd
);
5212 GEN_LOAD_FREG_FTN(DT0
, fs
);
5213 GEN_LOAD_FREG_FTN(DT1
, ft
);
5214 gen_op_float_div_d();
5215 GEN_STORE_FTN_FREG(fd
, DT2
);
5220 check_cp1_registers(ctx
, fs
| fd
);
5221 GEN_LOAD_FREG_FTN(DT0
, fs
);
5222 gen_op_float_sqrt_d();
5223 GEN_STORE_FTN_FREG(fd
, DT2
);
5227 check_cp1_registers(ctx
, fs
| fd
);
5228 GEN_LOAD_FREG_FTN(DT0
, fs
);
5229 gen_op_float_abs_d();
5230 GEN_STORE_FTN_FREG(fd
, DT2
);
5234 check_cp1_registers(ctx
, fs
| fd
);
5235 GEN_LOAD_FREG_FTN(DT0
, fs
);
5236 gen_op_float_mov_d();
5237 GEN_STORE_FTN_FREG(fd
, DT2
);
5241 check_cp1_registers(ctx
, fs
| fd
);
5242 GEN_LOAD_FREG_FTN(DT0
, fs
);
5243 gen_op_float_chs_d();
5244 GEN_STORE_FTN_FREG(fd
, DT2
);
5248 check_cp1_64bitmode(ctx
);
5249 GEN_LOAD_FREG_FTN(DT0
, fs
);
5250 gen_op_float_roundl_d();
5251 GEN_STORE_FTN_FREG(fd
, DT2
);
5255 check_cp1_64bitmode(ctx
);
5256 GEN_LOAD_FREG_FTN(DT0
, fs
);
5257 gen_op_float_truncl_d();
5258 GEN_STORE_FTN_FREG(fd
, DT2
);
5262 check_cp1_64bitmode(ctx
);
5263 GEN_LOAD_FREG_FTN(DT0
, fs
);
5264 gen_op_float_ceill_d();
5265 GEN_STORE_FTN_FREG(fd
, DT2
);
5269 check_cp1_64bitmode(ctx
);
5270 GEN_LOAD_FREG_FTN(DT0
, fs
);
5271 gen_op_float_floorl_d();
5272 GEN_STORE_FTN_FREG(fd
, DT2
);
5276 check_cp1_registers(ctx
, fs
);
5277 GEN_LOAD_FREG_FTN(DT0
, fs
);
5278 gen_op_float_roundw_d();
5279 GEN_STORE_FTN_FREG(fd
, WT2
);
5283 check_cp1_registers(ctx
, fs
);
5284 GEN_LOAD_FREG_FTN(DT0
, fs
);
5285 gen_op_float_truncw_d();
5286 GEN_STORE_FTN_FREG(fd
, WT2
);
5290 check_cp1_registers(ctx
, fs
);
5291 GEN_LOAD_FREG_FTN(DT0
, fs
);
5292 gen_op_float_ceilw_d();
5293 GEN_STORE_FTN_FREG(fd
, WT2
);
5297 check_cp1_registers(ctx
, fs
);
5298 GEN_LOAD_FREG_FTN(DT0
, fs
);
5299 gen_op_float_floorw_d();
5300 GEN_STORE_FTN_FREG(fd
, WT2
);
5304 GEN_LOAD_REG_T0(ft
);
5305 GEN_LOAD_FREG_FTN(DT0
, fs
);
5306 GEN_LOAD_FREG_FTN(DT2
, fd
);
5307 gen_movcf_d(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5308 GEN_STORE_FTN_FREG(fd
, DT2
);
5312 GEN_LOAD_REG_T0(ft
);
5313 GEN_LOAD_FREG_FTN(DT0
, fs
);
5314 GEN_LOAD_FREG_FTN(DT2
, fd
);
5315 gen_op_float_movz_d();
5316 GEN_STORE_FTN_FREG(fd
, DT2
);
5320 GEN_LOAD_REG_T0(ft
);
5321 GEN_LOAD_FREG_FTN(DT0
, fs
);
5322 GEN_LOAD_FREG_FTN(DT2
, fd
);
5323 gen_op_float_movn_d();
5324 GEN_STORE_FTN_FREG(fd
, DT2
);
5328 check_cp1_registers(ctx
, fs
| fd
);
5329 GEN_LOAD_FREG_FTN(DT0
, fs
);
5330 gen_op_float_recip_d();
5331 GEN_STORE_FTN_FREG(fd
, DT2
);
5335 check_cp1_registers(ctx
, fs
| fd
);
5336 GEN_LOAD_FREG_FTN(DT0
, fs
);
5337 gen_op_float_rsqrt_d();
5338 GEN_STORE_FTN_FREG(fd
, DT2
);
5342 check_cp1_64bitmode(ctx
);
5343 GEN_LOAD_FREG_FTN(DT0
, fs
);
5344 GEN_LOAD_FREG_FTN(DT2
, ft
);
5345 gen_op_float_recip2_d();
5346 GEN_STORE_FTN_FREG(fd
, DT2
);
5350 check_cp1_64bitmode(ctx
);
5351 GEN_LOAD_FREG_FTN(DT0
, fs
);
5352 gen_op_float_recip1_d();
5353 GEN_STORE_FTN_FREG(fd
, DT2
);
5357 check_cp1_64bitmode(ctx
);
5358 GEN_LOAD_FREG_FTN(DT0
, fs
);
5359 gen_op_float_rsqrt1_d();
5360 GEN_STORE_FTN_FREG(fd
, DT2
);
5364 check_cp1_64bitmode(ctx
);
5365 GEN_LOAD_FREG_FTN(DT0
, fs
);
5366 GEN_LOAD_FREG_FTN(DT2
, ft
);
5367 gen_op_float_rsqrt2_d();
5368 GEN_STORE_FTN_FREG(fd
, DT2
);
5387 GEN_LOAD_FREG_FTN(DT0
, fs
);
5388 GEN_LOAD_FREG_FTN(DT1
, ft
);
5389 if (ctx
->opcode
& (1 << 6)) {
5390 check_cp1_64bitmode(ctx
);
5391 gen_cmpabs_d(func
-48, cc
);
5392 opn
= condnames_abs
[func
-48];
5394 check_cp1_registers(ctx
, fs
| ft
);
5395 gen_cmp_d(func
-48, cc
);
5396 opn
= condnames
[func
-48];
5400 check_cp1_registers(ctx
, fs
);
5401 GEN_LOAD_FREG_FTN(DT0
, fs
);
5402 gen_op_float_cvts_d();
5403 GEN_STORE_FTN_FREG(fd
, WT2
);
5407 check_cp1_registers(ctx
, fs
);
5408 GEN_LOAD_FREG_FTN(DT0
, fs
);
5409 gen_op_float_cvtw_d();
5410 GEN_STORE_FTN_FREG(fd
, WT2
);
5414 check_cp1_64bitmode(ctx
);
5415 GEN_LOAD_FREG_FTN(DT0
, fs
);
5416 gen_op_float_cvtl_d();
5417 GEN_STORE_FTN_FREG(fd
, DT2
);
5421 GEN_LOAD_FREG_FTN(WT0
, fs
);
5422 gen_op_float_cvts_w();
5423 GEN_STORE_FTN_FREG(fd
, WT2
);
5427 check_cp1_registers(ctx
, fd
);
5428 GEN_LOAD_FREG_FTN(WT0
, fs
);
5429 gen_op_float_cvtd_w();
5430 GEN_STORE_FTN_FREG(fd
, DT2
);
5434 check_cp1_64bitmode(ctx
);
5435 GEN_LOAD_FREG_FTN(DT0
, fs
);
5436 gen_op_float_cvts_l();
5437 GEN_STORE_FTN_FREG(fd
, WT2
);
5441 check_cp1_64bitmode(ctx
);
5442 GEN_LOAD_FREG_FTN(DT0
, fs
);
5443 gen_op_float_cvtd_l();
5444 GEN_STORE_FTN_FREG(fd
, DT2
);
5448 check_cp1_64bitmode(ctx
);
5449 GEN_LOAD_FREG_FTN(WT0
, fs
);
5450 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5451 gen_op_float_cvtps_pw();
5452 GEN_STORE_FTN_FREG(fd
, WT2
);
5453 GEN_STORE_FTN_FREG(fd
, WTH2
);
5457 check_cp1_64bitmode(ctx
);
5458 GEN_LOAD_FREG_FTN(WT0
, fs
);
5459 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5460 GEN_LOAD_FREG_FTN(WT1
, ft
);
5461 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5462 gen_op_float_add_ps();
5463 GEN_STORE_FTN_FREG(fd
, WT2
);
5464 GEN_STORE_FTN_FREG(fd
, WTH2
);
5468 check_cp1_64bitmode(ctx
);
5469 GEN_LOAD_FREG_FTN(WT0
, fs
);
5470 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5471 GEN_LOAD_FREG_FTN(WT1
, ft
);
5472 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5473 gen_op_float_sub_ps();
5474 GEN_STORE_FTN_FREG(fd
, WT2
);
5475 GEN_STORE_FTN_FREG(fd
, WTH2
);
5479 check_cp1_64bitmode(ctx
);
5480 GEN_LOAD_FREG_FTN(WT0
, fs
);
5481 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5482 GEN_LOAD_FREG_FTN(WT1
, ft
);
5483 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5484 gen_op_float_mul_ps();
5485 GEN_STORE_FTN_FREG(fd
, WT2
);
5486 GEN_STORE_FTN_FREG(fd
, WTH2
);
5490 check_cp1_64bitmode(ctx
);
5491 GEN_LOAD_FREG_FTN(WT0
, fs
);
5492 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5493 gen_op_float_abs_ps();
5494 GEN_STORE_FTN_FREG(fd
, WT2
);
5495 GEN_STORE_FTN_FREG(fd
, WTH2
);
5499 check_cp1_64bitmode(ctx
);
5500 GEN_LOAD_FREG_FTN(WT0
, fs
);
5501 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5502 gen_op_float_mov_ps();
5503 GEN_STORE_FTN_FREG(fd
, WT2
);
5504 GEN_STORE_FTN_FREG(fd
, WTH2
);
5508 check_cp1_64bitmode(ctx
);
5509 GEN_LOAD_FREG_FTN(WT0
, fs
);
5510 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5511 gen_op_float_chs_ps();
5512 GEN_STORE_FTN_FREG(fd
, WT2
);
5513 GEN_STORE_FTN_FREG(fd
, WTH2
);
5517 check_cp1_64bitmode(ctx
);
5518 GEN_LOAD_REG_T0(ft
);
5519 GEN_LOAD_FREG_FTN(WT0
, fs
);
5520 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5521 GEN_LOAD_FREG_FTN(WT2
, fd
);
5522 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5523 gen_movcf_ps(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
5524 GEN_STORE_FTN_FREG(fd
, WT2
);
5525 GEN_STORE_FTN_FREG(fd
, WTH2
);
5529 check_cp1_64bitmode(ctx
);
5530 GEN_LOAD_REG_T0(ft
);
5531 GEN_LOAD_FREG_FTN(WT0
, fs
);
5532 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5533 GEN_LOAD_FREG_FTN(WT2
, fd
);
5534 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5535 gen_op_float_movz_ps();
5536 GEN_STORE_FTN_FREG(fd
, WT2
);
5537 GEN_STORE_FTN_FREG(fd
, WTH2
);
5541 check_cp1_64bitmode(ctx
);
5542 GEN_LOAD_REG_T0(ft
);
5543 GEN_LOAD_FREG_FTN(WT0
, fs
);
5544 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5545 GEN_LOAD_FREG_FTN(WT2
, fd
);
5546 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5547 gen_op_float_movn_ps();
5548 GEN_STORE_FTN_FREG(fd
, WT2
);
5549 GEN_STORE_FTN_FREG(fd
, WTH2
);
5553 check_cp1_64bitmode(ctx
);
5554 GEN_LOAD_FREG_FTN(WT0
, ft
);
5555 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5556 GEN_LOAD_FREG_FTN(WT1
, fs
);
5557 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5558 gen_op_float_addr_ps();
5559 GEN_STORE_FTN_FREG(fd
, WT2
);
5560 GEN_STORE_FTN_FREG(fd
, WTH2
);
5564 check_cp1_64bitmode(ctx
);
5565 GEN_LOAD_FREG_FTN(WT0
, ft
);
5566 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5567 GEN_LOAD_FREG_FTN(WT1
, fs
);
5568 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5569 gen_op_float_mulr_ps();
5570 GEN_STORE_FTN_FREG(fd
, WT2
);
5571 GEN_STORE_FTN_FREG(fd
, WTH2
);
5575 check_cp1_64bitmode(ctx
);
5576 GEN_LOAD_FREG_FTN(WT0
, fs
);
5577 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5578 GEN_LOAD_FREG_FTN(WT2
, fd
);
5579 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5580 gen_op_float_recip2_ps();
5581 GEN_STORE_FTN_FREG(fd
, WT2
);
5582 GEN_STORE_FTN_FREG(fd
, WTH2
);
5586 check_cp1_64bitmode(ctx
);
5587 GEN_LOAD_FREG_FTN(WT0
, fs
);
5588 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5589 gen_op_float_recip1_ps();
5590 GEN_STORE_FTN_FREG(fd
, WT2
);
5591 GEN_STORE_FTN_FREG(fd
, WTH2
);
5595 check_cp1_64bitmode(ctx
);
5596 GEN_LOAD_FREG_FTN(WT0
, fs
);
5597 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5598 gen_op_float_rsqrt1_ps();
5599 GEN_STORE_FTN_FREG(fd
, WT2
);
5600 GEN_STORE_FTN_FREG(fd
, WTH2
);
5604 check_cp1_64bitmode(ctx
);
5605 GEN_LOAD_FREG_FTN(WT0
, fs
);
5606 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5607 GEN_LOAD_FREG_FTN(WT2
, ft
);
5608 GEN_LOAD_FREG_FTN(WTH2
, ft
);
5609 gen_op_float_rsqrt2_ps();
5610 GEN_STORE_FTN_FREG(fd
, WT2
);
5611 GEN_STORE_FTN_FREG(fd
, WTH2
);
5615 check_cp1_64bitmode(ctx
);
5616 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5617 gen_op_float_cvts_pu();
5618 GEN_STORE_FTN_FREG(fd
, WT2
);
5622 check_cp1_64bitmode(ctx
);
5623 GEN_LOAD_FREG_FTN(WT0
, fs
);
5624 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5625 gen_op_float_cvtpw_ps();
5626 GEN_STORE_FTN_FREG(fd
, WT2
);
5627 GEN_STORE_FTN_FREG(fd
, WTH2
);
5631 check_cp1_64bitmode(ctx
);
5632 GEN_LOAD_FREG_FTN(WT0
, fs
);
5633 gen_op_float_cvts_pl();
5634 GEN_STORE_FTN_FREG(fd
, WT2
);
5638 check_cp1_64bitmode(ctx
);
5639 GEN_LOAD_FREG_FTN(WT0
, fs
);
5640 GEN_LOAD_FREG_FTN(WT1
, ft
);
5641 gen_op_float_pll_ps();
5642 GEN_STORE_FTN_FREG(fd
, DT2
);
5646 check_cp1_64bitmode(ctx
);
5647 GEN_LOAD_FREG_FTN(WT0
, fs
);
5648 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5649 gen_op_float_plu_ps();
5650 GEN_STORE_FTN_FREG(fd
, DT2
);
5654 check_cp1_64bitmode(ctx
);
5655 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5656 GEN_LOAD_FREG_FTN(WT1
, ft
);
5657 gen_op_float_pul_ps();
5658 GEN_STORE_FTN_FREG(fd
, DT2
);
5662 check_cp1_64bitmode(ctx
);
5663 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5664 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5665 gen_op_float_puu_ps();
5666 GEN_STORE_FTN_FREG(fd
, DT2
);
5685 check_cp1_64bitmode(ctx
);
5686 GEN_LOAD_FREG_FTN(WT0
, fs
);
5687 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5688 GEN_LOAD_FREG_FTN(WT1
, ft
);
5689 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5690 if (ctx
->opcode
& (1 << 6)) {
5691 gen_cmpabs_ps(func
-48, cc
);
5692 opn
= condnames_abs
[func
-48];
5694 gen_cmp_ps(func
-48, cc
);
5695 opn
= condnames
[func
-48];
5700 generate_exception (ctx
, EXCP_RI
);
5705 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
5708 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
5711 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
5716 /* Coprocessor 3 (FPU) */
5717 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
5718 int fd
, int fs
, int base
, int index
)
5720 const char *opn
= "extended float load/store";
5723 /* All of those work only on 64bit FPUs. */
5724 check_cp1_64bitmode(ctx
);
5729 GEN_LOAD_REG_T0(index
);
5730 } else if (index
== 0) {
5731 GEN_LOAD_REG_T0(base
);
5733 GEN_LOAD_REG_T0(base
);
5734 GEN_LOAD_REG_T1(index
);
5737 /* Don't do NOP if destination is zero: we must perform the actual
5742 GEN_STORE_FTN_FREG(fd
, WT0
);
5747 GEN_STORE_FTN_FREG(fd
, DT0
);
5752 GEN_STORE_FTN_FREG(fd
, DT0
);
5756 GEN_LOAD_FREG_FTN(WT0
, fs
);
5762 GEN_LOAD_FREG_FTN(DT0
, fs
);
5768 GEN_LOAD_FREG_FTN(DT0
, fs
);
5775 generate_exception(ctx
, EXCP_RI
);
5778 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
5779 regnames
[index
], regnames
[base
]);
5782 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
5783 int fd
, int fr
, int fs
, int ft
)
5785 const char *opn
= "flt3_arith";
5787 /* All of those work only on 64bit FPUs. */
5788 check_cp1_64bitmode(ctx
);
5791 GEN_LOAD_REG_T0(fr
);
5792 GEN_LOAD_FREG_FTN(DT0
, fs
);
5793 GEN_LOAD_FREG_FTN(DT1
, ft
);
5794 gen_op_float_alnv_ps();
5795 GEN_STORE_FTN_FREG(fd
, DT2
);
5799 GEN_LOAD_FREG_FTN(WT0
, fs
);
5800 GEN_LOAD_FREG_FTN(WT1
, ft
);
5801 GEN_LOAD_FREG_FTN(WT2
, fr
);
5802 gen_op_float_muladd_s();
5803 GEN_STORE_FTN_FREG(fd
, WT2
);
5807 GEN_LOAD_FREG_FTN(DT0
, fs
);
5808 GEN_LOAD_FREG_FTN(DT1
, ft
);
5809 GEN_LOAD_FREG_FTN(DT2
, fr
);
5810 gen_op_float_muladd_d();
5811 GEN_STORE_FTN_FREG(fd
, DT2
);
5815 GEN_LOAD_FREG_FTN(WT0
, fs
);
5816 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5817 GEN_LOAD_FREG_FTN(WT1
, ft
);
5818 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5819 GEN_LOAD_FREG_FTN(WT2
, fr
);
5820 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5821 gen_op_float_muladd_ps();
5822 GEN_STORE_FTN_FREG(fd
, WT2
);
5823 GEN_STORE_FTN_FREG(fd
, WTH2
);
5827 GEN_LOAD_FREG_FTN(WT0
, fs
);
5828 GEN_LOAD_FREG_FTN(WT1
, ft
);
5829 GEN_LOAD_FREG_FTN(WT2
, fr
);
5830 gen_op_float_mulsub_s();
5831 GEN_STORE_FTN_FREG(fd
, WT2
);
5835 GEN_LOAD_FREG_FTN(DT0
, fs
);
5836 GEN_LOAD_FREG_FTN(DT1
, ft
);
5837 GEN_LOAD_FREG_FTN(DT2
, fr
);
5838 gen_op_float_mulsub_d();
5839 GEN_STORE_FTN_FREG(fd
, DT2
);
5843 GEN_LOAD_FREG_FTN(WT0
, fs
);
5844 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5845 GEN_LOAD_FREG_FTN(WT1
, ft
);
5846 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5847 GEN_LOAD_FREG_FTN(WT2
, fr
);
5848 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5849 gen_op_float_mulsub_ps();
5850 GEN_STORE_FTN_FREG(fd
, WT2
);
5851 GEN_STORE_FTN_FREG(fd
, WTH2
);
5855 GEN_LOAD_FREG_FTN(WT0
, fs
);
5856 GEN_LOAD_FREG_FTN(WT1
, ft
);
5857 GEN_LOAD_FREG_FTN(WT2
, fr
);
5858 gen_op_float_nmuladd_s();
5859 GEN_STORE_FTN_FREG(fd
, WT2
);
5863 GEN_LOAD_FREG_FTN(DT0
, fs
);
5864 GEN_LOAD_FREG_FTN(DT1
, ft
);
5865 GEN_LOAD_FREG_FTN(DT2
, fr
);
5866 gen_op_float_nmuladd_d();
5867 GEN_STORE_FTN_FREG(fd
, DT2
);
5871 GEN_LOAD_FREG_FTN(WT0
, fs
);
5872 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5873 GEN_LOAD_FREG_FTN(WT1
, ft
);
5874 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5875 GEN_LOAD_FREG_FTN(WT2
, fr
);
5876 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5877 gen_op_float_nmuladd_ps();
5878 GEN_STORE_FTN_FREG(fd
, WT2
);
5879 GEN_STORE_FTN_FREG(fd
, WTH2
);
5883 GEN_LOAD_FREG_FTN(WT0
, fs
);
5884 GEN_LOAD_FREG_FTN(WT1
, ft
);
5885 GEN_LOAD_FREG_FTN(WT2
, fr
);
5886 gen_op_float_nmulsub_s();
5887 GEN_STORE_FTN_FREG(fd
, WT2
);
5891 GEN_LOAD_FREG_FTN(DT0
, fs
);
5892 GEN_LOAD_FREG_FTN(DT1
, ft
);
5893 GEN_LOAD_FREG_FTN(DT2
, fr
);
5894 gen_op_float_nmulsub_d();
5895 GEN_STORE_FTN_FREG(fd
, DT2
);
5899 GEN_LOAD_FREG_FTN(WT0
, fs
);
5900 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5901 GEN_LOAD_FREG_FTN(WT1
, ft
);
5902 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5903 GEN_LOAD_FREG_FTN(WT2
, fr
);
5904 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5905 gen_op_float_nmulsub_ps();
5906 GEN_STORE_FTN_FREG(fd
, WT2
);
5907 GEN_STORE_FTN_FREG(fd
, WTH2
);
5912 generate_exception (ctx
, EXCP_RI
);
5915 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
5916 fregnames
[fs
], fregnames
[ft
]);
5919 /* ISA extensions (ASEs) */
5920 /* MIPS16 extension to MIPS32 */
5921 /* SmartMIPS extension to MIPS32 */
5923 #if defined(TARGET_MIPS64)
5925 /* MDMX extension to MIPS64 */
5929 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
5933 uint32_t op
, op1
, op2
;
5936 /* make sure instructions are on a word boundary */
5937 if (ctx
->pc
& 0x3) {
5938 env
->CP0_BadVAddr
= ctx
->pc
;
5939 generate_exception(ctx
, EXCP_AdEL
);
5943 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
5945 /* Handle blikely not taken case */
5946 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
5947 l1
= gen_new_label();
5949 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
5950 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
5953 op
= MASK_OP_MAJOR(ctx
->opcode
);
5954 rs
= (ctx
->opcode
>> 21) & 0x1f;
5955 rt
= (ctx
->opcode
>> 16) & 0x1f;
5956 rd
= (ctx
->opcode
>> 11) & 0x1f;
5957 sa
= (ctx
->opcode
>> 6) & 0x1f;
5958 imm
= (int16_t)ctx
->opcode
;
5961 op1
= MASK_SPECIAL(ctx
->opcode
);
5963 case OPC_SLL
: /* Arithmetic with immediate */
5964 case OPC_SRL
... OPC_SRA
:
5965 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
5967 case OPC_MOVZ
... OPC_MOVN
:
5968 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5969 case OPC_SLLV
: /* Arithmetic */
5970 case OPC_SRLV
... OPC_SRAV
:
5971 case OPC_ADD
... OPC_NOR
:
5972 case OPC_SLT
... OPC_SLTU
:
5973 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
5975 case OPC_MULT
... OPC_DIVU
:
5976 gen_muldiv(ctx
, op1
, rs
, rt
);
5978 case OPC_JR
... OPC_JALR
:
5979 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
5981 case OPC_TGE
... OPC_TEQ
: /* Traps */
5983 gen_trap(ctx
, op1
, rs
, rt
, -1);
5985 case OPC_MFHI
: /* Move from HI/LO */
5987 gen_HILO(ctx
, op1
, rd
);
5990 case OPC_MTLO
: /* Move to HI/LO */
5991 gen_HILO(ctx
, op1
, rs
);
5993 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
5994 #ifdef MIPS_STRICT_STANDARD
5995 MIPS_INVAL("PMON / selsl");
5996 generate_exception(ctx
, EXCP_RI
);
6002 generate_exception(ctx
, EXCP_SYSCALL
);
6005 generate_exception(ctx
, EXCP_BREAK
);
6008 #ifdef MIPS_STRICT_STANDARD
6010 generate_exception(ctx
, EXCP_RI
);
6012 /* Implemented as RI exception for now. */
6013 MIPS_INVAL("spim (unofficial)");
6014 generate_exception(ctx
, EXCP_RI
);
6022 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6023 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6024 save_cpu_state(ctx
, 1);
6025 check_cp1_enabled(ctx
);
6026 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
6027 (ctx
->opcode
>> 16) & 1);
6029 generate_exception_err(ctx
, EXCP_CpU
, 1);
6033 #if defined(TARGET_MIPS64)
6034 /* MIPS64 specific opcodes */
6036 case OPC_DSRL
... OPC_DSRA
:
6038 case OPC_DSRL32
... OPC_DSRA32
:
6039 check_insn(env
, ctx
, ISA_MIPS3
);
6041 gen_arith_imm(env
, ctx
, op1
, rd
, rt
, sa
);
6044 case OPC_DSRLV
... OPC_DSRAV
:
6045 case OPC_DADD
... OPC_DSUBU
:
6046 check_insn(env
, ctx
, ISA_MIPS3
);
6048 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6050 case OPC_DMULT
... OPC_DDIVU
:
6051 check_insn(env
, ctx
, ISA_MIPS3
);
6053 gen_muldiv(ctx
, op1
, rs
, rt
);
6056 default: /* Invalid */
6057 MIPS_INVAL("special");
6058 generate_exception(ctx
, EXCP_RI
);
6063 op1
= MASK_SPECIAL2(ctx
->opcode
);
6065 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
6066 case OPC_MSUB
... OPC_MSUBU
:
6067 check_insn(env
, ctx
, ISA_MIPS32
);
6068 gen_muldiv(ctx
, op1
, rs
, rt
);
6071 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
6073 case OPC_CLZ
... OPC_CLO
:
6074 check_insn(env
, ctx
, ISA_MIPS32
);
6075 gen_cl(ctx
, op1
, rd
, rs
);
6078 /* XXX: not clear which exception should be raised
6079 * when in debug mode...
6081 check_insn(env
, ctx
, ISA_MIPS32
);
6082 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
6083 generate_exception(ctx
, EXCP_DBp
);
6085 generate_exception(ctx
, EXCP_DBp
);
6089 #if defined(TARGET_MIPS64)
6090 case OPC_DCLZ
... OPC_DCLO
:
6091 check_insn(env
, ctx
, ISA_MIPS64
);
6093 gen_cl(ctx
, op1
, rd
, rs
);
6096 default: /* Invalid */
6097 MIPS_INVAL("special2");
6098 generate_exception(ctx
, EXCP_RI
);
6103 op1
= MASK_SPECIAL3(ctx
->opcode
);
6107 check_insn(env
, ctx
, ISA_MIPS32R2
);
6108 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
6111 check_insn(env
, ctx
, ISA_MIPS32R2
);
6112 op2
= MASK_BSHFL(ctx
->opcode
);
6115 GEN_LOAD_REG_T1(rt
);
6119 GEN_LOAD_REG_T1(rt
);
6123 GEN_LOAD_REG_T1(rt
);
6126 default: /* Invalid */
6127 MIPS_INVAL("bshfl");
6128 generate_exception(ctx
, EXCP_RI
);
6131 GEN_STORE_T0_REG(rd
);
6134 check_insn(env
, ctx
, ISA_MIPS32R2
);
6137 save_cpu_state(ctx
, 1);
6138 gen_op_rdhwr_cpunum();
6141 save_cpu_state(ctx
, 1);
6142 gen_op_rdhwr_synci_step();
6145 save_cpu_state(ctx
, 1);
6149 save_cpu_state(ctx
, 1);
6150 gen_op_rdhwr_ccres();
6153 #if defined (CONFIG_USER_ONLY)
6157 default: /* Invalid */
6158 MIPS_INVAL("rdhwr");
6159 generate_exception(ctx
, EXCP_RI
);
6162 GEN_STORE_T0_REG(rt
);
6165 check_insn(env
, ctx
, ASE_MT
);
6166 GEN_LOAD_REG_T0(rt
);
6167 GEN_LOAD_REG_T1(rs
);
6171 check_insn(env
, ctx
, ASE_MT
);
6172 GEN_LOAD_REG_T0(rs
);
6174 GEN_STORE_T0_REG(rd
);
6176 #if defined(TARGET_MIPS64)
6177 case OPC_DEXTM
... OPC_DEXT
:
6178 case OPC_DINSM
... OPC_DINS
:
6179 check_insn(env
, ctx
, ISA_MIPS64R2
);
6181 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
6184 check_insn(env
, ctx
, ISA_MIPS64R2
);
6186 op2
= MASK_DBSHFL(ctx
->opcode
);
6189 GEN_LOAD_REG_T1(rt
);
6193 GEN_LOAD_REG_T1(rt
);
6196 default: /* Invalid */
6197 MIPS_INVAL("dbshfl");
6198 generate_exception(ctx
, EXCP_RI
);
6201 GEN_STORE_T0_REG(rd
);
6204 default: /* Invalid */
6205 MIPS_INVAL("special3");
6206 generate_exception(ctx
, EXCP_RI
);
6211 op1
= MASK_REGIMM(ctx
->opcode
);
6213 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
6214 case OPC_BLTZAL
... OPC_BGEZALL
:
6215 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
6217 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
6219 gen_trap(ctx
, op1
, rs
, -1, imm
);
6222 check_insn(env
, ctx
, ISA_MIPS32R2
);
6225 default: /* Invalid */
6226 MIPS_INVAL("regimm");
6227 generate_exception(ctx
, EXCP_RI
);
6232 check_cp0_enabled(ctx
);
6233 op1
= MASK_CP0(ctx
->opcode
);
6239 #if defined(TARGET_MIPS64)
6243 gen_cp0(env
, ctx
, op1
, rt
, rd
);
6245 case OPC_C0_FIRST
... OPC_C0_LAST
:
6246 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
6249 op2
= MASK_MFMC0(ctx
->opcode
);
6252 check_insn(env
, ctx
, ASE_MT
);
6256 check_insn(env
, ctx
, ASE_MT
);
6260 check_insn(env
, ctx
, ASE_MT
);
6264 check_insn(env
, ctx
, ASE_MT
);
6268 check_insn(env
, ctx
, ISA_MIPS32R2
);
6269 save_cpu_state(ctx
, 1);
6271 /* Stop translation as we may have switched the execution mode */
6272 ctx
->bstate
= BS_STOP
;
6275 check_insn(env
, ctx
, ISA_MIPS32R2
);
6276 save_cpu_state(ctx
, 1);
6278 /* Stop translation as we may have switched the execution mode */
6279 ctx
->bstate
= BS_STOP
;
6281 default: /* Invalid */
6282 MIPS_INVAL("mfmc0");
6283 generate_exception(ctx
, EXCP_RI
);
6286 GEN_STORE_T0_REG(rt
);
6289 check_insn(env
, ctx
, ISA_MIPS32R2
);
6290 GEN_LOAD_SRSREG_TN(T0
, rt
);
6291 GEN_STORE_T0_REG(rd
);
6294 check_insn(env
, ctx
, ISA_MIPS32R2
);
6295 GEN_LOAD_REG_T0(rt
);
6296 GEN_STORE_TN_SRSREG(rd
, T0
);
6300 generate_exception(ctx
, EXCP_RI
);
6304 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
6305 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
6307 case OPC_J
... OPC_JAL
: /* Jump */
6308 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
6309 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
6311 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
6312 case OPC_BEQL
... OPC_BGTZL
:
6313 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
6315 case OPC_LB
... OPC_LWR
: /* Load and stores */
6316 case OPC_SB
... OPC_SW
:
6320 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6323 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
6327 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
6331 /* Floating point (COP1). */
6336 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6337 save_cpu_state(ctx
, 1);
6338 check_cp1_enabled(ctx
);
6339 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
6341 generate_exception_err(ctx
, EXCP_CpU
, 1);
6346 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6347 save_cpu_state(ctx
, 1);
6348 check_cp1_enabled(ctx
);
6349 op1
= MASK_CP1(ctx
->opcode
);
6353 check_insn(env
, ctx
, ISA_MIPS32R2
);
6358 gen_cp1(ctx
, op1
, rt
, rd
);
6360 #if defined(TARGET_MIPS64)
6363 check_insn(env
, ctx
, ISA_MIPS3
);
6364 gen_cp1(ctx
, op1
, rt
, rd
);
6369 check_insn(env
, ctx
, ASE_MIPS3D
);
6372 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
6373 (rt
>> 2) & 0x7, imm
<< 2);
6380 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
6385 generate_exception (ctx
, EXCP_RI
);
6389 generate_exception_err(ctx
, EXCP_CpU
, 1);
6399 /* COP2: Not implemented. */
6400 generate_exception_err(ctx
, EXCP_CpU
, 2);
6404 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
6405 save_cpu_state(ctx
, 1);
6406 check_cp1_enabled(ctx
);
6407 op1
= MASK_CP3(ctx
->opcode
);
6415 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
6433 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
6437 generate_exception (ctx
, EXCP_RI
);
6441 generate_exception_err(ctx
, EXCP_CpU
, 1);
6445 #if defined(TARGET_MIPS64)
6446 /* MIPS64 opcodes */
6448 case OPC_LDL
... OPC_LDR
:
6449 case OPC_SDL
... OPC_SDR
:
6454 check_insn(env
, ctx
, ISA_MIPS3
);
6456 gen_ldst(ctx
, op
, rt
, rs
, imm
);
6458 case OPC_DADDI
... OPC_DADDIU
:
6459 check_insn(env
, ctx
, ISA_MIPS3
);
6461 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
6465 check_insn(env
, ctx
, ASE_MIPS16
);
6466 /* MIPS16: Not implemented. */
6468 check_insn(env
, ctx
, ASE_MDMX
);
6469 /* MDMX: Not implemented. */
6470 default: /* Invalid */
6471 MIPS_INVAL("major opcode");
6472 generate_exception(ctx
, EXCP_RI
);
6475 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
6476 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
6477 /* Branches completion */
6478 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
6479 ctx
->bstate
= BS_BRANCH
;
6480 save_cpu_state(ctx
, 0);
6483 /* unconditional branch */
6484 MIPS_DEBUG("unconditional branch");
6485 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6488 /* blikely taken case */
6489 MIPS_DEBUG("blikely branch taken");
6490 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6493 /* Conditional branch */
6494 MIPS_DEBUG("conditional branch");
6497 l1
= gen_new_label();
6499 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
6501 gen_goto_tb(ctx
, 0, ctx
->btarget
);
6505 /* unconditional branch to register */
6506 MIPS_DEBUG("branch to register");
6512 MIPS_DEBUG("unknown branch");
6518 static always_inline
int
6519 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
6523 target_ulong pc_start
;
6524 uint16_t *gen_opc_end
;
6527 if (search_pc
&& loglevel
)
6528 fprintf (logfile
, "search pc %d\n", search_pc
);
6531 gen_opc_ptr
= gen_opc_buf
;
6532 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6533 gen_opparam_ptr
= gen_opparam_buf
;
6538 ctx
.bstate
= BS_NONE
;
6539 /* Restore delay slot state from the tb context. */
6540 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
6541 restore_cpu_state(env
, &ctx
);
6542 #if defined(CONFIG_USER_ONLY)
6543 ctx
.mem_idx
= MIPS_HFLAG_UM
;
6545 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
6548 if (loglevel
& CPU_LOG_TB_CPU
) {
6549 fprintf(logfile
, "------------------------------------------------\n");
6550 /* FIXME: This may print out stale hflags from env... */
6551 cpu_dump_state(env
, logfile
, fprintf
, 0);
6554 #ifdef MIPS_DEBUG_DISAS
6555 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6556 fprintf(logfile
, "\ntb %p idx %d hflags %04x\n",
6557 tb
, ctx
.mem_idx
, ctx
.hflags
);
6559 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6560 if (env
->nb_breakpoints
> 0) {
6561 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
6562 if (env
->breakpoints
[j
] == ctx
.pc
) {
6563 save_cpu_state(&ctx
, 1);
6564 ctx
.bstate
= BS_BRANCH
;
6566 /* Include the breakpoint location or the tb won't
6567 * be flushed when it must be. */
6569 goto done_generating
;
6575 j
= gen_opc_ptr
- gen_opc_buf
;
6579 gen_opc_instr_start
[lj
++] = 0;
6581 gen_opc_pc
[lj
] = ctx
.pc
;
6582 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
6583 gen_opc_instr_start
[lj
] = 1;
6585 ctx
.opcode
= ldl_code(ctx
.pc
);
6586 decode_opc(env
, &ctx
);
6589 if (env
->singlestep_enabled
)
6592 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
6595 #if defined (MIPS_SINGLE_STEP)
6599 if (env
->singlestep_enabled
) {
6600 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
6603 switch (ctx
.bstate
) {
6605 gen_op_interrupt_restart();
6606 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6609 save_cpu_state(&ctx
, 0);
6610 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6613 gen_op_interrupt_restart();
6623 ctx
.last_T0_store
= NULL
;
6624 *gen_opc_ptr
= INDEX_op_end
;
6626 j
= gen_opc_ptr
- gen_opc_buf
;
6629 gen_opc_instr_start
[lj
++] = 0;
6631 tb
->size
= ctx
.pc
- pc_start
;
6634 #if defined MIPS_DEBUG_DISAS
6635 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6636 fprintf(logfile
, "\n");
6638 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6639 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6640 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
6641 fprintf(logfile
, "\n");
6643 if (loglevel
& CPU_LOG_TB_OP
) {
6644 fprintf(logfile
, "OP:\n");
6645 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6646 fprintf(logfile
, "\n");
6648 if (loglevel
& CPU_LOG_TB_CPU
) {
6649 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
6656 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6658 return gen_intermediate_code_internal(env
, tb
, 0);
6661 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6663 return gen_intermediate_code_internal(env
, tb
, 1);
6666 void fpu_dump_state(CPUState
*env
, FILE *f
,
6667 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6671 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
6673 #define printfpr(fp) \
6676 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
6677 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
6678 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
6681 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
6682 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
6683 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
6684 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
6685 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
6690 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
6691 env
->fpu
->fcr0
, env
->fpu
->fcr31
, is_fpu64
, env
->fpu
->fp_status
,
6692 get_float_exception_flags(&env
->fpu
->fp_status
));
6693 fpu_fprintf(f
, "FT0: "); printfpr(&env
->fpu
->ft0
);
6694 fpu_fprintf(f
, "FT1: "); printfpr(&env
->fpu
->ft1
);
6695 fpu_fprintf(f
, "FT2: "); printfpr(&env
->fpu
->ft2
);
6696 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
6697 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
6698 printfpr(&env
->fpu
->fpr
[i
]);
6704 void dump_fpu (CPUState
*env
)
6707 fprintf(logfile
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6708 env
->PC
[env
->current_tc
], env
->HI
[0][env
->current_tc
], env
->LO
[0][env
->current_tc
], env
->hflags
, env
->btarget
, env
->bcond
);
6709 fpu_dump_state(env
, logfile
, fprintf
, 0);
6713 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6714 /* Debug help: The architecture requires 32bit code to maintain proper
6715 sign-extened values on 64bit machines. */
6717 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
6719 void cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
6720 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6725 if (!SIGN_EXT_P(env
->PC
[env
->current_tc
]))
6726 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->PC
[env
->current_tc
]);
6727 if (!SIGN_EXT_P(env
->HI
[env
->current_tc
]))
6728 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->HI
[env
->current_tc
]);
6729 if (!SIGN_EXT_P(env
->LO
[env
->current_tc
]))
6730 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->LO
[env
->current_tc
]);
6731 if (!SIGN_EXT_P(env
->btarget
))
6732 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
6734 for (i
= 0; i
< 32; i
++) {
6735 if (!SIGN_EXT_P(env
->gpr
[i
][env
->current_tc
]))
6736 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->gpr
[i
][env
->current_tc
]);
6739 if (!SIGN_EXT_P(env
->CP0_EPC
))
6740 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
6741 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
6742 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
6746 void cpu_dump_state (CPUState
*env
, FILE *f
,
6747 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6752 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6753 env
->PC
[env
->current_tc
], env
->HI
[env
->current_tc
], env
->LO
[env
->current_tc
], env
->hflags
, env
->btarget
, env
->bcond
);
6754 for (i
= 0; i
< 32; i
++) {
6756 cpu_fprintf(f
, "GPR%02d:", i
);
6757 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->gpr
[i
][env
->current_tc
]);
6759 cpu_fprintf(f
, "\n");
6762 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
6763 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
6764 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
6765 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
6766 if (env
->hflags
& MIPS_HFLAG_FPU
)
6767 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
6768 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6769 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
6773 #include "translate_init.c"
6775 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
6778 const mips_def_t
*def
;
6780 def
= cpu_mips_find_by_name(cpu_model
);
6783 env
= qemu_mallocz(sizeof(CPUMIPSState
));
6786 env
->cpu_model
= def
;
6789 env
->cpu_model_str
= cpu_model
;
6794 void cpu_reset (CPUMIPSState
*env
)
6796 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
6801 #if !defined(CONFIG_USER_ONLY)
6802 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
6803 /* If the exception was raised from a delay slot,
6804 * come back to the jump. */
6805 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
] - 4;
6807 env
->CP0_ErrorEPC
= env
->PC
[env
->current_tc
];
6809 env
->PC
[env
->current_tc
] = (int32_t)0xBFC00000;
6811 /* SMP not implemented */
6812 env
->CP0_EBase
= 0x80000000;
6813 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
6814 /* vectored interrupts not implemented, timer on int 7,
6815 no performance counters. */
6816 env
->CP0_IntCtl
= 0xe0000000;
6820 for (i
= 0; i
< 7; i
++) {
6821 env
->CP0_WatchLo
[i
] = 0;
6822 env
->CP0_WatchHi
[i
] = 0x80000000;
6824 env
->CP0_WatchLo
[7] = 0;
6825 env
->CP0_WatchHi
[7] = 0;
6827 /* Count register increments in debug mode, EJTAG version 1 */
6828 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
6830 env
->exception_index
= EXCP_NONE
;
6831 #if defined(CONFIG_USER_ONLY)
6832 env
->hflags
= MIPS_HFLAG_UM
;
6833 env
->user_mode_only
= 1;
6835 env
->hflags
= MIPS_HFLAG_CP0
;
6837 cpu_mips_register(env
, env
->cpu_model
);