target-mips/op.c

   1 /*
   2  *  MIPS emulation micro-operations for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2006 Marius Groeger (FPU operations)
   6  *  Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include "config.h"
  24 #include "exec.h"
  25 #include "host-utils.h"
  26
  27 #ifndef CALL_FROM_TB0
  28 #define CALL_FROM_TB0(func) func()
  29 #endif
  30 #ifndef CALL_FROM_TB1
  31 #define CALL_FROM_TB1(func, arg0) func(arg0)
  32 #endif
  33 #ifndef CALL_FROM_TB1_CONST16
  34 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
  35 #endif
  36 #ifndef CALL_FROM_TB2
  37 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
  38 #endif
  39 #ifndef CALL_FROM_TB2_CONST16
  40 #define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
  41         CALL_FROM_TB2(func, arg0, arg1)
  42 #endif
  43 #ifndef CALL_FROM_TB3
  44 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
  45 #endif
  46 #ifndef CALL_FROM_TB4
  47 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
  48         func(arg0, arg1, arg2, arg3)
  49 #endif
  50
  51 #define REG 1
  52 #include "op_template.c"
  53 #undef REG
  54 #define REG 2
  55 #include "op_template.c"
  56 #undef REG
  57 #define REG 3
  58 #include "op_template.c"
  59 #undef REG
  60 #define REG 4
  61 #include "op_template.c"
  62 #undef REG
  63 #define REG 5
  64 #include "op_template.c"
  65 #undef REG
  66 #define REG 6
  67 #include "op_template.c"
  68 #undef REG
  69 #define REG 7
  70 #include "op_template.c"
  71 #undef REG
  72 #define REG 8
  73 #include "op_template.c"
  74 #undef REG
  75 #define REG 9
  76 #include "op_template.c"
  77 #undef REG
  78 #define REG 10
  79 #include "op_template.c"
  80 #undef REG
  81 #define REG 11
  82 #include "op_template.c"
  83 #undef REG
  84 #define REG 12
  85 #include "op_template.c"
  86 #undef REG
  87 #define REG 13
  88 #include "op_template.c"
  89 #undef REG
  90 #define REG 14
  91 #include "op_template.c"
  92 #undef REG
  93 #define REG 15
  94 #include "op_template.c"
  95 #undef REG
  96 #define REG 16
  97 #include "op_template.c"
  98 #undef REG
  99 #define REG 17
 100 #include "op_template.c"
 101 #undef REG
 102 #define REG 18
 103 #include "op_template.c"
 104 #undef REG
 105 #define REG 19
 106 #include "op_template.c"
 107 #undef REG
 108 #define REG 20
 109 #include "op_template.c"
 110 #undef REG
 111 #define REG 21
 112 #include "op_template.c"
 113 #undef REG
 114 #define REG 22
 115 #include "op_template.c"
 116 #undef REG
 117 #define REG 23
 118 #include "op_template.c"
 119 #undef REG
 120 #define REG 24
 121 #include "op_template.c"
 122 #undef REG
 123 #define REG 25
 124 #include "op_template.c"
 125 #undef REG
 126 #define REG 26
 127 #include "op_template.c"
 128 #undef REG
 129 #define REG 27
 130 #include "op_template.c"
 131 #undef REG
 132 #define REG 28
 133 #include "op_template.c"
 134 #undef REG
 135 #define REG 29
 136 #include "op_template.c"
 137 #undef REG
 138 #define REG 30
 139 #include "op_template.c"
 140 #undef REG
 141 #define REG 31
 142 #include "op_template.c"
 143 #undef REG
 144
 145 #define TN
 146 #include "op_template.c"
 147 #undef TN
 148
 149 #define FREG 0
 150 #include "fop_template.c"
 151 #undef FREG
 152 #define FREG 1
 153 #include "fop_template.c"
 154 #undef FREG
 155 #define FREG 2
 156 #include "fop_template.c"
 157 #undef FREG
 158 #define FREG 3
 159 #include "fop_template.c"
 160 #undef FREG
 161 #define FREG 4
 162 #include "fop_template.c"
 163 #undef FREG
 164 #define FREG 5
 165 #include "fop_template.c"
 166 #undef FREG
 167 #define FREG 6
 168 #include "fop_template.c"
 169 #undef FREG
 170 #define FREG 7
 171 #include "fop_template.c"
 172 #undef FREG
 173 #define FREG 8
 174 #include "fop_template.c"
 175 #undef FREG
 176 #define FREG 9
 177 #include "fop_template.c"
 178 #undef FREG
 179 #define FREG 10
 180 #include "fop_template.c"
 181 #undef FREG
 182 #define FREG 11
 183 #include "fop_template.c"
 184 #undef FREG
 185 #define FREG 12
 186 #include "fop_template.c"
 187 #undef FREG
 188 #define FREG 13
 189 #include "fop_template.c"
 190 #undef FREG
 191 #define FREG 14
 192 #include "fop_template.c"
 193 #undef FREG
 194 #define FREG 15
 195 #include "fop_template.c"
 196 #undef FREG
 197 #define FREG 16
 198 #include "fop_template.c"
 199 #undef FREG
 200 #define FREG 17
 201 #include "fop_template.c"
 202 #undef FREG
 203 #define FREG 18
 204 #include "fop_template.c"
 205 #undef FREG
 206 #define FREG 19
 207 #include "fop_template.c"
 208 #undef FREG
 209 #define FREG 20
 210 #include "fop_template.c"
 211 #undef FREG
 212 #define FREG 21
 213 #include "fop_template.c"
 214 #undef FREG
 215 #define FREG 22
 216 #include "fop_template.c"
 217 #undef FREG
 218 #define FREG 23
 219 #include "fop_template.c"
 220 #undef FREG
 221 #define FREG 24
 222 #include "fop_template.c"
 223 #undef FREG
 224 #define FREG 25
 225 #include "fop_template.c"
 226 #undef FREG
 227 #define FREG 26
 228 #include "fop_template.c"
 229 #undef FREG
 230 #define FREG 27
 231 #include "fop_template.c"
 232 #undef FREG
 233 #define FREG 28
 234 #include "fop_template.c"
 235 #undef FREG
 236 #define FREG 29
 237 #include "fop_template.c"
 238 #undef FREG
 239 #define FREG 30
 240 #include "fop_template.c"
 241 #undef FREG
 242 #define FREG 31
 243 #include "fop_template.c"
 244 #undef FREG
 245
 246 #define FTN
 247 #include "fop_template.c"
 248 #undef FTN
 249
 250 void op_dup_T0 (void)
 251 {
 252     T2 = T0;
 253     FORCE_RET();
 254 }
 255
 256 void op_load_HI (void)
 257 {
 258     T0 = env->HI[PARAM1][env->current_tc];
 259     FORCE_RET();
 260 }
 261
 262 void op_store_HI (void)
 263 {
 264     env->HI[PARAM1][env->current_tc] = T0;
 265     FORCE_RET();
 266 }
 267
 268 void op_load_LO (void)
 269 {
 270     T0 = env->LO[PARAM1][env->current_tc];
 271     FORCE_RET();
 272 }
 273
 274 void op_store_LO (void)
 275 {
 276     env->LO[PARAM1][env->current_tc] = T0;
 277     FORCE_RET();
 278 }
 279
 280 /* Load and store */
 281 #define MEMSUFFIX _raw
 282 #include "op_mem.c"
 283 #undef MEMSUFFIX
 284 #if !defined(CONFIG_USER_ONLY)
 285 #define MEMSUFFIX _user
 286 #include "op_mem.c"
 287 #undef MEMSUFFIX
 288
 289 #define MEMSUFFIX _super
 290 #include "op_mem.c"
 291 #undef MEMSUFFIX
 292
 293 #define MEMSUFFIX _kernel
 294 #include "op_mem.c"
 295 #undef MEMSUFFIX
 296 #endif
 297
 298 /* Addresses computation */
 299 void op_addr_add (void)
 300 {
 301 /* For compatibility with 32-bit code, data reference in user mode
 302    with Status_UX = 0 should be casted to 32-bit and sign extended.
 303    See the MIPS64 PRA manual, section 4.10. */
 304 #if defined(TARGET_MIPS64)
 305     if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 306         !(env->CP0_Status & (1 << CP0St_UX)))
 307         T0 = (int64_t)(int32_t)(T0 + T1);
 308     else
 309 #endif
 310         T0 += T1;
 311     FORCE_RET();
 312 }
 313
 314 /* Arithmetic */
 315 void op_add (void)
 316 {
 317     T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
 318     FORCE_RET();
 319 }
 320
 321 void op_addo (void)
 322 {
 323     target_ulong tmp;
 324
 325     tmp = (int32_t)T0;
 326     T0 = (int32_t)T0 + (int32_t)T1;
 327     if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
 328         /* operands of same sign, result different sign */
 329         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 330     }
 331     T0 = (int32_t)T0;
 332     FORCE_RET();
 333 }
 334
 335 void op_sub (void)
 336 {
 337     T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
 338     FORCE_RET();
 339 }
 340
 341 void op_subo (void)
 342 {
 343     target_ulong tmp;
 344
 345     tmp = (int32_t)T0;
 346     T0 = (int32_t)T0 - (int32_t)T1;
 347     if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
 348         /* operands of different sign, first operand and result different sign */
 349         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 350     }
 351     T0 = (int32_t)T0;
 352     FORCE_RET();
 353 }
 354
 355 void op_mul (void)
 356 {
 357     T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
 358     FORCE_RET();
 359 }
 360
 361 #if HOST_LONG_BITS < 64
 362 void op_div (void)
 363 {
 364     CALL_FROM_TB0(do_div);
 365     FORCE_RET();
 366 }
 367 #else
 368 void op_div (void)
 369 {
 370     if (T1 != 0) {
 371         env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
 372         env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
 373     }
 374     FORCE_RET();
 375 }
 376 #endif
 377
 378 void op_divu (void)
 379 {
 380     if (T1 != 0) {
 381         env->LO[0][env->current_tc] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
 382         env->HI[0][env->current_tc] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
 383     }
 384     FORCE_RET();
 385 }
 386
 387 #if defined(TARGET_MIPS64)
 388 /* Arithmetic */
 389 void op_dadd (void)
 390 {
 391     T0 += T1;
 392     FORCE_RET();
 393 }
 394
 395 void op_daddo (void)
 396 {
 397     target_long tmp;
 398
 399     tmp = T0;
 400     T0 += T1;
 401     if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
 402         /* operands of same sign, result different sign */
 403         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 404     }
 405     FORCE_RET();
 406 }
 407
 408 void op_dsub (void)
 409 {
 410     T0 -= T1;
 411     FORCE_RET();
 412 }
 413
 414 void op_dsubo (void)
 415 {
 416     target_long tmp;
 417
 418     tmp = T0;
 419     T0 = (int64_t)T0 - (int64_t)T1;
 420     if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
 421         /* operands of different sign, first operand and result different sign */
 422         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 423     }
 424     FORCE_RET();
 425 }
 426
 427 void op_dmul (void)
 428 {
 429     T0 = (int64_t)T0 * (int64_t)T1;
 430     FORCE_RET();
 431 }
 432
 433 /* Those might call libgcc functions.  */
 434 void op_ddiv (void)
 435 {
 436     do_ddiv();
 437     FORCE_RET();
 438 }
 439
 440 #if TARGET_LONG_BITS > HOST_LONG_BITS
 441 void op_ddivu (void)
 442 {
 443     do_ddivu();
 444     FORCE_RET();
 445 }
 446 #else
 447 void op_ddivu (void)
 448 {
 449     if (T1 != 0) {
 450         env->LO[0][env->current_tc] = T0 / T1;
 451         env->HI[0][env->current_tc] = T0 % T1;
 452     }
 453     FORCE_RET();
 454 }
 455 #endif
 456 #endif /* TARGET_MIPS64 */
 457
 458 /* Logical */
 459 void op_and (void)
 460 {
 461     T0 &= T1;
 462     FORCE_RET();
 463 }
 464
 465 void op_nor (void)
 466 {
 467     T0 = ~(T0 | T1);
 468     FORCE_RET();
 469 }
 470
 471 void op_or (void)
 472 {
 473     T0 |= T1;
 474     FORCE_RET();
 475 }
 476
 477 void op_xor (void)
 478 {
 479     T0 ^= T1;
 480     FORCE_RET();
 481 }
 482
 483 void op_sll (void)
 484 {
 485     T0 = (int32_t)((uint32_t)T0 << T1);
 486     FORCE_RET();
 487 }
 488
 489 void op_sra (void)
 490 {
 491     T0 = (int32_t)((int32_t)T0 >> T1);
 492     FORCE_RET();
 493 }
 494
 495 void op_srl (void)
 496 {
 497     T0 = (int32_t)((uint32_t)T0 >> T1);
 498     FORCE_RET();
 499 }
 500
 501 void op_rotr (void)
 502 {
 503     target_ulong tmp;
 504
 505     if (T1) {
 506        tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
 507        T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
 508     }
 509     FORCE_RET();
 510 }
 511
 512 void op_sllv (void)
 513 {
 514     T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
 515     FORCE_RET();
 516 }
 517
 518 void op_srav (void)
 519 {
 520     T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
 521     FORCE_RET();
 522 }
 523
 524 void op_srlv (void)
 525 {
 526     T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
 527     FORCE_RET();
 528 }
 529
 530 void op_rotrv (void)
 531 {
 532     target_ulong tmp;
 533
 534     T0 &= 0x1F;
 535     if (T0) {
 536        tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
 537        T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
 538     } else
 539        T0 = T1;
 540     FORCE_RET();
 541 }
 542
 543 void op_clo (void)
 544 {
 545     T0 = clo32(T0);
 546     FORCE_RET();
 547 }
 548
 549 void op_clz (void)
 550 {
 551     T0 = clz32(T0);
 552     FORCE_RET();
 553 }
 554
 555 #if defined(TARGET_MIPS64)
 556
 557 #if TARGET_LONG_BITS > HOST_LONG_BITS
 558 /* Those might call libgcc functions.  */
 559 void op_dsll (void)
 560 {
 561     CALL_FROM_TB0(do_dsll);
 562     FORCE_RET();
 563 }
 564
 565 void op_dsll32 (void)
 566 {
 567     CALL_FROM_TB0(do_dsll32);
 568     FORCE_RET();
 569 }
 570
 571 void op_dsra (void)
 572 {
 573     CALL_FROM_TB0(do_dsra);
 574     FORCE_RET();
 575 }
 576
 577 void op_dsra32 (void)
 578 {
 579     CALL_FROM_TB0(do_dsra32);
 580     FORCE_RET();
 581 }
 582
 583 void op_dsrl (void)
 584 {
 585     CALL_FROM_TB0(do_dsrl);
 586     FORCE_RET();
 587 }
 588
 589 void op_dsrl32 (void)
 590 {
 591     CALL_FROM_TB0(do_dsrl32);
 592     FORCE_RET();
 593 }
 594
 595 void op_drotr (void)
 596 {
 597     CALL_FROM_TB0(do_drotr);
 598     FORCE_RET();
 599 }
 600
 601 void op_drotr32 (void)
 602 {
 603     CALL_FROM_TB0(do_drotr32);
 604     FORCE_RET();
 605 }
 606
 607 void op_dsllv (void)
 608 {
 609     CALL_FROM_TB0(do_dsllv);
 610     FORCE_RET();
 611 }
 612
 613 void op_dsrav (void)
 614 {
 615     CALL_FROM_TB0(do_dsrav);
 616     FORCE_RET();
 617 }
 618
 619 void op_dsrlv (void)
 620 {
 621     CALL_FROM_TB0(do_dsrlv);
 622     FORCE_RET();
 623 }
 624
 625 void op_drotrv (void)
 626 {
 627     CALL_FROM_TB0(do_drotrv);
 628     FORCE_RET();
 629 }
 630
 631 void op_dclo (void)
 632 {
 633     CALL_FROM_TB0(do_dclo);
 634     FORCE_RET();
 635 }
 636
 637 void op_dclz (void)
 638 {
 639     CALL_FROM_TB0(do_dclz);
 640     FORCE_RET();
 641 }
 642
 643 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
 644
 645 void op_dsll (void)
 646 {
 647     T0 = T0 << T1;
 648     FORCE_RET();
 649 }
 650
 651 void op_dsll32 (void)
 652 {
 653     T0 = T0 << (T1 + 32);
 654     FORCE_RET();
 655 }
 656
 657 void op_dsra (void)
 658 {
 659     T0 = (int64_t)T0 >> T1;
 660     FORCE_RET();
 661 }
 662
 663 void op_dsra32 (void)
 664 {
 665     T0 = (int64_t)T0 >> (T1 + 32);
 666     FORCE_RET();
 667 }
 668
 669 void op_dsrl (void)
 670 {
 671     T0 = T0 >> T1;
 672     FORCE_RET();
 673 }
 674
 675 void op_dsrl32 (void)
 676 {
 677     T0 = T0 >> (T1 + 32);
 678     FORCE_RET();
 679 }
 680
 681 void op_drotr (void)
 682 {
 683     target_ulong tmp;
 684
 685     if (T1) {
 686         tmp = T0 << (0x40 - T1);
 687         T0 = (T0 >> T1) | tmp;
 688     }
 689     FORCE_RET();
 690 }
 691
 692 void op_drotr32 (void)
 693 {
 694     target_ulong tmp;
 695
 696     tmp = T0 << (0x40 - (32 + T1));
 697     T0 = (T0 >> (32 + T1)) | tmp;
 698     FORCE_RET();
 699 }
 700
 701 void op_dsllv (void)
 702 {
 703     T0 = T1 << (T0 & 0x3F);
 704     FORCE_RET();
 705 }
 706
 707 void op_dsrav (void)
 708 {
 709     T0 = (int64_t)T1 >> (T0 & 0x3F);
 710     FORCE_RET();
 711 }
 712
 713 void op_dsrlv (void)
 714 {
 715     T0 = T1 >> (T0 & 0x3F);
 716     FORCE_RET();
 717 }
 718
 719 void op_drotrv (void)
 720 {
 721     target_ulong tmp;
 722
 723     T0 &= 0x3F;
 724     if (T0) {
 725         tmp = T1 << (0x40 - T0);
 726         T0 = (T1 >> T0) | tmp;
 727     } else
 728         T0 = T1;
 729     FORCE_RET();
 730 }
 731
 732 void op_dclo (void)
 733 {
 734     T0 = clo64(T0);
 735     FORCE_RET();
 736 }
 737
 738 void op_dclz (void)
 739 {
 740     T0 = clz64(T0);
 741     FORCE_RET();
 742 }
 743 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 744 #endif /* TARGET_MIPS64 */
 745
 746 /* 64 bits arithmetic */
 747 #if TARGET_LONG_BITS > HOST_LONG_BITS
 748 void op_mult (void)
 749 {
 750     CALL_FROM_TB0(do_mult);
 751     FORCE_RET();
 752 }
 753
 754 void op_multu (void)
 755 {
 756     CALL_FROM_TB0(do_multu);
 757     FORCE_RET();
 758 }
 759
 760 void op_madd (void)
 761 {
 762     CALL_FROM_TB0(do_madd);
 763     FORCE_RET();
 764 }
 765
 766 void op_maddu (void)
 767 {
 768     CALL_FROM_TB0(do_maddu);
 769     FORCE_RET();
 770 }
 771
 772 void op_msub (void)
 773 {
 774     CALL_FROM_TB0(do_msub);
 775     FORCE_RET();
 776 }
 777
 778 void op_msubu (void)
 779 {
 780     CALL_FROM_TB0(do_msubu);
 781     FORCE_RET();
 782 }
 783
 784 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
 785
 786 static always_inline uint64_t get_HILO (void)
 787 {
 788     return ((uint64_t)env->HI[0][env->current_tc] << 32) |
 789             ((uint64_t)(uint32_t)env->LO[0][env->current_tc]);
 790 }
 791
 792 static always_inline void set_HILO (uint64_t HILO)
 793 {
 794     env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
 795     env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
 796 }
 797
 798 void op_mult (void)
 799 {
 800     set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 801     FORCE_RET();
 802 }
 803
 804 void op_multu (void)
 805 {
 806     set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 807     FORCE_RET();
 808 }
 809
 810 void op_madd (void)
 811 {
 812     int64_t tmp;
 813
 814     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 815     set_HILO((int64_t)get_HILO() + tmp);
 816     FORCE_RET();
 817 }
 818
 819 void op_maddu (void)
 820 {
 821     uint64_t tmp;
 822
 823     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 824     set_HILO(get_HILO() + tmp);
 825     FORCE_RET();
 826 }
 827
 828 void op_msub (void)
 829 {
 830     int64_t tmp;
 831
 832     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 833     set_HILO((int64_t)get_HILO() - tmp);
 834     FORCE_RET();
 835 }
 836
 837 void op_msubu (void)
 838 {
 839     uint64_t tmp;
 840
 841     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 842     set_HILO(get_HILO() - tmp);
 843     FORCE_RET();
 844 }
 845 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 846
 847 #if defined(TARGET_MIPS64)
 848 void op_dmult (void)
 849 {
 850     CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
 851     FORCE_RET();
 852 }
 853
 854 void op_dmultu (void)
 855 {
 856     CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1);
 857     FORCE_RET();
 858 }
 859 #endif
 860
 861 /* Conditional moves */
 862 void op_movn (void)
 863 {
 864     if (T1 != 0)
 865         env->gpr[PARAM1][env->current_tc] = T0;
 866     FORCE_RET();
 867 }
 868
 869 void op_movz (void)
 870 {
 871     if (T1 == 0)
 872         env->gpr[PARAM1][env->current_tc] = T0;
 873     FORCE_RET();
 874 }
 875
 876 void op_movf (void)
 877 {
 878     if (!(env->fpu->fcr31 & PARAM1))
 879         T0 = T1;
 880     FORCE_RET();
 881 }
 882
 883 void op_movt (void)
 884 {
 885     if (env->fpu->fcr31 & PARAM1)
 886         T0 = T1;
 887     FORCE_RET();
 888 }
 889
 890 /* Tests */
 891 #define OP_COND(name, cond) \
 892 void glue(op_, name) (void) \
 893 {                           \
 894     if (cond) {             \
 895         T0 = 1;             \
 896     } else {                \
 897         T0 = 0;             \
 898     }                       \
 899     FORCE_RET();            \
 900 }
 901
 902 OP_COND(eq, T0 == T1);
 903 OP_COND(ne, T0 != T1);
 904 OP_COND(ge, (target_long)T0 >= (target_long)T1);
 905 OP_COND(geu, T0 >= T1);
 906 OP_COND(lt, (target_long)T0 < (target_long)T1);
 907 OP_COND(ltu, T0 < T1);
 908 OP_COND(gez, (target_long)T0 >= 0);
 909 OP_COND(gtz, (target_long)T0 > 0);
 910 OP_COND(lez, (target_long)T0 <= 0);
 911 OP_COND(ltz, (target_long)T0 < 0);
 912
 913 /* Branches */
 914 void OPPROTO op_goto_tb0(void)
 915 {
 916     GOTO_TB(op_goto_tb0, PARAM1, 0);
 917     FORCE_RET();
 918 }
 919
 920 void OPPROTO op_goto_tb1(void)
 921 {
 922     GOTO_TB(op_goto_tb1, PARAM1, 1);
 923     FORCE_RET();
 924 }
 925
 926 /* Branch to register */
 927 void op_save_breg_target (void)
 928 {
 929     env->btarget = T2;
 930     FORCE_RET();
 931 }
 932
 933 void op_restore_breg_target (void)
 934 {
 935     T2 = env->btarget;
 936     FORCE_RET();
 937 }
 938
 939 void op_breg (void)
 940 {
 941     env->PC[env->current_tc] = T2;
 942     FORCE_RET();
 943 }
 944
 945 void op_save_btarget (void)
 946 {
 947     env->btarget = PARAM1;
 948     FORCE_RET();
 949 }
 950
 951 #if defined(TARGET_MIPS64)
 952 void op_save_btarget64 (void)
 953 {
 954     env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
 955     FORCE_RET();
 956 }
 957 #endif
 958
 959 /* Conditional branch */
 960 void op_set_bcond (void)
 961 {
 962     T2 = T0;
 963     FORCE_RET();
 964 }
 965
 966 void op_save_bcond (void)
 967 {
 968     env->bcond = T2;
 969     FORCE_RET();
 970 }
 971
 972 void op_restore_bcond (void)
 973 {
 974     T2 = env->bcond;
 975     FORCE_RET();
 976 }
 977
 978 void op_jnz_T2 (void)
 979 {
 980     if (T2)
 981         GOTO_LABEL_PARAM(1);
 982     FORCE_RET();
 983 }
 984
 985 /* CP0 functions */
 986 void op_mfc0_index (void)
 987 {
 988     T0 = env->CP0_Index;
 989     FORCE_RET();
 990 }
 991
 992 void op_mfc0_mvpcontrol (void)
 993 {
 994     T0 = env->mvp->CP0_MVPControl;
 995     FORCE_RET();
 996 }
 997
 998 void op_mfc0_mvpconf0 (void)
 999 {
1000     T0 = env->mvp->CP0_MVPConf0;
1001     FORCE_RET();
1002 }
1003
1004 void op_mfc0_mvpconf1 (void)
1005 {
1006     T0 = env->mvp->CP0_MVPConf1;
1007     FORCE_RET();
1008 }
1009
1010 void op_mfc0_random (void)
1011 {
1012     CALL_FROM_TB0(do_mfc0_random);
1013     FORCE_RET();
1014 }
1015
1016 void op_mfc0_vpecontrol (void)
1017 {
1018     T0 = env->CP0_VPEControl;
1019     FORCE_RET();
1020 }
1021
1022 void op_mfc0_vpeconf0 (void)
1023 {
1024     T0 = env->CP0_VPEConf0;
1025     FORCE_RET();
1026 }
1027
1028 void op_mfc0_vpeconf1 (void)
1029 {
1030     T0 = env->CP0_VPEConf1;
1031     FORCE_RET();
1032 }
1033
1034 void op_mfc0_yqmask (void)
1035 {
1036     T0 = env->CP0_YQMask;
1037     FORCE_RET();
1038 }
1039
1040 void op_mfc0_vpeschedule (void)
1041 {
1042     T0 = env->CP0_VPESchedule;
1043     FORCE_RET();
1044 }
1045
1046 void op_mfc0_vpeschefback (void)
1047 {
1048     T0 = env->CP0_VPEScheFBack;
1049     FORCE_RET();
1050 }
1051
1052 void op_mfc0_vpeopt (void)
1053 {
1054     T0 = env->CP0_VPEOpt;
1055     FORCE_RET();
1056 }
1057
1058 void op_mfc0_entrylo0 (void)
1059 {
1060     T0 = (int32_t)env->CP0_EntryLo0;
1061     FORCE_RET();
1062 }
1063
1064 void op_mfc0_tcstatus (void)
1065 {
1066     T0 = env->CP0_TCStatus[env->current_tc];
1067     FORCE_RET();
1068 }
1069
1070 void op_mftc0_tcstatus(void)
1071 {
1072     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1073
1074     T0 = env->CP0_TCStatus[other_tc];
1075     FORCE_RET();
1076 }
1077
1078 void op_mfc0_tcbind (void)
1079 {
1080     T0 = env->CP0_TCBind[env->current_tc];
1081     FORCE_RET();
1082 }
1083
1084 void op_mftc0_tcbind(void)
1085 {
1086     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1087
1088     T0 = env->CP0_TCBind[other_tc];
1089     FORCE_RET();
1090 }
1091
1092 void op_mfc0_tcrestart (void)
1093 {
1094     T0 = env->PC[env->current_tc];
1095     FORCE_RET();
1096 }
1097
1098 void op_mftc0_tcrestart(void)
1099 {
1100     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1101
1102     T0 = env->PC[other_tc];
1103     FORCE_RET();
1104 }
1105
1106 void op_mfc0_tchalt (void)
1107 {
1108     T0 = env->CP0_TCHalt[env->current_tc];
1109     FORCE_RET();
1110 }
1111
1112 void op_mftc0_tchalt(void)
1113 {
1114     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1115
1116     T0 = env->CP0_TCHalt[other_tc];
1117     FORCE_RET();
1118 }
1119
1120 void op_mfc0_tccontext (void)
1121 {
1122     T0 = env->CP0_TCContext[env->current_tc];
1123     FORCE_RET();
1124 }
1125
1126 void op_mftc0_tccontext(void)
1127 {
1128     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1129
1130     T0 = env->CP0_TCContext[other_tc];
1131     FORCE_RET();
1132 }
1133
1134 void op_mfc0_tcschedule (void)
1135 {
1136     T0 = env->CP0_TCSchedule[env->current_tc];
1137     FORCE_RET();
1138 }
1139
1140 void op_mftc0_tcschedule(void)
1141 {
1142     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1143
1144     T0 = env->CP0_TCSchedule[other_tc];
1145     FORCE_RET();
1146 }
1147
1148 void op_mfc0_tcschefback (void)
1149 {
1150     T0 = env->CP0_TCScheFBack[env->current_tc];
1151     FORCE_RET();
1152 }
1153
1154 void op_mftc0_tcschefback(void)
1155 {
1156     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1157
1158     T0 = env->CP0_TCScheFBack[other_tc];
1159     FORCE_RET();
1160 }
1161
1162 void op_mfc0_entrylo1 (void)
1163 {
1164     T0 = (int32_t)env->CP0_EntryLo1;
1165     FORCE_RET();
1166 }
1167
1168 void op_mfc0_context (void)
1169 {
1170     T0 = (int32_t)env->CP0_Context;
1171     FORCE_RET();
1172 }
1173
1174 void op_mfc0_pagemask (void)
1175 {
1176     T0 = env->CP0_PageMask;
1177     FORCE_RET();
1178 }
1179
1180 void op_mfc0_pagegrain (void)
1181 {
1182     T0 = env->CP0_PageGrain;
1183     FORCE_RET();
1184 }
1185
1186 void op_mfc0_wired (void)
1187 {
1188     T0 = env->CP0_Wired;
1189     FORCE_RET();
1190 }
1191
1192 void op_mfc0_srsconf0 (void)
1193 {
1194     T0 = env->CP0_SRSConf0;
1195     FORCE_RET();
1196 }
1197
1198 void op_mfc0_srsconf1 (void)
1199 {
1200     T0 = env->CP0_SRSConf1;
1201     FORCE_RET();
1202 }
1203
1204 void op_mfc0_srsconf2 (void)
1205 {
1206     T0 = env->CP0_SRSConf2;
1207     FORCE_RET();
1208 }
1209
1210 void op_mfc0_srsconf3 (void)
1211 {
1212     T0 = env->CP0_SRSConf3;
1213     FORCE_RET();
1214 }
1215
1216 void op_mfc0_srsconf4 (void)
1217 {
1218     T0 = env->CP0_SRSConf4;
1219     FORCE_RET();
1220 }
1221
1222 void op_mfc0_hwrena (void)
1223 {
1224     T0 = env->CP0_HWREna;
1225     FORCE_RET();
1226 }
1227
1228 void op_mfc0_badvaddr (void)
1229 {
1230     T0 = (int32_t)env->CP0_BadVAddr;
1231     FORCE_RET();
1232 }
1233
1234 void op_mfc0_count (void)
1235 {
1236     CALL_FROM_TB0(do_mfc0_count);
1237     FORCE_RET();
1238 }
1239
1240 void op_mfc0_entryhi (void)
1241 {
1242     T0 = (int32_t)env->CP0_EntryHi;
1243     FORCE_RET();
1244 }
1245
1246 void op_mftc0_entryhi(void)
1247 {
1248     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1249
1250     T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
1251     FORCE_RET();
1252 }
1253
1254 void op_mfc0_compare (void)
1255 {
1256     T0 = env->CP0_Compare;
1257     FORCE_RET();
1258 }
1259
1260 void op_mfc0_status (void)
1261 {
1262     T0 = env->CP0_Status;
1263     FORCE_RET();
1264 }
1265
1266 void op_mftc0_status(void)
1267 {
1268     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1269     uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1270
1271     T0 = env->CP0_Status & ~0xf1000018;
1272     T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
1273     T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
1274     T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
1275     FORCE_RET();
1276 }
1277
1278 void op_mfc0_intctl (void)
1279 {
1280     T0 = env->CP0_IntCtl;
1281     FORCE_RET();
1282 }
1283
1284 void op_mfc0_srsctl (void)
1285 {
1286     T0 = env->CP0_SRSCtl;
1287     FORCE_RET();
1288 }
1289
1290 void op_mfc0_srsmap (void)
1291 {
1292     T0 = env->CP0_SRSMap;
1293     FORCE_RET();
1294 }
1295
1296 void op_mfc0_cause (void)
1297 {
1298     T0 = env->CP0_Cause;
1299     FORCE_RET();
1300 }
1301
1302 void op_mfc0_epc (void)
1303 {
1304     T0 = (int32_t)env->CP0_EPC;
1305     FORCE_RET();
1306 }
1307
1308 void op_mfc0_prid (void)
1309 {
1310     T0 = env->CP0_PRid;
1311     FORCE_RET();
1312 }
1313
1314 void op_mfc0_ebase (void)
1315 {
1316     T0 = env->CP0_EBase;
1317     FORCE_RET();
1318 }
1319
1320 void op_mfc0_config0 (void)
1321 {
1322     T0 = env->CP0_Config0;
1323     FORCE_RET();
1324 }
1325
1326 void op_mfc0_config1 (void)
1327 {
1328     T0 = env->CP0_Config1;
1329     FORCE_RET();
1330 }
1331
1332 void op_mfc0_config2 (void)
1333 {
1334     T0 = env->CP0_Config2;
1335     FORCE_RET();
1336 }
1337
1338 void op_mfc0_config3 (void)
1339 {
1340     T0 = env->CP0_Config3;
1341     FORCE_RET();
1342 }
1343
1344 void op_mfc0_config6 (void)
1345 {
1346     T0 = env->CP0_Config6;
1347     FORCE_RET();
1348 }
1349
1350 void op_mfc0_config7 (void)
1351 {
1352     T0 = env->CP0_Config7;
1353     FORCE_RET();
1354 }
1355
1356 void op_mfc0_lladdr (void)
1357 {
1358     T0 = (int32_t)env->CP0_LLAddr >> 4;
1359     FORCE_RET();
1360 }
1361
1362 void op_mfc0_watchlo (void)
1363 {
1364     T0 = (int32_t)env->CP0_WatchLo[PARAM1];
1365     FORCE_RET();
1366 }
1367
1368 void op_mfc0_watchhi (void)
1369 {
1370     T0 = env->CP0_WatchHi[PARAM1];
1371     FORCE_RET();
1372 }
1373
1374 void op_mfc0_xcontext (void)
1375 {
1376     T0 = (int32_t)env->CP0_XContext;
1377     FORCE_RET();
1378 }
1379
1380 void op_mfc0_framemask (void)
1381 {
1382     T0 = env->CP0_Framemask;
1383     FORCE_RET();
1384 }
1385
1386 void op_mfc0_debug (void)
1387 {
1388     T0 = env->CP0_Debug;
1389     if (env->hflags & MIPS_HFLAG_DM)
1390         T0 |= 1 << CP0DB_DM;
1391     FORCE_RET();
1392 }
1393
1394 void op_mftc0_debug(void)
1395 {
1396     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1397
1398     /* XXX: Might be wrong, check with EJTAG spec. */
1399     T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1400          (env->CP0_Debug_tcstatus[other_tc] &
1401           ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1402     FORCE_RET();
1403 }
1404
1405 void op_mfc0_depc (void)
1406 {
1407     T0 = (int32_t)env->CP0_DEPC;
1408     FORCE_RET();
1409 }
1410
1411 void op_mfc0_performance0 (void)
1412 {
1413     T0 = env->CP0_Performance0;
1414     FORCE_RET();
1415 }
1416
1417 void op_mfc0_taglo (void)
1418 {
1419     T0 = env->CP0_TagLo;
1420     FORCE_RET();
1421 }
1422
1423 void op_mfc0_datalo (void)
1424 {
1425     T0 = env->CP0_DataLo;
1426     FORCE_RET();
1427 }
1428
1429 void op_mfc0_taghi (void)
1430 {
1431     T0 = env->CP0_TagHi;
1432     FORCE_RET();
1433 }
1434
1435 void op_mfc0_datahi (void)
1436 {
1437     T0 = env->CP0_DataHi;
1438     FORCE_RET();
1439 }
1440
1441 void op_mfc0_errorepc (void)
1442 {
1443     T0 = (int32_t)env->CP0_ErrorEPC;
1444     FORCE_RET();
1445 }
1446
1447 void op_mfc0_desave (void)
1448 {
1449     T0 = env->CP0_DESAVE;
1450     FORCE_RET();
1451 }
1452
1453 void op_mtc0_index (void)
1454 {
1455     int num = 1;
1456     unsigned int tmp = env->tlb->nb_tlb;
1457
1458     do {
1459         tmp >>= 1;
1460         num <<= 1;
1461     } while (tmp);
1462     env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
1463     FORCE_RET();
1464 }
1465
1466 void op_mtc0_mvpcontrol (void)
1467 {
1468     uint32_t mask = 0;
1469     uint32_t newval;
1470
1471     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1472         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1473                 (1 << CP0MVPCo_EVP);
1474     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1475         mask |= (1 << CP0MVPCo_STLB);
1476     newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);
1477
1478     // TODO: Enable/disable shared TLB, enable/disable VPEs.
1479
1480     env->mvp->CP0_MVPControl = newval;
1481     FORCE_RET();
1482 }
1483
1484 void op_mtc0_vpecontrol (void)
1485 {
1486     uint32_t mask;
1487     uint32_t newval;
1488
1489     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1490            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1491     newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);
1492
1493     /* Yield scheduler intercept not implemented. */
1494     /* Gating storage scheduler intercept not implemented. */
1495
1496     // TODO: Enable/disable TCs.
1497
1498     env->CP0_VPEControl = newval;
1499     FORCE_RET();
1500 }
1501
1502 void op_mtc0_vpeconf0 (void)
1503 {
1504     uint32_t mask = 0;
1505     uint32_t newval;
1506
1507     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1508         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1509             mask |= (0xff << CP0VPEC0_XTC);
1510         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1511     }
1512     newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);
1513
1514     // TODO: TC exclusive handling due to ERL/EXL.
1515
1516     env->CP0_VPEConf0 = newval;
1517     FORCE_RET();
1518 }
1519
1520 void op_mtc0_vpeconf1 (void)
1521 {
1522     uint32_t mask = 0;
1523     uint32_t newval;
1524
1525     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1526         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1527                 (0xff << CP0VPEC1_NCP1);
1528     newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);
1529
1530     /* UDI not implemented. */
1531     /* CP2 not implemented. */
1532
1533     // TODO: Handle FPU (CP1) binding.
1534
1535     env->CP0_VPEConf1 = newval;
1536     FORCE_RET();
1537 }
1538
1539 void op_mtc0_yqmask (void)
1540 {
1541     /* Yield qualifier inputs not implemented. */
1542     env->CP0_YQMask = 0x00000000;
1543     FORCE_RET();
1544 }
1545
1546 void op_mtc0_vpeschedule (void)
1547 {
1548     env->CP0_VPESchedule = T0;
1549     FORCE_RET();
1550 }
1551
1552 void op_mtc0_vpeschefback (void)
1553 {
1554     env->CP0_VPEScheFBack = T0;
1555     FORCE_RET();
1556 }
1557
1558 void op_mtc0_vpeopt (void)
1559 {
1560     env->CP0_VPEOpt = T0 & 0x0000ffff;
1561     FORCE_RET();
1562 }
1563
1564 void op_mtc0_entrylo0 (void)
1565 {
1566     /* Large physaddr not implemented */
1567     /* 1k pages not implemented */
1568     env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1569     FORCE_RET();
1570 }
1571
1572 void op_mtc0_tcstatus (void)
1573 {
1574     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1575     uint32_t newval;
1576
1577     newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);
1578
1579     // TODO: Sync with CP0_Status.
1580
1581     env->CP0_TCStatus[env->current_tc] = newval;
1582     FORCE_RET();
1583 }
1584
1585 void op_mttc0_tcstatus (void)
1586 {
1587     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1588
1589     // TODO: Sync with CP0_Status.
1590
1591     env->CP0_TCStatus[other_tc] = T0;
1592     FORCE_RET();
1593 }
1594
1595 void op_mtc0_tcbind (void)
1596 {
1597     uint32_t mask = (1 << CP0TCBd_TBE);
1598     uint32_t newval;
1599
1600     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1601         mask |= (1 << CP0TCBd_CurVPE);
1602     newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
1603     env->CP0_TCBind[env->current_tc] = newval;
1604     FORCE_RET();
1605 }
1606
1607 void op_mttc0_tcbind (void)
1608 {
1609     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1610     uint32_t mask = (1 << CP0TCBd_TBE);
1611     uint32_t newval;
1612
1613     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1614         mask |= (1 << CP0TCBd_CurVPE);
1615     newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
1616     env->CP0_TCBind[other_tc] = newval;
1617     FORCE_RET();
1618 }
1619
1620 void op_mtc0_tcrestart (void)
1621 {
1622     env->PC[env->current_tc] = T0;
1623     env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
1624     env->CP0_LLAddr = 0ULL;
1625     /* MIPS16 not implemented. */
1626     FORCE_RET();
1627 }
1628
1629 void op_mttc0_tcrestart (void)
1630 {
1631     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1632
1633     env->PC[other_tc] = T0;
1634     env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
1635     env->CP0_LLAddr = 0ULL;
1636     /* MIPS16 not implemented. */
1637     FORCE_RET();
1638 }
1639
1640 void op_mtc0_tchalt (void)
1641 {
1642     env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
1643
1644     // TODO: Halt TC / Restart (if allocated+active) TC.
1645
1646     FORCE_RET();
1647 }
1648
1649 void op_mttc0_tchalt (void)
1650 {
1651     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1652
1653     // TODO: Halt TC / Restart (if allocated+active) TC.
1654
1655     env->CP0_TCHalt[other_tc] = T0;
1656     FORCE_RET();
1657 }
1658
1659 void op_mtc0_tccontext (void)
1660 {
1661     env->CP0_TCContext[env->current_tc] = T0;
1662     FORCE_RET();
1663 }
1664
1665 void op_mttc0_tccontext (void)
1666 {
1667     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1668
1669     env->CP0_TCContext[other_tc] = T0;
1670     FORCE_RET();
1671 }
1672
1673 void op_mtc0_tcschedule (void)
1674 {
1675     env->CP0_TCSchedule[env->current_tc] = T0;
1676     FORCE_RET();
1677 }
1678
1679 void op_mttc0_tcschedule (void)
1680 {
1681     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1682
1683     env->CP0_TCSchedule[other_tc] = T0;
1684     FORCE_RET();
1685 }
1686
1687 void op_mtc0_tcschefback (void)
1688 {
1689     env->CP0_TCScheFBack[env->current_tc] = T0;
1690     FORCE_RET();
1691 }
1692
1693 void op_mttc0_tcschefback (void)
1694 {
1695     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1696
1697     env->CP0_TCScheFBack[other_tc] = T0;
1698     FORCE_RET();
1699 }
1700
1701 void op_mtc0_entrylo1 (void)
1702 {
1703     /* Large physaddr not implemented */
1704     /* 1k pages not implemented */
1705     env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1706     FORCE_RET();
1707 }
1708
1709 void op_mtc0_context (void)
1710 {
1711     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1712     FORCE_RET();
1713 }
1714
1715 void op_mtc0_pagemask (void)
1716 {
1717     /* 1k pages not implemented */
1718     env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1719     FORCE_RET();
1720 }
1721
1722 void op_mtc0_pagegrain (void)
1723 {
1724     /* SmartMIPS not implemented */
1725     /* Large physaddr not implemented */
1726     /* 1k pages not implemented */
1727     env->CP0_PageGrain = 0;
1728     FORCE_RET();
1729 }
1730
1731 void op_mtc0_wired (void)
1732 {
1733     env->CP0_Wired = T0 % env->tlb->nb_tlb;
1734     FORCE_RET();
1735 }
1736
1737 void op_mtc0_srsconf0 (void)
1738 {
1739     env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
1740     FORCE_RET();
1741 }
1742
1743 void op_mtc0_srsconf1 (void)
1744 {
1745     env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
1746     FORCE_RET();
1747 }
1748
1749 void op_mtc0_srsconf2 (void)
1750 {
1751     env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
1752     FORCE_RET();
1753 }
1754
1755 void op_mtc0_srsconf3 (void)
1756 {
1757     env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
1758     FORCE_RET();
1759 }
1760
1761 void op_mtc0_srsconf4 (void)
1762 {
1763     env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
1764     FORCE_RET();
1765 }
1766
1767 void op_mtc0_hwrena (void)
1768 {
1769     env->CP0_HWREna = T0 & 0x0000000F;
1770     FORCE_RET();
1771 }
1772
1773 void op_mtc0_count (void)
1774 {
1775     CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1776     FORCE_RET();
1777 }
1778
1779 void op_mtc0_entryhi (void)
1780 {
1781     target_ulong old, val;
1782
1783     /* 1k pages not implemented */
1784     val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1785 #if defined(TARGET_MIPS64)
1786     val &= env->SEGMask;
1787 #endif
1788     old = env->CP0_EntryHi;
1789     env->CP0_EntryHi = val;
1790     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1791         uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
1792         env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
1793     }
1794     /* If the ASID changes, flush qemu's TLB.  */
1795     if ((old & 0xFF) != (val & 0xFF))
1796         CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1797     FORCE_RET();
1798 }
1799
1800 void op_mttc0_entryhi(void)
1801 {
1802     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1803
1804     env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
1805     env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
1806     FORCE_RET();
1807 }
1808
1809 void op_mtc0_compare (void)
1810 {
1811     CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1812     FORCE_RET();
1813 }
1814
1815 void op_mtc0_status (void)
1816 {
1817     uint32_t val, old;
1818     uint32_t mask = env->CP0_Status_rw_bitmask;
1819
1820     val = T0 & mask;
1821     old = env->CP0_Status;
1822     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1823     CALL_FROM_TB1(compute_hflags, env);
1824     if (loglevel & CPU_LOG_EXEC)
1825         CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1826     CALL_FROM_TB1(cpu_mips_update_irq, env);
1827     FORCE_RET();
1828 }
1829
1830 void op_mttc0_status(void)
1831 {
1832     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1833     uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1834
1835     env->CP0_Status = T0 & ~0xf1000018;
1836     tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
1837     tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1838     tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1839     env->CP0_TCStatus[other_tc] = tcstatus;
1840     FORCE_RET();
1841 }
1842
1843 void op_mtc0_intctl (void)
1844 {
1845     /* vectored interrupts not implemented, no performance counters. */
1846     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
1847     FORCE_RET();
1848 }
1849
1850 void op_mtc0_srsctl (void)
1851 {
1852     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1853     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
1854     FORCE_RET();
1855 }
1856
1857 void op_mtc0_srsmap (void)
1858 {
1859     env->CP0_SRSMap = T0;
1860     FORCE_RET();
1861 }
1862
1863 void op_mtc0_cause (void)
1864 {
1865     uint32_t mask = 0x00C00300;
1866     uint32_t old = env->CP0_Cause;
1867
1868     if (env->insn_flags & ISA_MIPS32R2)
1869         mask |= 1 << CP0Ca_DC;
1870
1871     env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1872
1873     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1874         if (env->CP0_Cause & (1 << CP0Ca_DC))
1875             CALL_FROM_TB1(cpu_mips_stop_count, env);
1876         else
1877             CALL_FROM_TB1(cpu_mips_start_count, env);
1878     }
1879
1880     /* Handle the software interrupt as an hardware one, as they
1881        are very similar */
1882     if (T0 & CP0Ca_IP_mask) {
1883         CALL_FROM_TB1(cpu_mips_update_irq, env);
1884     }
1885     FORCE_RET();
1886 }
1887
1888 void op_mtc0_epc (void)
1889 {
1890     env->CP0_EPC = T0;
1891     FORCE_RET();
1892 }
1893
1894 void op_mtc0_ebase (void)
1895 {
1896     /* vectored interrupts not implemented */
1897     /* Multi-CPU not implemented */
1898     env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1899     FORCE_RET();
1900 }
1901
1902 void op_mtc0_config0 (void)
1903 {
1904     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
1905     FORCE_RET();
1906 }
1907
1908 void op_mtc0_config2 (void)
1909 {
1910     /* tertiary/secondary caches not implemented */
1911     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1912     FORCE_RET();
1913 }
1914
1915 void op_mtc0_watchlo (void)
1916 {
1917     /* Watch exceptions for instructions, data loads, data stores
1918        not implemented. */
1919     env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
1920     FORCE_RET();
1921 }
1922
1923 void op_mtc0_watchhi (void)
1924 {
1925     env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
1926     env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
1927     FORCE_RET();
1928 }
1929
1930 void op_mtc0_xcontext (void)
1931 {
1932     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1933     env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
1934     FORCE_RET();
1935 }
1936
1937 void op_mtc0_framemask (void)
1938 {
1939     env->CP0_Framemask = T0; /* XXX */
1940     FORCE_RET();
1941 }
1942
1943 void op_mtc0_debug (void)
1944 {
1945     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1946     if (T0 & (1 << CP0DB_DM))
1947         env->hflags |= MIPS_HFLAG_DM;
1948     else
1949         env->hflags &= ~MIPS_HFLAG_DM;
1950     FORCE_RET();
1951 }
1952
1953 void op_mttc0_debug(void)
1954 {
1955     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1956
1957     /* XXX: Might be wrong, check with EJTAG spec. */
1958     env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1959     env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1960                      (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1961     FORCE_RET();
1962 }
1963
1964 void op_mtc0_depc (void)
1965 {
1966     env->CP0_DEPC = T0;
1967     FORCE_RET();
1968 }
1969
1970 void op_mtc0_performance0 (void)
1971 {
1972     env->CP0_Performance0 = T0 & 0x000007ff;
1973     FORCE_RET();
1974 }
1975
1976 void op_mtc0_taglo (void)
1977 {
1978     env->CP0_TagLo = T0 & 0xFFFFFCF6;
1979     FORCE_RET();
1980 }
1981
1982 void op_mtc0_datalo (void)
1983 {
1984     env->CP0_DataLo = T0; /* XXX */
1985     FORCE_RET();
1986 }
1987
1988 void op_mtc0_taghi (void)
1989 {
1990     env->CP0_TagHi = T0; /* XXX */
1991     FORCE_RET();
1992 }
1993
1994 void op_mtc0_datahi (void)
1995 {
1996     env->CP0_DataHi = T0; /* XXX */
1997     FORCE_RET();
1998 }
1999
2000 void op_mtc0_errorepc (void)
2001 {
2002     env->CP0_ErrorEPC = T0;
2003     FORCE_RET();
2004 }
2005
2006 void op_mtc0_desave (void)
2007 {
2008     env->CP0_DESAVE = T0;
2009     FORCE_RET();
2010 }
2011
2012 #if defined(TARGET_MIPS64)
2013 void op_dmfc0_yqmask (void)
2014 {
2015     T0 = env->CP0_YQMask;
2016     FORCE_RET();
2017 }
2018
2019 void op_dmfc0_vpeschedule (void)
2020 {
2021     T0 = env->CP0_VPESchedule;
2022     FORCE_RET();
2023 }
2024
2025 void op_dmfc0_vpeschefback (void)
2026 {
2027     T0 = env->CP0_VPEScheFBack;
2028     FORCE_RET();
2029 }
2030
2031 void op_dmfc0_entrylo0 (void)
2032 {
2033     T0 = env->CP0_EntryLo0;
2034     FORCE_RET();
2035 }
2036
2037 void op_dmfc0_tcrestart (void)
2038 {
2039     T0 = env->PC[env->current_tc];
2040     FORCE_RET();
2041 }
2042
2043 void op_dmfc0_tchalt (void)
2044 {
2045     T0 = env->CP0_TCHalt[env->current_tc];
2046     FORCE_RET();
2047 }
2048
2049 void op_dmfc0_tccontext (void)
2050 {
2051     T0 = env->CP0_TCContext[env->current_tc];
2052     FORCE_RET();
2053 }
2054
2055 void op_dmfc0_tcschedule (void)
2056 {
2057     T0 = env->CP0_TCSchedule[env->current_tc];
2058     FORCE_RET();
2059 }
2060
2061 void op_dmfc0_tcschefback (void)
2062 {
2063     T0 = env->CP0_TCScheFBack[env->current_tc];
2064     FORCE_RET();
2065 }
2066
2067 void op_dmfc0_entrylo1 (void)
2068 {
2069     T0 = env->CP0_EntryLo1;
2070     FORCE_RET();
2071 }
2072
2073 void op_dmfc0_context (void)
2074 {
2075     T0 = env->CP0_Context;
2076     FORCE_RET();
2077 }
2078
2079 void op_dmfc0_badvaddr (void)
2080 {
2081     T0 = env->CP0_BadVAddr;
2082     FORCE_RET();
2083 }
2084
2085 void op_dmfc0_entryhi (void)
2086 {
2087     T0 = env->CP0_EntryHi;
2088     FORCE_RET();
2089 }
2090
2091 void op_dmfc0_epc (void)
2092 {
2093     T0 = env->CP0_EPC;
2094     FORCE_RET();
2095 }
2096
2097 void op_dmfc0_lladdr (void)
2098 {
2099     T0 = env->CP0_LLAddr >> 4;
2100     FORCE_RET();
2101 }
2102
2103 void op_dmfc0_watchlo (void)
2104 {
2105     T0 = env->CP0_WatchLo[PARAM1];
2106     FORCE_RET();
2107 }
2108
2109 void op_dmfc0_xcontext (void)
2110 {
2111     T0 = env->CP0_XContext;
2112     FORCE_RET();
2113 }
2114
2115 void op_dmfc0_depc (void)
2116 {
2117     T0 = env->CP0_DEPC;
2118     FORCE_RET();
2119 }
2120
2121 void op_dmfc0_errorepc (void)
2122 {
2123     T0 = env->CP0_ErrorEPC;
2124     FORCE_RET();
2125 }
2126 #endif /* TARGET_MIPS64 */
2127
2128 /* MIPS MT functions */
2129 void op_mftgpr(void)
2130 {
2131     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2132
2133     T0 = env->gpr[PARAM1][other_tc];
2134     FORCE_RET();
2135 }
2136
2137 void op_mftlo(void)
2138 {
2139     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2140
2141     T0 = env->LO[PARAM1][other_tc];
2142     FORCE_RET();
2143 }
2144
2145 void op_mfthi(void)
2146 {
2147     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2148
2149     T0 = env->HI[PARAM1][other_tc];
2150     FORCE_RET();
2151 }
2152
2153 void op_mftacx(void)
2154 {
2155     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2156
2157     T0 = env->ACX[PARAM1][other_tc];
2158     FORCE_RET();
2159 }
2160
2161 void op_mftdsp(void)
2162 {
2163     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2164
2165     T0 = env->DSPControl[other_tc];
2166     FORCE_RET();
2167 }
2168
2169 void op_mttgpr(void)
2170 {
2171     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2172
2173     T0 = env->gpr[PARAM1][other_tc];
2174     FORCE_RET();
2175 }
2176
2177 void op_mttlo(void)
2178 {
2179     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2180
2181     T0 = env->LO[PARAM1][other_tc];
2182     FORCE_RET();
2183 }
2184
2185 void op_mtthi(void)
2186 {
2187     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2188
2189     T0 = env->HI[PARAM1][other_tc];
2190     FORCE_RET();
2191 }
2192
2193 void op_mttacx(void)
2194 {
2195     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2196
2197     T0 = env->ACX[PARAM1][other_tc];
2198     FORCE_RET();
2199 }
2200
2201 void op_mttdsp(void)
2202 {
2203     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2204
2205     T0 = env->DSPControl[other_tc];
2206     FORCE_RET();
2207 }
2208
2209
2210 void op_dmt(void)
2211 {
2212     // TODO
2213     T0 = 0;
2214     // rt = T0
2215     FORCE_RET();
2216 }
2217
2218 void op_emt(void)
2219 {
2220     // TODO
2221     T0 = 0;
2222     // rt = T0
2223     FORCE_RET();
2224 }
2225
2226 void op_dvpe(void)
2227 {
2228     // TODO
2229     T0 = 0;
2230     // rt = T0
2231     FORCE_RET();
2232 }
2233
2234 void op_evpe(void)
2235 {
2236     // TODO
2237     T0 = 0;
2238     // rt = T0
2239     FORCE_RET();
2240 }
2241
2242 void op_fork(void)
2243 {
2244     // T0 = rt, T1 = rs
2245     T0 = 0;
2246     // TODO: store to TC register
2247     FORCE_RET();
2248 }
2249
2250 void op_yield(void)
2251 {
2252     if (T0 < 0) {
2253         /* No scheduling policy implemented. */
2254         if (T0 != -2) {
2255             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2256                 env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
2257                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2258                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2259                 CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
2260             }
2261         }
2262     } else if (T0 == 0) {
2263         if (0 /* TODO: TC underflow */) {
2264             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2265             CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
2266         } else {
2267             // TODO: Deallocate TC
2268         }
2269     } else if (T0 > 0) {
2270         /* Yield qualifier inputs not implemented. */
2271         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2272         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2273         CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
2274     }
2275     T0 = env->CP0_YQMask;
2276     FORCE_RET();
2277 }
2278
2279 /* CP1 functions */
2280 #if 0
2281 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
2282 #else
2283 # define DEBUG_FPU_STATE() do { } while(0)
2284 #endif
2285
2286 void op_cfc1 (void)
2287 {
2288     CALL_FROM_TB1(do_cfc1, PARAM1);
2289     DEBUG_FPU_STATE();
2290     FORCE_RET();
2291 }
2292
2293 void op_ctc1 (void)
2294 {
2295     CALL_FROM_TB1(do_ctc1, PARAM1);
2296     DEBUG_FPU_STATE();
2297     FORCE_RET();
2298 }
2299
2300 void op_mfc1 (void)
2301 {
2302     T0 = (int32_t)WT0;
2303     DEBUG_FPU_STATE();
2304     FORCE_RET();
2305 }
2306
2307 void op_mtc1 (void)
2308 {
2309     WT0 = T0;
2310     DEBUG_FPU_STATE();
2311     FORCE_RET();
2312 }
2313
2314 void op_dmfc1 (void)
2315 {
2316     T0 = DT0;
2317     DEBUG_FPU_STATE();
2318     FORCE_RET();
2319 }
2320
2321 void op_dmtc1 (void)
2322 {
2323     DT0 = T0;
2324     DEBUG_FPU_STATE();
2325     FORCE_RET();
2326 }
2327
2328 void op_mfhc1 (void)
2329 {
2330     T0 = (int32_t)WTH0;
2331     DEBUG_FPU_STATE();
2332     FORCE_RET();
2333 }
2334
2335 void op_mthc1 (void)
2336 {
2337     WTH0 = T0;
2338     DEBUG_FPU_STATE();
2339     FORCE_RET();
2340 }
2341
2342 /* Float support.
2343    Single precition routines have a "s" suffix, double precision a
2344    "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
2345    paired single lowwer "pl", paired single upper "pu".  */
2346
2347 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
2348
2349 FLOAT_OP(cvtd, s)
2350 {
2351     CALL_FROM_TB0(do_float_cvtd_s);
2352     DEBUG_FPU_STATE();
2353     FORCE_RET();
2354 }
2355 FLOAT_OP(cvtd, w)
2356 {
2357     CALL_FROM_TB0(do_float_cvtd_w);
2358     DEBUG_FPU_STATE();
2359     FORCE_RET();
2360 }
2361 FLOAT_OP(cvtd, l)
2362 {
2363     CALL_FROM_TB0(do_float_cvtd_l);
2364     DEBUG_FPU_STATE();
2365     FORCE_RET();
2366 }
2367 FLOAT_OP(cvtl, d)
2368 {
2369     CALL_FROM_TB0(do_float_cvtl_d);
2370     DEBUG_FPU_STATE();
2371     FORCE_RET();
2372 }
2373 FLOAT_OP(cvtl, s)
2374 {
2375     CALL_FROM_TB0(do_float_cvtl_s);
2376     DEBUG_FPU_STATE();
2377     FORCE_RET();
2378 }
2379 FLOAT_OP(cvtps, s)
2380 {
2381     WT2 = WT0;
2382     WTH2 = WT1;
2383     DEBUG_FPU_STATE();
2384     FORCE_RET();
2385 }
2386 FLOAT_OP(cvtps, pw)
2387 {
2388     CALL_FROM_TB0(do_float_cvtps_pw);
2389     DEBUG_FPU_STATE();
2390     FORCE_RET();
2391 }
2392 FLOAT_OP(cvtpw, ps)
2393 {
2394     CALL_FROM_TB0(do_float_cvtpw_ps);
2395     DEBUG_FPU_STATE();
2396     FORCE_RET();
2397 }
2398 FLOAT_OP(cvts, d)
2399 {
2400     CALL_FROM_TB0(do_float_cvts_d);
2401     DEBUG_FPU_STATE();
2402     FORCE_RET();
2403 }
2404 FLOAT_OP(cvts, w)
2405 {
2406     CALL_FROM_TB0(do_float_cvts_w);
2407     DEBUG_FPU_STATE();
2408     FORCE_RET();
2409 }
2410 FLOAT_OP(cvts, l)
2411 {
2412     CALL_FROM_TB0(do_float_cvts_l);
2413     DEBUG_FPU_STATE();
2414     FORCE_RET();
2415 }
2416 FLOAT_OP(cvts, pl)
2417 {
2418     CALL_FROM_TB0(do_float_cvts_pl);
2419     DEBUG_FPU_STATE();
2420     FORCE_RET();
2421 }
2422 FLOAT_OP(cvts, pu)
2423 {
2424     CALL_FROM_TB0(do_float_cvts_pu);
2425     DEBUG_FPU_STATE();
2426     FORCE_RET();
2427 }
2428 FLOAT_OP(cvtw, s)
2429 {
2430     CALL_FROM_TB0(do_float_cvtw_s);
2431     DEBUG_FPU_STATE();
2432     FORCE_RET();
2433 }
2434 FLOAT_OP(cvtw, d)
2435 {
2436     CALL_FROM_TB0(do_float_cvtw_d);
2437     DEBUG_FPU_STATE();
2438     FORCE_RET();
2439 }
2440
2441 FLOAT_OP(pll, ps)
2442 {
2443     DT2 = ((uint64_t)WT0 << 32) | WT1;
2444     DEBUG_FPU_STATE();
2445     FORCE_RET();
2446 }
2447 FLOAT_OP(plu, ps)
2448 {
2449     DT2 = ((uint64_t)WT0 << 32) | WTH1;
2450     DEBUG_FPU_STATE();
2451     FORCE_RET();
2452 }
2453 FLOAT_OP(pul, ps)
2454 {
2455     DT2 = ((uint64_t)WTH0 << 32) | WT1;
2456     DEBUG_FPU_STATE();
2457     FORCE_RET();
2458 }
2459 FLOAT_OP(puu, ps)
2460 {
2461     DT2 = ((uint64_t)WTH0 << 32) | WTH1;
2462     DEBUG_FPU_STATE();
2463     FORCE_RET();
2464 }
2465
2466 #define FLOAT_ROUNDOP(op, ttype, stype)                    \
2467 FLOAT_OP(op ## ttype, stype)                               \
2468 {                                                          \
2469     CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
2470     DEBUG_FPU_STATE();                                     \
2471     FORCE_RET();                                           \
2472 }
2473
2474 FLOAT_ROUNDOP(round, l, d)
2475 FLOAT_ROUNDOP(round, l, s)
2476 FLOAT_ROUNDOP(round, w, d)
2477 FLOAT_ROUNDOP(round, w, s)
2478
2479 FLOAT_ROUNDOP(trunc, l, d)
2480 FLOAT_ROUNDOP(trunc, l, s)
2481 FLOAT_ROUNDOP(trunc, w, d)
2482 FLOAT_ROUNDOP(trunc, w, s)
2483
2484 FLOAT_ROUNDOP(ceil, l, d)
2485 FLOAT_ROUNDOP(ceil, l, s)
2486 FLOAT_ROUNDOP(ceil, w, d)
2487 FLOAT_ROUNDOP(ceil, w, s)
2488
2489 FLOAT_ROUNDOP(floor, l, d)
2490 FLOAT_ROUNDOP(floor, l, s)
2491 FLOAT_ROUNDOP(floor, w, d)
2492 FLOAT_ROUNDOP(floor, w, s)
2493 #undef FLOAR_ROUNDOP
2494
2495 FLOAT_OP(movf, d)
2496 {
2497     if (!(env->fpu->fcr31 & PARAM1))
2498         DT2 = DT0;
2499     DEBUG_FPU_STATE();
2500     FORCE_RET();
2501 }
2502 FLOAT_OP(movf, s)
2503 {
2504     if (!(env->fpu->fcr31 & PARAM1))
2505         WT2 = WT0;
2506     DEBUG_FPU_STATE();
2507     FORCE_RET();
2508 }
2509 FLOAT_OP(movf, ps)
2510 {
2511     if (!(env->fpu->fcr31 & PARAM1)) {
2512         WT2 = WT0;
2513         WTH2 = WTH0;
2514     }
2515     DEBUG_FPU_STATE();
2516     FORCE_RET();
2517 }
2518 FLOAT_OP(movt, d)
2519 {
2520     if (env->fpu->fcr31 & PARAM1)
2521         DT2 = DT0;
2522     DEBUG_FPU_STATE();
2523     FORCE_RET();
2524 }
2525 FLOAT_OP(movt, s)
2526 {
2527     if (env->fpu->fcr31 & PARAM1)
2528         WT2 = WT0;
2529     DEBUG_FPU_STATE();
2530     FORCE_RET();
2531 }
2532 FLOAT_OP(movt, ps)
2533 {
2534     if (env->fpu->fcr31 & PARAM1) {
2535         WT2 = WT0;
2536         WTH2 = WTH0;
2537     }
2538     DEBUG_FPU_STATE();
2539     FORCE_RET();
2540 }
2541 FLOAT_OP(movz, d)
2542 {
2543     if (!T0)
2544         DT2 = DT0;
2545     DEBUG_FPU_STATE();
2546     FORCE_RET();
2547 }
2548 FLOAT_OP(movz, s)
2549 {
2550     if (!T0)
2551         WT2 = WT0;
2552     DEBUG_FPU_STATE();
2553     FORCE_RET();
2554 }
2555 FLOAT_OP(movz, ps)
2556 {
2557     if (!T0) {
2558         WT2 = WT0;
2559         WTH2 = WTH0;
2560     }
2561     DEBUG_FPU_STATE();
2562     FORCE_RET();
2563 }
2564 FLOAT_OP(movn, d)
2565 {
2566     if (T0)
2567         DT2 = DT0;
2568     DEBUG_FPU_STATE();
2569     FORCE_RET();
2570 }
2571 FLOAT_OP(movn, s)
2572 {
2573     if (T0)
2574         WT2 = WT0;
2575     DEBUG_FPU_STATE();
2576     FORCE_RET();
2577 }
2578 FLOAT_OP(movn, ps)
2579 {
2580     if (T0) {
2581         WT2 = WT0;
2582         WTH2 = WTH0;
2583     }
2584     DEBUG_FPU_STATE();
2585     FORCE_RET();
2586 }
2587
2588 /* operations calling helpers, for s, d and ps */
2589 #define FLOAT_HOP(name)   \
2590 FLOAT_OP(name, d)         \
2591 {                         \
2592     CALL_FROM_TB0(do_float_ ## name ## _d);  \
2593     DEBUG_FPU_STATE();    \
2594     FORCE_RET();          \
2595 }                         \
2596 FLOAT_OP(name, s)         \
2597 {                         \
2598     CALL_FROM_TB0(do_float_ ## name ## _s);  \
2599     DEBUG_FPU_STATE();    \
2600     FORCE_RET();          \
2601 }                         \
2602 FLOAT_OP(name, ps)        \
2603 {                         \
2604     CALL_FROM_TB0(do_float_ ## name ## _ps); \
2605     DEBUG_FPU_STATE();    \
2606     FORCE_RET();          \
2607 }
2608 FLOAT_HOP(add)
2609 FLOAT_HOP(sub)
2610 FLOAT_HOP(mul)
2611 FLOAT_HOP(div)
2612 FLOAT_HOP(recip2)
2613 FLOAT_HOP(rsqrt2)
2614 FLOAT_HOP(rsqrt1)
2615 FLOAT_HOP(recip1)
2616 #undef FLOAT_HOP
2617
2618 /* operations calling helpers, for s and d */
2619 #define FLOAT_HOP(name)   \
2620 FLOAT_OP(name, d)         \
2621 {                         \
2622     CALL_FROM_TB0(do_float_ ## name ## _d);  \
2623     DEBUG_FPU_STATE();    \
2624     FORCE_RET();          \
2625 }                         \
2626 FLOAT_OP(name, s)         \
2627 {                         \
2628     CALL_FROM_TB0(do_float_ ## name ## _s);  \
2629     DEBUG_FPU_STATE();    \
2630     FORCE_RET();          \
2631 }
2632 FLOAT_HOP(rsqrt)
2633 FLOAT_HOP(recip)
2634 #undef FLOAT_HOP
2635
2636 /* operations calling helpers, for ps */
2637 #define FLOAT_HOP(name)   \
2638 FLOAT_OP(name, ps)        \
2639 {                         \
2640     CALL_FROM_TB0(do_float_ ## name ## _ps); \
2641     DEBUG_FPU_STATE();    \
2642     FORCE_RET();          \
2643 }
2644 FLOAT_HOP(addr)
2645 FLOAT_HOP(mulr)
2646 #undef FLOAT_HOP
2647
2648 /* ternary operations */
2649 #define FLOAT_TERNOP(name1, name2) \
2650 FLOAT_OP(name1 ## name2, d)        \
2651 {                                  \
2652     FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status);    \
2653     FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status);    \
2654     DEBUG_FPU_STATE();             \
2655     FORCE_RET();                   \
2656 }                                  \
2657 FLOAT_OP(name1 ## name2, s)        \
2658 {                                  \
2659     FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2660     FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2661     DEBUG_FPU_STATE();             \
2662     FORCE_RET();                   \
2663 }                                  \
2664 FLOAT_OP(name1 ## name2, ps)       \
2665 {                                  \
2666     FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2667     FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2668     FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2669     FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2670     DEBUG_FPU_STATE();             \
2671     FORCE_RET();                   \
2672 }
2673 FLOAT_TERNOP(mul, add)
2674 FLOAT_TERNOP(mul, sub)
2675 #undef FLOAT_TERNOP
2676
2677 /* negated ternary operations */
2678 #define FLOAT_NTERNOP(name1, name2) \
2679 FLOAT_OP(n ## name1 ## name2, d)    \
2680 {                                   \
2681     FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status);    \
2682     FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status);    \
2683     FDT2 = float64_chs(FDT2);       \
2684     DEBUG_FPU_STATE();              \
2685     FORCE_RET();                    \
2686 }                                   \
2687 FLOAT_OP(n ## name1 ## name2, s)    \
2688 {                                   \
2689     FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2690     FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2691     FST2 = float32_chs(FST2);       \
2692     DEBUG_FPU_STATE();              \
2693     FORCE_RET();                    \
2694 }                                   \
2695 FLOAT_OP(n ## name1 ## name2, ps)   \
2696 {                                   \
2697     FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
2698     FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2699     FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
2700     FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2701     FST2 = float32_chs(FST2);       \
2702     FSTH2 = float32_chs(FSTH2);     \
2703     DEBUG_FPU_STATE();              \
2704     FORCE_RET();                    \
2705 }
2706 FLOAT_NTERNOP(mul, add)
2707 FLOAT_NTERNOP(mul, sub)
2708 #undef FLOAT_NTERNOP
2709
2710 /* unary operations, modifying fp status  */
2711 #define FLOAT_UNOP(name)  \
2712 FLOAT_OP(name, d)         \
2713 {                         \
2714     FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
2715     DEBUG_FPU_STATE();    \
2716     FORCE_RET();          \
2717 }                         \
2718 FLOAT_OP(name, s)         \
2719 {                         \
2720     FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
2721     DEBUG_FPU_STATE();    \
2722     FORCE_RET();          \
2723 }
2724 FLOAT_UNOP(sqrt)
2725 #undef FLOAT_UNOP
2726
2727 /* unary operations, not modifying fp status  */
2728 #define FLOAT_UNOP(name)  \
2729 FLOAT_OP(name, d)         \
2730 {                         \
2731     FDT2 = float64_ ## name(FDT0);   \
2732     DEBUG_FPU_STATE();    \
2733     FORCE_RET();          \
2734 }                         \
2735 FLOAT_OP(name, s)         \
2736 {                         \
2737     FST2 = float32_ ## name(FST0);   \
2738     DEBUG_FPU_STATE();    \
2739     FORCE_RET();          \
2740 }                         \
2741 FLOAT_OP(name, ps)        \
2742 {                         \
2743     FST2 = float32_ ## name(FST0);   \
2744     FSTH2 = float32_ ## name(FSTH0); \
2745     DEBUG_FPU_STATE();    \
2746     FORCE_RET();          \
2747 }
2748 FLOAT_UNOP(abs)
2749 FLOAT_UNOP(chs)
2750 #undef FLOAT_UNOP
2751
2752 FLOAT_OP(mov, d)
2753 {
2754     FDT2 = FDT0;
2755     DEBUG_FPU_STATE();
2756     FORCE_RET();
2757 }
2758 FLOAT_OP(mov, s)
2759 {
2760     FST2 = FST0;
2761     DEBUG_FPU_STATE();
2762     FORCE_RET();
2763 }
2764 FLOAT_OP(mov, ps)
2765 {
2766     FST2 = FST0;
2767     FSTH2 = FSTH0;
2768     DEBUG_FPU_STATE();
2769     FORCE_RET();
2770 }
2771 FLOAT_OP(alnv, ps)
2772 {
2773     switch (T0 & 0x7) {
2774     case 0:
2775         FST2 = FST0;
2776         FSTH2 = FSTH0;
2777         break;
2778     case 4:
2779 #ifdef TARGET_WORDS_BIGENDIAN
2780         FSTH2 = FST0;
2781         FST2 = FSTH1;
2782 #else
2783         FSTH2 = FST1;
2784         FST2 = FSTH0;
2785 #endif
2786         break;
2787     default: /* unpredictable */
2788         break;
2789     }
2790     DEBUG_FPU_STATE();
2791     FORCE_RET();
2792 }
2793
2794 #ifdef CONFIG_SOFTFLOAT
2795 #define clear_invalid() do {                                \
2796     int flags = get_float_exception_flags(&env->fpu->fp_status); \
2797     flags &= ~float_flag_invalid;                           \
2798     set_float_exception_flags(flags, &env->fpu->fp_status); \
2799 } while(0)
2800 #else
2801 #define clear_invalid() do { } while(0)
2802 #endif
2803
2804 extern void dump_fpu_s(CPUState *env);
2805
2806 #define CMP_OP(fmt, op)                                \
2807 void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void)       \
2808 {                                                      \
2809     CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
2810     DEBUG_FPU_STATE();                                 \
2811     FORCE_RET();                                       \
2812 }                                                      \
2813 void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void)    \
2814 {                                                      \
2815     CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
2816     DEBUG_FPU_STATE();                                 \
2817     FORCE_RET();                                       \
2818 }
2819 #define CMP_OPS(op)   \
2820 CMP_OP(d, op)         \
2821 CMP_OP(s, op)         \
2822 CMP_OP(ps, op)
2823
2824 CMP_OPS(f)
2825 CMP_OPS(un)
2826 CMP_OPS(eq)
2827 CMP_OPS(ueq)
2828 CMP_OPS(olt)
2829 CMP_OPS(ult)
2830 CMP_OPS(ole)
2831 CMP_OPS(ule)
2832 CMP_OPS(sf)
2833 CMP_OPS(ngle)
2834 CMP_OPS(seq)
2835 CMP_OPS(ngl)
2836 CMP_OPS(lt)
2837 CMP_OPS(nge)
2838 CMP_OPS(le)
2839 CMP_OPS(ngt)
2840 #undef CMP_OPS
2841 #undef CMP_OP
2842
2843 void op_bc1f (void)
2844 {
2845     T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2846     DEBUG_FPU_STATE();
2847     FORCE_RET();
2848 }
2849 void op_bc1any2f (void)
2850 {
2851     T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2852     DEBUG_FPU_STATE();
2853     FORCE_RET();
2854 }
2855 void op_bc1any4f (void)
2856 {
2857     T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
2858     DEBUG_FPU_STATE();
2859     FORCE_RET();
2860 }
2861
2862 void op_bc1t (void)
2863 {
2864     T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
2865     DEBUG_FPU_STATE();
2866     FORCE_RET();
2867 }
2868 void op_bc1any2t (void)
2869 {
2870     T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
2871     DEBUG_FPU_STATE();
2872     FORCE_RET();
2873 }
2874 void op_bc1any4t (void)
2875 {
2876     T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
2877     DEBUG_FPU_STATE();
2878     FORCE_RET();
2879 }
2880
2881 void op_tlbwi (void)
2882 {
2883     CALL_FROM_TB0(env->tlb->do_tlbwi);
2884     FORCE_RET();
2885 }
2886
2887 void op_tlbwr (void)
2888 {
2889     CALL_FROM_TB0(env->tlb->do_tlbwr);
2890     FORCE_RET();
2891 }
2892
2893 void op_tlbp (void)
2894 {
2895     CALL_FROM_TB0(env->tlb->do_tlbp);
2896     FORCE_RET();
2897 }
2898
2899 void op_tlbr (void)
2900 {
2901     CALL_FROM_TB0(env->tlb->do_tlbr);
2902     FORCE_RET();
2903 }
2904
2905 /* Specials */
2906 #if defined (CONFIG_USER_ONLY)
2907 void op_tls_value (void)
2908 {
2909     T0 = env->tls_value;
2910 }
2911 #endif
2912
2913 void op_pmon (void)
2914 {
2915     CALL_FROM_TB1(do_pmon, PARAM1);
2916     FORCE_RET();
2917 }
2918
2919 void op_di (void)
2920 {
2921     T0 = env->CP0_Status;
2922     env->CP0_Status = T0 & ~(1 << CP0St_IE);
2923     CALL_FROM_TB1(cpu_mips_update_irq, env);
2924     FORCE_RET();
2925 }
2926
2927 void op_ei (void)
2928 {
2929     T0 = env->CP0_Status;
2930     env->CP0_Status = T0 | (1 << CP0St_IE);
2931     CALL_FROM_TB1(cpu_mips_update_irq, env);
2932     FORCE_RET();
2933 }
2934
2935 void op_trap (void)
2936 {
2937     if (T0) {
2938         CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2939     }
2940     FORCE_RET();
2941 }
2942
2943 void op_debug (void)
2944 {
2945     CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2946     FORCE_RET();
2947 }
2948
2949 void op_set_lladdr (void)
2950 {
2951     env->CP0_LLAddr = T2;
2952     FORCE_RET();
2953 }
2954
2955 void debug_pre_eret (void);
2956 void debug_post_eret (void);
2957 void op_eret (void)
2958 {
2959     if (loglevel & CPU_LOG_EXEC)
2960         CALL_FROM_TB0(debug_pre_eret);
2961     if (env->CP0_Status & (1 << CP0St_ERL)) {
2962         env->PC[env->current_tc] = env->CP0_ErrorEPC;
2963         env->CP0_Status &= ~(1 << CP0St_ERL);
2964     } else {
2965         env->PC[env->current_tc] = env->CP0_EPC;
2966         env->CP0_Status &= ~(1 << CP0St_EXL);
2967     }
2968     CALL_FROM_TB1(compute_hflags, env);
2969     if (loglevel & CPU_LOG_EXEC)
2970         CALL_FROM_TB0(debug_post_eret);
2971     env->CP0_LLAddr = 1;
2972     FORCE_RET();
2973 }
2974
2975 void op_deret (void)
2976 {
2977     if (loglevel & CPU_LOG_EXEC)
2978         CALL_FROM_TB0(debug_pre_eret);
2979     env->PC[env->current_tc] = env->CP0_DEPC;
2980     env->hflags &= MIPS_HFLAG_DM;
2981     CALL_FROM_TB1(compute_hflags, env);
2982     if (loglevel & CPU_LOG_EXEC)
2983         CALL_FROM_TB0(debug_post_eret);
2984     env->CP0_LLAddr = 1;
2985     FORCE_RET();
2986 }
2987
2988 void op_rdhwr_cpunum(void)
2989 {
2990     if ((env->hflags & MIPS_HFLAG_CP0) ||
2991         (env->CP0_HWREna & (1 << 0)))
2992         T0 = env->CP0_EBase & 0x3ff;
2993     else
2994         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2995     FORCE_RET();
2996 }
2997
2998 void op_rdhwr_synci_step(void)
2999 {
3000     if ((env->hflags & MIPS_HFLAG_CP0) ||
3001         (env->CP0_HWREna & (1 << 1)))
3002         T0 = env->SYNCI_Step;
3003     else
3004         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3005     FORCE_RET();
3006 }
3007
3008 void op_rdhwr_cc(void)
3009 {
3010     if ((env->hflags & MIPS_HFLAG_CP0) ||
3011         (env->CP0_HWREna & (1 << 2)))
3012         T0 = env->CP0_Count;
3013     else
3014         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3015     FORCE_RET();
3016 }
3017
3018 void op_rdhwr_ccres(void)
3019 {
3020     if ((env->hflags & MIPS_HFLAG_CP0) ||
3021         (env->CP0_HWREna & (1 << 3)))
3022         T0 = env->CCRes;
3023     else
3024         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
3025     FORCE_RET();
3026 }
3027
3028 void op_save_state (void)
3029 {
3030     env->hflags = PARAM1;
3031     FORCE_RET();
3032 }
3033
3034 void op_save_pc (void)
3035 {
3036     env->PC[env->current_tc] = PARAM1;
3037     FORCE_RET();
3038 }
3039
3040 #if defined(TARGET_MIPS64)
3041 void op_save_pc64 (void)
3042 {
3043     env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
3044     FORCE_RET();
3045 }
3046 #endif
3047
3048 void op_interrupt_restart (void)
3049 {
3050     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
3051         !(env->CP0_Status & (1 << CP0St_ERL)) &&
3052         !(env->hflags & MIPS_HFLAG_DM) &&
3053         (env->CP0_Status & (1 << CP0St_IE)) &&
3054         (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
3055         env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
3056         CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
3057     }
3058     FORCE_RET();
3059 }
3060
3061 void op_raise_exception (void)
3062 {
3063     CALL_FROM_TB1(do_raise_exception, PARAM1);
3064     FORCE_RET();
3065 }
3066
3067 void op_raise_exception_err (void)
3068 {
3069     CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
3070     FORCE_RET();
3071 }
3072
3073 void op_exit_tb (void)
3074 {
3075     EXIT_TB();
3076     FORCE_RET();
3077 }
3078
3079 void op_wait (void)
3080 {
3081     env->halted = 1;
3082     CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
3083     FORCE_RET();
3084 }
3085
3086 /* Bitfield operations. */
3087 void op_ext(void)
3088 {
3089     unsigned int pos = PARAM1;
3090     unsigned int size = PARAM2;
3091
3092     T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
3093     FORCE_RET();
3094 }
3095
3096 void op_ins(void)
3097 {
3098     unsigned int pos = PARAM1;
3099     unsigned int size = PARAM2;
3100     target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
3101
3102     T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask));
3103     FORCE_RET();
3104 }
3105
3106 void op_wsbh(void)
3107 {
3108     T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF));
3109     FORCE_RET();
3110 }
3111
3112 #if defined(TARGET_MIPS64)
3113 void op_dext(void)
3114 {
3115     unsigned int pos = PARAM1;
3116     unsigned int size = PARAM2;
3117
3118     T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
3119     FORCE_RET();
3120 }
3121
3122 void op_dins(void)
3123 {
3124     unsigned int pos = PARAM1;
3125     unsigned int size = PARAM2;
3126     target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
3127
3128     T0 = (T0 & ~mask) | ((T1 << pos) & mask);
3129     FORCE_RET();
3130 }
3131
3132 void op_dsbh(void)
3133 {
3134     T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
3135     FORCE_RET();
3136 }
3137
3138 void op_dshd(void)
3139 {
3140     T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
3141     T0 = (T1 << 32) | (T1 >> 32);
3142     FORCE_RET();
3143 }
3144 #endif
3145
3146 void op_seb(void)
3147 {
3148     T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
3149     FORCE_RET();
3150 }
3151
3152 void op_seh(void)
3153 {
3154     T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
3155     FORCE_RET();
3156 }