hw/eccmemctl.c

   1 /*
   2  * QEMU Sparc Sun4m ECC memory controller emulation
   3  *
   4  * Copyright (c) 2007 Robert Reif
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "sysemu.h"
  27
  28 //#define DEBUG_ECC
  29
  30 #ifdef DEBUG_ECC
  31 #define DPRINTF(fmt, args...)                           \
  32     do { printf("ECC: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 /* There are 3 versions of this chip used in SMP sun4m systems:
  38  * MCC (version 0, implementation 0) SS-600MP
  39  * EMC (version 0, implementation 1) SS-10
  40  * SMC (version 0, implementation 2) SS-10SX and SS-20
  41  */
  42
  43 /* Register offsets */
  44 #define ECC_FCR_REG    0
  45 #define ECC_FSR_REG    8
  46 #define ECC_FAR0_REG   16
  47 #define ECC_FAR1_REG   20
  48 #define ECC_DIAG_REG   24
  49
  50 /* ECC fault control register */
  51 #define ECC_FCR_EE     0x00000001      /* Enable ECC checking */
  52 #define ECC_FCR_EI     0x00000010      /* Enable Interrupts on correctable errors */
  53 #define ECC_FCR_VER    0x0f000000      /* Version */
  54 #define ECC_FCR_IMPL   0xf0000000      /* Implementation */
  55
  56 /* ECC fault status register */
  57 #define ECC_FSR_CE     0x00000001      /* Correctable error */
  58 #define ECC_FSR_BS     0x00000002      /* C2 graphics bad slot access */
  59 #define ECC_FSR_TO     0x00000004      /* Timeout on write */
  60 #define ECC_FSR_UE     0x00000008      /* Uncorrectable error */
  61 #define ECC_FSR_DW     0x000000f0      /* Index of double word in block */
  62 #define ECC_FSR_SYND   0x0000ff00      /* Syndrome for correctable error */
  63 #define ECC_FSR_ME     0x00010000      /* Multiple errors */
  64 #define ECC_FSR_C2ERR  0x00020000      /* C2 graphics error */
  65
  66 /* ECC fault address register 0 */
  67 #define ECC_FAR0_PADDR 0x0000000f      /* PA[32-35] */
  68 #define ECC_FAR0_TYPE  0x000000f0      /* Transaction type */
  69 #define ECC_FAR0_SIZE  0x00000700      /* Transaction size */
  70 #define ECC_FAR0_CACHE 0x00000800      /* Mapped cacheable */
  71 #define ECC_FAR0_LOCK  0x00001000      /* Error occurred in attomic cycle */
  72 #define ECC_FAR0_BMODE 0x00002000      /* Boot mode */
  73 #define ECC_FAR0_VADDR 0x003fc000      /* VA[12-19] (superset bits) */
  74 #define ECC_FAR0_S     0x08000000      /* Supervisor mode */
  75 #define ECC_FARO_MID   0xf0000000      /* Module ID */
  76
  77 /* ECC diagnostic register */
  78 #define ECC_DIAG_CBX   0x00000001
  79 #define ECC_DIAG_CB0   0x00000002
  80 #define ECC_DIAG_CB1   0x00000004
  81 #define ECC_DIAG_CB2   0x00000008
  82 #define ECC_DIAG_CB4   0x00000010
  83 #define ECC_DIAG_CB8   0x00000020
  84 #define ECC_DIAG_CB16  0x00000040
  85 #define ECC_DIAG_CB32  0x00000080
  86 #define ECC_DIAG_DMODE 0x00000c00
  87
  88 #define ECC_NREGS      8
  89 #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
  90 #define ECC_ADDR_MASK  (ECC_SIZE - 1)
  91
  92 typedef struct ECCState {
  93     uint32_t regs[ECC_NREGS];
  94 } ECCState;
  95
  96 static void ecc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  97 {
  98     printf("ECC: Unsupported write 0x" TARGET_FMT_plx " %02x\n",
  99            addr, val & 0xff);
 100 }
 101
 102 static uint32_t ecc_mem_readb(void *opaque, target_phys_addr_t addr)
 103 {
 104     printf("ECC: Unsupported read 0x" TARGET_FMT_plx " 00\n", addr);
 105     return 0;
 106 }
 107
 108 static void ecc_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 109 {
 110     printf("ECC: Unsupported write 0x" TARGET_FMT_plx " %04x\n",
 111            addr, val & 0xffff);
 112 }
 113
 114 static uint32_t ecc_mem_readw(void *opaque, target_phys_addr_t addr)
 115 {
 116     printf("ECC: Unsupported read 0x" TARGET_FMT_plx " 0000\n", addr);
 117     return 0;
 118 }
 119
 120 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 121 {
 122     ECCState *s = opaque;
 123
 124     switch (addr & ECC_ADDR_MASK) {
 125     case ECC_FCR_REG:
 126         s->regs[0] = (s->regs[0] & (ECC_FCR_VER | ECC_FCR_IMPL)) |
 127                      (val & ~(ECC_FCR_VER | ECC_FCR_IMPL));
 128         DPRINTF("Write fault control %08x\n", val);
 129         break;
 130     case 4:
 131         s->regs[1] =  val;
 132         DPRINTF("Write reg[1] %08x\n", val);
 133         break;
 134     case ECC_FSR_REG:
 135         s->regs[2] =  val;
 136         DPRINTF("Write fault status %08x\n", val);
 137         break;
 138     case 12:
 139         s->regs[3] =  val;
 140         DPRINTF("Write reg[3] %08x\n", val);
 141         break;
 142     case ECC_FAR0_REG:
 143         s->regs[4] =  val;
 144         DPRINTF("Write fault address 0 %08x\n", val);
 145         break;
 146     case ECC_FAR1_REG:
 147         s->regs[5] =  val;
 148         DPRINTF("Write fault address 1 %08x\n", val);
 149         break;
 150     case ECC_DIAG_REG:
 151         s->regs[6] =  val;
 152         DPRINTF("Write diag %08x\n", val);
 153         break;
 154     case 28:
 155         s->regs[7] =  val;
 156         DPRINTF("Write reg[7] %08x\n", val);
 157         break;
 158     }
 159 }
 160
 161 static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
 162 {
 163     ECCState *s = opaque;
 164     uint32_t ret = 0;
 165
 166     switch (addr & ECC_ADDR_MASK) {
 167     case ECC_FCR_REG:
 168         ret = s->regs[0];
 169         DPRINTF("Read enable %08x\n", ret);
 170         break;
 171     case 4:
 172         ret = s->regs[1];
 173         DPRINTF("Read register[1] %08x\n", ret);
 174         break;
 175     case ECC_FSR_REG:
 176         ret = s->regs[2];
 177         DPRINTF("Read fault status %08x\n", ret);
 178         break;
 179     case 12:
 180         ret = s->regs[3];
 181         DPRINTF("Read reg[3] %08x\n", ret);
 182         break;
 183     case ECC_FAR0_REG:
 184         ret = s->regs[4];
 185         DPRINTF("Read fault address 0 %08x\n", ret);
 186         break;
 187     case ECC_FAR1_REG:
 188         ret = s->regs[5];
 189         DPRINTF("Read fault address 1 %08x\n", ret);
 190         break;
 191     case ECC_DIAG_REG:
 192         ret = s->regs[6];
 193         DPRINTF("Read diag %08x\n", ret);
 194         break;
 195     case 28:
 196         ret = s->regs[7];
 197         DPRINTF("Read reg[7] %08x\n", ret);
 198         break;
 199     }
 200     return ret;
 201 }
 202
 203 static CPUReadMemoryFunc *ecc_mem_read[3] = {
 204     ecc_mem_readb,
 205     ecc_mem_readw,
 206     ecc_mem_readl,
 207 };
 208
 209 static CPUWriteMemoryFunc *ecc_mem_write[3] = {
 210     ecc_mem_writeb,
 211     ecc_mem_writew,
 212     ecc_mem_writel,
 213 };
 214
 215 static int ecc_load(QEMUFile *f, void *opaque, int version_id)
 216 {
 217     ECCState *s = opaque;
 218     int i;
 219
 220     if (version_id != 1)
 221         return -EINVAL;
 222
 223     for (i = 0; i < ECC_NREGS; i++)
 224         qemu_get_be32s(f, &s->regs[i]);
 225
 226     return 0;
 227 }
 228
 229 static void ecc_save(QEMUFile *f, void *opaque)
 230 {
 231     ECCState *s = opaque;
 232     int i;
 233
 234     for (i = 0; i < ECC_NREGS; i++)
 235         qemu_put_be32s(f, &s->regs[i]);
 236 }
 237
 238 static void ecc_reset(void *opaque)
 239 {
 240     ECCState *s = opaque;
 241     int i;
 242
 243     s->regs[ECC_FCR_REG] &= (ECC_FCR_VER | ECC_FCR_IMPL);
 244
 245     for (i = 1; i < ECC_NREGS; i++)
 246         s->regs[i] = 0;
 247 }
 248
 249 void * ecc_init(target_phys_addr_t base, uint32_t version)
 250 {
 251     int ecc_io_memory;
 252     ECCState *s;
 253
 254     s = qemu_mallocz(sizeof(ECCState));
 255     if (!s)
 256         return NULL;
 257
 258     s->regs[0] = version;
 259
 260     ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
 261     cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
 262     register_savevm("ECC", base, 1, ecc_save, ecc_load, s);
 263     qemu_register_reset(ecc_reset, s);
 264     ecc_reset(s);
 265     return s;
 266 }