2 * QEMU Cirrus CLGD 54xx VGA Emulator.
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
37 * - destination write mask support not complete (bits 5..7)
38 * - optimize linear mappings
39 * - optimize bitblt functions
42 //#define DEBUG_CIRRUS
43 //#define DEBUG_BITBLT
45 /***************************************
49 ***************************************/
51 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
54 #define CIRRUS_ID_CLGD5422 (0x23<<2)
55 #define CIRRUS_ID_CLGD5426 (0x24<<2)
56 #define CIRRUS_ID_CLGD5424 (0x25<<2)
57 #define CIRRUS_ID_CLGD5428 (0x26<<2)
58 #define CIRRUS_ID_CLGD5430 (0x28<<2)
59 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
60 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
61 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64 #define CIRRUS_SR7_BPP_VGA 0x00
65 #define CIRRUS_SR7_BPP_SVGA 0x01
66 #define CIRRUS_SR7_BPP_MASK 0x0e
67 #define CIRRUS_SR7_BPP_8 0x00
68 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69 #define CIRRUS_SR7_BPP_24 0x04
70 #define CIRRUS_SR7_BPP_16 0x06
71 #define CIRRUS_SR7_BPP_32 0x08
72 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75 #define CIRRUS_MEMSIZE_512k 0x08
76 #define CIRRUS_MEMSIZE_1M 0x10
77 #define CIRRUS_MEMSIZE_2M 0x18
78 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81 #define CIRRUS_CURSOR_SHOW 0x01
82 #define CIRRUS_CURSOR_HIDDENPEL 0x02
83 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86 #define CIRRUS_BUSTYPE_VLBFAST 0x10
87 #define CIRRUS_BUSTYPE_PCI 0x20
88 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
89 #define CIRRUS_BUSTYPE_ISA 0x38
90 #define CIRRUS_MMIO_ENABLE 0x04
91 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95 #define CIRRUS_BANKING_DUAL 0x01
96 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99 #define CIRRUS_BLTMODE_BACKWARDS 0x01
100 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
105 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112 #define CIRRUS_BLT_BUSY 0x01
113 #define CIRRUS_BLT_START 0x02
114 #define CIRRUS_BLT_RESET 0x04
115 #define CIRRUS_BLT_FIFOUSED 0x10
116 #define CIRRUS_BLT_AUTOSTART 0x80
119 #define CIRRUS_ROP_0 0x00
120 #define CIRRUS_ROP_SRC_AND_DST 0x05
121 #define CIRRUS_ROP_NOP 0x06
122 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123 #define CIRRUS_ROP_NOTDST 0x0b
124 #define CIRRUS_ROP_SRC 0x0d
125 #define CIRRUS_ROP_1 0x0e
126 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127 #define CIRRUS_ROP_SRC_XOR_DST 0x59
128 #define CIRRUS_ROP_SRC_OR_DST 0x6d
129 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132 #define CIRRUS_ROP_NOTSRC 0xd0
133 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136 #define CIRRUS_ROP_NOP_INDEX 2
137 #define CIRRUS_ROP_SRC_INDEX 5
140 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
141 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
142 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
155 #define CIRRUS_MMIO_BLTROP 0x1a // byte
156 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175 // PCI 0x00: vendor, 0x02: device
176 #define PCI_VENDOR_CIRRUS 0x1013
177 #define PCI_DEVICE_CLGD5462 0x00d0
178 #define PCI_DEVICE_CLGD5465 0x00d6
180 // PCI 0x04: command(word), 0x06(word): status
181 #define PCI_COMMAND_IOACCESS 0x0001
182 #define PCI_COMMAND_MEMACCESS 0x0002
183 #define PCI_COMMAND_BUSMASTER 0x0004
184 #define PCI_COMMAND_SPECIALCYCLE 0x0008
185 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
186 #define PCI_COMMAND_PALETTESNOOPING 0x0020
187 #define PCI_COMMAND_PARITYDETECTION 0x0040
188 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
189 #define PCI_COMMAND_SERR 0x0100
190 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
191 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
192 #define PCI_CLASS_BASE_DISPLAY 0x03
193 // PCI 0x08, 0x00ff0000
194 #define PCI_CLASS_SUB_VGA 0x00
195 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
196 #define PCI_CLASS_HEADERTYPE_00h 0x00
197 // 0x10-0x3f (headertype 00h)
198 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
199 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
200 #define PCI_MAP_MEM 0x0
201 #define PCI_MAP_IO 0x1
202 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
203 #define PCI_MAP_IO_ADDR_MASK (~0x3)
204 #define PCI_MAP_MEMFLAGS_32BIT 0x0
205 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
206 #define PCI_MAP_MEMFLAGS_64BIT 0x4
207 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
208 // PCI 0x28: cardbus CIS pointer
209 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
210 // PCI 0x30: expansion ROM base address
211 #define PCI_ROMBIOS_ENABLED 0x1
212 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
213 // PCI 0x38: reserved
214 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
216 #define CIRRUS_PNPMMIO_SIZE 0x1000
219 /* I/O and memory hook */
220 #define CIRRUS_HOOK_NOT_HANDLED 0
221 #define CIRRUS_HOOK_HANDLED 1
223 struct CirrusVGAState
;
224 typedef void (*cirrus_bitblt_rop_t
) (struct CirrusVGAState
*s
,
225 uint8_t * dst
, const uint8_t * src
,
226 int dstpitch
, int srcpitch
,
227 int bltwidth
, int bltheight
);
228 typedef void (*cirrus_fill_t
)(struct CirrusVGAState
*s
,
229 uint8_t *dst
, int dst_pitch
, int width
, int height
);
231 typedef struct CirrusVGAState
{
234 int cirrus_linear_io_addr
;
235 int cirrus_linear_bitblt_io_addr
;
236 int cirrus_mmio_io_addr
;
237 uint32_t cirrus_addr_mask
;
238 uint32_t linear_mmio_mask
;
239 uint8_t cirrus_shadow_gr0
;
240 uint8_t cirrus_shadow_gr1
;
241 uint8_t cirrus_hidden_dac_lockindex
;
242 uint8_t cirrus_hidden_dac_data
;
243 uint32_t cirrus_bank_base
[2];
244 uint32_t cirrus_bank_limit
[2];
245 uint8_t cirrus_hidden_palette
[48];
246 uint32_t hw_cursor_x
;
247 uint32_t hw_cursor_y
;
248 int cirrus_blt_pixelwidth
;
249 int cirrus_blt_width
;
250 int cirrus_blt_height
;
251 int cirrus_blt_dstpitch
;
252 int cirrus_blt_srcpitch
;
253 uint32_t cirrus_blt_fgcol
;
254 uint32_t cirrus_blt_bgcol
;
255 uint32_t cirrus_blt_dstaddr
;
256 uint32_t cirrus_blt_srcaddr
;
257 uint8_t cirrus_blt_mode
;
258 uint8_t cirrus_blt_modeext
;
259 cirrus_bitblt_rop_t cirrus_rop
;
260 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
261 uint8_t cirrus_bltbuf
[CIRRUS_BLTBUFSIZE
];
262 uint8_t *cirrus_srcptr
;
263 uint8_t *cirrus_srcptr_end
;
264 uint32_t cirrus_srccounter
;
265 /* hwcursor display state */
266 int last_hw_cursor_size
;
267 int last_hw_cursor_x
;
268 int last_hw_cursor_y
;
269 int last_hw_cursor_y_start
;
270 int last_hw_cursor_y_end
;
271 int real_vram_size
; /* XXX: suppress that */
272 CPUWriteMemoryFunc
**cirrus_linear_write
;
275 typedef struct PCICirrusVGAState
{
277 CirrusVGAState cirrus_vga
;
280 static uint8_t rop_to_index
[256];
282 /***************************************
286 ***************************************/
289 static void cirrus_bitblt_reset(CirrusVGAState
*s
);
290 static void cirrus_update_memory_access(CirrusVGAState
*s
);
292 /***************************************
296 ***************************************/
298 static void cirrus_bitblt_rop_nop(CirrusVGAState
*s
,
299 uint8_t *dst
,const uint8_t *src
,
300 int dstpitch
,int srcpitch
,
301 int bltwidth
,int bltheight
)
305 static void cirrus_bitblt_fill_nop(CirrusVGAState
*s
,
307 int dstpitch
, int bltwidth
,int bltheight
)
312 #define ROP_OP(d, s) d = 0
313 #include "cirrus_vga_rop.h"
315 #define ROP_NAME src_and_dst
316 #define ROP_OP(d, s) d = (s) & (d)
317 #include "cirrus_vga_rop.h"
319 #define ROP_NAME src_and_notdst
320 #define ROP_OP(d, s) d = (s) & (~(d))
321 #include "cirrus_vga_rop.h"
323 #define ROP_NAME notdst
324 #define ROP_OP(d, s) d = ~(d)
325 #include "cirrus_vga_rop.h"
328 #define ROP_OP(d, s) d = s
329 #include "cirrus_vga_rop.h"
332 #define ROP_OP(d, s) d = ~0
333 #include "cirrus_vga_rop.h"
335 #define ROP_NAME notsrc_and_dst
336 #define ROP_OP(d, s) d = (~(s)) & (d)
337 #include "cirrus_vga_rop.h"
339 #define ROP_NAME src_xor_dst
340 #define ROP_OP(d, s) d = (s) ^ (d)
341 #include "cirrus_vga_rop.h"
343 #define ROP_NAME src_or_dst
344 #define ROP_OP(d, s) d = (s) | (d)
345 #include "cirrus_vga_rop.h"
347 #define ROP_NAME notsrc_or_notdst
348 #define ROP_OP(d, s) d = (~(s)) | (~(d))
349 #include "cirrus_vga_rop.h"
351 #define ROP_NAME src_notxor_dst
352 #define ROP_OP(d, s) d = ~((s) ^ (d))
353 #include "cirrus_vga_rop.h"
355 #define ROP_NAME src_or_notdst
356 #define ROP_OP(d, s) d = (s) | (~(d))
357 #include "cirrus_vga_rop.h"
359 #define ROP_NAME notsrc
360 #define ROP_OP(d, s) d = (~(s))
361 #include "cirrus_vga_rop.h"
363 #define ROP_NAME notsrc_or_dst
364 #define ROP_OP(d, s) d = (~(s)) | (d)
365 #include "cirrus_vga_rop.h"
367 #define ROP_NAME notsrc_and_notdst
368 #define ROP_OP(d, s) d = (~(s)) & (~(d))
369 #include "cirrus_vga_rop.h"
371 static const cirrus_bitblt_rop_t cirrus_fwd_rop
[16] = {
372 cirrus_bitblt_rop_fwd_0
,
373 cirrus_bitblt_rop_fwd_src_and_dst
,
374 cirrus_bitblt_rop_nop
,
375 cirrus_bitblt_rop_fwd_src_and_notdst
,
376 cirrus_bitblt_rop_fwd_notdst
,
377 cirrus_bitblt_rop_fwd_src
,
378 cirrus_bitblt_rop_fwd_1
,
379 cirrus_bitblt_rop_fwd_notsrc_and_dst
,
380 cirrus_bitblt_rop_fwd_src_xor_dst
,
381 cirrus_bitblt_rop_fwd_src_or_dst
,
382 cirrus_bitblt_rop_fwd_notsrc_or_notdst
,
383 cirrus_bitblt_rop_fwd_src_notxor_dst
,
384 cirrus_bitblt_rop_fwd_src_or_notdst
,
385 cirrus_bitblt_rop_fwd_notsrc
,
386 cirrus_bitblt_rop_fwd_notsrc_or_dst
,
387 cirrus_bitblt_rop_fwd_notsrc_and_notdst
,
390 static const cirrus_bitblt_rop_t cirrus_bkwd_rop
[16] = {
391 cirrus_bitblt_rop_bkwd_0
,
392 cirrus_bitblt_rop_bkwd_src_and_dst
,
393 cirrus_bitblt_rop_nop
,
394 cirrus_bitblt_rop_bkwd_src_and_notdst
,
395 cirrus_bitblt_rop_bkwd_notdst
,
396 cirrus_bitblt_rop_bkwd_src
,
397 cirrus_bitblt_rop_bkwd_1
,
398 cirrus_bitblt_rop_bkwd_notsrc_and_dst
,
399 cirrus_bitblt_rop_bkwd_src_xor_dst
,
400 cirrus_bitblt_rop_bkwd_src_or_dst
,
401 cirrus_bitblt_rop_bkwd_notsrc_or_notdst
,
402 cirrus_bitblt_rop_bkwd_src_notxor_dst
,
403 cirrus_bitblt_rop_bkwd_src_or_notdst
,
404 cirrus_bitblt_rop_bkwd_notsrc
,
405 cirrus_bitblt_rop_bkwd_notsrc_or_dst
,
406 cirrus_bitblt_rop_bkwd_notsrc_and_notdst
,
409 #define TRANSP_ROP(name) {\
413 #define TRANSP_NOP(func) {\
418 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop
[16][2] = {
419 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0
),
420 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst
),
421 TRANSP_NOP(cirrus_bitblt_rop_nop
),
422 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst
),
423 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst
),
424 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src
),
425 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1
),
426 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst
),
427 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst
),
428 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst
),
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst
),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst
),
431 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst
),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc
),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst
),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst
),
437 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop
[16][2] = {
438 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0
),
439 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst
),
440 TRANSP_NOP(cirrus_bitblt_rop_nop
),
441 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst
),
442 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst
),
443 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src
),
444 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1
),
445 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst
),
446 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst
),
447 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst
),
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst
),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst
),
450 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst
),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc
),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst
),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst
),
456 #define ROP2(name) {\
463 #define ROP_NOP2(func) {\
470 static const cirrus_bitblt_rop_t cirrus_patternfill
[16][4] = {
471 ROP2(cirrus_patternfill_0
),
472 ROP2(cirrus_patternfill_src_and_dst
),
473 ROP_NOP2(cirrus_bitblt_rop_nop
),
474 ROP2(cirrus_patternfill_src_and_notdst
),
475 ROP2(cirrus_patternfill_notdst
),
476 ROP2(cirrus_patternfill_src
),
477 ROP2(cirrus_patternfill_1
),
478 ROP2(cirrus_patternfill_notsrc_and_dst
),
479 ROP2(cirrus_patternfill_src_xor_dst
),
480 ROP2(cirrus_patternfill_src_or_dst
),
481 ROP2(cirrus_patternfill_notsrc_or_notdst
),
482 ROP2(cirrus_patternfill_src_notxor_dst
),
483 ROP2(cirrus_patternfill_src_or_notdst
),
484 ROP2(cirrus_patternfill_notsrc
),
485 ROP2(cirrus_patternfill_notsrc_or_dst
),
486 ROP2(cirrus_patternfill_notsrc_and_notdst
),
489 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp
[16][4] = {
490 ROP2(cirrus_colorexpand_transp_0
),
491 ROP2(cirrus_colorexpand_transp_src_and_dst
),
492 ROP_NOP2(cirrus_bitblt_rop_nop
),
493 ROP2(cirrus_colorexpand_transp_src_and_notdst
),
494 ROP2(cirrus_colorexpand_transp_notdst
),
495 ROP2(cirrus_colorexpand_transp_src
),
496 ROP2(cirrus_colorexpand_transp_1
),
497 ROP2(cirrus_colorexpand_transp_notsrc_and_dst
),
498 ROP2(cirrus_colorexpand_transp_src_xor_dst
),
499 ROP2(cirrus_colorexpand_transp_src_or_dst
),
500 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst
),
501 ROP2(cirrus_colorexpand_transp_src_notxor_dst
),
502 ROP2(cirrus_colorexpand_transp_src_or_notdst
),
503 ROP2(cirrus_colorexpand_transp_notsrc
),
504 ROP2(cirrus_colorexpand_transp_notsrc_or_dst
),
505 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst
),
508 static const cirrus_bitblt_rop_t cirrus_colorexpand
[16][4] = {
509 ROP2(cirrus_colorexpand_0
),
510 ROP2(cirrus_colorexpand_src_and_dst
),
511 ROP_NOP2(cirrus_bitblt_rop_nop
),
512 ROP2(cirrus_colorexpand_src_and_notdst
),
513 ROP2(cirrus_colorexpand_notdst
),
514 ROP2(cirrus_colorexpand_src
),
515 ROP2(cirrus_colorexpand_1
),
516 ROP2(cirrus_colorexpand_notsrc_and_dst
),
517 ROP2(cirrus_colorexpand_src_xor_dst
),
518 ROP2(cirrus_colorexpand_src_or_dst
),
519 ROP2(cirrus_colorexpand_notsrc_or_notdst
),
520 ROP2(cirrus_colorexpand_src_notxor_dst
),
521 ROP2(cirrus_colorexpand_src_or_notdst
),
522 ROP2(cirrus_colorexpand_notsrc
),
523 ROP2(cirrus_colorexpand_notsrc_or_dst
),
524 ROP2(cirrus_colorexpand_notsrc_and_notdst
),
527 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp
[16][4] = {
528 ROP2(cirrus_colorexpand_pattern_transp_0
),
529 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst
),
530 ROP_NOP2(cirrus_bitblt_rop_nop
),
531 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst
),
532 ROP2(cirrus_colorexpand_pattern_transp_notdst
),
533 ROP2(cirrus_colorexpand_pattern_transp_src
),
534 ROP2(cirrus_colorexpand_pattern_transp_1
),
535 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst
),
536 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst
),
537 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst
),
538 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst
),
539 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst
),
540 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst
),
541 ROP2(cirrus_colorexpand_pattern_transp_notsrc
),
542 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst
),
543 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst
),
546 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern
[16][4] = {
547 ROP2(cirrus_colorexpand_pattern_0
),
548 ROP2(cirrus_colorexpand_pattern_src_and_dst
),
549 ROP_NOP2(cirrus_bitblt_rop_nop
),
550 ROP2(cirrus_colorexpand_pattern_src_and_notdst
),
551 ROP2(cirrus_colorexpand_pattern_notdst
),
552 ROP2(cirrus_colorexpand_pattern_src
),
553 ROP2(cirrus_colorexpand_pattern_1
),
554 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst
),
555 ROP2(cirrus_colorexpand_pattern_src_xor_dst
),
556 ROP2(cirrus_colorexpand_pattern_src_or_dst
),
557 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst
),
558 ROP2(cirrus_colorexpand_pattern_src_notxor_dst
),
559 ROP2(cirrus_colorexpand_pattern_src_or_notdst
),
560 ROP2(cirrus_colorexpand_pattern_notsrc
),
561 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst
),
562 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst
),
565 static const cirrus_fill_t cirrus_fill
[16][4] = {
567 ROP2(cirrus_fill_src_and_dst
),
568 ROP_NOP2(cirrus_bitblt_fill_nop
),
569 ROP2(cirrus_fill_src_and_notdst
),
570 ROP2(cirrus_fill_notdst
),
571 ROP2(cirrus_fill_src
),
573 ROP2(cirrus_fill_notsrc_and_dst
),
574 ROP2(cirrus_fill_src_xor_dst
),
575 ROP2(cirrus_fill_src_or_dst
),
576 ROP2(cirrus_fill_notsrc_or_notdst
),
577 ROP2(cirrus_fill_src_notxor_dst
),
578 ROP2(cirrus_fill_src_or_notdst
),
579 ROP2(cirrus_fill_notsrc
),
580 ROP2(cirrus_fill_notsrc_or_dst
),
581 ROP2(cirrus_fill_notsrc_and_notdst
),
584 static inline void cirrus_bitblt_fgcol(CirrusVGAState
*s
)
587 switch (s
->cirrus_blt_pixelwidth
) {
589 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
;
592 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8);
593 s
->cirrus_blt_fgcol
= le16_to_cpu(color
);
596 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
|
597 (s
->gr
[0x11] << 8) | (s
->gr
[0x13] << 16);
601 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8) |
602 (s
->gr
[0x13] << 16) | (s
->gr
[0x15] << 24);
603 s
->cirrus_blt_fgcol
= le32_to_cpu(color
);
608 static inline void cirrus_bitblt_bgcol(CirrusVGAState
*s
)
611 switch (s
->cirrus_blt_pixelwidth
) {
613 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
;
616 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8);
617 s
->cirrus_blt_bgcol
= le16_to_cpu(color
);
620 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
|
621 (s
->gr
[0x10] << 8) | (s
->gr
[0x12] << 16);
625 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8) |
626 (s
->gr
[0x12] << 16) | (s
->gr
[0x14] << 24);
627 s
->cirrus_blt_bgcol
= le32_to_cpu(color
);
632 static void cirrus_invalidate_region(CirrusVGAState
* s
, int off_begin
,
633 int off_pitch
, int bytesperline
,
640 for (y
= 0; y
< lines
; y
++) {
642 off_cur_end
= off_cur
+ bytesperline
;
643 off_cur
&= TARGET_PAGE_MASK
;
644 while (off_cur
< off_cur_end
) {
645 cpu_physical_memory_set_dirty(s
->vram_offset
+ off_cur
);
646 off_cur
+= TARGET_PAGE_SIZE
;
648 off_begin
+= off_pitch
;
652 static int cirrus_bitblt_common_patterncopy(CirrusVGAState
* s
,
657 dst
= s
->vram_ptr
+ s
->cirrus_blt_dstaddr
;
658 (*s
->cirrus_rop
) (s
, dst
, src
,
659 s
->cirrus_blt_dstpitch
, 0,
660 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
661 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
662 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
663 s
->cirrus_blt_height
);
669 static int cirrus_bitblt_solidfill(CirrusVGAState
*s
, int blt_rop
)
671 cirrus_fill_t rop_func
;
673 rop_func
= cirrus_fill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
674 rop_func(s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
675 s
->cirrus_blt_dstpitch
,
676 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
677 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
678 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
679 s
->cirrus_blt_height
);
680 cirrus_bitblt_reset(s
);
684 /***************************************
686 * bitblt (video-to-video)
688 ***************************************/
690 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState
* s
)
692 return cirrus_bitblt_common_patterncopy(s
,
694 (s
->cirrus_blt_srcaddr
& ~7));
697 static void cirrus_do_copy(CirrusVGAState
*s
, int dst
, int src
, int w
, int h
)
705 depth
= s
->get_bpp((VGAState
*)s
) / 8;
706 s
->get_resolution((VGAState
*)s
, &width
, &height
);
709 sx
= (src
% (width
* depth
)) / depth
;
710 sy
= (src
/ (width
* depth
));
711 dx
= (dst
% (width
*depth
)) / depth
;
712 dy
= (dst
/ (width
* depth
));
714 /* normalize width */
717 /* if we're doing a backward copy, we have to adjust
718 our x/y to be the upper left corner (instead of the lower
720 if (s
->cirrus_blt_dstpitch
< 0) {
721 sx
-= (s
->cirrus_blt_width
/ depth
) - 1;
722 dx
-= (s
->cirrus_blt_width
/ depth
) - 1;
723 sy
-= s
->cirrus_blt_height
- 1;
724 dy
-= s
->cirrus_blt_height
- 1;
727 /* are we in the visible portion of memory? */
728 if (sx
>= 0 && sy
>= 0 && dx
>= 0 && dy
>= 0 &&
729 (sx
+ w
) <= width
&& (sy
+ h
) <= height
&&
730 (dx
+ w
) <= width
&& (dy
+ h
) <= height
) {
734 /* make to sure only copy if it's a plain copy ROP */
735 if (*s
->cirrus_rop
!= cirrus_bitblt_rop_fwd_src
&&
736 *s
->cirrus_rop
!= cirrus_bitblt_rop_bkwd_src
)
739 /* we have to flush all pending changes so that the copy
740 is generated at the appropriate moment in time */
744 (*s
->cirrus_rop
) (s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
745 s
->vram_ptr
+ s
->cirrus_blt_srcaddr
,
746 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
747 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
750 s
->ds
->dpy_copy(s
->ds
,
752 s
->cirrus_blt_width
/ depth
,
753 s
->cirrus_blt_height
);
755 /* we don't have to notify the display that this portion has
756 changed since dpy_copy implies this */
759 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
760 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
761 s
->cirrus_blt_height
);
764 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState
* s
)
766 if (s
->ds
->dpy_copy
) {
767 cirrus_do_copy(s
, s
->cirrus_blt_dstaddr
- s
->start_addr
,
768 s
->cirrus_blt_srcaddr
- s
->start_addr
,
769 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
771 (*s
->cirrus_rop
) (s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
772 s
->vram_ptr
+ s
->cirrus_blt_srcaddr
,
773 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
774 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
776 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
777 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
778 s
->cirrus_blt_height
);
784 /***************************************
786 * bitblt (cpu-to-video)
788 ***************************************/
790 static void cirrus_bitblt_cputovideo_next(CirrusVGAState
* s
)
795 if (s
->cirrus_srccounter
> 0) {
796 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
797 cirrus_bitblt_common_patterncopy(s
, s
->cirrus_bltbuf
);
799 s
->cirrus_srccounter
= 0;
800 cirrus_bitblt_reset(s
);
802 /* at least one scan line */
804 (*s
->cirrus_rop
)(s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
805 s
->cirrus_bltbuf
, 0, 0, s
->cirrus_blt_width
, 1);
806 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
, 0,
807 s
->cirrus_blt_width
, 1);
808 s
->cirrus_blt_dstaddr
+= s
->cirrus_blt_dstpitch
;
809 s
->cirrus_srccounter
-= s
->cirrus_blt_srcpitch
;
810 if (s
->cirrus_srccounter
<= 0)
812 /* more bytes than needed can be transfered because of
813 word alignment, so we keep them for the next line */
814 /* XXX: keep alignment to speed up transfer */
815 end_ptr
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
816 copy_count
= s
->cirrus_srcptr_end
- end_ptr
;
817 memmove(s
->cirrus_bltbuf
, end_ptr
, copy_count
);
818 s
->cirrus_srcptr
= s
->cirrus_bltbuf
+ copy_count
;
819 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
820 } while (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
);
825 /***************************************
829 ***************************************/
831 static void cirrus_bitblt_reset(CirrusVGAState
* s
)
834 ~(CIRRUS_BLT_START
| CIRRUS_BLT_BUSY
| CIRRUS_BLT_FIFOUSED
);
835 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
836 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
837 s
->cirrus_srccounter
= 0;
838 cirrus_update_memory_access(s
);
841 static int cirrus_bitblt_cputovideo(CirrusVGAState
* s
)
845 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_MEMSYSSRC
;
846 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
847 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
849 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
850 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
851 s
->cirrus_blt_srcpitch
= 8;
853 /* XXX: check for 24 bpp */
854 s
->cirrus_blt_srcpitch
= 8 * 8 * s
->cirrus_blt_pixelwidth
;
856 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
;
858 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
859 w
= s
->cirrus_blt_width
/ s
->cirrus_blt_pixelwidth
;
860 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_DWORDGRANULARITY
)
861 s
->cirrus_blt_srcpitch
= ((w
+ 31) >> 5);
863 s
->cirrus_blt_srcpitch
= ((w
+ 7) >> 3);
865 /* always align input size to 32 bits */
866 s
->cirrus_blt_srcpitch
= (s
->cirrus_blt_width
+ 3) & ~3;
868 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
* s
->cirrus_blt_height
;
870 s
->cirrus_srcptr
= s
->cirrus_bltbuf
;
871 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
872 cirrus_update_memory_access(s
);
876 static int cirrus_bitblt_videotocpu(CirrusVGAState
* s
)
880 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
885 static int cirrus_bitblt_videotovideo(CirrusVGAState
* s
)
889 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
890 ret
= cirrus_bitblt_videotovideo_patterncopy(s
);
892 ret
= cirrus_bitblt_videotovideo_copy(s
);
895 cirrus_bitblt_reset(s
);
899 static void cirrus_bitblt_start(CirrusVGAState
* s
)
903 s
->gr
[0x31] |= CIRRUS_BLT_BUSY
;
905 s
->cirrus_blt_width
= (s
->gr
[0x20] | (s
->gr
[0x21] << 8)) + 1;
906 s
->cirrus_blt_height
= (s
->gr
[0x22] | (s
->gr
[0x23] << 8)) + 1;
907 s
->cirrus_blt_dstpitch
= (s
->gr
[0x24] | (s
->gr
[0x25] << 8));
908 s
->cirrus_blt_srcpitch
= (s
->gr
[0x26] | (s
->gr
[0x27] << 8));
909 s
->cirrus_blt_dstaddr
=
910 (s
->gr
[0x28] | (s
->gr
[0x29] << 8) | (s
->gr
[0x2a] << 16));
911 s
->cirrus_blt_srcaddr
=
912 (s
->gr
[0x2c] | (s
->gr
[0x2d] << 8) | (s
->gr
[0x2e] << 16));
913 s
->cirrus_blt_mode
= s
->gr
[0x30];
914 s
->cirrus_blt_modeext
= s
->gr
[0x33];
915 blt_rop
= s
->gr
[0x32];
918 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
921 s
->cirrus_blt_modeext
,
923 s
->cirrus_blt_height
,
924 s
->cirrus_blt_dstpitch
,
925 s
->cirrus_blt_srcpitch
,
926 s
->cirrus_blt_dstaddr
,
927 s
->cirrus_blt_srcaddr
,
931 switch (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PIXELWIDTHMASK
) {
932 case CIRRUS_BLTMODE_PIXELWIDTH8
:
933 s
->cirrus_blt_pixelwidth
= 1;
935 case CIRRUS_BLTMODE_PIXELWIDTH16
:
936 s
->cirrus_blt_pixelwidth
= 2;
938 case CIRRUS_BLTMODE_PIXELWIDTH24
:
939 s
->cirrus_blt_pixelwidth
= 3;
941 case CIRRUS_BLTMODE_PIXELWIDTH32
:
942 s
->cirrus_blt_pixelwidth
= 4;
946 printf("cirrus: bitblt - pixel width is unknown\n");
950 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_PIXELWIDTHMASK
;
953 cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSSRC
|
954 CIRRUS_BLTMODE_MEMSYSDEST
))
955 == (CIRRUS_BLTMODE_MEMSYSSRC
| CIRRUS_BLTMODE_MEMSYSDEST
)) {
957 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
962 if ((s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_SOLIDFILL
) &&
963 (s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSDEST
|
964 CIRRUS_BLTMODE_TRANSPARENTCOMP
|
965 CIRRUS_BLTMODE_PATTERNCOPY
|
966 CIRRUS_BLTMODE_COLOREXPAND
)) ==
967 (CIRRUS_BLTMODE_PATTERNCOPY
| CIRRUS_BLTMODE_COLOREXPAND
)) {
968 cirrus_bitblt_fgcol(s
);
969 cirrus_bitblt_solidfill(s
, blt_rop
);
971 if ((s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_COLOREXPAND
|
972 CIRRUS_BLTMODE_PATTERNCOPY
)) ==
973 CIRRUS_BLTMODE_COLOREXPAND
) {
975 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
976 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
977 cirrus_bitblt_bgcol(s
);
979 cirrus_bitblt_fgcol(s
);
980 s
->cirrus_rop
= cirrus_colorexpand_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
982 cirrus_bitblt_fgcol(s
);
983 cirrus_bitblt_bgcol(s
);
984 s
->cirrus_rop
= cirrus_colorexpand
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
986 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
987 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
988 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
989 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
990 cirrus_bitblt_bgcol(s
);
992 cirrus_bitblt_fgcol(s
);
993 s
->cirrus_rop
= cirrus_colorexpand_pattern_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
995 cirrus_bitblt_fgcol(s
);
996 cirrus_bitblt_bgcol(s
);
997 s
->cirrus_rop
= cirrus_colorexpand_pattern
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1000 s
->cirrus_rop
= cirrus_patternfill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1003 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1004 if (s
->cirrus_blt_pixelwidth
> 2) {
1005 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1008 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1009 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1010 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1011 s
->cirrus_rop
= cirrus_bkwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1013 s
->cirrus_rop
= cirrus_fwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1016 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1017 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1018 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1019 s
->cirrus_rop
= cirrus_bkwd_rop
[rop_to_index
[blt_rop
]];
1021 s
->cirrus_rop
= cirrus_fwd_rop
[rop_to_index
[blt_rop
]];
1025 // setup bitblt engine.
1026 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSSRC
) {
1027 if (!cirrus_bitblt_cputovideo(s
))
1029 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSDEST
) {
1030 if (!cirrus_bitblt_videotocpu(s
))
1033 if (!cirrus_bitblt_videotovideo(s
))
1039 cirrus_bitblt_reset(s
);
1042 static void cirrus_write_bitblt(CirrusVGAState
* s
, unsigned reg_value
)
1046 old_value
= s
->gr
[0x31];
1047 s
->gr
[0x31] = reg_value
;
1049 if (((old_value
& CIRRUS_BLT_RESET
) != 0) &&
1050 ((reg_value
& CIRRUS_BLT_RESET
) == 0)) {
1051 cirrus_bitblt_reset(s
);
1052 } else if (((old_value
& CIRRUS_BLT_START
) == 0) &&
1053 ((reg_value
& CIRRUS_BLT_START
) != 0)) {
1054 cirrus_bitblt_start(s
);
1059 /***************************************
1063 ***************************************/
1065 static void cirrus_get_offsets(VGAState
*s1
,
1066 uint32_t *pline_offset
,
1067 uint32_t *pstart_addr
,
1068 uint32_t *pline_compare
)
1070 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1071 uint32_t start_addr
, line_offset
, line_compare
;
1073 line_offset
= s
->cr
[0x13]
1074 | ((s
->cr
[0x1b] & 0x10) << 4);
1076 *pline_offset
= line_offset
;
1078 start_addr
= (s
->cr
[0x0c] << 8)
1080 | ((s
->cr
[0x1b] & 0x01) << 16)
1081 | ((s
->cr
[0x1b] & 0x0c) << 15)
1082 | ((s
->cr
[0x1d] & 0x80) << 12);
1083 *pstart_addr
= start_addr
;
1085 line_compare
= s
->cr
[0x18] |
1086 ((s
->cr
[0x07] & 0x10) << 4) |
1087 ((s
->cr
[0x09] & 0x40) << 3);
1088 *pline_compare
= line_compare
;
1091 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState
* s
)
1095 switch (s
->cirrus_hidden_dac_data
& 0xf) {
1098 break; /* Sierra HiColor */
1101 break; /* XGA HiColor */
1104 printf("cirrus: invalid DAC value %x in 16bpp\n",
1105 (s
->cirrus_hidden_dac_data
& 0xf));
1113 static int cirrus_get_bpp(VGAState
*s1
)
1115 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1118 if ((s
->sr
[0x07] & 0x01) != 0) {
1120 switch (s
->sr
[0x07] & CIRRUS_SR7_BPP_MASK
) {
1121 case CIRRUS_SR7_BPP_8
:
1124 case CIRRUS_SR7_BPP_16_DOUBLEVCLK
:
1125 ret
= cirrus_get_bpp16_depth(s
);
1127 case CIRRUS_SR7_BPP_24
:
1130 case CIRRUS_SR7_BPP_16
:
1131 ret
= cirrus_get_bpp16_depth(s
);
1133 case CIRRUS_SR7_BPP_32
:
1138 printf("cirrus: unknown bpp - sr7=%x\n", s
->sr
[0x7]);
1151 static void cirrus_get_resolution(VGAState
*s
, int *pwidth
, int *pheight
)
1155 width
= (s
->cr
[0x01] + 1) * 8;
1156 height
= s
->cr
[0x12] |
1157 ((s
->cr
[0x07] & 0x02) << 7) |
1158 ((s
->cr
[0x07] & 0x40) << 3);
1159 height
= (height
+ 1);
1160 /* interlace support */
1161 if (s
->cr
[0x1a] & 0x01)
1162 height
= height
* 2;
1167 /***************************************
1171 ***************************************/
1173 static void cirrus_update_bank_ptr(CirrusVGAState
* s
, unsigned bank_index
)
1178 if ((s
->gr
[0x0b] & 0x01) != 0) /* dual bank */
1179 offset
= s
->gr
[0x09 + bank_index
];
1180 else /* single bank */
1181 offset
= s
->gr
[0x09];
1183 if ((s
->gr
[0x0b] & 0x20) != 0)
1188 if (s
->real_vram_size
<= offset
)
1191 limit
= s
->real_vram_size
- offset
;
1193 if (((s
->gr
[0x0b] & 0x01) == 0) && (bank_index
!= 0)) {
1194 if (limit
> 0x8000) {
1203 s
->cirrus_bank_base
[bank_index
] = offset
;
1204 s
->cirrus_bank_limit
[bank_index
] = limit
;
1206 s
->cirrus_bank_base
[bank_index
] = 0;
1207 s
->cirrus_bank_limit
[bank_index
] = 0;
1211 /***************************************
1213 * I/O access between 0x3c4-0x3c5
1215 ***************************************/
1218 cirrus_hook_read_sr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1220 switch (reg_index
) {
1221 case 0x00: // Standard VGA
1222 case 0x01: // Standard VGA
1223 case 0x02: // Standard VGA
1224 case 0x03: // Standard VGA
1225 case 0x04: // Standard VGA
1226 return CIRRUS_HOOK_NOT_HANDLED
;
1227 case 0x06: // Unlock Cirrus extensions
1228 *reg_value
= s
->sr
[reg_index
];
1233 case 0x70: // Graphics Cursor X
1237 case 0xf0: // Graphics Cursor X
1238 *reg_value
= s
->sr
[0x10];
1243 case 0x71: // Graphics Cursor Y
1247 case 0xf1: // Graphics Cursor Y
1248 *reg_value
= s
->sr
[0x11];
1251 case 0x07: // Extended Sequencer Mode
1252 case 0x08: // EEPROM Control
1253 case 0x09: // Scratch Register 0
1254 case 0x0a: // Scratch Register 1
1255 case 0x0b: // VCLK 0
1256 case 0x0c: // VCLK 1
1257 case 0x0d: // VCLK 2
1258 case 0x0e: // VCLK 3
1259 case 0x0f: // DRAM Control
1260 case 0x12: // Graphics Cursor Attribute
1261 case 0x13: // Graphics Cursor Pattern Address
1262 case 0x14: // Scratch Register 2
1263 case 0x15: // Scratch Register 3
1264 case 0x16: // Performance Tuning Register
1265 case 0x17: // Configuration Readback and Extended Control
1266 case 0x18: // Signature Generator Control
1267 case 0x19: // Signal Generator Result
1268 case 0x1a: // Signal Generator Result
1269 case 0x1b: // VCLK 0 Denominator & Post
1270 case 0x1c: // VCLK 1 Denominator & Post
1271 case 0x1d: // VCLK 2 Denominator & Post
1272 case 0x1e: // VCLK 3 Denominator & Post
1273 case 0x1f: // BIOS Write Enable and MCLK select
1275 printf("cirrus: handled inport sr_index %02x\n", reg_index
);
1277 *reg_value
= s
->sr
[reg_index
];
1281 printf("cirrus: inport sr_index %02x\n", reg_index
);
1287 return CIRRUS_HOOK_HANDLED
;
1291 cirrus_hook_write_sr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1293 switch (reg_index
) {
1294 case 0x00: // Standard VGA
1295 case 0x01: // Standard VGA
1296 case 0x02: // Standard VGA
1297 case 0x03: // Standard VGA
1298 case 0x04: // Standard VGA
1299 return CIRRUS_HOOK_NOT_HANDLED
;
1300 case 0x06: // Unlock Cirrus extensions
1302 if (reg_value
== 0x12) {
1303 s
->sr
[reg_index
] = 0x12;
1305 s
->sr
[reg_index
] = 0x0f;
1311 case 0x70: // Graphics Cursor X
1315 case 0xf0: // Graphics Cursor X
1316 s
->sr
[0x10] = reg_value
;
1317 s
->hw_cursor_x
= (reg_value
<< 3) | (reg_index
>> 5);
1322 case 0x71: // Graphics Cursor Y
1326 case 0xf1: // Graphics Cursor Y
1327 s
->sr
[0x11] = reg_value
;
1328 s
->hw_cursor_y
= (reg_value
<< 3) | (reg_index
>> 5);
1330 case 0x07: // Extended Sequencer Mode
1331 case 0x08: // EEPROM Control
1332 case 0x09: // Scratch Register 0
1333 case 0x0a: // Scratch Register 1
1334 case 0x0b: // VCLK 0
1335 case 0x0c: // VCLK 1
1336 case 0x0d: // VCLK 2
1337 case 0x0e: // VCLK 3
1338 case 0x0f: // DRAM Control
1339 case 0x12: // Graphics Cursor Attribute
1340 case 0x13: // Graphics Cursor Pattern Address
1341 case 0x14: // Scratch Register 2
1342 case 0x15: // Scratch Register 3
1343 case 0x16: // Performance Tuning Register
1344 case 0x18: // Signature Generator Control
1345 case 0x19: // Signature Generator Result
1346 case 0x1a: // Signature Generator Result
1347 case 0x1b: // VCLK 0 Denominator & Post
1348 case 0x1c: // VCLK 1 Denominator & Post
1349 case 0x1d: // VCLK 2 Denominator & Post
1350 case 0x1e: // VCLK 3 Denominator & Post
1351 case 0x1f: // BIOS Write Enable and MCLK select
1352 s
->sr
[reg_index
] = reg_value
;
1354 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1355 reg_index
, reg_value
);
1358 case 0x17: // Configuration Readback and Extended Control
1359 s
->sr
[reg_index
] = (s
->sr
[reg_index
] & 0x38) | (reg_value
& 0xc7);
1360 cirrus_update_memory_access(s
);
1364 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index
,
1370 return CIRRUS_HOOK_HANDLED
;
1373 /***************************************
1375 * I/O access at 0x3c6
1377 ***************************************/
1379 static void cirrus_read_hidden_dac(CirrusVGAState
* s
, int *reg_value
)
1382 if (++s
->cirrus_hidden_dac_lockindex
== 5) {
1383 *reg_value
= s
->cirrus_hidden_dac_data
;
1384 s
->cirrus_hidden_dac_lockindex
= 0;
1388 static void cirrus_write_hidden_dac(CirrusVGAState
* s
, int reg_value
)
1390 if (s
->cirrus_hidden_dac_lockindex
== 4) {
1391 s
->cirrus_hidden_dac_data
= reg_value
;
1392 #if defined(DEBUG_CIRRUS)
1393 printf("cirrus: outport hidden DAC, value %02x\n", reg_value
);
1396 s
->cirrus_hidden_dac_lockindex
= 0;
1399 /***************************************
1401 * I/O access at 0x3c9
1403 ***************************************/
1405 static int cirrus_hook_read_palette(CirrusVGAState
* s
, int *reg_value
)
1407 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1408 return CIRRUS_HOOK_NOT_HANDLED
;
1410 s
->cirrus_hidden_palette
[(s
->dac_read_index
& 0x0f) * 3 +
1412 if (++s
->dac_sub_index
== 3) {
1413 s
->dac_sub_index
= 0;
1414 s
->dac_read_index
++;
1416 return CIRRUS_HOOK_HANDLED
;
1419 static int cirrus_hook_write_palette(CirrusVGAState
* s
, int reg_value
)
1421 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1422 return CIRRUS_HOOK_NOT_HANDLED
;
1423 s
->dac_cache
[s
->dac_sub_index
] = reg_value
;
1424 if (++s
->dac_sub_index
== 3) {
1425 memcpy(&s
->cirrus_hidden_palette
[(s
->dac_write_index
& 0x0f) * 3],
1427 /* XXX update cursor */
1428 s
->dac_sub_index
= 0;
1429 s
->dac_write_index
++;
1431 return CIRRUS_HOOK_HANDLED
;
1434 /***************************************
1436 * I/O access between 0x3ce-0x3cf
1438 ***************************************/
1441 cirrus_hook_read_gr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1443 switch (reg_index
) {
1444 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1445 *reg_value
= s
->cirrus_shadow_gr0
;
1446 return CIRRUS_HOOK_HANDLED
;
1447 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1448 *reg_value
= s
->cirrus_shadow_gr1
;
1449 return CIRRUS_HOOK_HANDLED
;
1450 case 0x02: // Standard VGA
1451 case 0x03: // Standard VGA
1452 case 0x04: // Standard VGA
1453 case 0x06: // Standard VGA
1454 case 0x07: // Standard VGA
1455 case 0x08: // Standard VGA
1456 return CIRRUS_HOOK_NOT_HANDLED
;
1457 case 0x05: // Standard VGA, Cirrus extended mode
1462 if (reg_index
< 0x3a) {
1463 *reg_value
= s
->gr
[reg_index
];
1466 printf("cirrus: inport gr_index %02x\n", reg_index
);
1471 return CIRRUS_HOOK_HANDLED
;
1475 cirrus_hook_write_gr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1477 #if defined(DEBUG_BITBLT) && 0
1478 printf("gr%02x: %02x\n", reg_index
, reg_value
);
1480 switch (reg_index
) {
1481 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1482 s
->cirrus_shadow_gr0
= reg_value
;
1483 return CIRRUS_HOOK_NOT_HANDLED
;
1484 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1485 s
->cirrus_shadow_gr1
= reg_value
;
1486 return CIRRUS_HOOK_NOT_HANDLED
;
1487 case 0x02: // Standard VGA
1488 case 0x03: // Standard VGA
1489 case 0x04: // Standard VGA
1490 case 0x06: // Standard VGA
1491 case 0x07: // Standard VGA
1492 case 0x08: // Standard VGA
1493 return CIRRUS_HOOK_NOT_HANDLED
;
1494 case 0x05: // Standard VGA, Cirrus extended mode
1495 s
->gr
[reg_index
] = reg_value
& 0x7f;
1496 cirrus_update_memory_access(s
);
1498 case 0x09: // bank offset #0
1499 case 0x0A: // bank offset #1
1500 s
->gr
[reg_index
] = reg_value
;
1501 cirrus_update_bank_ptr(s
, 0);
1502 cirrus_update_bank_ptr(s
, 1);
1505 s
->gr
[reg_index
] = reg_value
;
1506 cirrus_update_bank_ptr(s
, 0);
1507 cirrus_update_bank_ptr(s
, 1);
1508 cirrus_update_memory_access(s
);
1510 case 0x10: // BGCOLOR 0x0000ff00
1511 case 0x11: // FGCOLOR 0x0000ff00
1512 case 0x12: // BGCOLOR 0x00ff0000
1513 case 0x13: // FGCOLOR 0x00ff0000
1514 case 0x14: // BGCOLOR 0xff000000
1515 case 0x15: // FGCOLOR 0xff000000
1516 case 0x20: // BLT WIDTH 0x0000ff
1517 case 0x22: // BLT HEIGHT 0x0000ff
1518 case 0x24: // BLT DEST PITCH 0x0000ff
1519 case 0x26: // BLT SRC PITCH 0x0000ff
1520 case 0x28: // BLT DEST ADDR 0x0000ff
1521 case 0x29: // BLT DEST ADDR 0x00ff00
1522 case 0x2c: // BLT SRC ADDR 0x0000ff
1523 case 0x2d: // BLT SRC ADDR 0x00ff00
1524 case 0x2f: // BLT WRITEMASK
1525 case 0x30: // BLT MODE
1526 case 0x32: // RASTER OP
1527 case 0x33: // BLT MODEEXT
1528 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1529 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1530 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1531 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1532 s
->gr
[reg_index
] = reg_value
;
1534 case 0x21: // BLT WIDTH 0x001f00
1535 case 0x23: // BLT HEIGHT 0x001f00
1536 case 0x25: // BLT DEST PITCH 0x001f00
1537 case 0x27: // BLT SRC PITCH 0x001f00
1538 s
->gr
[reg_index
] = reg_value
& 0x1f;
1540 case 0x2a: // BLT DEST ADDR 0x3f0000
1541 s
->gr
[reg_index
] = reg_value
& 0x3f;
1542 /* if auto start mode, starts bit blt now */
1543 if (s
->gr
[0x31] & CIRRUS_BLT_AUTOSTART
) {
1544 cirrus_bitblt_start(s
);
1547 case 0x2e: // BLT SRC ADDR 0x3f0000
1548 s
->gr
[reg_index
] = reg_value
& 0x3f;
1550 case 0x31: // BLT STATUS/START
1551 cirrus_write_bitblt(s
, reg_value
);
1555 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index
,
1561 return CIRRUS_HOOK_HANDLED
;
1564 /***************************************
1566 * I/O access between 0x3d4-0x3d5
1568 ***************************************/
1571 cirrus_hook_read_cr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1573 switch (reg_index
) {
1574 case 0x00: // Standard VGA
1575 case 0x01: // Standard VGA
1576 case 0x02: // Standard VGA
1577 case 0x03: // Standard VGA
1578 case 0x04: // Standard VGA
1579 case 0x05: // Standard VGA
1580 case 0x06: // Standard VGA
1581 case 0x07: // Standard VGA
1582 case 0x08: // Standard VGA
1583 case 0x09: // Standard VGA
1584 case 0x0a: // Standard VGA
1585 case 0x0b: // Standard VGA
1586 case 0x0c: // Standard VGA
1587 case 0x0d: // Standard VGA
1588 case 0x0e: // Standard VGA
1589 case 0x0f: // Standard VGA
1590 case 0x10: // Standard VGA
1591 case 0x11: // Standard VGA
1592 case 0x12: // Standard VGA
1593 case 0x13: // Standard VGA
1594 case 0x14: // Standard VGA
1595 case 0x15: // Standard VGA
1596 case 0x16: // Standard VGA
1597 case 0x17: // Standard VGA
1598 case 0x18: // Standard VGA
1599 return CIRRUS_HOOK_NOT_HANDLED
;
1600 case 0x19: // Interlace End
1601 case 0x1a: // Miscellaneous Control
1602 case 0x1b: // Extended Display Control
1603 case 0x1c: // Sync Adjust and Genlock
1604 case 0x1d: // Overlay Extended Control
1605 case 0x22: // Graphics Data Latches Readback (R)
1606 case 0x24: // Attribute Controller Toggle Readback (R)
1607 case 0x25: // Part Status
1608 case 0x27: // Part ID (R)
1609 *reg_value
= s
->cr
[reg_index
];
1611 case 0x26: // Attribute Controller Index Readback (R)
1612 *reg_value
= s
->ar_index
& 0x3f;
1616 printf("cirrus: inport cr_index %02x\n", reg_index
);
1622 return CIRRUS_HOOK_HANDLED
;
1626 cirrus_hook_write_cr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1628 switch (reg_index
) {
1629 case 0x00: // Standard VGA
1630 case 0x01: // Standard VGA
1631 case 0x02: // Standard VGA
1632 case 0x03: // Standard VGA
1633 case 0x04: // Standard VGA
1634 case 0x05: // Standard VGA
1635 case 0x06: // Standard VGA
1636 case 0x07: // Standard VGA
1637 case 0x08: // Standard VGA
1638 case 0x09: // Standard VGA
1639 case 0x0a: // Standard VGA
1640 case 0x0b: // Standard VGA
1641 case 0x0c: // Standard VGA
1642 case 0x0d: // Standard VGA
1643 case 0x0e: // Standard VGA
1644 case 0x0f: // Standard VGA
1645 case 0x10: // Standard VGA
1646 case 0x11: // Standard VGA
1647 case 0x12: // Standard VGA
1648 case 0x13: // Standard VGA
1649 case 0x14: // Standard VGA
1650 case 0x15: // Standard VGA
1651 case 0x16: // Standard VGA
1652 case 0x17: // Standard VGA
1653 case 0x18: // Standard VGA
1654 return CIRRUS_HOOK_NOT_HANDLED
;
1655 case 0x19: // Interlace End
1656 case 0x1a: // Miscellaneous Control
1657 case 0x1b: // Extended Display Control
1658 case 0x1c: // Sync Adjust and Genlock
1659 case 0x1d: // Overlay Extended Control
1660 s
->cr
[reg_index
] = reg_value
;
1662 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1663 reg_index
, reg_value
);
1666 case 0x22: // Graphics Data Latches Readback (R)
1667 case 0x24: // Attribute Controller Toggle Readback (R)
1668 case 0x26: // Attribute Controller Index Readback (R)
1669 case 0x27: // Part ID (R)
1671 case 0x25: // Part Status
1674 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index
,
1680 return CIRRUS_HOOK_HANDLED
;
1683 /***************************************
1685 * memory-mapped I/O (bitblt)
1687 ***************************************/
1689 static uint8_t cirrus_mmio_blt_read(CirrusVGAState
* s
, unsigned address
)
1694 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1695 cirrus_hook_read_gr(s
, 0x00, &value
);
1697 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1698 cirrus_hook_read_gr(s
, 0x10, &value
);
1700 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1701 cirrus_hook_read_gr(s
, 0x12, &value
);
1703 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1704 cirrus_hook_read_gr(s
, 0x14, &value
);
1706 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1707 cirrus_hook_read_gr(s
, 0x01, &value
);
1709 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1710 cirrus_hook_read_gr(s
, 0x11, &value
);
1712 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1713 cirrus_hook_read_gr(s
, 0x13, &value
);
1715 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1716 cirrus_hook_read_gr(s
, 0x15, &value
);
1718 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1719 cirrus_hook_read_gr(s
, 0x20, &value
);
1721 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1722 cirrus_hook_read_gr(s
, 0x21, &value
);
1724 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1725 cirrus_hook_read_gr(s
, 0x22, &value
);
1727 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1728 cirrus_hook_read_gr(s
, 0x23, &value
);
1730 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1731 cirrus_hook_read_gr(s
, 0x24, &value
);
1733 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1734 cirrus_hook_read_gr(s
, 0x25, &value
);
1736 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1737 cirrus_hook_read_gr(s
, 0x26, &value
);
1739 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1740 cirrus_hook_read_gr(s
, 0x27, &value
);
1742 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1743 cirrus_hook_read_gr(s
, 0x28, &value
);
1745 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1746 cirrus_hook_read_gr(s
, 0x29, &value
);
1748 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1749 cirrus_hook_read_gr(s
, 0x2a, &value
);
1751 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1752 cirrus_hook_read_gr(s
, 0x2c, &value
);
1754 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1755 cirrus_hook_read_gr(s
, 0x2d, &value
);
1757 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1758 cirrus_hook_read_gr(s
, 0x2e, &value
);
1760 case CIRRUS_MMIO_BLTWRITEMASK
:
1761 cirrus_hook_read_gr(s
, 0x2f, &value
);
1763 case CIRRUS_MMIO_BLTMODE
:
1764 cirrus_hook_read_gr(s
, 0x30, &value
);
1766 case CIRRUS_MMIO_BLTROP
:
1767 cirrus_hook_read_gr(s
, 0x32, &value
);
1769 case CIRRUS_MMIO_BLTMODEEXT
:
1770 cirrus_hook_read_gr(s
, 0x33, &value
);
1772 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1773 cirrus_hook_read_gr(s
, 0x34, &value
);
1775 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1776 cirrus_hook_read_gr(s
, 0x35, &value
);
1778 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1779 cirrus_hook_read_gr(s
, 0x38, &value
);
1781 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1782 cirrus_hook_read_gr(s
, 0x39, &value
);
1784 case CIRRUS_MMIO_BLTSTATUS
:
1785 cirrus_hook_read_gr(s
, 0x31, &value
);
1789 printf("cirrus: mmio read - address 0x%04x\n", address
);
1794 return (uint8_t) value
;
1797 static void cirrus_mmio_blt_write(CirrusVGAState
* s
, unsigned address
,
1801 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1802 cirrus_hook_write_gr(s
, 0x00, value
);
1804 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1805 cirrus_hook_write_gr(s
, 0x10, value
);
1807 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1808 cirrus_hook_write_gr(s
, 0x12, value
);
1810 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1811 cirrus_hook_write_gr(s
, 0x14, value
);
1813 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1814 cirrus_hook_write_gr(s
, 0x01, value
);
1816 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1817 cirrus_hook_write_gr(s
, 0x11, value
);
1819 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1820 cirrus_hook_write_gr(s
, 0x13, value
);
1822 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1823 cirrus_hook_write_gr(s
, 0x15, value
);
1825 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1826 cirrus_hook_write_gr(s
, 0x20, value
);
1828 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1829 cirrus_hook_write_gr(s
, 0x21, value
);
1831 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1832 cirrus_hook_write_gr(s
, 0x22, value
);
1834 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1835 cirrus_hook_write_gr(s
, 0x23, value
);
1837 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1838 cirrus_hook_write_gr(s
, 0x24, value
);
1840 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1841 cirrus_hook_write_gr(s
, 0x25, value
);
1843 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1844 cirrus_hook_write_gr(s
, 0x26, value
);
1846 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1847 cirrus_hook_write_gr(s
, 0x27, value
);
1849 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1850 cirrus_hook_write_gr(s
, 0x28, value
);
1852 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1853 cirrus_hook_write_gr(s
, 0x29, value
);
1855 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1856 cirrus_hook_write_gr(s
, 0x2a, value
);
1858 case (CIRRUS_MMIO_BLTDESTADDR
+ 3):
1861 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1862 cirrus_hook_write_gr(s
, 0x2c, value
);
1864 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1865 cirrus_hook_write_gr(s
, 0x2d, value
);
1867 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1868 cirrus_hook_write_gr(s
, 0x2e, value
);
1870 case CIRRUS_MMIO_BLTWRITEMASK
:
1871 cirrus_hook_write_gr(s
, 0x2f, value
);
1873 case CIRRUS_MMIO_BLTMODE
:
1874 cirrus_hook_write_gr(s
, 0x30, value
);
1876 case CIRRUS_MMIO_BLTROP
:
1877 cirrus_hook_write_gr(s
, 0x32, value
);
1879 case CIRRUS_MMIO_BLTMODEEXT
:
1880 cirrus_hook_write_gr(s
, 0x33, value
);
1882 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1883 cirrus_hook_write_gr(s
, 0x34, value
);
1885 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1886 cirrus_hook_write_gr(s
, 0x35, value
);
1888 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1889 cirrus_hook_write_gr(s
, 0x38, value
);
1891 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1892 cirrus_hook_write_gr(s
, 0x39, value
);
1894 case CIRRUS_MMIO_BLTSTATUS
:
1895 cirrus_hook_write_gr(s
, 0x31, value
);
1899 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1906 /***************************************
1910 * assume TARGET_PAGE_SIZE >= 16
1912 ***************************************/
1914 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState
* s
,
1920 unsigned val
= mem_value
;
1923 dst
= s
->vram_ptr
+ offset
;
1924 for (x
= 0; x
< 8; x
++) {
1926 *dst
= s
->cirrus_shadow_gr1
;
1927 } else if (mode
== 5) {
1928 *dst
= s
->cirrus_shadow_gr0
;
1933 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1934 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 7);
1937 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState
* s
,
1943 unsigned val
= mem_value
;
1946 dst
= s
->vram_ptr
+ offset
;
1947 for (x
= 0; x
< 8; x
++) {
1949 *dst
= s
->cirrus_shadow_gr1
;
1950 *(dst
+ 1) = s
->gr
[0x11];
1951 } else if (mode
== 5) {
1952 *dst
= s
->cirrus_shadow_gr0
;
1953 *(dst
+ 1) = s
->gr
[0x10];
1958 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1959 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 15);
1962 /***************************************
1964 * memory access between 0xa0000-0xbffff
1966 ***************************************/
1968 static uint32_t cirrus_vga_mem_readb(void *opaque
, target_phys_addr_t addr
)
1970 CirrusVGAState
*s
= opaque
;
1971 unsigned bank_index
;
1972 unsigned bank_offset
;
1975 if ((s
->sr
[0x07] & 0x01) == 0) {
1976 return vga_mem_readb(s
, addr
);
1981 if (addr
< 0x10000) {
1982 /* XXX handle bitblt */
1984 bank_index
= addr
>> 15;
1985 bank_offset
= addr
& 0x7fff;
1986 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
1987 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
1988 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
1990 } else if (s
->gr
[0x0B] & 0x02) {
1993 bank_offset
&= s
->cirrus_addr_mask
;
1994 val
= *(s
->vram_ptr
+ bank_offset
);
1997 } else if (addr
>= 0x18000 && addr
< 0x18100) {
1998 /* memory-mapped I/O */
2000 if ((s
->sr
[0x17] & 0x44) == 0x04) {
2001 val
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2006 printf("cirrus: mem_readb %06x\n", addr
);
2012 static uint32_t cirrus_vga_mem_readw(void *opaque
, target_phys_addr_t addr
)
2015 #ifdef TARGET_WORDS_BIGENDIAN
2016 v
= cirrus_vga_mem_readb(opaque
, addr
) << 8;
2017 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1);
2019 v
= cirrus_vga_mem_readb(opaque
, addr
);
2020 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
2025 static uint32_t cirrus_vga_mem_readl(void *opaque
, target_phys_addr_t addr
)
2028 #ifdef TARGET_WORDS_BIGENDIAN
2029 v
= cirrus_vga_mem_readb(opaque
, addr
) << 24;
2030 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 16;
2031 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 8;
2032 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3);
2034 v
= cirrus_vga_mem_readb(opaque
, addr
);
2035 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
2036 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 16;
2037 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3) << 24;
2042 static void cirrus_vga_mem_writeb(void *opaque
, target_phys_addr_t addr
,
2045 CirrusVGAState
*s
= opaque
;
2046 unsigned bank_index
;
2047 unsigned bank_offset
;
2050 if ((s
->sr
[0x07] & 0x01) == 0) {
2051 vga_mem_writeb(s
, addr
, mem_value
);
2057 if (addr
< 0x10000) {
2058 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2060 *s
->cirrus_srcptr
++ = (uint8_t) mem_value
;
2061 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2062 cirrus_bitblt_cputovideo_next(s
);
2066 bank_index
= addr
>> 15;
2067 bank_offset
= addr
& 0x7fff;
2068 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2069 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2070 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2072 } else if (s
->gr
[0x0B] & 0x02) {
2075 bank_offset
&= s
->cirrus_addr_mask
;
2076 mode
= s
->gr
[0x05] & 0x7;
2077 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2078 *(s
->vram_ptr
+ bank_offset
) = mem_value
;
2079 cpu_physical_memory_set_dirty(s
->vram_offset
+
2082 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2083 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
,
2087 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
,
2094 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2095 /* memory-mapped I/O */
2096 if ((s
->sr
[0x17] & 0x44) == 0x04) {
2097 cirrus_mmio_blt_write(s
, addr
& 0xff, mem_value
);
2101 printf("cirrus: mem_writeb %06x value %02x\n", addr
, mem_value
);
2106 static void cirrus_vga_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2108 #ifdef TARGET_WORDS_BIGENDIAN
2109 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2110 cirrus_vga_mem_writeb(opaque
, addr
+ 1, val
& 0xff);
2112 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2113 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2117 static void cirrus_vga_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2119 #ifdef TARGET_WORDS_BIGENDIAN
2120 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2121 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2122 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2123 cirrus_vga_mem_writeb(opaque
, addr
+ 3, val
& 0xff);
2125 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2126 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2127 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2128 cirrus_vga_mem_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2132 static CPUReadMemoryFunc
*cirrus_vga_mem_read
[3] = {
2133 cirrus_vga_mem_readb
,
2134 cirrus_vga_mem_readw
,
2135 cirrus_vga_mem_readl
,
2138 static CPUWriteMemoryFunc
*cirrus_vga_mem_write
[3] = {
2139 cirrus_vga_mem_writeb
,
2140 cirrus_vga_mem_writew
,
2141 cirrus_vga_mem_writel
,
2144 /***************************************
2148 ***************************************/
2150 static inline void invalidate_cursor1(CirrusVGAState
*s
)
2152 if (s
->last_hw_cursor_size
) {
2153 vga_invalidate_scanlines((VGAState
*)s
,
2154 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_start
,
2155 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_end
);
2159 static inline void cirrus_cursor_compute_yrange(CirrusVGAState
*s
)
2163 int y
, y_min
, y_max
;
2165 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2166 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2167 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2170 for(y
= 0; y
< 64; y
++) {
2171 content
= ((uint32_t *)src
)[0] |
2172 ((uint32_t *)src
)[1] |
2173 ((uint32_t *)src
)[2] |
2174 ((uint32_t *)src
)[3];
2184 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2187 for(y
= 0; y
< 32; y
++) {
2188 content
= ((uint32_t *)src
)[0] |
2189 ((uint32_t *)(src
+ 128))[0];
2199 if (y_min
> y_max
) {
2200 s
->last_hw_cursor_y_start
= 0;
2201 s
->last_hw_cursor_y_end
= 0;
2203 s
->last_hw_cursor_y_start
= y_min
;
2204 s
->last_hw_cursor_y_end
= y_max
+ 1;
2208 /* NOTE: we do not currently handle the cursor bitmap change, so we
2209 update the cursor only if it moves. */
2210 static void cirrus_cursor_invalidate(VGAState
*s1
)
2212 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2215 if (!s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
) {
2218 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
)
2223 /* invalidate last cursor and new cursor if any change */
2224 if (s
->last_hw_cursor_size
!= size
||
2225 s
->last_hw_cursor_x
!= s
->hw_cursor_x
||
2226 s
->last_hw_cursor_y
!= s
->hw_cursor_y
) {
2228 invalidate_cursor1(s
);
2230 s
->last_hw_cursor_size
= size
;
2231 s
->last_hw_cursor_x
= s
->hw_cursor_x
;
2232 s
->last_hw_cursor_y
= s
->hw_cursor_y
;
2233 /* compute the real cursor min and max y */
2234 cirrus_cursor_compute_yrange(s
);
2235 invalidate_cursor1(s
);
2239 static void cirrus_cursor_draw_line(VGAState
*s1
, uint8_t *d1
, int scr_y
)
2241 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2242 int w
, h
, bpp
, x1
, x2
, poffset
;
2243 unsigned int color0
, color1
;
2244 const uint8_t *palette
, *src
;
2247 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
))
2249 /* fast test to see if the cursor intersects with the scan line */
2250 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2255 if (scr_y
< s
->hw_cursor_y
||
2256 scr_y
>= (s
->hw_cursor_y
+ h
))
2259 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2260 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2261 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2262 src
+= (scr_y
- s
->hw_cursor_y
) * 16;
2264 content
= ((uint32_t *)src
)[0] |
2265 ((uint32_t *)src
)[1] |
2266 ((uint32_t *)src
)[2] |
2267 ((uint32_t *)src
)[3];
2269 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2270 src
+= (scr_y
- s
->hw_cursor_y
) * 4;
2272 content
= ((uint32_t *)src
)[0] |
2273 ((uint32_t *)(src
+ 128))[0];
2275 /* if nothing to draw, no need to continue */
2280 x1
= s
->hw_cursor_x
;
2281 if (x1
>= s
->last_scr_width
)
2283 x2
= s
->hw_cursor_x
+ w
;
2284 if (x2
> s
->last_scr_width
)
2285 x2
= s
->last_scr_width
;
2287 palette
= s
->cirrus_hidden_palette
;
2288 color0
= s
->rgb_to_pixel(c6_to_8(palette
[0x0 * 3]),
2289 c6_to_8(palette
[0x0 * 3 + 1]),
2290 c6_to_8(palette
[0x0 * 3 + 2]));
2291 color1
= s
->rgb_to_pixel(c6_to_8(palette
[0xf * 3]),
2292 c6_to_8(palette
[0xf * 3 + 1]),
2293 c6_to_8(palette
[0xf * 3 + 2]));
2294 bpp
= ((s
->ds
->depth
+ 7) >> 3);
2296 switch(s
->ds
->depth
) {
2300 vga_draw_cursor_line_8(d1
, src
, poffset
, w
, color0
, color1
, 0xff);
2303 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0x7fff);
2306 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0xffff);
2309 vga_draw_cursor_line_32(d1
, src
, poffset
, w
, color0
, color1
, 0xffffff);
2314 /***************************************
2318 ***************************************/
2320 static uint32_t cirrus_linear_readb(void *opaque
, target_phys_addr_t addr
)
2322 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2325 addr
&= s
->cirrus_addr_mask
;
2327 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2328 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2329 /* memory-mapped I/O */
2330 ret
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2332 /* XXX handle bitblt */
2336 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2338 } else if (s
->gr
[0x0B] & 0x02) {
2341 addr
&= s
->cirrus_addr_mask
;
2342 ret
= *(s
->vram_ptr
+ addr
);
2348 static uint32_t cirrus_linear_readw(void *opaque
, target_phys_addr_t addr
)
2351 #ifdef TARGET_WORDS_BIGENDIAN
2352 v
= cirrus_linear_readb(opaque
, addr
) << 8;
2353 v
|= cirrus_linear_readb(opaque
, addr
+ 1);
2355 v
= cirrus_linear_readb(opaque
, addr
);
2356 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2361 static uint32_t cirrus_linear_readl(void *opaque
, target_phys_addr_t addr
)
2364 #ifdef TARGET_WORDS_BIGENDIAN
2365 v
= cirrus_linear_readb(opaque
, addr
) << 24;
2366 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 16;
2367 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 8;
2368 v
|= cirrus_linear_readb(opaque
, addr
+ 3);
2370 v
= cirrus_linear_readb(opaque
, addr
);
2371 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2372 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 16;
2373 v
|= cirrus_linear_readb(opaque
, addr
+ 3) << 24;
2378 static void cirrus_linear_writeb(void *opaque
, target_phys_addr_t addr
,
2381 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2384 addr
&= s
->cirrus_addr_mask
;
2386 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2387 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2388 /* memory-mapped I/O */
2389 cirrus_mmio_blt_write(s
, addr
& 0xff, val
);
2390 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2392 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2393 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2394 cirrus_bitblt_cputovideo_next(s
);
2398 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2400 } else if (s
->gr
[0x0B] & 0x02) {
2403 addr
&= s
->cirrus_addr_mask
;
2405 mode
= s
->gr
[0x05] & 0x7;
2406 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2407 *(s
->vram_ptr
+ addr
) = (uint8_t) val
;
2408 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2410 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2411 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
, addr
, val
);
2413 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
, addr
, val
);
2419 static void cirrus_linear_writew(void *opaque
, target_phys_addr_t addr
,
2422 #ifdef TARGET_WORDS_BIGENDIAN
2423 cirrus_linear_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2424 cirrus_linear_writeb(opaque
, addr
+ 1, val
& 0xff);
2426 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2427 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2431 static void cirrus_linear_writel(void *opaque
, target_phys_addr_t addr
,
2434 #ifdef TARGET_WORDS_BIGENDIAN
2435 cirrus_linear_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2436 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2437 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2438 cirrus_linear_writeb(opaque
, addr
+ 3, val
& 0xff);
2440 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2441 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2442 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2443 cirrus_linear_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2448 static CPUReadMemoryFunc
*cirrus_linear_read
[3] = {
2449 cirrus_linear_readb
,
2450 cirrus_linear_readw
,
2451 cirrus_linear_readl
,
2454 static CPUWriteMemoryFunc
*cirrus_linear_write
[3] = {
2455 cirrus_linear_writeb
,
2456 cirrus_linear_writew
,
2457 cirrus_linear_writel
,
2460 static void cirrus_linear_mem_writeb(void *opaque
, target_phys_addr_t addr
,
2463 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2465 addr
&= s
->cirrus_addr_mask
;
2466 *(s
->vram_ptr
+ addr
) = val
;
2467 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2470 static void cirrus_linear_mem_writew(void *opaque
, target_phys_addr_t addr
,
2473 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2475 addr
&= s
->cirrus_addr_mask
;
2476 cpu_to_le16w((uint16_t *)(s
->vram_ptr
+ addr
), val
);
2477 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2480 static void cirrus_linear_mem_writel(void *opaque
, target_phys_addr_t addr
,
2483 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2485 addr
&= s
->cirrus_addr_mask
;
2486 cpu_to_le32w((uint32_t *)(s
->vram_ptr
+ addr
), val
);
2487 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2490 /***************************************
2492 * system to screen memory access
2494 ***************************************/
2497 static uint32_t cirrus_linear_bitblt_readb(void *opaque
, target_phys_addr_t addr
)
2501 /* XXX handle bitblt */
2506 static uint32_t cirrus_linear_bitblt_readw(void *opaque
, target_phys_addr_t addr
)
2509 #ifdef TARGET_WORDS_BIGENDIAN
2510 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 8;
2511 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1);
2513 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2514 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2519 static uint32_t cirrus_linear_bitblt_readl(void *opaque
, target_phys_addr_t addr
)
2522 #ifdef TARGET_WORDS_BIGENDIAN
2523 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 24;
2524 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 16;
2525 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 8;
2526 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3);
2528 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2529 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2530 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 16;
2531 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3) << 24;
2536 static void cirrus_linear_bitblt_writeb(void *opaque
, target_phys_addr_t addr
,
2539 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2541 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2543 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2544 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2545 cirrus_bitblt_cputovideo_next(s
);
2550 static void cirrus_linear_bitblt_writew(void *opaque
, target_phys_addr_t addr
,
2553 #ifdef TARGET_WORDS_BIGENDIAN
2554 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2555 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, val
& 0xff);
2557 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2558 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2562 static void cirrus_linear_bitblt_writel(void *opaque
, target_phys_addr_t addr
,
2565 #ifdef TARGET_WORDS_BIGENDIAN
2566 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2567 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2568 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2569 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, val
& 0xff);
2571 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2572 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2573 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2574 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2579 static CPUReadMemoryFunc
*cirrus_linear_bitblt_read
[3] = {
2580 cirrus_linear_bitblt_readb
,
2581 cirrus_linear_bitblt_readw
,
2582 cirrus_linear_bitblt_readl
,
2585 static CPUWriteMemoryFunc
*cirrus_linear_bitblt_write
[3] = {
2586 cirrus_linear_bitblt_writeb
,
2587 cirrus_linear_bitblt_writew
,
2588 cirrus_linear_bitblt_writel
,
2591 /* Compute the memory access functions */
2592 static void cirrus_update_memory_access(CirrusVGAState
*s
)
2596 if ((s
->sr
[0x17] & 0x44) == 0x44) {
2598 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2601 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2603 } else if (s
->gr
[0x0B] & 0x02) {
2607 mode
= s
->gr
[0x05] & 0x7;
2608 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2609 s
->cirrus_linear_write
[0] = cirrus_linear_mem_writeb
;
2610 s
->cirrus_linear_write
[1] = cirrus_linear_mem_writew
;
2611 s
->cirrus_linear_write
[2] = cirrus_linear_mem_writel
;
2614 s
->cirrus_linear_write
[0] = cirrus_linear_writeb
;
2615 s
->cirrus_linear_write
[1] = cirrus_linear_writew
;
2616 s
->cirrus_linear_write
[2] = cirrus_linear_writel
;
2624 static uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
2626 CirrusVGAState
*s
= opaque
;
2629 /* check port range access depending on color/monochrome mode */
2630 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2631 || (addr
>= 0x3d0 && addr
<= 0x3df
2632 && !(s
->msr
& MSR_COLOR_EMULATION
))) {
2637 if (s
->ar_flip_flop
== 0) {
2644 index
= s
->ar_index
& 0x1f;
2657 if (cirrus_hook_read_sr(s
, s
->sr_index
, &val
))
2659 val
= s
->sr
[s
->sr_index
];
2660 #ifdef DEBUG_VGA_REG
2661 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
2665 cirrus_read_hidden_dac(s
, &val
);
2671 val
= s
->dac_write_index
;
2672 s
->cirrus_hidden_dac_lockindex
= 0;
2675 if (cirrus_hook_read_palette(s
, &val
))
2677 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
2678 if (++s
->dac_sub_index
== 3) {
2679 s
->dac_sub_index
= 0;
2680 s
->dac_read_index
++;
2693 if (cirrus_hook_read_gr(s
, s
->gr_index
, &val
))
2695 val
= s
->gr
[s
->gr_index
];
2696 #ifdef DEBUG_VGA_REG
2697 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
2706 if (cirrus_hook_read_cr(s
, s
->cr_index
, &val
))
2708 val
= s
->cr
[s
->cr_index
];
2709 #ifdef DEBUG_VGA_REG
2710 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
2715 /* just toggle to fool polling */
2716 s
->st01
^= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
2718 s
->ar_flip_flop
= 0;
2725 #if defined(DEBUG_VGA)
2726 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
2731 static void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
2733 CirrusVGAState
*s
= opaque
;
2736 /* check port range access depending on color/monochrome mode */
2737 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2738 || (addr
>= 0x3d0 && addr
<= 0x3df
2739 && !(s
->msr
& MSR_COLOR_EMULATION
)))
2743 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
2748 if (s
->ar_flip_flop
== 0) {
2752 index
= s
->ar_index
& 0x1f;
2755 s
->ar
[index
] = val
& 0x3f;
2758 s
->ar
[index
] = val
& ~0x10;
2764 s
->ar
[index
] = val
& ~0xc0;
2767 s
->ar
[index
] = val
& ~0xf0;
2770 s
->ar
[index
] = val
& ~0xf0;
2776 s
->ar_flip_flop
^= 1;
2779 s
->msr
= val
& ~0x10;
2785 if (cirrus_hook_write_sr(s
, s
->sr_index
, val
))
2787 #ifdef DEBUG_VGA_REG
2788 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
2790 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
2793 cirrus_write_hidden_dac(s
, val
);
2796 s
->dac_read_index
= val
;
2797 s
->dac_sub_index
= 0;
2801 s
->dac_write_index
= val
;
2802 s
->dac_sub_index
= 0;
2806 if (cirrus_hook_write_palette(s
, val
))
2808 s
->dac_cache
[s
->dac_sub_index
] = val
;
2809 if (++s
->dac_sub_index
== 3) {
2810 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
2811 s
->dac_sub_index
= 0;
2812 s
->dac_write_index
++;
2819 if (cirrus_hook_write_gr(s
, s
->gr_index
, val
))
2821 #ifdef DEBUG_VGA_REG
2822 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
2824 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
2832 if (cirrus_hook_write_cr(s
, s
->cr_index
, val
))
2834 #ifdef DEBUG_VGA_REG
2835 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
2837 /* handle CR0-7 protection */
2838 if ((s
->cr
[0x11] & 0x80) && s
->cr_index
<= 7) {
2839 /* can always write bit 4 of CR7 */
2840 if (s
->cr_index
== 7)
2841 s
->cr
[7] = (s
->cr
[7] & ~0x10) | (val
& 0x10);
2844 switch (s
->cr_index
) {
2845 case 0x01: /* horizontal display end */
2850 case 0x12: /* vertical display end */
2851 s
->cr
[s
->cr_index
] = val
;
2855 s
->cr
[s
->cr_index
] = val
;
2861 s
->fcr
= val
& 0x10;
2866 /***************************************
2868 * memory-mapped I/O access
2870 ***************************************/
2872 static uint32_t cirrus_mmio_readb(void *opaque
, target_phys_addr_t addr
)
2874 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2876 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
2878 if (addr
>= 0x100) {
2879 return cirrus_mmio_blt_read(s
, addr
- 0x100);
2881 return vga_ioport_read(s
, addr
+ 0x3c0);
2885 static uint32_t cirrus_mmio_readw(void *opaque
, target_phys_addr_t addr
)
2888 #ifdef TARGET_WORDS_BIGENDIAN
2889 v
= cirrus_mmio_readb(opaque
, addr
) << 8;
2890 v
|= cirrus_mmio_readb(opaque
, addr
+ 1);
2892 v
= cirrus_mmio_readb(opaque
, addr
);
2893 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
2898 static uint32_t cirrus_mmio_readl(void *opaque
, target_phys_addr_t addr
)
2901 #ifdef TARGET_WORDS_BIGENDIAN
2902 v
= cirrus_mmio_readb(opaque
, addr
) << 24;
2903 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 16;
2904 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 8;
2905 v
|= cirrus_mmio_readb(opaque
, addr
+ 3);
2907 v
= cirrus_mmio_readb(opaque
, addr
);
2908 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
2909 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 16;
2910 v
|= cirrus_mmio_readb(opaque
, addr
+ 3) << 24;
2915 static void cirrus_mmio_writeb(void *opaque
, target_phys_addr_t addr
,
2918 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2920 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
2922 if (addr
>= 0x100) {
2923 cirrus_mmio_blt_write(s
, addr
- 0x100, val
);
2925 vga_ioport_write(s
, addr
+ 0x3c0, val
);
2929 static void cirrus_mmio_writew(void *opaque
, target_phys_addr_t addr
,
2932 #ifdef TARGET_WORDS_BIGENDIAN
2933 cirrus_mmio_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2934 cirrus_mmio_writeb(opaque
, addr
+ 1, val
& 0xff);
2936 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
2937 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2941 static void cirrus_mmio_writel(void *opaque
, target_phys_addr_t addr
,
2944 #ifdef TARGET_WORDS_BIGENDIAN
2945 cirrus_mmio_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2946 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2947 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2948 cirrus_mmio_writeb(opaque
, addr
+ 3, val
& 0xff);
2950 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
2951 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2952 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2953 cirrus_mmio_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2958 static CPUReadMemoryFunc
*cirrus_mmio_read
[3] = {
2964 static CPUWriteMemoryFunc
*cirrus_mmio_write
[3] = {
2970 /* load/save state */
2972 static void cirrus_vga_save(QEMUFile
*f
, void *opaque
)
2974 CirrusVGAState
*s
= opaque
;
2977 pci_device_save(s
->pci_dev
, f
);
2979 qemu_put_be32s(f
, &s
->latch
);
2980 qemu_put_8s(f
, &s
->sr_index
);
2981 qemu_put_buffer(f
, s
->sr
, 256);
2982 qemu_put_8s(f
, &s
->gr_index
);
2983 qemu_put_8s(f
, &s
->cirrus_shadow_gr0
);
2984 qemu_put_8s(f
, &s
->cirrus_shadow_gr1
);
2985 qemu_put_buffer(f
, s
->gr
+ 2, 254);
2986 qemu_put_8s(f
, &s
->ar_index
);
2987 qemu_put_buffer(f
, s
->ar
, 21);
2988 qemu_put_be32(f
, s
->ar_flip_flop
);
2989 qemu_put_8s(f
, &s
->cr_index
);
2990 qemu_put_buffer(f
, s
->cr
, 256);
2991 qemu_put_8s(f
, &s
->msr
);
2992 qemu_put_8s(f
, &s
->fcr
);
2993 qemu_put_8s(f
, &s
->st00
);
2994 qemu_put_8s(f
, &s
->st01
);
2996 qemu_put_8s(f
, &s
->dac_state
);
2997 qemu_put_8s(f
, &s
->dac_sub_index
);
2998 qemu_put_8s(f
, &s
->dac_read_index
);
2999 qemu_put_8s(f
, &s
->dac_write_index
);
3000 qemu_put_buffer(f
, s
->dac_cache
, 3);
3001 qemu_put_buffer(f
, s
->palette
, 768);
3003 qemu_put_be32(f
, s
->bank_offset
);
3005 qemu_put_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
3006 qemu_put_8s(f
, &s
->cirrus_hidden_dac_data
);
3008 qemu_put_be32s(f
, &s
->hw_cursor_x
);
3009 qemu_put_be32s(f
, &s
->hw_cursor_y
);
3010 /* XXX: we do not save the bitblt state - we assume we do not save
3011 the state when the blitter is active */
3014 static int cirrus_vga_load(QEMUFile
*f
, void *opaque
, int version_id
)
3016 CirrusVGAState
*s
= opaque
;
3022 if (s
->pci_dev
&& version_id
>= 2) {
3023 ret
= pci_device_load(s
->pci_dev
, f
);
3028 qemu_get_be32s(f
, &s
->latch
);
3029 qemu_get_8s(f
, &s
->sr_index
);
3030 qemu_get_buffer(f
, s
->sr
, 256);
3031 qemu_get_8s(f
, &s
->gr_index
);
3032 qemu_get_8s(f
, &s
->cirrus_shadow_gr0
);
3033 qemu_get_8s(f
, &s
->cirrus_shadow_gr1
);
3034 s
->gr
[0x00] = s
->cirrus_shadow_gr0
& 0x0f;
3035 s
->gr
[0x01] = s
->cirrus_shadow_gr1
& 0x0f;
3036 qemu_get_buffer(f
, s
->gr
+ 2, 254);
3037 qemu_get_8s(f
, &s
->ar_index
);
3038 qemu_get_buffer(f
, s
->ar
, 21);
3039 s
->ar_flip_flop
=qemu_get_be32(f
);
3040 qemu_get_8s(f
, &s
->cr_index
);
3041 qemu_get_buffer(f
, s
->cr
, 256);
3042 qemu_get_8s(f
, &s
->msr
);
3043 qemu_get_8s(f
, &s
->fcr
);
3044 qemu_get_8s(f
, &s
->st00
);
3045 qemu_get_8s(f
, &s
->st01
);
3047 qemu_get_8s(f
, &s
->dac_state
);
3048 qemu_get_8s(f
, &s
->dac_sub_index
);
3049 qemu_get_8s(f
, &s
->dac_read_index
);
3050 qemu_get_8s(f
, &s
->dac_write_index
);
3051 qemu_get_buffer(f
, s
->dac_cache
, 3);
3052 qemu_get_buffer(f
, s
->palette
, 768);
3054 s
->bank_offset
=qemu_get_be32(f
);
3056 qemu_get_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
3057 qemu_get_8s(f
, &s
->cirrus_hidden_dac_data
);
3059 qemu_get_be32s(f
, &s
->hw_cursor_x
);
3060 qemu_get_be32s(f
, &s
->hw_cursor_y
);
3063 s
->graphic_mode
= -1;
3064 cirrus_update_bank_ptr(s
, 0);
3065 cirrus_update_bank_ptr(s
, 1);
3069 /***************************************
3073 ***************************************/
3075 static void cirrus_init_common(CirrusVGAState
* s
, int device_id
, int is_pci
)
3077 int vga_io_memory
, i
;
3082 for(i
= 0;i
< 256; i
++)
3083 rop_to_index
[i
] = CIRRUS_ROP_NOP_INDEX
; /* nop rop */
3084 rop_to_index
[CIRRUS_ROP_0
] = 0;
3085 rop_to_index
[CIRRUS_ROP_SRC_AND_DST
] = 1;
3086 rop_to_index
[CIRRUS_ROP_NOP
] = 2;
3087 rop_to_index
[CIRRUS_ROP_SRC_AND_NOTDST
] = 3;
3088 rop_to_index
[CIRRUS_ROP_NOTDST
] = 4;
3089 rop_to_index
[CIRRUS_ROP_SRC
] = 5;
3090 rop_to_index
[CIRRUS_ROP_1
] = 6;
3091 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_DST
] = 7;
3092 rop_to_index
[CIRRUS_ROP_SRC_XOR_DST
] = 8;
3093 rop_to_index
[CIRRUS_ROP_SRC_OR_DST
] = 9;
3094 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_NOTDST
] = 10;
3095 rop_to_index
[CIRRUS_ROP_SRC_NOTXOR_DST
] = 11;
3096 rop_to_index
[CIRRUS_ROP_SRC_OR_NOTDST
] = 12;
3097 rop_to_index
[CIRRUS_ROP_NOTSRC
] = 13;
3098 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_DST
] = 14;
3099 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_NOTDST
] = 15;
3102 register_ioport_write(0x3c0, 16, 1, vga_ioport_write
, s
);
3104 register_ioport_write(0x3b4, 2, 1, vga_ioport_write
, s
);
3105 register_ioport_write(0x3d4, 2, 1, vga_ioport_write
, s
);
3106 register_ioport_write(0x3ba, 1, 1, vga_ioport_write
, s
);
3107 register_ioport_write(0x3da, 1, 1, vga_ioport_write
, s
);
3109 register_ioport_read(0x3c0, 16, 1, vga_ioport_read
, s
);
3111 register_ioport_read(0x3b4, 2, 1, vga_ioport_read
, s
);
3112 register_ioport_read(0x3d4, 2, 1, vga_ioport_read
, s
);
3113 register_ioport_read(0x3ba, 1, 1, vga_ioport_read
, s
);
3114 register_ioport_read(0x3da, 1, 1, vga_ioport_read
, s
);
3116 vga_io_memory
= cpu_register_io_memory(0, cirrus_vga_mem_read
,
3117 cirrus_vga_mem_write
, s
);
3118 cpu_register_physical_memory(isa_mem_base
+ 0x000a0000, 0x20000,
3122 if (device_id
== CIRRUS_ID_CLGD5446
) {
3123 /* 4MB 64 bit memory config, always PCI */
3124 s
->sr
[0x1F] = 0x2d; // MemClock
3125 s
->gr
[0x18] = 0x0f; // fastest memory configuration
3129 s
->sr
[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3130 s
->real_vram_size
= 4096 * 1024;
3134 s
->sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3135 s
->real_vram_size
= 2048 * 1024;
3138 s
->sr
[0x1F] = 0x22; // MemClock
3139 s
->sr
[0x0F] = CIRRUS_MEMSIZE_2M
;
3141 s
->sr
[0x17] = CIRRUS_BUSTYPE_PCI
;
3143 s
->sr
[0x17] = CIRRUS_BUSTYPE_ISA
;
3144 s
->real_vram_size
= 2048 * 1024;
3145 s
->sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3147 s
->cr
[0x27] = device_id
;
3149 /* Win2K seems to assume that the pattern buffer is at 0xff
3151 memset(s
->vram_ptr
, 0xff, s
->real_vram_size
);
3153 s
->cirrus_hidden_dac_lockindex
= 5;
3154 s
->cirrus_hidden_dac_data
= 0;
3156 /* I/O handler for LFB */
3157 s
->cirrus_linear_io_addr
=
3158 cpu_register_io_memory(0, cirrus_linear_read
, cirrus_linear_write
,
3160 s
->cirrus_linear_write
= cpu_get_io_memory_write(s
->cirrus_linear_io_addr
);
3162 /* I/O handler for LFB */
3163 s
->cirrus_linear_bitblt_io_addr
=
3164 cpu_register_io_memory(0, cirrus_linear_bitblt_read
, cirrus_linear_bitblt_write
,
3167 /* I/O handler for memory-mapped I/O */
3168 s
->cirrus_mmio_io_addr
=
3169 cpu_register_io_memory(0, cirrus_mmio_read
, cirrus_mmio_write
, s
);
3171 /* XXX: s->vram_size must be a power of two */
3172 s
->cirrus_addr_mask
= s
->real_vram_size
- 1;
3173 s
->linear_mmio_mask
= s
->real_vram_size
- 256;
3175 s
->get_bpp
= cirrus_get_bpp
;
3176 s
->get_offsets
= cirrus_get_offsets
;
3177 s
->get_resolution
= cirrus_get_resolution
;
3178 s
->cursor_invalidate
= cirrus_cursor_invalidate
;
3179 s
->cursor_draw_line
= cirrus_cursor_draw_line
;
3181 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save
, cirrus_vga_load
, s
);
3184 /***************************************
3188 ***************************************/
3190 void isa_cirrus_vga_init(DisplayState
*ds
, uint8_t *vga_ram_base
,
3191 unsigned long vga_ram_offset
, int vga_ram_size
)
3195 s
= qemu_mallocz(sizeof(CirrusVGAState
));
3197 vga_common_init((VGAState
*)s
,
3198 ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3199 cirrus_init_common(s
, CIRRUS_ID_CLGD5430
, 0);
3200 /* XXX ISA-LFB support */
3203 /***************************************
3207 ***************************************/
3209 static void cirrus_pci_lfb_map(PCIDevice
*d
, int region_num
,
3210 uint32_t addr
, uint32_t size
, int type
)
3212 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3214 /* XXX: add byte swapping apertures */
3215 cpu_register_physical_memory(addr
, s
->vram_size
,
3216 s
->cirrus_linear_io_addr
);
3217 cpu_register_physical_memory(addr
+ 0x1000000, 0x400000,
3218 s
->cirrus_linear_bitblt_io_addr
);
3221 static void cirrus_pci_mmio_map(PCIDevice
*d
, int region_num
,
3222 uint32_t addr
, uint32_t size
, int type
)
3224 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3226 cpu_register_physical_memory(addr
, CIRRUS_PNPMMIO_SIZE
,
3227 s
->cirrus_mmio_io_addr
);
3230 void pci_cirrus_vga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
3231 unsigned long vga_ram_offset
, int vga_ram_size
)
3233 PCICirrusVGAState
*d
;
3238 device_id
= CIRRUS_ID_CLGD5446
;
3240 /* setup PCI configuration registers */
3241 d
= (PCICirrusVGAState
*)pci_register_device(bus
, "Cirrus VGA",
3242 sizeof(PCICirrusVGAState
),
3244 pci_conf
= d
->dev
.config
;
3245 pci_conf
[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS
& 0xff);
3246 pci_conf
[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS
>> 8);
3247 pci_conf
[0x02] = (uint8_t) (device_id
& 0xff);
3248 pci_conf
[0x03] = (uint8_t) (device_id
>> 8);
3249 pci_conf
[0x04] = PCI_COMMAND_IOACCESS
| PCI_COMMAND_MEMACCESS
;
3250 pci_conf
[0x0a] = PCI_CLASS_SUB_VGA
;
3251 pci_conf
[0x0b] = PCI_CLASS_BASE_DISPLAY
;
3252 pci_conf
[0x0e] = PCI_CLASS_HEADERTYPE_00h
;
3256 vga_common_init((VGAState
*)s
,
3257 ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3258 cirrus_init_common(s
, device_id
, 1);
3260 graphic_console_init(s
->ds
, s
->update
, s
->invalidate
, s
->screen_dump
, s
);
3262 s
->pci_dev
= (PCIDevice
*)d
;
3264 /* setup memory space */
3266 /* memory #1 memory-mapped I/O */
3267 /* XXX: s->vram_size must be a power of two */
3268 pci_register_io_region((PCIDevice
*)d
, 0, 0x2000000,
3269 PCI_ADDRESS_SPACE_MEM_PREFETCH
, cirrus_pci_lfb_map
);
3270 if (device_id
== CIRRUS_ID_CLGD5446
) {
3271 pci_register_io_region((PCIDevice
*)d
, 1, CIRRUS_PNPMMIO_SIZE
,
3272 PCI_ADDRESS_SPACE_MEM
, cirrus_pci_mmio_map
);