hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 //#define DEBUG_IRQ_COUNT
  26 //#define DEBUG_IRQ
  27
  28 #ifdef DEBUG_IRQ
  29 #define DPRINTF(fmt, args...) \
  30 do { printf("IRQ: " fmt , ##args); } while (0)
  31 #else
  32 #define DPRINTF(fmt, args...)
  33 #endif
  34
  35 /*
  36  * Registers of interrupt controller in sun4m.
  37  *
  38  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  39  * produced as NCR89C105. See
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  41  *
  42  * There is a system master controller and one for each cpu.
  43  *
  44  */
  45
  46 #define MAX_CPUS 16
  47
  48 typedef struct SLAVIO_INTCTLState {
  49     uint32_t intreg_pending[MAX_CPUS];
  50     uint32_t intregm_pending;
  51     uint32_t intregm_disabled;
  52     uint32_t target_cpu;
  53 #ifdef DEBUG_IRQ_COUNT
  54     uint64_t irq_count[32];
  55 #endif
  56     CPUState *cpu_envs[MAX_CPUS];
  57     const uint32_t *intbit_to_level;
  58     uint32_t cputimer_bit;
  59 } SLAVIO_INTCTLState;
  60
  61 #define INTCTL_MAXADDR 0xf
  62 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  63 #define INTCTLM_MAXADDR 0x13
  64 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
  65 #define INTCTLM_MASK 0x1f
  66 static void slavio_check_interrupts(void *opaque);
  67
  68 // per-cpu interrupt controller
  69 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  70 {
  71     SLAVIO_INTCTLState *s = opaque;
  72     uint32_t saddr;
  73     int cpu;
  74
  75     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  76     saddr = (addr & INTCTL_MAXADDR) >> 2;
  77     switch (saddr) {
  78     case 0:
  79         return s->intreg_pending[cpu];
  80     default:
  81         break;
  82     }
  83     return 0;
  84 }
  85
  86 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  87 {
  88     SLAVIO_INTCTLState *s = opaque;
  89     uint32_t saddr;
  90     int cpu;
  91
  92     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  93     saddr = (addr & INTCTL_MAXADDR) >> 2;
  94     switch (saddr) {
  95     case 1: // clear pending softints
  96         if (val & 0x4000)
  97             val |= 80000000;
  98         val &= 0xfffe0000;
  99         s->intreg_pending[cpu] &= ~val;
 100         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 101         break;
 102     case 2: // set softint
 103         val &= 0xfffe0000;
 104         s->intreg_pending[cpu] |= val;
 105         slavio_check_interrupts(s);
 106         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 107         break;
 108     default:
 109         break;
 110     }
 111 }
 112
 113 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 114     slavio_intctl_mem_readl,
 115     slavio_intctl_mem_readl,
 116     slavio_intctl_mem_readl,
 117 };
 118
 119 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 120     slavio_intctl_mem_writel,
 121     slavio_intctl_mem_writel,
 122     slavio_intctl_mem_writel,
 123 };
 124
 125 // master system interrupt controller
 126 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 127 {
 128     SLAVIO_INTCTLState *s = opaque;
 129     uint32_t saddr;
 130
 131     saddr = (addr & INTCTLM_MAXADDR) >> 2;
 132     switch (saddr) {
 133     case 0:
 134         return s->intregm_pending & 0x7fffffff;
 135     case 1:
 136         return s->intregm_disabled;
 137     case 4:
 138         return s->target_cpu;
 139     default:
 140         break;
 141     }
 142     return 0;
 143 }
 144
 145 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 146 {
 147     SLAVIO_INTCTLState *s = opaque;
 148     uint32_t saddr;
 149
 150     saddr = (addr & INTCTLM_MASK) >> 2;
 151     switch (saddr) {
 152     case 2: // clear (enable)
 153         // Force clear unused bits
 154         val &= ~0x4fb2007f;
 155         s->intregm_disabled &= ~val;
 156         DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 157         slavio_check_interrupts(s);
 158         break;
 159     case 3: // set (disable, clear pending)
 160         // Force clear unused bits
 161         val &= ~0x4fb2007f;
 162         s->intregm_disabled |= val;
 163         s->intregm_pending &= ~val;
 164         DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 165         break;
 166     case 4:
 167         s->target_cpu = val & (MAX_CPUS - 1);
 168         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 169         break;
 170     default:
 171         break;
 172     }
 173 }
 174
 175 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 176     slavio_intctlm_mem_readl,
 177     slavio_intctlm_mem_readl,
 178     slavio_intctlm_mem_readl,
 179 };
 180
 181 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 182     slavio_intctlm_mem_writel,
 183     slavio_intctlm_mem_writel,
 184     slavio_intctlm_mem_writel,
 185 };
 186
 187 void slavio_pic_info(void *opaque)
 188 {
 189     SLAVIO_INTCTLState *s = opaque;
 190     int i;
 191
 192     for (i = 0; i < MAX_CPUS; i++) {
 193         term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
 194     }
 195     term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
 196 }
 197
 198 void slavio_irq_info(void *opaque)
 199 {
 200 #ifndef DEBUG_IRQ_COUNT
 201     term_printf("irq statistic code not compiled.\n");
 202 #else
 203     SLAVIO_INTCTLState *s = opaque;
 204     int i;
 205     int64_t count;
 206
 207     term_printf("IRQ statistics:\n");
 208     for (i = 0; i < 32; i++) {
 209         count = s->irq_count[i];
 210         if (count > 0)
 211             term_printf("%2d: %" PRId64 "\n", i, count);
 212     }
 213 #endif
 214 }
 215
 216 static void slavio_check_interrupts(void *opaque)
 217 {
 218     CPUState *env;
 219     SLAVIO_INTCTLState *s = opaque;
 220     uint32_t pending = s->intregm_pending;
 221     unsigned int i, j, max = 0;
 222
 223     pending &= ~s->intregm_disabled;
 224
 225     if (pending && !(s->intregm_disabled & 0x80000000)) {
 226         for (i = 0; i < 32; i++) {
 227             if (pending & (1 << i)) {
 228                 if (max < s->intbit_to_level[i])
 229                     max = s->intbit_to_level[i];
 230             }
 231         }
 232         env = s->cpu_envs[s->target_cpu];
 233         if (!env) {
 234             DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
 235         }
 236         else {
 237             if (env->halted)
 238                 env->halted = 0;
 239             if (env->interrupt_index == 0) {
 240                 DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
 241 #ifdef DEBUG_IRQ_COUNT
 242                 s->irq_count[max]++;
 243 #endif
 244                 env->interrupt_index = TT_EXTINT | max;
 245                 cpu_interrupt(env, CPU_INTERRUPT_HARD);
 246             }
 247             else
 248                 DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
 249         }
 250     }
 251     else
 252         DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
 253
 254     for (i = 0; i < MAX_CPUS; i++) {
 255         max = 0;
 256         env = s->cpu_envs[i];
 257         if (!env)
 258             continue;
 259         for (j = 17; j < 32; j++) {
 260             if (s->intreg_pending[i] & (1 << j)) {
 261                 if (max < j - 16)
 262                     max = j - 16;
 263             }
 264         }
 265         if (max > 0) {
 266             if (env->halted)
 267                 env->halted = 0;
 268             if (env->interrupt_index == 0) {
 269                 DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
 270 #ifdef DEBUG_IRQ_COUNT
 271                 s->irq_count[max]++;
 272 #endif
 273                 env->interrupt_index = TT_EXTINT | max;
 274                 cpu_interrupt(env, CPU_INTERRUPT_HARD);
 275             }
 276         }
 277     }
 278 }
 279
 280 /*
 281  * "irq" here is the bit number in the system interrupt register to
 282  * separate serial and keyboard interrupts sharing a level.
 283  */
 284 static void slavio_set_irq(void *opaque, int irq, int level)
 285 {
 286     SLAVIO_INTCTLState *s = opaque;
 287
 288     DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
 289     if (irq < 32) {
 290         uint32_t mask = 1 << irq;
 291         uint32_t pil = s->intbit_to_level[irq];
 292         if (pil > 0) {
 293             if (level) {
 294                 s->intregm_pending |= mask;
 295                 s->intreg_pending[s->target_cpu] |= 1 << pil;
 296                 slavio_check_interrupts(s);
 297             }
 298             else {
 299                 s->intregm_pending &= ~mask;
 300                 s->intreg_pending[s->target_cpu] &= ~(1 << pil);
 301             }
 302         }
 303     }
 304 }
 305
 306 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 307 {
 308     SLAVIO_INTCTLState *s = opaque;
 309
 310     DPRINTF("Set cpu %d local level %d\n", cpu, level);
 311     if (!s->cpu_envs[cpu])
 312         return;
 313
 314     if (level) {
 315         s->intreg_pending[cpu] |= s->cputimer_bit;
 316     } else {
 317         s->intreg_pending[cpu] &= ~s->cputimer_bit;
 318     }
 319
 320     slavio_check_interrupts(s);
 321 }
 322
 323 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 324 {
 325     SLAVIO_INTCTLState *s = opaque;
 326     int i;
 327
 328     for (i = 0; i < MAX_CPUS; i++) {
 329         qemu_put_be32s(f, &s->intreg_pending[i]);
 330     }
 331     qemu_put_be32s(f, &s->intregm_pending);
 332     qemu_put_be32s(f, &s->intregm_disabled);
 333     qemu_put_be32s(f, &s->target_cpu);
 334 }
 335
 336 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 337 {
 338     SLAVIO_INTCTLState *s = opaque;
 339     int i;
 340
 341     if (version_id != 1)
 342         return -EINVAL;
 343
 344     for (i = 0; i < MAX_CPUS; i++) {
 345         qemu_get_be32s(f, &s->intreg_pending[i]);
 346     }
 347     qemu_get_be32s(f, &s->intregm_pending);
 348     qemu_get_be32s(f, &s->intregm_disabled);
 349     qemu_get_be32s(f, &s->target_cpu);
 350     return 0;
 351 }
 352
 353 static void slavio_intctl_reset(void *opaque)
 354 {
 355     SLAVIO_INTCTLState *s = opaque;
 356     int i;
 357
 358     for (i = 0; i < MAX_CPUS; i++) {
 359         s->intreg_pending[i] = 0;
 360     }
 361     s->intregm_disabled = ~0xffb2007f;
 362     s->intregm_pending = 0;
 363     s->target_cpu = 0;
 364 }
 365
 366 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
 367 {
 368     SLAVIO_INTCTLState *s = opaque;
 369
 370     s->cpu_envs[cpu] = env;
 371 }
 372
 373 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
 374                          const uint32_t *intbit_to_level,
 375                          qemu_irq **irq, qemu_irq **cpu_irq,
 376                          unsigned int cputimer)
 377
 378 {
 379     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
 380     SLAVIO_INTCTLState *s;
 381
 382     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
 383     if (!s)
 384         return NULL;
 385
 386     s->intbit_to_level = intbit_to_level;
 387     for (i = 0; i < MAX_CPUS; i++) {
 388         slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
 389         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
 390                                      slavio_intctl_io_memory);
 391     }
 392
 393     slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
 394     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 395
 396     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
 397     qemu_register_reset(slavio_intctl_reset, s);
 398     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
 399
 400     *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
 401     s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
 402     slavio_intctl_reset(s);
 403     return s;
 404 }
 405