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Share input pins and internal interrupt controller between all PowerPC 40x.
[qemu/qemu_0_9_1_stable.git] / vl.h
blob0add259de8845e61fc83490f312e3c5ae651664b
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef likely
97 #if __GNUC__ < 3
98 #define __builtin_expect(x, n) (x)
99 #endif
100
101 #define likely(x) __builtin_expect(!!(x), 1)
102 #define unlikely(x) __builtin_expect(!!(x), 0)
103 #endif
104
105 #ifndef MIN
106 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
107 #endif
108 #ifndef MAX
109 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
110 #endif
111
112 #ifndef always_inline
113 #if (__GNUC__ < 3) || defined(__APPLE__)
114 #define always_inline inline
115 #else
116 #define always_inline __attribute__ (( always_inline )) inline
117 #endif
118 #endif
119
120 /* cutils.c */
121 void pstrcpy(char *buf, int buf_size, const char *str);
122 char *pstrcat(char *buf, int buf_size, const char *s);
123 int strstart(const char *str, const char *val, const char **ptr);
124 int stristart(const char *str, const char *val, const char **ptr);
125
126 /* vl.c */
127 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
128
129 void hw_error(const char *fmt, ...);
130
131 extern const char *bios_dir;
132
133 extern int vm_running;
134 extern const char *qemu_name;
135
136 typedef struct vm_change_state_entry VMChangeStateEntry;
137 typedef void VMChangeStateHandler(void *opaque, int running);
138 typedef void VMStopHandler(void *opaque, int reason);
139
140 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
141 void *opaque);
142 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
143
144 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
145 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
146
147 void vm_start(void);
148 void vm_stop(int reason);
149
150 typedef void QEMUResetHandler(void *opaque);
151
152 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
153 void qemu_system_reset_request(void);
154 void qemu_system_shutdown_request(void);
155 void qemu_system_powerdown_request(void);
156 #if !defined(TARGET_SPARC)
157 // Please implement a power failure function to signal the OS
158 #define qemu_system_powerdown() do{}while(0)
159 #else
160 void qemu_system_powerdown(void);
161 #endif
162
163 void main_loop_wait(int timeout);
164
165 extern int ram_size;
166 extern int bios_size;
167 extern int rtc_utc;
168 extern int cirrus_vga_enabled;
169 extern int vmsvga_enabled;
170 extern int graphic_width;
171 extern int graphic_height;
172 extern int graphic_depth;
173 extern const char *keyboard_layout;
174 extern int kqemu_allowed;
175 extern int win2k_install_hack;
176 extern int alt_grab;
177 extern int usb_enabled;
178 extern int smp_cpus;
179 extern int cursor_hide;
180 extern int graphic_rotate;
181 extern int no_quit;
182 extern int semihosting_enabled;
183 extern int autostart;
184 extern int old_param;
185 extern const char *bootp_filename;
186
187 #define MAX_OPTION_ROMS 16
188 extern const char *option_rom[MAX_OPTION_ROMS];
189 extern int nb_option_roms;
190
191 #ifdef TARGET_SPARC
192 #define MAX_PROM_ENVS 128
193 extern const char *prom_envs[MAX_PROM_ENVS];
194 extern unsigned int nb_prom_envs;
195 #endif
196
197 /* XXX: make it dynamic */
198 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
199 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
200 #define BIOS_SIZE ((512 + 32) * 1024)
201 #elif defined(TARGET_MIPS)
202 #define BIOS_SIZE (4 * 1024 * 1024)
203 #endif
204
205 /* keyboard/mouse support */
206
207 #define MOUSE_EVENT_LBUTTON 0x01
208 #define MOUSE_EVENT_RBUTTON 0x02
209 #define MOUSE_EVENT_MBUTTON 0x04
210
211 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
212 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
213
214 typedef struct QEMUPutMouseEntry {
215 QEMUPutMouseEvent *qemu_put_mouse_event;
216 void *qemu_put_mouse_event_opaque;
217 int qemu_put_mouse_event_absolute;
218 char *qemu_put_mouse_event_name;
219
220 /* used internally by qemu for handling mice */
221 struct QEMUPutMouseEntry *next;
222 } QEMUPutMouseEntry;
223
224 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
225 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
226 void *opaque, int absolute,
227 const char *name);
228 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
229
230 void kbd_put_keycode(int keycode);
231 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
232 int kbd_mouse_is_absolute(void);
233
234 void do_info_mice(void);
235 void do_mouse_set(int index);
236
237 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
238 constants) */
239 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
240 #define QEMU_KEY_BACKSPACE 0x007f
241 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
242 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
243 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
244 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
245 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
246 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
247 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
248 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
249 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
250
251 #define QEMU_KEY_CTRL_UP 0xe400
252 #define QEMU_KEY_CTRL_DOWN 0xe401
253 #define QEMU_KEY_CTRL_LEFT 0xe402
254 #define QEMU_KEY_CTRL_RIGHT 0xe403
255 #define QEMU_KEY_CTRL_HOME 0xe404
256 #define QEMU_KEY_CTRL_END 0xe405
257 #define QEMU_KEY_CTRL_PAGEUP 0xe406
258 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
259
260 void kbd_put_keysym(int keysym);
261
262 /* async I/O support */
263
264 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
265 typedef int IOCanRWHandler(void *opaque);
266 typedef void IOHandler(void *opaque);
267
268 int qemu_set_fd_handler2(int fd,
269 IOCanRWHandler *fd_read_poll,
270 IOHandler *fd_read,
271 IOHandler *fd_write,
272 void *opaque);
273 int qemu_set_fd_handler(int fd,
274 IOHandler *fd_read,
275 IOHandler *fd_write,
276 void *opaque);
277
278 /* Polling handling */
279
280 /* return TRUE if no sleep should be done afterwards */
281 typedef int PollingFunc(void *opaque);
282
283 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
284 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
285
286 #ifdef _WIN32
287 /* Wait objects handling */
288 typedef void WaitObjectFunc(void *opaque);
289
290 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
291 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
292 #endif
293
294 typedef struct QEMUBH QEMUBH;
295
296 /* character device */
297
298 #define CHR_EVENT_BREAK 0 /* serial break char */
299 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
300 #define CHR_EVENT_RESET 2 /* new connection established */
301
302
303 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
304 typedef struct {
305 int speed;
306 int parity;
307 int data_bits;
308 int stop_bits;
309 } QEMUSerialSetParams;
310
311 #define CHR_IOCTL_SERIAL_SET_BREAK 2
312
313 #define CHR_IOCTL_PP_READ_DATA 3
314 #define CHR_IOCTL_PP_WRITE_DATA 4
315 #define CHR_IOCTL_PP_READ_CONTROL 5
316 #define CHR_IOCTL_PP_WRITE_CONTROL 6
317 #define CHR_IOCTL_PP_READ_STATUS 7
318 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
319 #define CHR_IOCTL_PP_EPP_READ 9
320 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
321 #define CHR_IOCTL_PP_EPP_WRITE 11
322
323 typedef void IOEventHandler(void *opaque, int event);
324
325 typedef struct CharDriverState {
326 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
327 void (*chr_update_read_handler)(struct CharDriverState *s);
328 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
329 IOEventHandler *chr_event;
330 IOCanRWHandler *chr_can_read;
331 IOReadHandler *chr_read;
332 void *handler_opaque;
333 void (*chr_send_event)(struct CharDriverState *chr, int event);
334 void (*chr_close)(struct CharDriverState *chr);
335 void *opaque;
336 int focus;
337 QEMUBH *bh;
338 } CharDriverState;
339
340 CharDriverState *qemu_chr_open(const char *filename);
341 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
342 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
343 void qemu_chr_send_event(CharDriverState *s, int event);
344 void qemu_chr_add_handlers(CharDriverState *s,
345 IOCanRWHandler *fd_can_read,
346 IOReadHandler *fd_read,
347 IOEventHandler *fd_event,
348 void *opaque);
349 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
350 void qemu_chr_reset(CharDriverState *s);
351 int qemu_chr_can_read(CharDriverState *s);
352 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
353
354 /* consoles */
355
356 typedef struct DisplayState DisplayState;
357 typedef struct TextConsole TextConsole;
358
359 typedef void (*vga_hw_update_ptr)(void *);
360 typedef void (*vga_hw_invalidate_ptr)(void *);
361 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
362
363 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
364 vga_hw_invalidate_ptr invalidate,
365 vga_hw_screen_dump_ptr screen_dump,
366 void *opaque);
367 void vga_hw_update(void);
368 void vga_hw_invalidate(void);
369 void vga_hw_screen_dump(const char *filename);
370
371 int is_graphic_console(void);
372 CharDriverState *text_console_init(DisplayState *ds, const char *p);
373 void console_select(unsigned int index);
374
375 /* serial ports */
376
377 #define MAX_SERIAL_PORTS 4
378
379 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
380
381 /* parallel ports */
382
383 #define MAX_PARALLEL_PORTS 3
384
385 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
386
387 struct ParallelIOArg {
388 void *buffer;
389 int count;
390 };
391
392 /* VLANs support */
393
394 typedef struct VLANClientState VLANClientState;
395
396 struct VLANClientState {
397 IOReadHandler *fd_read;
398 /* Packets may still be sent if this returns zero. It's used to
399 rate-limit the slirp code. */
400 IOCanRWHandler *fd_can_read;
401 void *opaque;
402 struct VLANClientState *next;
403 struct VLANState *vlan;
404 char info_str[256];
405 };
406
407 typedef struct VLANState {
408 int id;
409 VLANClientState *first_client;
410 struct VLANState *next;
411 unsigned int nb_guest_devs, nb_host_devs;
412 } VLANState;
413
414 VLANState *qemu_find_vlan(int id);
415 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
416 IOReadHandler *fd_read,
417 IOCanRWHandler *fd_can_read,
418 void *opaque);
419 int qemu_can_send_packet(VLANClientState *vc);
420 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
421 void qemu_handler_true(void *opaque);
422
423 void do_info_network(void);
424
425 /* TAP win32 */
426 int tap_win32_init(VLANState *vlan, const char *ifname);
427
428 /* NIC info */
429
430 #define MAX_NICS 8
431
432 typedef struct NICInfo {
433 uint8_t macaddr[6];
434 const char *model;
435 VLANState *vlan;
436 } NICInfo;
437
438 extern int nb_nics;
439 extern NICInfo nd_table[MAX_NICS];
440
441 /* timers */
442
443 typedef struct QEMUClock QEMUClock;
444 typedef struct QEMUTimer QEMUTimer;
445 typedef void QEMUTimerCB(void *opaque);
446
447 /* The real time clock should be used only for stuff which does not
448 change the virtual machine state, as it is run even if the virtual
449 machine is stopped. The real time clock has a frequency of 1000
450 Hz. */
451 extern QEMUClock *rt_clock;
452
453 /* The virtual clock is only run during the emulation. It is stopped
454 when the virtual machine is stopped. Virtual timers use a high
455 precision clock, usually cpu cycles (use ticks_per_sec). */
456 extern QEMUClock *vm_clock;
457
458 int64_t qemu_get_clock(QEMUClock *clock);
459
460 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
461 void qemu_free_timer(QEMUTimer *ts);
462 void qemu_del_timer(QEMUTimer *ts);
463 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
464 int qemu_timer_pending(QEMUTimer *ts);
465
466 extern int64_t ticks_per_sec;
467
468 int64_t cpu_get_ticks(void);
469 void cpu_enable_ticks(void);
470 void cpu_disable_ticks(void);
471
472 /* VM Load/Save */
473
474 typedef struct QEMUFile QEMUFile;
475
476 QEMUFile *qemu_fopen(const char *filename, const char *mode);
477 void qemu_fflush(QEMUFile *f);
478 void qemu_fclose(QEMUFile *f);
479 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
480 void qemu_put_byte(QEMUFile *f, int v);
481 void qemu_put_be16(QEMUFile *f, unsigned int v);
482 void qemu_put_be32(QEMUFile *f, unsigned int v);
483 void qemu_put_be64(QEMUFile *f, uint64_t v);
484 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
485 int qemu_get_byte(QEMUFile *f);
486 unsigned int qemu_get_be16(QEMUFile *f);
487 unsigned int qemu_get_be32(QEMUFile *f);
488 uint64_t qemu_get_be64(QEMUFile *f);
489
490 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
491 {
492 qemu_put_be64(f, *pv);
493 }
494
495 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
496 {
497 qemu_put_be32(f, *pv);
498 }
499
500 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
501 {
502 qemu_put_be16(f, *pv);
503 }
504
505 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
506 {
507 qemu_put_byte(f, *pv);
508 }
509
510 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
511 {
512 *pv = qemu_get_be64(f);
513 }
514
515 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
516 {
517 *pv = qemu_get_be32(f);
518 }
519
520 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
521 {
522 *pv = qemu_get_be16(f);
523 }
524
525 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
526 {
527 *pv = qemu_get_byte(f);
528 }
529
530 #if TARGET_LONG_BITS == 64
531 #define qemu_put_betl qemu_put_be64
532 #define qemu_get_betl qemu_get_be64
533 #define qemu_put_betls qemu_put_be64s
534 #define qemu_get_betls qemu_get_be64s
535 #else
536 #define qemu_put_betl qemu_put_be32
537 #define qemu_get_betl qemu_get_be32
538 #define qemu_put_betls qemu_put_be32s
539 #define qemu_get_betls qemu_get_be32s
540 #endif
541
542 int64_t qemu_ftell(QEMUFile *f);
543 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
544
545 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
546 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
547
548 int register_savevm(const char *idstr,
549 int instance_id,
550 int version_id,
551 SaveStateHandler *save_state,
552 LoadStateHandler *load_state,
553 void *opaque);
554 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
555 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
556
557 void cpu_save(QEMUFile *f, void *opaque);
558 int cpu_load(QEMUFile *f, void *opaque, int version_id);
559
560 void do_savevm(const char *name);
561 void do_loadvm(const char *name);
562 void do_delvm(const char *name);
563 void do_info_snapshots(void);
564
565 /* bottom halves */
566 typedef void QEMUBHFunc(void *opaque);
567
568 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
569 void qemu_bh_schedule(QEMUBH *bh);
570 void qemu_bh_cancel(QEMUBH *bh);
571 void qemu_bh_delete(QEMUBH *bh);
572 int qemu_bh_poll(void);
573
574 /* block.c */
575 typedef struct BlockDriverState BlockDriverState;
576 typedef struct BlockDriver BlockDriver;
577
578 extern BlockDriver bdrv_raw;
579 extern BlockDriver bdrv_host_device;
580 extern BlockDriver bdrv_cow;
581 extern BlockDriver bdrv_qcow;
582 extern BlockDriver bdrv_vmdk;
583 extern BlockDriver bdrv_cloop;
584 extern BlockDriver bdrv_dmg;
585 extern BlockDriver bdrv_bochs;
586 extern BlockDriver bdrv_vpc;
587 extern BlockDriver bdrv_vvfat;
588 extern BlockDriver bdrv_qcow2;
589 extern BlockDriver bdrv_parallels;
590
591 typedef struct BlockDriverInfo {
592 /* in bytes, 0 if irrelevant */
593 int cluster_size;
594 /* offset at which the VM state can be saved (0 if not possible) */
595 int64_t vm_state_offset;
596 } BlockDriverInfo;
597
598 typedef struct QEMUSnapshotInfo {
599 char id_str[128]; /* unique snapshot id */
600 /* the following fields are informative. They are not needed for
601 the consistency of the snapshot */
602 char name[256]; /* user choosen name */
603 uint32_t vm_state_size; /* VM state info size */
604 uint32_t date_sec; /* UTC date of the snapshot */
605 uint32_t date_nsec;
606 uint64_t vm_clock_nsec; /* VM clock relative to boot */
607 } QEMUSnapshotInfo;
608
609 #define BDRV_O_RDONLY 0x0000
610 #define BDRV_O_RDWR 0x0002
611 #define BDRV_O_ACCESS 0x0003
612 #define BDRV_O_CREAT 0x0004 /* create an empty file */
613 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
614 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
615 use a disk image format on top of
616 it (default for
617 bdrv_file_open()) */
618
619 void bdrv_init(void);
620 BlockDriver *bdrv_find_format(const char *format_name);
621 int bdrv_create(BlockDriver *drv,
622 const char *filename, int64_t size_in_sectors,
623 const char *backing_file, int flags);
624 BlockDriverState *bdrv_new(const char *device_name);
625 void bdrv_delete(BlockDriverState *bs);
626 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
627 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
628 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
629 BlockDriver *drv);
630 void bdrv_close(BlockDriverState *bs);
631 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
632 uint8_t *buf, int nb_sectors);
633 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
634 const uint8_t *buf, int nb_sectors);
635 int bdrv_pread(BlockDriverState *bs, int64_t offset,
636 void *buf, int count);
637 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
638 const void *buf, int count);
639 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
640 int64_t bdrv_getlength(BlockDriverState *bs);
641 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
642 int bdrv_commit(BlockDriverState *bs);
643 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
644 /* async block I/O */
645 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
646 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
647
648 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
649 uint8_t *buf, int nb_sectors,
650 BlockDriverCompletionFunc *cb, void *opaque);
651 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
652 const uint8_t *buf, int nb_sectors,
653 BlockDriverCompletionFunc *cb, void *opaque);
654 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
655
656 void qemu_aio_init(void);
657 void qemu_aio_poll(void);
658 void qemu_aio_flush(void);
659 void qemu_aio_wait_start(void);
660 void qemu_aio_wait(void);
661 void qemu_aio_wait_end(void);
662
663 int qemu_key_check(BlockDriverState *bs, const char *name);
664
665 /* Ensure contents are flushed to disk. */
666 void bdrv_flush(BlockDriverState *bs);
667
668 #define BDRV_TYPE_HD 0
669 #define BDRV_TYPE_CDROM 1
670 #define BDRV_TYPE_FLOPPY 2
671 #define BIOS_ATA_TRANSLATION_AUTO 0
672 #define BIOS_ATA_TRANSLATION_NONE 1
673 #define BIOS_ATA_TRANSLATION_LBA 2
674 #define BIOS_ATA_TRANSLATION_LARGE 3
675 #define BIOS_ATA_TRANSLATION_RECHS 4
676
677 void bdrv_set_geometry_hint(BlockDriverState *bs,
678 int cyls, int heads, int secs);
679 void bdrv_set_type_hint(BlockDriverState *bs, int type);
680 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
681 void bdrv_get_geometry_hint(BlockDriverState *bs,
682 int *pcyls, int *pheads, int *psecs);
683 int bdrv_get_type_hint(BlockDriverState *bs);
684 int bdrv_get_translation_hint(BlockDriverState *bs);
685 int bdrv_is_removable(BlockDriverState *bs);
686 int bdrv_is_read_only(BlockDriverState *bs);
687 int bdrv_is_inserted(BlockDriverState *bs);
688 int bdrv_media_changed(BlockDriverState *bs);
689 int bdrv_is_locked(BlockDriverState *bs);
690 void bdrv_set_locked(BlockDriverState *bs, int locked);
691 void bdrv_eject(BlockDriverState *bs, int eject_flag);
692 void bdrv_set_change_cb(BlockDriverState *bs,
693 void (*change_cb)(void *opaque), void *opaque);
694 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
695 void bdrv_info(void);
696 BlockDriverState *bdrv_find(const char *name);
697 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
698 int bdrv_is_encrypted(BlockDriverState *bs);
699 int bdrv_set_key(BlockDriverState *bs, const char *key);
700 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
701 void *opaque);
702 const char *bdrv_get_device_name(BlockDriverState *bs);
703 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
704 const uint8_t *buf, int nb_sectors);
705 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
706
707 void bdrv_get_backing_filename(BlockDriverState *bs,
708 char *filename, int filename_size);
709 int bdrv_snapshot_create(BlockDriverState *bs,
710 QEMUSnapshotInfo *sn_info);
711 int bdrv_snapshot_goto(BlockDriverState *bs,
712 const char *snapshot_id);
713 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
714 int bdrv_snapshot_list(BlockDriverState *bs,
715 QEMUSnapshotInfo **psn_info);
716 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
717
718 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
719 int path_is_absolute(const char *path);
720 void path_combine(char *dest, int dest_size,
721 const char *base_path,
722 const char *filename);
723
724 #ifndef QEMU_TOOL
725
726 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
727 int boot_device,
728 DisplayState *ds, const char **fd_filename, int snapshot,
729 const char *kernel_filename, const char *kernel_cmdline,
730 const char *initrd_filename, const char *cpu_model);
731
732 typedef struct QEMUMachine {
733 const char *name;
734 const char *desc;
735 QEMUMachineInitFunc *init;
736 struct QEMUMachine *next;
737 } QEMUMachine;
738
739 int qemu_register_machine(QEMUMachine *m);
740
741 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
742
743 #if defined(TARGET_PPC)
744 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
745 #endif
746
747 #if defined(TARGET_MIPS)
748 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
749 #endif
750
751 #include "hw/irq.h"
752
753 /* ISA bus */
754
755 extern target_phys_addr_t isa_mem_base;
756
757 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
758 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
759
760 int register_ioport_read(int start, int length, int size,
761 IOPortReadFunc *func, void *opaque);
762 int register_ioport_write(int start, int length, int size,
763 IOPortWriteFunc *func, void *opaque);
764 void isa_unassign_ioport(int start, int length);
765
766 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
767
768 /* PCI bus */
769
770 extern target_phys_addr_t pci_mem_base;
771
772 typedef struct PCIBus PCIBus;
773 typedef struct PCIDevice PCIDevice;
774
775 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
776 uint32_t address, uint32_t data, int len);
777 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
778 uint32_t address, int len);
779 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
780 uint32_t addr, uint32_t size, int type);
781
782 #define PCI_ADDRESS_SPACE_MEM 0x00
783 #define PCI_ADDRESS_SPACE_IO 0x01
784 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
785
786 typedef struct PCIIORegion {
787 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
788 uint32_t size;
789 uint8_t type;
790 PCIMapIORegionFunc *map_func;
791 } PCIIORegion;
792
793 #define PCI_ROM_SLOT 6
794 #define PCI_NUM_REGIONS 7
795
796 #define PCI_DEVICES_MAX 64
797
798 #define PCI_VENDOR_ID 0x00 /* 16 bits */
799 #define PCI_DEVICE_ID 0x02 /* 16 bits */
800 #define PCI_COMMAND 0x04 /* 16 bits */
801 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
802 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
803 #define PCI_CLASS_DEVICE 0x0a /* Device class */
804 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
805 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
806 #define PCI_MIN_GNT 0x3e /* 8 bits */
807 #define PCI_MAX_LAT 0x3f /* 8 bits */
808
809 struct PCIDevice {
810 /* PCI config space */
811 uint8_t config[256];
812
813 /* the following fields are read only */
814 PCIBus *bus;
815 int devfn;
816 char name[64];
817 PCIIORegion io_regions[PCI_NUM_REGIONS];
818
819 /* do not access the following fields */
820 PCIConfigReadFunc *config_read;
821 PCIConfigWriteFunc *config_write;
822 /* ??? This is a PC-specific hack, and should be removed. */
823 int irq_index;
824
825 /* IRQ objects for the INTA-INTD pins. */
826 qemu_irq *irq;
827
828 /* Current IRQ levels. Used internally by the generic PCI code. */
829 int irq_state[4];
830 };
831
832 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
833 int instance_size, int devfn,
834 PCIConfigReadFunc *config_read,
835 PCIConfigWriteFunc *config_write);
836
837 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
838 uint32_t size, int type,
839 PCIMapIORegionFunc *map_func);
840
841 uint32_t pci_default_read_config(PCIDevice *d,
842 uint32_t address, int len);
843 void pci_default_write_config(PCIDevice *d,
844 uint32_t address, uint32_t val, int len);
845 void pci_device_save(PCIDevice *s, QEMUFile *f);
846 int pci_device_load(PCIDevice *s, QEMUFile *f);
847
848 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
849 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
850 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
851 qemu_irq *pic, int devfn_min, int nirq);
852
853 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
854 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
855 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
856 int pci_bus_num(PCIBus *s);
857 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
858
859 void pci_info(void);
860 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
861 pci_map_irq_fn map_irq, const char *name);
862
863 /* prep_pci.c */
864 PCIBus *pci_prep_init(qemu_irq *pic);
865
866 /* grackle_pci.c */
867 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
868
869 /* unin_pci.c */
870 PCIBus *pci_pmac_init(qemu_irq *pic);
871
872 /* apb_pci.c */
873 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
874 qemu_irq *pic);
875
876 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
877
878 /* piix_pci.c */
879 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
880 void i440fx_set_smm(PCIDevice *d, int val);
881 int piix3_init(PCIBus *bus, int devfn);
882 void i440fx_init_memory_mappings(PCIDevice *d);
883
884 int piix4_init(PCIBus *bus, int devfn);
885
886 /* openpic.c */
887 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
888 enum {
889 OPENPIC_OUTPUT_INT = 0, /* IRQ */
890 OPENPIC_OUTPUT_CINT, /* critical IRQ */
891 OPENPIC_OUTPUT_MCK, /* Machine check event */
892 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
893 OPENPIC_OUTPUT_RESET, /* Core reset event */
894 OPENPIC_OUTPUT_NB,
895 };
896 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
897 qemu_irq **irqs, qemu_irq irq_out);
898
899 /* heathrow_pic.c */
900 qemu_irq *heathrow_pic_init(int *pmem_index);
901
902 /* gt64xxx.c */
903 PCIBus *pci_gt64120_init(qemu_irq *pic);
904
905 #ifdef HAS_AUDIO
906 struct soundhw {
907 const char *name;
908 const char *descr;
909 int enabled;
910 int isa;
911 union {
912 int (*init_isa) (AudioState *s, qemu_irq *pic);
913 int (*init_pci) (PCIBus *bus, AudioState *s);
914 } init;
915 };
916
917 extern struct soundhw soundhw[];
918 #endif
919
920 /* vga.c */
921
922 #ifndef TARGET_SPARC
923 #define VGA_RAM_SIZE (8192 * 1024)
924 #else
925 #define VGA_RAM_SIZE (9 * 1024 * 1024)
926 #endif
927
928 struct DisplayState {
929 uint8_t *data;
930 int linesize;
931 int depth;
932 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
933 int width;
934 int height;
935 void *opaque;
936 QEMUTimer *gui_timer;
937
938 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
939 void (*dpy_resize)(struct DisplayState *s, int w, int h);
940 void (*dpy_refresh)(struct DisplayState *s);
941 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
942 int dst_x, int dst_y, int w, int h);
943 void (*dpy_fill)(struct DisplayState *s, int x, int y,
944 int w, int h, uint32_t c);
945 void (*mouse_set)(int x, int y, int on);
946 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
947 uint8_t *image, uint8_t *mask);
948 };
949
950 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
951 {
952 s->dpy_update(s, x, y, w, h);
953 }
954
955 static inline void dpy_resize(DisplayState *s, int w, int h)
956 {
957 s->dpy_resize(s, w, h);
958 }
959
960 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
961 unsigned long vga_ram_offset, int vga_ram_size);
962 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
963 unsigned long vga_ram_offset, int vga_ram_size,
964 unsigned long vga_bios_offset, int vga_bios_size);
965 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
966 unsigned long vga_ram_offset, int vga_ram_size,
967 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
968 int it_shift);
969
970 /* cirrus_vga.c */
971 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
972 unsigned long vga_ram_offset, int vga_ram_size);
973 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
974 unsigned long vga_ram_offset, int vga_ram_size);
975
976 /* vmware_vga.c */
977 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
978 unsigned long vga_ram_offset, int vga_ram_size);
979
980 /* sdl.c */
981 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
982
983 /* cocoa.m */
984 void cocoa_display_init(DisplayState *ds, int full_screen);
985
986 /* vnc.c */
987 void vnc_display_init(DisplayState *ds);
988 void vnc_display_close(DisplayState *ds);
989 int vnc_display_open(DisplayState *ds, const char *display);
990 int vnc_display_password(DisplayState *ds, const char *password);
991 void do_info_vnc(void);
992
993 /* x_keymap.c */
994 extern uint8_t _translate_keycode(const int key);
995
996 /* ide.c */
997 #define MAX_DISKS 4
998
999 extern BlockDriverState *bs_table[MAX_DISKS + 1];
1000 extern BlockDriverState *sd_bdrv;
1001 extern BlockDriverState *mtd_bdrv;
1002
1003 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1004 BlockDriverState *hd0, BlockDriverState *hd1);
1005 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1006 int secondary_ide_enabled);
1007 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1008 qemu_irq *pic);
1009 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1010 qemu_irq *pic);
1011 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1012
1013 /* cdrom.c */
1014 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1015 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1016
1017 /* ds1225y.c */
1018 typedef struct ds1225y_t ds1225y_t;
1019 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1020
1021 /* es1370.c */
1022 int es1370_init (PCIBus *bus, AudioState *s);
1023
1024 /* sb16.c */
1025 int SB16_init (AudioState *s, qemu_irq *pic);
1026
1027 /* adlib.c */
1028 int Adlib_init (AudioState *s, qemu_irq *pic);
1029
1030 /* gus.c */
1031 int GUS_init (AudioState *s, qemu_irq *pic);
1032
1033 /* dma.c */
1034 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1035 int DMA_get_channel_mode (int nchan);
1036 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1037 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1038 void DMA_hold_DREQ (int nchan);
1039 void DMA_release_DREQ (int nchan);
1040 void DMA_schedule(int nchan);
1041 void DMA_run (void);
1042 void DMA_init (int high_page_enable);
1043 void DMA_register_channel (int nchan,
1044 DMA_transfer_handler transfer_handler,
1045 void *opaque);
1046 /* fdc.c */
1047 #define MAX_FD 2
1048 extern BlockDriverState *fd_table[MAX_FD];
1049
1050 typedef struct fdctrl_t fdctrl_t;
1051
1052 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1053 target_phys_addr_t io_base,
1054 BlockDriverState **fds);
1055 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1056
1057 /* eepro100.c */
1058
1059 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1060 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1061 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1062
1063 /* ne2000.c */
1064
1065 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1066 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1067
1068 /* rtl8139.c */
1069
1070 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1071
1072 /* pcnet.c */
1073
1074 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1075 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1076 qemu_irq irq, qemu_irq *reset);
1077
1078 /* vmmouse.c */
1079 void *vmmouse_init(void *m);
1080
1081 /* vmport.c */
1082 #ifdef TARGET_I386
1083 void vmport_init(CPUState *env);
1084 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1085 #endif
1086
1087 /* pckbd.c */
1088
1089 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1090 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1091 target_phys_addr_t base, int it_shift);
1092
1093 /* mc146818rtc.c */
1094
1095 typedef struct RTCState RTCState;
1096
1097 RTCState *rtc_init(int base, qemu_irq irq);
1098 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1099 void rtc_set_memory(RTCState *s, int addr, int val);
1100 void rtc_set_date(RTCState *s, const struct tm *tm);
1101
1102 /* serial.c */
1103
1104 typedef struct SerialState SerialState;
1105 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1106 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1107 qemu_irq irq, CharDriverState *chr,
1108 int ioregister);
1109 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1110 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1111 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1112 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1113 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1114 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1115
1116 /* parallel.c */
1117
1118 typedef struct ParallelState ParallelState;
1119 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1120 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1121
1122 /* i8259.c */
1123
1124 typedef struct PicState2 PicState2;
1125 extern PicState2 *isa_pic;
1126 void pic_set_irq(int irq, int level);
1127 void pic_set_irq_new(void *opaque, int irq, int level);
1128 qemu_irq *i8259_init(qemu_irq parent_irq);
1129 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1130 void *alt_irq_opaque);
1131 int pic_read_irq(PicState2 *s);
1132 void pic_update_irq(PicState2 *s);
1133 uint32_t pic_intack_read(PicState2 *s);
1134 void pic_info(void);
1135 void irq_info(void);
1136
1137 /* APIC */
1138 typedef struct IOAPICState IOAPICState;
1139
1140 int apic_init(CPUState *env);
1141 int apic_get_interrupt(CPUState *env);
1142 IOAPICState *ioapic_init(void);
1143 void ioapic_set_irq(void *opaque, int vector, int level);
1144
1145 /* i8254.c */
1146
1147 #define PIT_FREQ 1193182
1148
1149 typedef struct PITState PITState;
1150
1151 PITState *pit_init(int base, qemu_irq irq);
1152 void pit_set_gate(PITState *pit, int channel, int val);
1153 int pit_get_gate(PITState *pit, int channel);
1154 int pit_get_initial_count(PITState *pit, int channel);
1155 int pit_get_mode(PITState *pit, int channel);
1156 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1157
1158 /* jazz_led.c */
1159 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1160
1161 /* pcspk.c */
1162 void pcspk_init(PITState *);
1163 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1164
1165 #include "hw/i2c.h"
1166
1167 #include "hw/smbus.h"
1168
1169 /* acpi.c */
1170 extern int acpi_enabled;
1171 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1172 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1173 void acpi_bios_init(void);
1174
1175 /* pc.c */
1176 extern QEMUMachine pc_machine;
1177 extern QEMUMachine isapc_machine;
1178 extern int fd_bootchk;
1179
1180 void ioport_set_a20(int enable);
1181 int ioport_get_a20(void);
1182
1183 /* ppc.c */
1184 extern QEMUMachine prep_machine;
1185 extern QEMUMachine core99_machine;
1186 extern QEMUMachine heathrow_machine;
1187 extern QEMUMachine ref405ep_machine;
1188 extern QEMUMachine taihu_machine;
1189
1190 /* mips_r4k.c */
1191 extern QEMUMachine mips_machine;
1192
1193 /* mips_malta.c */
1194 extern QEMUMachine mips_malta_machine;
1195
1196 /* mips_int.c */
1197 extern void cpu_mips_irq_init_cpu(CPUState *env);
1198
1199 /* mips_pica61.c */
1200 extern QEMUMachine mips_pica61_machine;
1201
1202 /* mips_timer.c */
1203 extern void cpu_mips_clock_init(CPUState *);
1204 extern void cpu_mips_irqctrl_init (void);
1205
1206 /* shix.c */
1207 extern QEMUMachine shix_machine;
1208
1209 /* r2d.c */
1210 extern QEMUMachine r2d_machine;
1211
1212 #ifdef TARGET_PPC
1213 /* PowerPC hardware exceptions management helpers */
1214 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1215 typedef struct clk_setup_t clk_setup_t;
1216 struct clk_setup_t {
1217 clk_setup_cb cb;
1218 void *opaque;
1219 };
1220 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1221 {
1222 if (clk->cb != NULL)
1223 (*clk->cb)(clk->opaque, freq);
1224 }
1225
1226 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1227 /* Embedded PowerPC DCR management */
1228 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1229 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1230 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1231 int (*dcr_write_error)(int dcrn));
1232 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1233 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1234 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1235 /* Embedded PowerPC reset */
1236 void ppc40x_core_reset (CPUState *env);
1237 void ppc40x_chip_reset (CPUState *env);
1238 void ppc40x_system_reset (CPUState *env);
1239 #endif
1240 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1241
1242 extern CPUWriteMemoryFunc *PPC_io_write[];
1243 extern CPUReadMemoryFunc *PPC_io_read[];
1244 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1245
1246 /* sun4m.c */
1247 extern QEMUMachine ss5_machine, ss10_machine;
1248
1249 /* iommu.c */
1250 void *iommu_init(target_phys_addr_t addr);
1251 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1252 uint8_t *buf, int len, int is_write);
1253 static inline void sparc_iommu_memory_read(void *opaque,
1254 target_phys_addr_t addr,
1255 uint8_t *buf, int len)
1256 {
1257 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1258 }
1259
1260 static inline void sparc_iommu_memory_write(void *opaque,
1261 target_phys_addr_t addr,
1262 uint8_t *buf, int len)
1263 {
1264 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1265 }
1266
1267 /* tcx.c */
1268 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1269 unsigned long vram_offset, int vram_size, int width, int height,
1270 int depth);
1271
1272 /* slavio_intctl.c */
1273 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1274 const uint32_t *intbit_to_level,
1275 qemu_irq **irq, qemu_irq **cpu_irq,
1276 qemu_irq **parent_irq, unsigned int cputimer);
1277 void slavio_pic_info(void *opaque);
1278 void slavio_irq_info(void *opaque);
1279
1280 /* loader.c */
1281 int get_image_size(const char *filename);
1282 int load_image(const char *filename, uint8_t *addr);
1283 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1284 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1285 int load_aout(const char *filename, uint8_t *addr);
1286 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1287
1288 /* slavio_timer.c */
1289 void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1290
1291 /* slavio_serial.c */
1292 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1293 CharDriverState *chr1, CharDriverState *chr2);
1294 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1295
1296 /* slavio_misc.c */
1297 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1298 qemu_irq irq);
1299 void slavio_set_power_fail(void *opaque, int power_failing);
1300
1301 /* esp.c */
1302 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1303 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1304 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1305
1306 /* sparc32_dma.c */
1307 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1308 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1309 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1310 uint8_t *buf, int len, int do_bswap);
1311 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1312 uint8_t *buf, int len, int do_bswap);
1313 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1314 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1315
1316 /* cs4231.c */
1317 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1318
1319 /* sun4u.c */
1320 extern QEMUMachine sun4u_machine;
1321
1322 /* NVRAM helpers */
1323 #include "hw/m48t59.h"
1324
1325 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1326 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1327 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1328 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1329 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1330 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1331 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1332 const unsigned char *str, uint32_t max);
1333 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1334 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1335 uint32_t start, uint32_t count);
1336 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1337 const unsigned char *arch,
1338 uint32_t RAM_size, int boot_device,
1339 uint32_t kernel_image, uint32_t kernel_size,
1340 const char *cmdline,
1341 uint32_t initrd_image, uint32_t initrd_size,
1342 uint32_t NVRAM_image,
1343 int width, int height, int depth);
1344
1345 /* adb.c */
1346
1347 #define MAX_ADB_DEVICES 16
1348
1349 #define ADB_MAX_OUT_LEN 16
1350
1351 typedef struct ADBDevice ADBDevice;
1352
1353 /* buf = NULL means polling */
1354 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1355 const uint8_t *buf, int len);
1356 typedef int ADBDeviceReset(ADBDevice *d);
1357
1358 struct ADBDevice {
1359 struct ADBBusState *bus;
1360 int devaddr;
1361 int handler;
1362 ADBDeviceRequest *devreq;
1363 ADBDeviceReset *devreset;
1364 void *opaque;
1365 };
1366
1367 typedef struct ADBBusState {
1368 ADBDevice devices[MAX_ADB_DEVICES];
1369 int nb_devices;
1370 int poll_index;
1371 } ADBBusState;
1372
1373 int adb_request(ADBBusState *s, uint8_t *buf_out,
1374 const uint8_t *buf, int len);
1375 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1376
1377 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1378 ADBDeviceRequest *devreq,
1379 ADBDeviceReset *devreset,
1380 void *opaque);
1381 void adb_kbd_init(ADBBusState *bus);
1382 void adb_mouse_init(ADBBusState *bus);
1383
1384 /* cuda.c */
1385
1386 extern ADBBusState adb_bus;
1387 int cuda_init(qemu_irq irq);
1388
1389 #include "hw/usb.h"
1390
1391 /* usb ports of the VM */
1392
1393 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1394 usb_attachfn attach);
1395
1396 #define VM_USB_HUB_SIZE 8
1397
1398 void do_usb_add(const char *devname);
1399 void do_usb_del(const char *devname);
1400 void usb_info(void);
1401
1402 /* scsi-disk.c */
1403 enum scsi_reason {
1404 SCSI_REASON_DONE, /* Command complete. */
1405 SCSI_REASON_DATA /* Transfer complete, more data required. */
1406 };
1407
1408 typedef struct SCSIDevice SCSIDevice;
1409 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1410 uint32_t arg);
1411
1412 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1413 int tcq,
1414 scsi_completionfn completion,
1415 void *opaque);
1416 void scsi_disk_destroy(SCSIDevice *s);
1417
1418 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1419 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1420 layer the completion routine may be called directly by
1421 scsi_{read,write}_data. */
1422 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1423 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1424 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1425 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1426
1427 /* lsi53c895a.c */
1428 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1429 void *lsi_scsi_init(PCIBus *bus, int devfn);
1430
1431 /* integratorcp.c */
1432 extern QEMUMachine integratorcp_machine;
1433
1434 /* versatilepb.c */
1435 extern QEMUMachine versatilepb_machine;
1436 extern QEMUMachine versatileab_machine;
1437
1438 /* realview.c */
1439 extern QEMUMachine realview_machine;
1440
1441 /* spitz.c */
1442 extern QEMUMachine akitapda_machine;
1443 extern QEMUMachine spitzpda_machine;
1444 extern QEMUMachine borzoipda_machine;
1445 extern QEMUMachine terrierpda_machine;
1446
1447 /* palm.c */
1448 extern QEMUMachine palmte_machine;
1449
1450 /* ps2.c */
1451 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1452 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1453 void ps2_write_mouse(void *, int val);
1454 void ps2_write_keyboard(void *, int val);
1455 uint32_t ps2_read_data(void *);
1456 void ps2_queue(void *, int b);
1457 void ps2_keyboard_set_translation(void *opaque, int mode);
1458 void ps2_mouse_fake_event(void *opaque);
1459
1460 /* smc91c111.c */
1461 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1462
1463 /* pl031.c */
1464 void pl031_init(uint32_t base, qemu_irq irq);
1465
1466 /* pl110.c */
1467 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1468
1469 /* pl011.c */
1470 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1471
1472 /* pl050.c */
1473 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1474
1475 /* pl080.c */
1476 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1477
1478 /* pl181.c */
1479 void pl181_init(uint32_t base, BlockDriverState *bd,
1480 qemu_irq irq0, qemu_irq irq1);
1481
1482 /* pl190.c */
1483 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1484
1485 /* arm-timer.c */
1486 void sp804_init(uint32_t base, qemu_irq irq);
1487 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1488
1489 /* arm_sysctl.c */
1490 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1491
1492 /* arm_gic.c */
1493 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1494
1495 /* arm_boot.c */
1496
1497 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1498 const char *kernel_cmdline, const char *initrd_filename,
1499 int board_id, target_phys_addr_t loader_start);
1500
1501 /* sh7750.c */
1502 struct SH7750State;
1503
1504 struct SH7750State *sh7750_init(CPUState * cpu);
1505
1506 typedef struct {
1507 /* The callback will be triggered if any of the designated lines change */
1508 uint16_t portamask_trigger;
1509 uint16_t portbmask_trigger;
1510 /* Return 0 if no action was taken */
1511 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1512 uint16_t * periph_pdtra,
1513 uint16_t * periph_portdira,
1514 uint16_t * periph_pdtrb,
1515 uint16_t * periph_portdirb);
1516 } sh7750_io_device;
1517
1518 int sh7750_register_io_device(struct SH7750State *s,
1519 sh7750_io_device * device);
1520 /* sh_timer.c */
1521 #define TMU012_FEAT_TOCR (1 << 0)
1522 #define TMU012_FEAT_3CHAN (1 << 1)
1523 #define TMU012_FEAT_EXTCLK (1 << 2)
1524 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1525
1526 /* sh_serial.c */
1527 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1528 void sh_serial_init (target_phys_addr_t base, int feat,
1529 uint32_t freq, CharDriverState *chr);
1530
1531 /* tc58128.c */
1532 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1533
1534 /* NOR flash devices */
1535 #define MAX_PFLASH 4
1536 extern BlockDriverState *pflash_table[MAX_PFLASH];
1537 typedef struct pflash_t pflash_t;
1538
1539 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1540 BlockDriverState *bs,
1541 uint32_t sector_len, int nb_blocs, int width,
1542 uint16_t id0, uint16_t id1,
1543 uint16_t id2, uint16_t id3);
1544
1545 /* nand.c */
1546 struct nand_flash_s;
1547 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1548 void nand_done(struct nand_flash_s *s);
1549 void nand_setpins(struct nand_flash_s *s,
1550 int cle, int ale, int ce, int wp, int gnd);
1551 void nand_getpins(struct nand_flash_s *s, int *rb);
1552 void nand_setio(struct nand_flash_s *s, uint8_t value);
1553 uint8_t nand_getio(struct nand_flash_s *s);
1554
1555 #define NAND_MFR_TOSHIBA 0x98
1556 #define NAND_MFR_SAMSUNG 0xec
1557 #define NAND_MFR_FUJITSU 0x04
1558 #define NAND_MFR_NATIONAL 0x8f
1559 #define NAND_MFR_RENESAS 0x07
1560 #define NAND_MFR_STMICRO 0x20
1561 #define NAND_MFR_HYNIX 0xad
1562 #define NAND_MFR_MICRON 0x2c
1563
1564 /* ecc.c */
1565 struct ecc_state_s {
1566 uint8_t cp; /* Column parity */
1567 uint16_t lp[2]; /* Line parity */
1568 uint16_t count;
1569 };
1570
1571 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1572 void ecc_reset(struct ecc_state_s *s);
1573 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1574 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1575
1576 /* GPIO */
1577 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1578
1579 /* ads7846.c */
1580 struct ads7846_state_s;
1581 uint32_t ads7846_read(void *opaque);
1582 void ads7846_write(void *opaque, uint32_t value);
1583 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1584
1585 /* max111x.c */
1586 struct max111x_s;
1587 uint32_t max111x_read(void *opaque);
1588 void max111x_write(void *opaque, uint32_t value);
1589 struct max111x_s *max1110_init(qemu_irq cb);
1590 struct max111x_s *max1111_init(qemu_irq cb);
1591 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1592
1593 /* PCMCIA/Cardbus */
1594
1595 struct pcmcia_socket_s {
1596 qemu_irq irq;
1597 int attached;
1598 const char *slot_string;
1599 const char *card_string;
1600 };
1601
1602 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1603 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1604 void pcmcia_info(void);
1605
1606 struct pcmcia_card_s {
1607 void *state;
1608 struct pcmcia_socket_s *slot;
1609 int (*attach)(void *state);
1610 int (*detach)(void *state);
1611 const uint8_t *cis;
1612 int cis_len;
1613
1614 /* Only valid if attached */
1615 uint8_t (*attr_read)(void *state, uint32_t address);
1616 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1617 uint16_t (*common_read)(void *state, uint32_t address);
1618 void (*common_write)(void *state, uint32_t address, uint16_t value);
1619 uint16_t (*io_read)(void *state, uint32_t address);
1620 void (*io_write)(void *state, uint32_t address, uint16_t value);
1621 };
1622
1623 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1624 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1625 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1626 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1627 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1628 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1629 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1630 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1631 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1632 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1633 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1634 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1635 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1636 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1637 #define CISTPL_END 0xff /* Tuple End */
1638 #define CISTPL_ENDMARK 0xff
1639
1640 /* dscm1xxxx.c */
1641 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1642
1643 /* ptimer.c */
1644 typedef struct ptimer_state ptimer_state;
1645 typedef void (*ptimer_cb)(void *opaque);
1646
1647 ptimer_state *ptimer_init(QEMUBH *bh);
1648 void ptimer_set_period(ptimer_state *s, int64_t period);
1649 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1650 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1651 uint64_t ptimer_get_count(ptimer_state *s);
1652 void ptimer_set_count(ptimer_state *s, uint64_t count);
1653 void ptimer_run(ptimer_state *s, int oneshot);
1654 void ptimer_stop(ptimer_state *s);
1655 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1656 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1657
1658 #include "hw/pxa.h"
1659
1660 #include "hw/omap.h"
1661
1662 /* mcf_uart.c */
1663 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1664 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1665 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1666 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1667 CharDriverState *chr);
1668
1669 /* mcf_intc.c */
1670 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1671
1672 /* mcf_fec.c */
1673 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1674
1675 /* mcf5206.c */
1676 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1677
1678 /* an5206.c */
1679 extern QEMUMachine an5206_machine;
1680
1681 /* mcf5208.c */
1682 extern QEMUMachine mcf5208evb_machine;
1683
1684 #include "gdbstub.h"
1685
1686 #endif /* defined(QEMU_TOOL) */
1687
1688 /* monitor.c */
1689 void monitor_init(CharDriverState *hd, int show_banner);
1690 void term_puts(const char *str);
1691 void term_vprintf(const char *fmt, va_list ap);
1692 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1693 void term_print_filename(const char *filename);
1694 void term_flush(void);
1695 void term_print_help(void);
1696 void monitor_readline(const char *prompt, int is_password,
1697 char *buf, int buf_size);
1698
1699 /* readline.c */
1700 typedef void ReadLineFunc(void *opaque, const char *str);
1701
1702 extern int completion_index;
1703 void add_completion(const char *str);
1704 void readline_handle_byte(int ch);
1705 void readline_find_completion(const char *cmdline);
1706 const char *readline_get_history(unsigned int index);
1707 void readline_start(const char *prompt, int is_password,
1708 ReadLineFunc *readline_func, void *opaque);
1709
1710 void kqemu_record_dump(void);
1711
1712 #endif /* VL_H */
Stable branch of Qemu 0.9.1